Memory system and operating method thereof, electronic device

Abstract

Embodiments of the present application provide a memory system and an operating method thereof, and an electronic device. The memory system comprises: a memory device configured to store data; a controller coupled to the memory device; the controller is configured to: perform a first training operation on a data sampling delay value based on first training data, determine a first delay value range that enables the memory device to correctly read and write the first training data; perform a second training operation on the data sampling delay value based on second training data, determine a second delay value range that enables the memory device to correctly read and write the second training data; wherein the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data and the second training data are different; and determine an actual data sampling delay value based on the first delay value range and the second delay value range.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of memory, and in particular to a memory system and an operating method thereof, and an electronic device. BACKGROUND

[0002] Memory is often used to meet different levels of data exchange and storage requirements. As the working frequency of a processor increases, the frequency of a memory interface is also required to be higher and higher. Higher frequency and signal quality problems of a signal line can easily lead to a decrease in the stability of memory access. Therefore, in order to improve the stability of memory access, the memory can be trained, and read and write operations are continuously adjusted by adjusting the delay value of the clock to obtain the optimal clock delay value. However, the existing memory training method still has problems such as poor accuracy and long time consumption. SUMMARY

[0003] Therefore, embodiments of the present application provide a memory system and an operating method thereof, and an electronic device.

[0004] In one aspect, the present application provides a memory system, comprising:

[0005] a memory device configured to store data;

[0006] a controller coupled to the memory device; the controller is configured to:

[0007] perform a first training operation on a data sampling delay value based on first training data, to determine a first delay value range that enables the memory device to correctly read and write the first training data;

[0008] perform a second training operation on a data sampling delay value based on second training data, to determine a second delay value range that enables the memory device to correctly read and write the second training data;

[0009] wherein the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data and the second training data are different;

[0010] determine an actual data sampling delay value based on the first delay value range and the second delay value range.

[0011] In some embodiments, each bit value corresponding to the first training data and the second training data is opposite.

[0012] In some embodiments, the controller is specifically configured to:

[0013] write the training data to the memory device and read corresponding data from the memory device based on different data sampling delay values, and determine a delay value range of the data sampling delay values that makes the read data identical to the training data; wherein the training data comprises the first training data, and the delay value range comprises the first delay value range; or the training data comprises the second training data, and the delay value range comprises the second delay value range.

[0014] In some embodiments, the controller is specifically configured to:

[0015] write the training data to the memory device and read corresponding data from the memory device based on a plurality of the data sampling delay values that are sequentially increased, determine a first boundary value of the delay value range as a first data sampling delay value that makes the read data identical to the training data, and determine a second boundary value of the delay value range as a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value.

[0016] Alternatively,

[0017] write the training data to the memory device and read corresponding data from the memory device based on a plurality of the data sampling delay values that are sequentially decreased, determine the second boundary value as a first data sampling delay value that makes the read data identical to the training data, and determine the first boundary value as a first data sampling delay value that makes the read data different from the training data and less than the second boundary value.

[0018] In some embodiments, determining the actual data sampling delay value based on the first delay value range and the second delay value range comprises:

[0019] determining an intersection of the first delay value range and the second delay value range;

[0020] determining the actual data sampling delay value based on the intersection.

[0021] In some embodiments, determining the actual data sampling delay value based on the intersection comprises:

[0022] determining one of a plurality of quartiles of the intersection as the actual data sampling delay value.

[0023] In some embodiments, the controller is coupled to the memory device through N data lines, where N is a positive integer; the first training data corresponds to N-bit data of each of the transmission periods being transmitted through N data lines respectively, and the second training data corresponds to N-bit data of each of the transmission periods being transmitted through N data lines respectively.

[0024] In another aspect, the embodiments of the present application also provide an operation method of a memory system, the memory system comprising a memory device and a controller coupled to the memory device; the operation method comprising:

[0025] performing a first training operation of a data sampling delay value based on first training data, to determine a first delay value range that enables the memory device to correctly read and write the first training data;

[0026] performing a second training operation of a data sampling delay value based on second training data, to determine a second delay value range that enables the memory device to correctly read and write the second training data;

[0027] wherein the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data;

[0028] determining an actual data sampling delay value based on the first delay value range and the second delay value range.

[0029] In some embodiments, each bit of the first training data and the second training data has opposite values.

[0030] In some embodiments, the method specifically comprises:

[0031] based on different data sampling delay values, writing training data to the memory device and reading corresponding data from the memory device, to determine a delay value range of the data sampling delay value that enables the read data to be the same as the training data; wherein the training data comprises the first training data, and the delay value range comprises the first delay value range; or, the training data comprises the second training data, and the delay value range comprises the second delay value range.

[0032] In some embodiments, the method specifically comprises:

[0033] based on a plurality of the data sampling delay values in turn increasing, writing the training data into the memory device and reading corresponding data from the memory device; determining a first data sampling delay value that makes the read data same as the training data as a first boundary value of the delay value range; determining a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value as a second boundary value of the delay value range;

[0034] or,

[0035] based on a plurality of the data sampling delay values in turn decreasing, writing the training data into the memory device and reading corresponding data from the memory device; determining a first data sampling delay value that makes the read data same as the training data as the second boundary value; determining a first data sampling delay value that makes the read data different from the training data and less than the second boundary value as the first boundary value.

[0036] In some embodiments, the determining the actual data sampling delay value based on the first delay value range and the second delay value range comprises:

[0037] determining an intersection of the first delay value range and the second delay value range;

[0038] determining the actual data sampling delay value based on the intersection.

[0039] In some embodiments, the determining the actual data sampling delay value based on the intersection comprises:

[0040] determining one of a plurality of quartiles of the intersection as the actual data sampling delay value.

[0041] In some embodiments, the controller is coupled to the memory device through N data lines, where N is a positive integer; the first training data corresponds to N-bit data of each transmission period transmitted through N data lines respectively, and the second training data corresponds to N-bit data of each transmission period transmitted through N data lines respectively.

[0042] In still another aspect, the embodiments of the present application also provide an electronic device, comprising: the memory system in any of the above embodiments; a processor coupled to the memory system.

[0043] In the embodiments of the present application, the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data. In this way, on the one hand, the data values of any two adjacent transmission periods in each training data are opposite, which ensures that the transmission level on the data line is always alternately changed between 0 and 1 during read and write operations, which is conducive to improving the accuracy of the training result of the data sampling delay value; on the other hand, the controller only uses two different training data to perform the training operation of the data sampling delay value, which is conducive to reducing the training time and improving the working efficiency of the memory system. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A schematic diagram of a memory system provided by the embodiments of the present application;

[0045] Figure 2 A schematic diagram of a data line in a memory system provided by the embodiments of the present application;

[0046] Figure 3 A flowchart of a data sampling delay value training operation based on training data provided by the embodiments of the present application;

[0047] Figure 4 A schematic diagram of an intersection of a first delay value range and a second delay value range provided by the embodiments of the present application;

[0048] Figure 5 A flowchart of an intersection operation provided by the embodiments of the present application;

[0049] Figure 6 A flowchart of an operation method of a memory system provided by the embodiments of the present application;

[0050] Figure 7 A schematic diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0052] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail to the extent that they would obscure the understanding of the present application. In this document, the terms "computer", "server", "processor", and "memory" are not limited to just these components, and can include processing

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0054] For a thorough understanding of the present application, reference will be made to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0055] In a memory system, data transmission between a memory device and a controller usually samples a data signal (DQ) with a data sampling (Data Strobe Signal, DQS) signal for read and write operations. In order to improve the stability of memory device access, the data sampling delay value of the data sampling signal can be trained, for example, read and write operations are performed at different data sampling delay values to obtain the optimal actual data sampling delay value.

[0056] In some embodiments, a plurality of data sampling delay values can be polled to read and write a fixed training data from the memory device through the bus at each data sampling delay value, and determine whether the written and read data are consistent, so as to find the actual data sampling delay value of the data sampling signal. Specifically, a fixed training data can be written and read based on a plurality of different data sampling delay values, and a data sampling delay value range that makes the written data and the read data the same is determined; and the actual data sampling delay value is determined based on the data sampling delay value range. However, since there can be signal quality problems in a plurality of data lines between the memory device and the controller, using only a fixed training data for training can result in inaccurate training results.

[0057] In some embodiments, a plurality of data sampling delay values can be polled to read and write a plurality of different training data from the memory device through the bus at each data sampling delay value and determine whether the written and read data are consistent to find the actual data sampling delay value of the data sampling signal. Specifically, based on a plurality of different data sampling delay values, the write and read of each training data can be performed and the data sampling delay value range that makes the written data identical to the read data can be determined; and based on the plurality of data sampling delay value ranges corresponding to the plurality of training data, the actual data sampling delay value can be determined. However, a large number of training data can result in a long training time and does not necessarily guarantee the effectiveness of the actual data sampling delay value.

[0058] As shown in Figure 1 The embodiments of the present application provide a memory system 100, comprising: a memory device 110 configured to store data; a controller 120 coupled to the memory device 110; the controller 120 is configured to: perform a first training operation of the data sampling delay value based on first training data, determine a first delay value range that makes the memory device 110 correctly read and write the first training data; perform a second training operation of the data sampling delay value based on second training data, determine a second delay value range that makes the memory device 110 correctly read and write the second training data; wherein the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data and the second training data are different; determine the actual data sampling delay value based on the first delay value range and the second delay value range.

[0059] In the embodiments of the present application, the memory system 100 includes at least one memory device 110 and a controller 120 coupled to the memory device 110. The memory device 110 can be a volatile memory, including but not limited to a static random access memory (SRAM), a synchronous static random access memory (SSRAM), a pseudo static random access memory (PSRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) synchronous dynamic random access memory, an enhanced synchronous dynamic random access memory (ESDRAM), a sync link dynamic random access memory (SLDRAM), a direct rambus random access memory (DRRAM), etc. The memory device 110 can also be a non-volatile memory, including but not limited to a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, etc. Here, the memory device 110 is taken as a pseudo static random access memory for example.

[0060] The controller 120 can be implemented by any suitable logic device, such as an application specific integrated circuit (ASIC), a DSP, a programmable logic device (PLD), a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general purpose processor, a controller, a micro controller unit (MCU), a microprocessor, etc. Here, the controller 120 is taken as an example implemented by part of circuits in a micro controller.

[0061] The controller 120 performs a training operation of the data sampling delay value using the first training data and the second training data. Exemplarily, the controller 120 can perform the read-write operation of the training data under a plurality of data sampling delay values respectively, the controller 120 can write and read the training data under one data sampling delay value each time, if the written and read data are all correct, the data sampling delay value is added to the delay value range; in this way, the delay value range composed of the data sampling delay value which makes the training data correctly read and write can be obtained; then, the controller 120 can determine the final actual data sampling delay value based on the first delay value range corresponding to the first training data and the second delay value range corresponding to the second training data. That is to say, the controller 120 adopts a polling manner for the first training data and the second training data, to find out the delay value range corresponding to the training data which is correctly written and read by the memory device 110. It should be noted that the plurality of data sampling delay values used in the training operation can be determined by pre-experiment or experience value. The plurality of data sampling delay values can be polled in order from small to large, from large to small, etc., or can be traversed in a completely random order.

[0062] The transmission of the first training data between the controller 120 and the memory device 110 can include a plurality of transmission periods, and the data values of any two adjacent transmission periods in the first training data are opposite, where the "opposite data values" refer to the pair of opposite binary values of "1" and "0". For example, the first training data corresponds to 8-bit data for each transmission period, for example, the data corresponding to the ith transmission period in the first training data is "00000000", i is an integer greater than 1, and the data corresponding to the i-1th transmission period and the i+1th transmission period in the first training data is "11111111". That is, when the first training data is transmitted between the controller 120 and the memory device 110, the levels of any two adjacent transmission periods are opposite, and sampling using the DQS signal at the alternating levels can improve the accuracy of the training result. The second training data can be understood with reference to the above example of the first training data, which will not be described here. However, it should be noted that the second training data is different from the first training data, so that the actual data sampling delay value is determined by combining the first delay value range and the second delay value range to enhance the robustness of the training process and further improve the accuracy of the data sampling delay value training result.

[0063] In this way, on the one hand, the data values of any two adjacent transmission periods in each training data are opposite, which ensures that the transmission level on the data line during read and write operations is always alternating between 0 and 1, which is beneficial to improve the accuracy of the data sampling delay value training result. On the other hand, the controller only uses two different training data for data sampling delay value training operation, which is beneficial to reduce the training time and improve the working efficiency of the memory system.

[0064] In some embodiments, each bit value corresponding to the first training data and the second training data is opposite.

[0065] In the embodiments of the present application, each bit value of the first training data is opposite to that of the second training data, i.e., each bit of the first training data is complementary to that of the second training data. For example, if the binary value of the first training data is "00000000 11111111 00000000 11111111", the binary value of the second training data is "11111111 00000000 11111111 00000000". It should be noted that the bit width of the data is taken as an example of 32 bits, but the bit width of the data in the present application is not limited to 32 bits. Through relevant tests, it can be found that the range of the delay value obtained by training is different when the data "0" or the data "1" is transmitted first on the data line between the controller 120 and the memory device 110. Therefore, by making each bit of the first training data complementary to that of the second training data, and then determining the actual data sampling delay value (such as taking the intersection) by synthesizing the corresponding first delay value range and the second delay value range, the robustness of the data sampling delay value training can be further improved, and the training result is more accurate. For example, the first training data can be 0x00FF00FF (hexadecimal value), and the second training data can be 0xFF00FF00.

[0066] In some embodiments, as shown in Figure 2 the controller 120 is coupled to the memory device 110 through N data lines, where N is a positive integer; the first training data corresponds to N-bit data transmitted through the N data lines in each transmission period, and the second training data corresponds to N-bit data transmitted through the N data lines in each transmission period.

[0067] In the embodiments of the present application, the controller 120 and the memory device 110 transmit data through N data lines, which are taken as an example of 8 data lines (DQ0~DQ7) as shown in Figure 2 The 8 data lines can transmit 8 bits of data at the same time, i.e., the edge of one clock signal (such as the DQS signal) can transmit 1 byte of data. Since the signal quality of each data line in the memory system 100 is inconsistent, it is necessary to perform data sampling delay value training to obtain a suitable data sampling delay value, so that the DQS signal can accurately sample the DQ signal.

[0068] The first training data corresponds to N-bit data transmitted through the N data lines in each transmission period. For example, the 8-bit data corresponding to the i-th transmission period in the first training data is "00000000", and each bit of "00000000" is transmitted through a corresponding data line. The second training data can be understood with reference to the example of the first training data described above, which will not be described here.

[0069] In some embodiments, the controller 120 is specifically configured to: write training data to the memory device 110 and read corresponding data from the memory device 110 based on different data sampling delay values, and determine a delay value range of the data sampling delay values that make the read data identical to the training data; wherein the training data comprises first training data, and the delay value range comprises a first delay value range; or the training data comprises second training data, and the delay value range comprises a second delay value range.

[0070] In embodiments of the present application, the controller 120 performs the writing and reading of the training data at a plurality of different data sampling delay values, respectively. For example, the controller 120 can write the training data to the memory device 110 and read corresponding data at one data sampling delay value each time, and if the read data is identical to the written training data, the data sampling delay value is added to the delay value range. In this way, all data sampling delay values that make the read data identical to the training data collectively constitute the delay value range corresponding to the training data. That is, the controller 120 can determine whether the data sampling delay value makes the memory device 110 correctly read and write the training data by comparing the read data and the training data. In some embodiments, the controller 120 can implement the above comparison process through a comparator hardware circuit or software.

[0071] In other embodiments, the memory system 100 can also determine whether the current data sampling delay value makes the memory device 110 correctly read and write the training data through other ways. For example, the training data can be written to the memory device 110 in advance, the controller 120 reads the training data from the memory device 110, and then rewrites the read data to the memory device 110, and then the memory device 110 determines whether the rewritten data is identical to the original training data to determine whether the current data sampling delay value makes the memory device 110 correctly read and write the training data.

[0072] In some embodiments, the controller 120 is specifically configured to: write training data to the memory device 110 and read corresponding data from the memory device 110 based on a plurality of data sampling delay values that are sequentially increased; determine a first data sampling delay value that makes the read data identical to the training data as a first boundary value of the delay value range; determine a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value as a second boundary value of the delay value range; or write training data to the memory device 110 and read corresponding data from the memory device 110 based on a plurality of data sampling delay values that are sequentially decreased; determine a first data sampling delay value that makes the read data identical to the training data as the second boundary value; and determine a first data sampling delay value that makes the read data different from the training data and less than the second boundary value as the first boundary value.

[0073] In the embodiments of the present application, the controller 120 can poll the plurality of data sampling delay values in ascending order or descending order in the training operation. For example, the controller 120 polls the plurality of data sampling delay values in ascending order, and the first data sampling delay value that makes the read data identical to the training data is the minimum boundary value of the delay value range, i.e., the first boundary value. As the data sampling delay value gradually increases, the read data remains identical to the training data within a certain range. When the data sampling delay value continues to increase and the read data is no longer identical to the training data, the data sampling delay value at this time can be determined as the maximum boundary value of the delay value range, i.e., the second boundary value. The specific process of polling the plurality of data sampling delay values in descending order is opposite to the polling process in ascending order, which will not be described here.

[0074] In some embodiments, the controller 120 is specifically configured to: based on the first delay value, write the training data to the memory device 110; read the corresponding data from the memory device 110; in the case that the read data is different from the training data, increase the first delay value by a first preset step, and based on the updated first delay value, write the training data to the memory device 110; in the case that the read data is identical to the training data, determine the first delay value as the first boundary value; increase the first boundary value by a second preset step as the second delay value, and based on the second delay value, write the training data to the memory device 110; read the corresponding data from the memory device 110; in the case that the read data is identical to the training data, increase the second delay value by the second preset step, and based on the updated second delay value, write the training data to the memory device 110; in the case that the read data is different from the training data, determine the second delay value as the second boundary value.

[0075] In the embodiments of the present application, as Figure 3 shown is a step flow chart of the controller performing data sampling delay value training based on any one training data to determine the delay value range corresponding to the training data. It should be noted that Figure 3 only the process of polling the plurality of data sampling delay values in ascending order is shown.

[0076] Specifically, first, the controller writes the training data into the memory device based on a first delay value (step S101), where the initial first delay value can be the minimum value in the plurality of data sampling delay values, and the initial first delay value can be determined by experiment or experience. Then the controller reads the corresponding data from the memory device (step S102), and judges whether the read data is the same as the training data (step S103). If the read data is different from the training data, the controller increases the first delay value by a first preset step (step S104), and writes the training data into the memory device again based on the updated first delay value, to perform the next round of reading and judging, and the first preset step can be determined by experiment or experience. If the read data is the same as the training data, the controller determines the current first delay value as the minimum boundary value of the delay value range, that is, the first boundary value (step S105).

[0077] After determining the first boundary value, the controller increases the first boundary value by a second preset step as a second delay value (step S106), and writes the training data into the memory device based on the second delay value (step S107). Then the controller reads the corresponding data from the memory device (step S108), and judges whether the read data is the same as the training data (step S109). If the read data is the same as the training data, the controller increases the second delay value by the second preset step (step S106), and writes the training data into the memory device again based on the updated second delay value, to perform the next round of reading and judging, and the second preset step can be determined by experiment or experience. If the read data is the same as the training data, the controller determines the current second delay value as the maximum boundary value of the delay value range, that is, the second boundary value (step S110).

[0078] It should be noted that the first preset step and the second preset step can be set according to the actual performance requirement of the memory system. The smaller the preset step is, the more the polling times are, and the training duration is correspondingly increased, but the boundary value obtained by training is more accurate. The larger the preset step is, the fewer the polling times are, and the training duration is correspondingly reduced, but the accuracy of the boundary value obtained by training is reduced.

[0079] In some embodiments, as shown in Figure 4 and Figure 5 , determining the actual data sampling delay value based on the first delay value range and the second delay value range includes: determining the intersection of the first delay value range and the second delay value range; and determining the actual data sampling delay value based on the intersection.

[0080] In the embodiments of the present application, referring to Figure 4 , the controller can take the intersection of the first delay value range and the second delay value range, and determine any value in the intersection as the actual data sampling delay value. Referring to Figure 5The illustrated steps, the controller can compare the first delay value range and the first boundary value of the second delay value range (step S201), and the larger one of the first boundary value left1 of the first delay value range and the first boundary value left2 of the second delay value range is taken as the minimum boundary value left of the intersection (step S202 and step S203). Then, the controller can compare the second boundary value of the first delay value range and the second boundary value of the second delay value range (step S204), and the smaller one of the second boundary value right1 of the first delay value range and the second boundary value right2 of the second delay value range is taken as the maximum boundary value right of the intersection (step S205 and step S206). Finally, the controller determines the actual data sampling delay value based on the intersection (step S207). In some embodiments, the controller can compare the above-mentioned comparison process through a comparator hardware circuit or software implementation.

[0081] In some embodiments, determining the actual data sampling delay value based on the intersection comprises: determining one of a plurality of quartiles of the intersection as the actual data sampling delay value.

[0082] In the embodiments of the present application, one of the first quartile, the median (i.e. the second quartile) and the third quartile of the intersection can be determined as the actual data sampling delay value according to the design requirements of the memory system. It should be noted that the present application can also determine other values within the intersection as the actual data sampling delay value, which is not limited here.

[0083] Based on the same inventive concept, the embodiments of the present application also provide an operation method of a memory system, the memory system comprising a memory device and a controller coupled to the memory device; as shown in the figure, Figure 6 The method comprises:

[0084] Step S301, performing a first training operation of a data sampling delay value based on first training data, to determine a first delay value range that enables the memory device to correctly read and write the first training data;

[0085] Step S302, performing a second training operation of a data sampling delay value based on second training data, to determine a second delay value range that enables the memory device to correctly read and write the second training data; wherein the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data and the second training data are different;

[0086] Step S303, determining an actual data sampling delay value based on the first delay value range and the second delay value range.

[0087] It should be understood that Figure 6The steps shown in the flowchart are not exclusive and other steps can be performed before, after, or in between any of the steps shown.

[0088] In this way, on the one hand, the data values of any two adjacent transmission periods in each training data are opposite, which ensures that the transmission level on the data line is always alternately changed between 0 and 1 during read and write operations, and is conducive to improving the accuracy of the training result of the data sampling delay value; on the other hand, the method only uses two different training data to perform the training operation of the data sampling delay value, which is conducive to reducing the training time and improving the working efficiency of the memory system.

[0089] In some embodiments, each bit value corresponding to the first training data and the second training data is opposite.

[0090] In some embodiments, the operation method specifically comprises: based on different data sampling delay values, writing training data into the memory device and reading corresponding data from the memory device, and determining a delay value range of the data sampling delay value that makes the read data same as the training data; wherein the training data comprises the first training data, and the delay value range comprises the first delay value range; or the training data comprises the second training data, and the delay value range comprises the second delay value range.

[0091] In some embodiments, the operation method specifically comprises: based on a plurality of data sampling delay values that are sequentially increased, writing training data into the memory device and reading corresponding data from the memory device; determining that the first data sampling delay value that makes the read data same as the training data is the first boundary value of the delay value range; determining that the first data sampling delay value that makes the read data different from the training data and greater than the first boundary value is the second boundary value of the delay value range; or based on a plurality of data sampling delay values that are sequentially decreased, writing training data into the memory device and reading corresponding data from the memory device; determining that the first data sampling delay value that makes the read data same as the training data is the second boundary value; determining that the first data sampling delay value that makes the read data different from the training data and less than the second boundary value is the first boundary value.

[0092] In some embodiments, the operation method specifically includes: writing training data into a memory device based on a first delay value; reading corresponding data from the memory device; if the read data is different from the training data, increasing the first delay value by a first preset step, and writing the training data into the memory device based on the updated first delay value; if the read data is the same as the training data, determining the first delay value as a first boundary value; increasing the first boundary value by a second preset step to obtain a second delay value, and writing the training data into the memory device based on the second delay value; reading corresponding data from the memory device; if the read data is the same as the training data, increasing the second delay value by a second preset step, and writing the training data into the memory device based on the updated second delay value; if the read data is different from the training data, determining the second delay value as a second boundary value.

[0093] In some embodiments, determining the actual data sampling delay value based on a first delay value range and a second delay value range includes: determining the intersection of the first delay value range and the second delay value range; and determining the actual data sampling delay value based on the intersection.

[0094] In some embodiments, determining the actual data sampling delay value based on the intersection includes: determining one of the plurality of quartiles of the intersection as the actual data sampling delay value.

[0095] In some embodiments, the controller is coupled to the memory device via N data lines, where N is a positive integer; the first training data, corresponding to N bits of data in each transmission cycle, is transmitted via the N data lines, and the second training data, corresponding to N bits of data in each transmission cycle, is transmitted via the N data lines.

[0096] Based on the same inventive concept, embodiments of this application also provide an electronic device, such as... Figure 7 As shown, the electronic device 200 includes: any of the memory systems 100 described in the above embodiments; and a processor 210 coupled to the memory system 100. Exemplarily, the processor 210 may be a microprocessor, the memory device 110 in the memory system 100 may be a pseudo-static random access memory, and the controller 120 may be the processor 210 or implemented by at least a portion of the circuitry in the processor 210. Figure 7 The controller 120 is shown only as an example of a portion of the circuitry implemented by the processor 210.

[0097] In the memory system, the operation method of the memory system and the electronic device provided in the application, on the one hand, the data values of any two adjacent transmission periods in each training data are opposite, so as to ensure that the transmission level on the data line is always alternately changed between 0 and 1 during read and write operations, and the accuracy of the training result of the data sampling delay value is improved; on the other hand, the method only uses two different training data to perform the training operation of the data sampling delay value, so as to reduce the training time and improve the working efficiency of the memory system.

[0098] The various embodiments / implementation modes provided in the application can be combined with each other without contradiction.

[0099] The above only describes the preferred embodiments of the application and is not intended to limit the application. Various modifications and changes can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A memory system, characterized by, The memory system comprises: a memory device configured to store data; a controller coupled to the memory device; the controller is configured to: perform a first training operation on a data sampling delay value based on first training data, to determine a first delay value range that makes the memory device correctly read and write the first training data; perform a second training operation on the data sampling delay value based on second training data, to determine a second delay value range that makes the memory device correctly read and write the second training data; wherein the data values of any two adjacent transmission periods in the first training data are opposite, the data values of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data; determine an actual data sampling delay value based on the first delay value range and the second delay value range.

2. The memory system of claim 1, wherein, The first training data and the second training data correspond to each bit value opposite.

3. The memory system of claim 1, wherein, The controller is specifically configured to: write training data into the memory device and read corresponding data from the memory device based on different data sampling delay values, to determine a delay value range of the data sampling delay value that makes the read data same as the training data; wherein the training data includes the first training data, and the delay value range includes the first delay value range; or, the training data includes the second training data, and the delay value range includes the second delay value range.

4. The memory system of claim 3, wherein, The controller is specifically configured to: write the training data into the memory device and read corresponding data from the memory device based on a plurality of data sampling delay values that are sequentially increased; determine a first boundary value of the delay value range as a first data sampling delay value that makes the read data same as the training data; and determine a second boundary value of the delay value range as a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value; Or, write the training data into the memory device and read corresponding data from the memory device based on a plurality of data sampling delay values that are sequentially decreased; determine the second boundary value as a first data sampling delay value that makes the read data same as the training data; and determine the first boundary value as a first data sampling delay value that makes the read data different from the training data and less than the second boundary value.

5. The memory system of claim 1, wherein, The determination of the actual data sampling delay value based on the first delay value range and the second delay value range comprises: determining an intersection of the first delay value range and the second delay value range; determining the actual data sampling delay value based on the intersection.

6. The memory system of claim 5, wherein, The determination of the actual data sampling delay value based on the intersection comprises: determining one of a plurality of quartiles of the intersection as the actual data sampling delay value.

7. The memory system according to any one of claims 1 to 6, wherein The controller is coupled to the memory device through N data lines, where N is a positive integer; the first training data corresponds to N-bit data of each transmission cycle transmitted through N data lines respectively, and the second training data corresponds to N-bit data of each transmission cycle transmitted through N data lines respectively.

8. An operating method of a memory system, characterized by, The memory system comprises a memory device and a controller coupled to the memory device; the operation method comprises: performing a first training operation of data sampling delay value based on first training data, to determine a first delay value range that enables the memory device to correctly read and write the first training data; performing a second training operation of data sampling delay value based on second training data, to determine a second delay value range that enables the memory device to correctly read and write the second training data; wherein the data values of any two adjacent transmission cycles in the first training data are opposite, the data values of any two adjacent transmission cycles in the second training data are opposite, and the first training data is different from the second training data; determining an actual data sampling delay value based on the first delay value range and the second delay value range.

9. The method of claim 8, wherein, The first training data and the second training data correspond to each bit value opposite.

10. The operating method according to claim 8, characterized in that, The method specifically comprises: based on different data sampling delay values, write training data into the memory device, and read corresponding data from the memory device, to determine a delay value range of the data sampling delay value that enables the read data to be the same as the training data; wherein the training data comprises the first training data, and the delay value range comprises the first delay value range; or, the training data comprises the second training data, and the delay value range comprises the second delay value range.

11. The method of claim 10, wherein, The method specifically comprises: based on a plurality of data sampling delay values that are sequentially increased, write the training data into the memory device, and read corresponding data from the memory device; determine that the first data sampling delay value that enables the read data to be the same as the training data is a first boundary value of the delay value range; determine that the first data sampling delay value that enables the read data to be different from the training data and greater than the first boundary value is a second boundary value of the delay value range; or, based on a plurality of data sampling delay values that are sequentially decreased, write the training data into the memory device, and read corresponding data from the memory device; determine that the first data sampling delay value that enables the read data to be the same as the training data is the second boundary value; determine that the first data sampling delay value that enables the read data to be different from the training data and less than the second boundary value is the first boundary value.

12. The operating method according to claim 8, characterized in that, The determination of the actual data sampling delay value based on the first delay value range and the second delay value range comprises: determine the intersection of the first delay value range and the second delay value range; determine the actual data sampling delay value based on the intersection.

13. The method of operation of claim 12, wherein, The determination of the actual data sampling delay value based on the intersection comprises: determining one of the plurality of quartiles of the intersection as the actual data sampling delay value.

14. The method of operation according to any one of claims 8 to 13, characterized in that, The controller is coupled to the memory device through N data lines, where N is a positive integer; the first training data corresponds to N-bit data of each transmission period transmitted through N data lines respectively, and the second training data corresponds to N-bit data of each transmission period transmitted through N data lines respectively.

15. An electronic device, comprising: comprising: The memory system of any one of claims 1 to 7; A processor coupled to the memory system.

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