Storage system and read-write method thereof

Abstract

The invention discloses a storage system and a read-write method thereof, the storage system comprises a first CPU, a second CPU, a register and a memory, the first CPU is used for compiling and sending a read command queue with a plurality of read commands, and the second CPU is connected with the first CPU and is used for receiving, reading and writing the read commands in the read command queue; the register is connected with the second CPU and is used for storing the reading command; the memory is connected with the register, storage data are arranged in the memory, and the memory reads the storage data according to the reading command. According to the method, the two CPUs are arranged in the storage system to reduce repeated command sending, the execution smooth time of the storage system is prolonged, and then the overall performance of the storage system is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a storage system and a reading and writing method thereof. Background Art

[0002] With the development of information technology, especially the popularization of the Internet, the amount of data of various types has increased rapidly, and there is an urgent need for large-capacity, high-performance storage systems to effectively store and quickly access this data.

[0003] Traditional storage systems have only one CPU and can only send one command at a time and then wait for the result. When there are many commands, the waiting time will be long, which greatly affects the storage and reading and writing efficiency of data. Summary of the invention

[0004] The purpose of this application is to provide a storage system and a read-write method thereof, which reduces repeated command sending by setting two CPUs in the storage system, improves the execution smoothness time of the storage system, and thereby improves the overall performance of the storage system.

[0005] The present application discloses a storage system, which includes a first CPU, a second CPU, a register and a memory. The first CPU is used to write and send a read command queue having multiple read commands. The second CPU is connected to the first CPU and is used to receive and read and write the read commands in the read command queue; the register is connected to the second CPU and is used to store the read commands; the memory is connected to the register, and the memory is provided with storage data, and the storage data is read according to the read command.

[0006] Optionally, the second CPU is connected to the first CPU via multiple channels.

[0007] Optionally, the second CPU is connected to the first CPU via four channels and two chip enable pins.

[0008] The present application also discloses a storage system reading and writing method, which is used for the storage system as described above. The storage system reading and writing method comprises the steps of:

[0009] Writing a read command queue containing a plurality of read commands in the first CPU, and sending the read command queue to the second CPU;

[0010] The second CPU reads the read commands in the read command queue in sequence, and writes the read commands into the register of the memory;

[0011] The second CPU sends an address latch enable signal to the memory;

[0012] The control module of the memory reads the read command from the register, and reads the storage data from the storage module of the memory according to the read command;

[0013] The control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device; and

[0014] Repeat the following three steps: the second CPU sends an address latch enable signal to the memory, the control module of the memory reads the read command from the register and reads storage data from the storage module of the memory according to the read command, the control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device, until the control module of the memory reads all the read commands in the read command queue.

[0015] Optionally, in the step of writing a read command queue containing multiple read commands in the first CPU and sending the read command queue to the second CPU, the read command includes a read address, a read length and a read storage block number, the read address corresponds to the physical address of the stored data, the read length corresponds to the data length of the stored data, and the read storage block number corresponds to the storage block number where the stored data is located.

[0016] Optionally, in the step of the second CPU sequentially reading the read commands in the command queue and writing the read read commands into a register of the memory, the second CPU reads multiple read commands from the first CPU at one time.

[0017] Optionally, the second CPU is connected to the first CPU via a plurality of channels, and the second CPU reads a plurality of read commands from the first CPU at one time via the plurality of channels.

[0018] Optionally, after the second CPU reads multiple read commands in the command queue in sequence, it identifies the storage block numbers corresponding to the multiple read commands. When the same storage block number has more than two read commands, the second CPU merges the two or more read commands corresponding to the same storage block number and writes them to the register of the memory at the same time; the control module of the memory reads the merged read commands at one time.

[0019] Optionally, in the step where the control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device, the second CPU includes a read command parsing module, a data processing module and a result output module, the read command parsing module is used to parse the storage data, the data processing module processes the parsed storage data, and the result output module transmits the processed storage data to an external device.

[0020] Optionally, while the first CPU sends the read command queue to the second CPU, the second CPU reads the received read command and writes it into a register of a memory.

[0021] The beneficial effects of the present application are as follows: relative to the current solution of having only one CPU in a storage system, the present application sets two CPUs in the storage system, and the first CPU sends a command queue table of a certain depth, that is, a read command queue with multiple read commands, and the first CPU does not need to wait for the result, the second CPU can process the read and write according to the read command queue, and then the first CPU can query the completion result, so that when the first CPU sends the command queue table, the second CPU can process the command at the same time, and the two operations can be performed synchronously, thereby improving the concurrent processing capability and data throughput of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0023] Figure 1 is a schematic diagram of a storage system provided in an embodiment of the present application;

[0024] Figure 2 It is a flow chart of a reading and writing method of a storage system provided in an embodiment of the present application.

[0025] Among them, 10, storage system; 100, first CPU; 200, second CPU; 300, register; 400, memory. DETAILED DESCRIPTION

[0026] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0027] like Figure 1 As shown, an embodiment of the present application provides a storage system, wherein the storage system 10 includes a first CPU 100, a second CPU 200, a register 300 and a memory 400, wherein the first CPU 100 is used to write and send a read command queue having multiple read commands, and the second CPU 200 is connected to the first CPU 100, and is used to receive and read and write the read commands in the read command queue; the register 300 is connected to the second CPU 200, and is used to store the read commands; the memory 400 is connected to the register 300, and the memory 400 is provided with storage data, and the storage data is read according to the read command.

[0028] In the current storage system, since there is only one CPU, after the CPU sends a command to the memory, it needs to wait for the memory state to be completed before it can send the next command to write or read data, which makes the data storage and read-write efficiency low. Compared with the current solution with only one CPU in the storage system, the embodiment of the present application improves the traditional embedded storage system by setting two CPUs in the storage system 10, and the two CPUs are processed in parallel; the first CPU 100 sends a command queue table of a certain depth, that is, a read command queue with multiple read commands, and the first CPU 100 does not need to wait for the result, the second CPU 200 can process the read and write according to the read command queue, and then the first CPU 100 can query the completion result, so that when the first CPU 100 sends the command queue table, the second CPU 200 can process the command at the same time, and the two operations can be performed synchronously, thereby improving the concurrent processing capability and data throughput of the storage system, and achieving more efficient data transmission and processing, thereby improving the efficiency and accuracy of data processing.

[0029] The first CPU 100 and the second CPU 200 are used together as a system on chip (SOC) in the storage system 10. The memory 400 can be a NAND Flash or other types of memory. For the convenience of description, NAND Flash is used as the memory in the following description. The SOC is responsible for receiving data, organizing the data, and then sending it to the NAND Flash for storage.

[0030] Correspondingly, such as Figure 2As shown, the embodiment of the present application also discloses a storage system reading and writing method, which is used for the storage system 10 as described above, and the storage system reading and writing method comprises the steps of:

[0031] S1: Writing a read command queue containing a plurality of read commands in the first CPU, and sending the read command queue to the second CPU;

[0032] S2: the second CPU reads the read commands in the read command queue in sequence, and writes the read commands into the register of the memory;

[0033] S3: the second CPU sends an address latch enable signal to the memory;

[0034] S4: the control module of the memory reads the read command from the register, and reads the storage data from the storage module of the memory according to the read command;

[0035] S5: the control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device;

[0036] S6: Repeat the following three steps: the second CPU sends an address latch enable signal to the memory, the control module of the memory reads the read command from the register and reads storage data from the storage module of the memory according to the read command, the control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device, until the control module of the memory reads all the read commands in the read command queue.

[0037] The embodiment of the present application optimizes the reading technology of NAND Flash. By writing the read and write commands into the register first, and then replacing the address latch enable signal ALE before triggering, it is possible to trigger without resending all the execution commands, thereby reducing repeated command sending, reducing repeated command sending, improving the execution smoothness time of the system, and thus improving the overall performance of the system. Moreover, the embodiment of the present application also improves the traditional embedded storage system, adopting a dual CPU design, the first CPU sends a command queue table of a certain depth, without waiting for the result, the second CPU can process the read and write according to the command queue, and then the first CPU can query the completion result, so that when the first CPU sends the command list, the second CPU can process the command at the same time, and the two CPUs can be performed synchronously, improving the concurrent processing capability and data throughput of the system.

[0038] Among them, in step S1, the read command queue may contain 100 read commands, and each of the read commands includes a read address, a read length, and a read storage block number, wherein the read address corresponds to the physical address of the storage data, the read length corresponds to the data length of the storage data, and the read storage block number corresponds to the storage block number where the storage data is located. The specific location and specific size of the corresponding storage data can be identified through the read command.

[0039] Furthermore, in step S2, the second CPU reads multiple read commands from the first CPU at one time, that is, when the first CPU writes the read command queue, it does not need to wait until all the read commands are written before sending them to the second CPU, but sends the first written part of the read commands to the second CPU for reading and writing, while the first CPU still keeps writing the subsequent read commands. The first CPU alternates between writing and sending, so that the first CPU and the second CPU can run simultaneously, thereby speeding up the reading and writing efficiency of the system until the first CPU finishes writing the entire read command queue.

[0040] It should be noted that the number of read commands read by the second CPU from the first CPU each time may be the same or different, and the specific design can be made according to actual conditions.

[0041] Meanwhile, since the second CPU can read multiple read commands from the first CPU each time, specifically, the second CPU is connected to the first CPU via multiple channels, and the second CPU reads multiple read commands from the first CPU at one time via the multiple channels.

[0042] The second CPU is connected to the first CPU through multiple CHs (channels) and CEs (chip enable pins) to perform read operations to speed up command preparation and transmission and achieve high data throughput. As a specific example, the second CPU is connected to the first CPU through four channels and two chip enable pins (4CH, 2CE). For example, the first CPU sends CE0 of CH0, CE0 of CE1, CE0 of CE2, CE0 of CH2, CE0 of CH3, and then goes back to query the CH0-CE0 status to achieve multi-channel data transmission.

[0043] In addition, in step S2, the second CPU reads multiple read commands in the command queue in sequence, and then identifies the storage block numbers corresponding to the multiple read commands. When the same storage block number has more than two read commands, the second CPU merges the two or more read commands corresponding to the same storage block number and writes them into the register of the memory at the same time; the control module of the memory reads the merged read commands at one time.

[0044] In the embodiment of the present application, by optimizing the combination design of commands, when the second CPU reads sequentially, if the received read commands are based on the same Block, two or more read commands can be assembled into one command, and then processed once for reading, and these assembled read commands can be completed in just one time, thereby improving the efficiency of data processing, while also reducing the sending of repeated commands, and further improving the execution time of the system.

[0045] It can be understood that the second CPU merges two or more read commands corresponding to the same storage block number, and the second CPU may replace the position of the read command so that the two or more read commands corresponding to the same storage block number are moved to adjacent positions; for example, the storage block number corresponding to the first read command is 006, the storage block number corresponding to the second read command is 002, the storage block number corresponding to the third read command is 013, and the storage block number corresponding to the fourth read command is 006. When these four read commands are sent to the second CPU by the first CPU in the same batch, and the second CPU reads the fourth read command in sequence from the first read command to the fourth read command, the fourth read command is interchanged with the second read command, so that the first read command is the original fourth read command after the first read command. Since the first read command and the adjacent fourth read command are both based on the storage block number of 006, the second CPU puts these two read commands together and writes them into the register of the memory, so that the control module of the memory reads the merged first read command and the adjacent fourth read command at one time. Or the read lengths of the two or more read commands corresponding to the same storage block number can be further merged, or the mapping tables corresponding to the two commands can be merged, or other methods can be used to merge, which are not limited here.

[0046] The embodiment of the present application can significantly improve the efficiency and performance of data reading by optimizing the read command assembly and queue processing of NAND Flash. In particular, when processing big data, the design of the embodiment of the present application can reduce repeated command sending and reduce the execution time of the system, thereby improving the overall performance of the system. The embodiment of the present application optimizes the assembly of commands, first writes the read command to the register, and then replaces the address of the CLO and ROW of the NAND before triggering. There is no need to reassemble all the command operations, and then directly execute and trigger.

[0047] In step S5, the second CPU includes a read command parsing module, a data processing module and a result output module. The read command parsing module is used to parse the stored data, the data processing module processes the parsed stored data, and the result output module transmits the processed stored data to an external device, which may be a mobile phone, a tablet, a computer, etc.

[0048] In the embodiment of the present application, the corresponding stored data in a part of the read command list can be transmitted to the external device, so that the writing of the first CPU and the reading and transmission of the second CPU can be carried out simultaneously, further improving the data processing efficiency. Of course, in other embodiments, the second CPU can wait to read and process the entire read command list before transmitting the data to the external device.

[0049] It should be noted that the limitations on the various steps involved in this solution, without affecting the implementation of the specific solution, are not deemed to limit the order of the steps. The steps written in front can be executed first, or later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0050] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A storage system, characterized in that: include: A first CPU, configured to write and send a read command queue having a plurality of read commands; A second CPU, connected to the first CPU, for receiving and reading and writing read commands in the read command queue; a register, connected to the second CPU, and used to store the read command; as well as A memory is connected to the register, wherein the memory is provided with storage data, and the storage data is read according to the read command.

2. The storage system according to claim 1, characterized in that: The second CPU is connected to the first CPU via a plurality of channels.

3. The storage system according to claim 2, characterized in that: The second CPU is connected to the first CPU via four channels and two chip enable pins.

4. A storage system reading and writing method, used in the storage system according to any one of claims 1 to 3, characterized in that: The storage system reading and writing method comprises the steps of: Writing a read command queue containing a plurality of read commands in the first CPU, and sending the read command queue to the second CPU; The second CPU reads the read commands in the read command queue in sequence, and writes the read commands into the register of the memory; The second CPU sends an address latch enable signal to the memory; The control module of the memory reads the read command from the register, and reads the storage data from the storage module of the memory according to the read command; The control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to the external device; as well as Repeat the following three steps: the second CPU sends an address latch enable signal to the memory, the control module of the memory reads the read command from the register and reads storage data from the storage module of the memory according to the read command, the control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device, until the control module of the memory reads all the read commands in the read command queue.

5. The storage system reading and writing method according to claim 4, characterized in that: In the step of writing a read command queue containing multiple read commands in the first CPU and sending the read command queue to the second CPU, the read command includes a read address, a read length and a read storage block number, the read address corresponds to the physical address of the stored data, the read length corresponds to the data length of the stored data, and the read storage block number corresponds to the storage block number where the stored data is located.

6. The storage system reading and writing method according to claim 5, characterized in that: In the step of the second CPU sequentially reading the read commands in the command queue and writing the read read commands into the register of the memory, the second CPU reads a plurality of read commands from the first CPU at one time.

7. The storage system reading and writing method according to claim 6, characterized in that: The second CPU is connected to the first CPU via a plurality of channels, and the second CPU reads a plurality of read commands from the first CPU at one time via the plurality of channels.

8. The storage system reading and writing method according to claim 6, characterized in that: After the second CPU sequentially reads the multiple read commands in the command queue, it identifies the storage block numbers corresponding to the multiple read commands. When the same storage block number has more than two read commands, the second CPU merges the two or more read commands corresponding to the same storage block number and writes them into the register of the memory at the same time. The control module of the memory reads the merged read commands at one time.

9. The storage system reading and writing method according to claim 4, characterized in that: In the step in which the control module of the memory transmits the read storage data to the second CPU, and the second CPU processes the storage data and then transmits it to an external device, the second CPU includes a read command parsing module, a data processing module and a result output module, the read command parsing module is used to parse the storage data, the data processing module processes the parsed storage data, and the result output module transmits the processed storage data to the external device.

10. The storage system reading and writing method according to claim 4, characterized in that: While the first CPU sends the read command queue to the second CPU, the second CPU reads the received read command and writes it into a register of a memory.

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