Memory management method, memory storage device and memory control circuit unit

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: setting a timer after startup, wherein the timer corresponds to a first physical unit; executing a reading program on the first physical unit, and judging whether a data error condition is met or not; and marking the first physical unit as a bad physical unit when the data error condition is satisfied and the elapsed time represented by the timer is less than a time threshold. Therefore, bad physical units can be marked as early as possible.

Description

Technical Field

[0001] The present disclosure relates to a memory management method for marking bad physical units, a memory storage device, and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and laptops have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] During the long-term use of rewritable non-volatile memory modules, the reliability of the data stored in the blocks will gradually decrease. In particular, when the number of erases of certain blocks increases, the data in these blocks are susceptible to interference, resulting in an increase in the number of error bits. When the number of error bits in a block exceeds the fault tolerance, the block will be marked as a bad block (BadBlock) and will be stopped from use. In addition to bad blocks caused by degradation of service life, during the manufacturing process, due to process variations or other production problems, some blocks may have potential defects since leaving the factory, making them prone to errors under normal use. Early marking and management of these defective blocks are crucial to the reliability of rewritable non-volatile memory modules. Summary of the invention

[0004] The present disclosure provides a memory management method, a memory storage device, and a memory control circuit unit, which can mark physical units that are defective during production and can also avoid incorrectly marking physical units due to endurance failure.

[0005] The present disclosure provides a memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units. The memory management method includes: after powering on, setting a timer, wherein the timer corresponds to a first physical unit; executing a read program on the first physical unit, and determining whether a data error condition is satisfied; and when the data error condition is satisfied and the elapsed time indicated by the timer is less than a time threshold, marking the first physical unit as a bad physical unit.

[0006] In an embodiment of the present disclosure, the memory management method further includes: resetting the timer when starting up the computer.

[0007] In an embodiment of the present disclosure, the memory management method further includes: resetting the timer when the first physical unit is programmed.

[0008] In one embodiment of the present disclosure, the reading program includes a hard decoding program, and the hard decoding program is used to detect multiple error bits in the first physical unit. The step of determining whether the data error condition is met includes: if the number of error bits is greater than a threshold value, increasing an error count; and if the error count is greater than the threshold value, determining that the data error condition is met.

[0009] In one embodiment of the present disclosure, the step of determining whether the data error condition is met includes: when the hard decoding program fails, executing the soft decoding program and increasing the number of errors; if the number of errors is greater than a threshold, determining that the data error condition is met.

[0010] In an embodiment of the present disclosure, the above number threshold is greater than or equal to 2. The memory management method further includes: resetting the number of errors when starting up.

[0011] In one embodiment of the present disclosure, the memory management method includes: when the hard decoding procedure fails, executing the soft decoding procedure; and if the soft decoding procedure fails, executing cross-frame decoding. The above step of determining whether the data error condition is met is based on non-cross-frame error correction information.

[0012] From another perspective, an embodiment of the present invention provides a memory storage device, comprising: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module, comprising a plurality of physical units; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform a plurality of steps: after powering on, setting a timer, the timer corresponding to a first physical unit; executing a read procedure on the first physical unit, and determining whether a data error condition is satisfied; and when the data error condition is satisfied and the elapsed time indicated by the timer is less than a time threshold, marking the first physical unit as a bad physical unit.

[0013] From another perspective, an embodiment of the present invention proposes a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to a rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface. The memory management circuit is used to perform multiple steps: setting a timer after powering on, the timer corresponding to a first physical unit; executing a read program on the first physical unit and determining whether a data error condition is met; and marking the first physical unit as a bad physical unit when the data error condition is met and the elapsed time represented by the timer is less than a time threshold.

[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of a memory control circuit unit drawn according to an exemplary embodiment of the present invention;

[0020] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0021] Figure 7 is a flowchart of a memory management method according to an embodiment;

[0022] Figure 8 It is to draw a schematic diagram of the operation of a timer based on a situation;

[0023] Fig. 9 It is to draw a schematic diagram of the operation of the timer based on another situation;

[0024] Fig.10 is a flowchart of a memory management method according to an embodiment;

[0025] Fig.11 The present invention is a flowchart of a memory management method according to another embodiment. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0027] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples of the systems and methods in the patent claims of the present invention.

[0028] The terms “first,” “second,” etc. used herein do not particularly refer to an order or sequence, but are only used to distinguish elements or operations described with the same technical term.

[0029] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0030] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0031] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0032] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0033] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0034] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless network (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0035] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0036] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3, the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0037] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0038] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be arranged outside a chip including the memory control circuit unit 42.

[0039] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0040] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0041] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0042] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0043] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage cells that are erased. For example, the physical erase unit is a physical block.

[0044] Figure 5 is a schematic diagram of a memory control circuit unit drawn according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0045] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0046] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0047] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0048] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0049] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0050] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing the read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0051] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0052] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or an error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code. For example, the ECC circuit 54 may use various encoding / decoding algorithms such as low density parity check code (LDPC code), BCH code, Reed-solomon code (RS code), exclusive OR (XOR) code, etc. to encode and decode data.

[0053] The basic unit for the error checking and correction circuit 54 to perform encoding / decoding is a frame (also called a data frame). A frame may include multiple data bits. In an exemplary embodiment, a frame includes 256 bits. However, in another exemplary embodiment, a frame may also include more (e.g., 4K bytes) or fewer bits. The error checking and correction circuit 54 may perform single-frame encoding and decoding on the data in a single frame, and the error checking and correction circuit 54 may also perform cross-frame encoding and decoding on the data in multiple frames. When performing cross-frame encoding and decoding, one or more data bits are obtained from each frame, and encoding and decoding are performed after obtaining the data bits of multiple frames.

[0054] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0055] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5The memory management circuit 51 may include a flash memory management circuit.

[0056] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (C) in the rewritable nonvolatile memory module 43 into a storage area 601 , a spare area 602 , and a system area 603 .

[0057] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a virtual block may include one or more physical erase units.

[0058] In an exemplary embodiment, the physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g., from Figure 1 The free area 602 may store user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 may store valid data and invalid data. The physical units 610(A+1) to 610(B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the free area 602. In addition, the physical units in the free area 602 (or the physical units that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the free area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool.

[0059] In an exemplary embodiment, the memory management circuit 51 may configure the logical units 612(0)-612(D) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0060] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit includes valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0061] In an exemplary embodiment, the memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table (L2Ptable). When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0062] In an exemplary embodiment, the memory management circuit 51 may store a specific type of data in the system area 603. For example, the physical units 610 (B+1) to 610 (C) in the system area 603 may be dedicated to store data of higher importance and / or data that is not intended to be accessed or modified by the host system 11. For example, the data of higher importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logical-to-physical mapping table, a bad block management table, a wear leveling management table, a valid data management table, and / or other types of management data, and the present invention is not limited thereto. The logical-to-physical mapping table is used to record mapping information. This mapping information may reflect the mapping relationship between the logical unit and the physical unit. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling management table may be used to record information related to the wear status of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table may be used to record information related to the valid count of at least one physical unit in the rewritable non-volatile memory module 43 .

[0063] In an exemplary embodiment, the memory management circuit 51 may not map any logical unit to a physical unit in the system area 603. Thus, the data stored in the system area 603 may be prevented from being accessed or modified by the host system 11.

[0064] Due to process variation or other factors, some physical units are defective during production, which makes the data stored therein prone to errors. For example, QLC NAND flash memory modules are more likely to have such physical units than TLC flash memory modules. If a physical unit has a serious data error shortly after being programmed, it may be a physical unit that is defective during production, and such a physical unit should be marked as a bad physical unit. In contrast, if a serious data error occurs long after being programmed (for example, after a year), it may be due to endurance failure, which can be solved by refreshing the data in the physical unit. Generally speaking, if many error bits are found when reading a physical unit (which can be corrected by an error correction code), the physical unit will be refreshed first. However, this approach will lead to frequent refreshes when facing physical units that have errors during production, which will reduce the performance of the entire memory storage device 10 or even make it unusable. Therefore, a method is proposed below to mark these bad physical units in advance.

[0065] Figure 7 is a flow chart showing a memory management method according to an embodiment. Figure 7 Each step is executed by the memory management circuit 51, and will not be described in detail below. Figure 7 In step 701, a timer is set after the computer is turned on. The timer corresponds to a first physical unit. In this embodiment, each physical unit has a corresponding timer. The first physical unit is used as an example. The first physical unit is, for example, a physical unit in the storage area 601 or the system area 603. For example, the timer includes a timestamp, and the memory management circuit 51 manages a clock. The time elapsed can be calculated by subtracting the current clock from the timestamp. In other embodiments, the timer includes a counter. The memory management circuit 51 accumulates the counter at regular intervals, so the counter can be used to represent the time elapsed.

[0066] In step 702, a read procedure is performed on the first physical unit. In some embodiments, the read procedure may include a hard decoding procedure, in which a read voltage is set, and a read bit can be obtained according to whether the corresponding storage unit is turned on under this read voltage. Next, an error correction code decoding procedure is implemented on these read bits to correct the error bits therein. If the number of error bits is too large and exceeds the correction capability of the error correction code, it indicates that the hard decoding procedure has failed. In some embodiments, the read procedure may also include a soft decoding procedure, in which multiple read voltages are set, and a probability value can be calculated according to whether the corresponding storage unit is turned on under these read voltages. Next, an error correction code (for example, LDPC) decoding procedure is implemented on these probability values ​​to obtain the final read bits. If these read bits cannot pass the error correction code check, it indicates that the soft decoding procedure has failed. In some embodiments, the read procedure includes a hard decoding procedure and a soft decoding procedure, and the soft decoding procedure is performed when the hard decoding procedure fails.

[0067] In step 703, determine whether the data error condition is met. This data error condition can have multiple aspects. In one aspect, the data error condition is met if the above-mentioned hard decoding program fails. In another aspect, the data error condition is met if the number of error bits is greater than the number threshold during the hard decoding program. In another aspect, the data error condition is met if the above-mentioned soft decoding program fails. In some embodiments, when the above-mentioned aspects occur, an error count can be accumulated, and the data error condition is determined to be met only when the error count is greater than the one-time count threshold. In other words, when the data error condition is met, it means that a serious data error has occurred in the first physical unit. If the result of step 703 is yes, proceed to step 704, otherwise end this process.

[0068] In step 704, it is determined whether the elapsed time indicated by the timer corresponding to the first physical unit is less than a time threshold (e.g., 5 minutes). If the result of step 704 is yes, the first physical unit is marked as a bad physical unit in step 705, and the bad physical unit will no longer be used. If the result of step 704 is no, other procedures are performed in step 706, such as refreshing the first physical unit or not performing any processing on the first physical unit. In step 706, the first physical unit will not be marked as a bad physical unit, and the first physical unit will continue to be used.

[0069] Figure 8 is a schematic diagram showing the operation of the timer according to a scenario. Figure 8, the horizontal axis is time. At time point T1, when the first physical unit 810 is programmed, the timer 820 corresponding to the first physical unit 810 will be reset, for example, the timestamp is set to the current time, or the count value is reset to 0. At time point T2, the first physical unit 810 is executed with a read program and meets the data error condition. The dotted line 830 represents the above-mentioned time threshold, so the elapsed time (T2-T1) represented by the timer 820 is less than the time threshold. In such an example, the first physical unit 810 meets the data error condition shortly after being programmed, so the first physical unit 810 will be marked as a bad physical unit.

[0070] Fig. 9 is a schematic diagram showing the operation of the timer according to another scenario. Fig. 9 . At time point T1, when the first physical unit 810 is programmed, the timer 820 corresponding to the first physical unit 810 will be reset. However, the memory storage device 10 is then shut down, the timer 820 will not be continuously updated, and the system clock will also stop. At time point T2, the computer is turned on. At this time, the timer 820 can no longer represent how much time has passed since the first physical unit 810 was programmed. Therefore, in one embodiment, the timer 820 is also reset when the computer is turned on. At time point T3, the first physical unit 810 is executed with a read program and meets the data error condition. Similarly, the dotted line 830 represents a time threshold. In this example, the elapsed time (T3-T2) represented by the timer 820 is less than the time threshold, so the first physical unit 810 is also marked as a bad physical unit.

[0071] Fig.10 is a flow chart showing a memory management method according to an embodiment. Fig.10, in step 1001, a timer is set after power-on. In step 1002, a hard decoding program is executed on the first physical unit. In step 1003, it is determined whether the hard decoding program is passed, and if so, this process is terminated. If the hard decoding program fails, a soft decoding program is executed on the first physical unit in step 1004, and the first physical unit is refreshed. In step 1005, it is determined whether the soft decoding program is passed. When the soft decoding program fails, cross-frame decoding is performed in step 1006. For example, the hard decoding program and the soft decoding program use single-frame decoding, that is, the data bits used for decoding come from the same frame. However, the data bits used in cross-frame decoding come from different multiple frames. In some embodiments, the data bits required for single-frame decoding are stored in the same physical unit, and the data bits required for cross-frame decoding are stored in multiple physical units, which can be distributed in the same (or different) memory planes, the same (or different) memory dies and / or the same (or different) chip enable (CE) area. If the soft decoding program is passed, it is determined in step 1007 whether the elapsed time represented by the timer is less than the time threshold. If the result of step 1007 is no, then the process ends. If the result of step 1007 is yes, then the number of errors is increased (e.g., by 1) in step 1008. In step 1009, it is determined whether the number of errors is greater than a number threshold. If the result of step 1009 is yes, then the first physical unit is marked as a bad physical unit in step 1010. If the result of step 1009 is no, then the process ends. Fig.10 In the example of , the data error condition includes the hard decoding procedure failing, the soft decoding procedure passing, and the number of errors being greater than a number threshold.

[0072] exist Fig.10 In a variation of the embodiment, step 1007 may also be performed after step 1006 is performed. Therefore, when the soft decoding procedure fails, the first physical unit may also be marked as a bad physical unit. In such a variation, the data error condition includes the hard decoding procedure failing and the number of errors being greater than the number threshold.

[0073] Fig.11 is a flow chart showing a memory management method according to another embodiment. Fig.11, in step 1101, a timer is set after power-on. In step 1102, a hard decoding program is executed on the first physical unit. Next, steps 1103 and 1108 are executed in parallel. The hard decoding program can detect how many error bits there are. If the number of error bits is less than or equal to the correction upper limit of the error correction code, these error bits can be corrected. If the number of error bits is greater than the correction upper limit of the error correction code, for example, it cannot pass the verification in LDPC, then these error bits cannot be corrected. In step 1103, it is determined whether the number of error bits is too much (greater than a number threshold). This number threshold can be greater than, equal to, or less than the correction upper limit of the error correction code. If the result of step 1103 is yes, in step 1104, it is determined whether the elapsed time represented by the timer is less than the time threshold. If the result of step 1104 is yes, the number of errors is increased in step 1105. Next, in step 1106, it is determined whether the number of errors is greater than the number threshold. If the result of step 1106 is yes, in step 1107, the first physical unit is marked as a bad physical unit. On the other hand, it is determined in step 1108 whether the hard decoding procedure has passed. If not, it proceeds to step 1109 to execute the soft decoding procedure. It is determined in step 1110 whether the soft decoding procedure has passed. If not, it executes cross-frame decoding in step 1111. Fig.11 In the embodiment of the present invention, the data error condition includes the number of error bits being greater than a number threshold and the number of errors being greater than a number threshold.

[0074] In some embodiments, the number threshold used in step 1009 and step 1106 is greater than or equal to 2, in order to avoid mistakenly marking an available physical unit as a bad physical unit. Fig. 9 Since the timer 820 is reset at startup, if the hard decoding program fails within the time threshold, it will be marked as a bad physical unit. The physical unit with durability failure will be marked as a bad physical unit, but such a physical unit can continue to be used as long as it is refreshed. Therefore, the number threshold is set to be greater than or equal to 2. Even if the hard decoding program fails due to durability failure, there is an additional opportunity to continue to use it. Through the above means, the situation of incorrect marking can be reduced.

[0075] In some embodiments, at power-on ( Fig. 9 At time point T2), the number of errors used in step 1009 and step 1106 will also be reset (for example, set to 0), and the number of errors will be recalculated after restarting the computer.

[0076] Please refer to Figure 7In some embodiments, step 703 of determining whether the data error condition is satisfied is based on non-RAID ECC parity information. In this embodiment, the non-RAID ECC parity information includes information such as the hard decoding program, the number of error bits, the number of errors, the time after being programmed, or the time after being powered on.

[0077] Through the above technical means, physical units that are defective during production can be detected and marked as bad physical units in real time, so as to avoid the continuous refresh of these physical units affecting system performance. The above approach can also avoid marking physical units with durability defects as bad physical units, thereby extending the service life of the memory.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory management method includes: After powering on, setting a timer, wherein the timer corresponds to a first physical unit among the plurality of physical units; executing a read procedure on the first physical unit and determining whether a data error condition is satisfied; and When the data error condition is met and the elapsed time indicated by the timer is less than a time threshold, the first physical unit is marked as a bad physical unit.

2. The memory management method according to claim 1, characterized in that: Also includes: At power-up, the timer is reset.

3. The memory management method according to claim 1, characterized in that: Also includes: When the first physical unit is programmed, the timer is reset.

4. The memory management method according to claim 1, characterized in that: The reading program includes a hard decoding program, and the hard decoding program is used to detect multiple error bits in the first physical unit. The step of determining whether the data error condition is met includes: If the number of the plurality of error bits is greater than the number threshold, increase the number of errors; and If the number of errors is greater than the number threshold, it is determined that the data error condition is met.

5. The memory management method according to claim 1, characterized in that: The reading program includes a hard decoding program, and the step of determining whether the data error condition is met includes: When the hard decoding procedure fails, a soft decoding procedure is executed and the number of errors is increased; If the number of errors is greater than the number threshold, it is determined that the data error condition is met.

6. The memory management method according to claim 4 or 5, characterized in that: Wherein the number threshold is greater than or equal to 2, the memory management method further includes: The error count is reset at power-up.

7. The memory management method according to claim 1, characterized in that: The reading program includes a hard decoding program, and the memory management method includes: When the hard decoding procedure fails, executing a soft decoding procedure; and If the soft decoding procedure fails, cross-frame decoding is performed. The step of determining whether the data error condition is satisfied is based on non-cross-frame error correction information.

8. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; as well as a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, The memory control circuit unit is used to perform multiple steps: After powering on, setting a timer, wherein the timer corresponds to a first physical unit among the plurality of physical units; executing a read procedure on the first physical unit and determining whether a data error condition is satisfied; as well as When the data error condition is met and the elapsed time indicated by the timer is less than a time threshold, the first physical unit is marked as a bad physical unit.

9. The memory storage device according to claim 8, characterized in that: The multiple steps also include: At power-up, the timer is reset.

10. The memory storage device according to claim 8, characterized in that The multiple steps also include: When the first physical unit is programmed, the timer is reset.

11. The memory storage device according to claim 8, characterized in that The reading program includes a hard decoding program, and the hard decoding program is used to detect multiple error bits in the first physical unit. The step of determining whether the data error condition is met includes: If the number of the plurality of error bits is greater than the number threshold, increase the number of errors; and If the number of errors is greater than the number threshold, it is determined that the data error condition is met.

12. The memory storage device according to claim 8, characterized in that The reading program includes a hard decoding program, and the step of determining whether the data error condition is met includes: When the hard decoding procedure fails, a soft decoding procedure is executed and the number of errors is increased; If the number of errors is greater than the number threshold, it is determined that the data error condition is met.

13. The memory storage device according to claim 11 or 12, characterized in that: Wherein the number threshold is greater than or equal to 2, the multiple steps further include: The error count is reset at power-up.

14. The memory storage device according to claim 8, characterized in that The step of determining whether the data error condition is satisfied is based on non-cross-frame error correction information.

15. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory control circuit unit includes: A host interface for coupling to a host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit is coupled to the host interface and the memory interface, The memory management circuit is used to perform multiple steps: After powering on, setting a timer, wherein the timer corresponds to a first physical unit among the plurality of physical units; executing a read procedure on the first physical unit and determining whether a data error condition is satisfied; and When the data error condition is met and the elapsed time indicated by the timer is less than a time threshold, the first physical unit is marked as a bad physical unit.

16. The memory control circuit unit according to claim 15, characterized in that: The multiple steps also include: At power-up, the timer is reset.

17. The memory control circuit unit according to claim 15, characterized in that: The multiple steps also include: When the first physical unit is programmed, the timer is reset.

18. The memory control circuit unit according to claim 15, characterized in that: The reading program includes a hard decoding program, and the hard decoding program is used to detect multiple error bits in the first physical unit. The step of determining whether the data error condition is met includes: If the number of the plurality of error bits is greater than a critical number, increase the number of errors; and If the number of errors is greater than the critical number, it is determined that the data error condition is met.

19. The memory control circuit unit according to claim 15, characterized in that: The reading program includes a hard decoding program, and the step of determining whether the data error condition is met includes: When the hard decoding procedure fails, a soft decoding procedure is executed and the number of errors is increased; If the number of errors is greater than the critical number, it is determined that the data error condition is met.

20. The memory control circuit unit according to claim 18 or 19, characterized in that: Wherein the critical value of times is greater than or equal to 2, the multiple steps further include: The error count is reset at power-up.

21. The memory control circuit unit according to claim 15, characterized in that: The step of determining whether the data error condition is satisfied is based on non-cross-frame error correction information.

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