A method for data caching and sending based on a multi-level FIFO

Abstract

The present invention discloses a method for data caching and sending based on a multi-level FIFO, belonging to the technical field of data caching, including: after writing data into a first-level FIFO, reducing the data transmission speed through a second-level FIFO, and then the read control logic of the second-level FIFO takes the data with timing as a part of the control condition and divides the data into four parts with similar quantities according to the read-out order. The first part is written into a first three-level FIFO. After receiving the data, the first three-level FIFO reads the data into a four-level FIFO, writes the second part of the data into a second three-level FIFO, and writes the third part of the data into the first three-level FIFO until the first part of the data is completely written into the four-level FIFO. When the four-level FIFO completely reads out the first part of the data, the subsequent data is written in sequence. The present invention uses the cache control of a multi-level FIFO, saving the space for deploying an external storage chip and reducing the complexity of the control system.

Description

Technical Field

[0001] The present invention belongs to the technical field of data caching, and particularly relates to a method for data caching and sending based on a multi-level FIFO. Background Art

[0002] A Field Programmable Gate Array (FPGA) is a programmable signal processing device with rich logic resources. Users can independently change the configuration information according to design requirements to define functions. The FIFO (First Input First Output) memory is one of the commonly used units in chip design and is widely used in system fields such as data reception, sending, and processing due to its first-in-first-out functional characteristics. Nowadays, FIFO is used as the main standard storage module in more and more FPGA design projects.

[0003] With the continuous increase of engineering requirements and the continuous expansion of the scale of engineering design, more and more digital chips need to be integrated in the control board. Especially in the space-based platform, space-based devices often need to complete the integration and wiring of multiple boards in a limited space, which often limits the number of chips. In the existing data caching technology, especially in the extreme case of fast clock domain crossing slow clock domain and parallel data signal conversion to serial data signal, a relatively reliable solution is to integrate DDR3 chips, realize data caching by calling large-capacity DDR3 chips, and finally design appropriate control logic to realize data sending. However, usually, more than one functional module of the DDR3 chip needs to be called, and increasing the number of space-grade DDR3 chips will bring additional space occupation and wiring pressure. Therefore, there is an urgent need for a technical route to realize data caching and sending in extreme cases such as space limitation by making full use of the resources of the digital chip itself, so as to provide a new solution for the design of the space-based device platform. Summary of the Invention

[0004] Aiming at the deficiencies of the existing data caching and sending methods in the application of the space-based platform, the present invention provides a method for data caching and sending based on a multi-level FIFO. This method gives full play to the characteristics of rich logic resources, high speed and high performance of the FPGA, and makes full use of the resources of the FPGA chip itself to replace the use of additional storage chips, so as to achieve the effect of reducing space occupation and wiring pressure in the space-based platform.

[0005] The technical solution adopted by the present invention is as follows: A method for data caching and sending based on a multi-level FIFO, comprising:

[0006] Step 1: The first-level FIFO obtains data.

[0007] Step 2: The secondary FIFO reads data from the primary FIFO according to the empty state of the primary FIFO and realizes the decelerated output of the data.

[0008] Step 3: The read control logic of the secondary FIFO divides the data into approximately four equal parts. The first part of the data is used to write to the first tertiary FIFO, and the second part of the data is used to write to the second tertiary FIFO. During this process, the decelerated output of the data is realized; Step 4: After the first tertiary FIFO writes the first part of the data, the write control logic of the quaternary FIFO writes the first part of the data by judging the empty state of the first tertiary FIFO. During this process, the second tertiary FIFO writes the second part of the data through the empty state of the secondary FIFO. While the first tertiary FIFO reads out the first part of the data, it writes the third part of the data according to the empty state of the secondary FIFO until the third part of the data is completely written into the first tertiary FIFO and the first part of the data is completely written into the quaternary FIFO.

[0009] Step 5: After the remote read control logic completely reads out the first part of the data, the quaternary FIFO writes the second part of the data through the empty state of the second tertiary FIFO. After the data is read out, the second tertiary FIFO writes the fourth part of the data from the secondary FIFO through its own empty state.

[0010] Step 6: After the remote read control logic completely reads out the second part of the data, the quaternary FIFO writes the third and fourth parts of the data in sequence through the empty state of the second tertiary FIFO and is read out by the remote control logic.

[0011] Thus, the caching and sending of the data are completed.

[0012] The advantages and beneficial effects of the present invention compared with the prior art are as follows:

[0013] In the design of the present invention, in the limited space of the space-based platform, the advantage of rich FPGA logic resources can be fully utilized, the use of storage chips can be reduced, the space occupation can be reduced, and the wiring pressure can be relieved.

[0014] The design of the present invention realizes the multi-level caching and transmission of data through multiple FIFOs. The connection method is simple, and the number of FIFOs used and the connection method can be flexibly adjusted according to actual situations such as timing requirements or data volume, thus broadening the application scenarios.

[0015] The design of the present invention replaces the control module of DDR3 with the read and write control of the FIFO module, reducing the complexity of the control logic.

[0016] The input and output interfaces of the design of the present invention are standard FIFO read and write interfaces, and the operation is simple.

[0017] In a multi-system integrated circuit environment, the present invention uses a multi-level FIFO cache control, saving the space for deploying external storage chips, reducing the complexity of the control system, with a simple data flow direction, facilitating further expansion, and being flexibly configurable according to the requirements of data volume and timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of a method for data caching and sending based on a multi-level FIFO according to the present invention;

[0019] Figure 2 It is a schematic flow chart of a method for data caching and sending based on a multi-level FIFO according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments. It should be understood that the specific embodiments described below are only used to explain the present invention and do not limit the present invention. Each technical feature involved in the embodiments can be combined as long as they do not conflict with each other.

[0021] According to an embodiment of the present invention, there is provided a method for data caching and sending based on a multi-level FIFO, the structural block diagram of which is as Figure 1 shown, and the flow chart is as Figure 2 shown. In Figure 1 and Figure 2 , FIFO1 refers to the first-level FIFO, FIFO2 refers to the second-level FIFO, FIFO3.1 refers to the first third-level FIFO, FIFO3.2 refers to the second third-level FIFO, and FIFO4 refers to the fourth-level FIFO. The first level, second level, third level, and fourth level refer to setting multiple FIFOs in the FIFO structure.

[0022] Step 1: The first-level FIFO acquires data, which is 836,000 bytes in total in one example, and writes it through the near-end write control logic.

[0023] Step 2: The second-level FIFO reads data from the first-level FIFO according to the empty state of the first-level FIFO and realizes the decelerated output of the data; in Figure 1 , the empty state is shown as empty1; in the decelerated output, the read speed of the second-level FIFO is reduced to 64% of the write speed.

[0024] Step 3: The read control logic of the secondary FIFO divides the data into four approximately equal parts. The first part of the data is used to write to the first tertiary FIFO, and the second part of the data is used to write to the second tertiary FIFO. During this process, the data is output at a reduced speed. During the reduced-speed output, the read speed of the tertiary FIFO is reduced to 62.5% of the write speed. Among the four parts of the data, the part with the least amount of data is 70.3% of the part with the most data. In one example, the first two parts of the data are both 100,000, the third part of the data is 90,000, and the fourth part of the data is 128,000. In fact, as long as it is within the allowable data volume range in the FIFO itself settings and can satisfy the temporary storage of the four parts of the data without causing any FIFO to overflow, the specific data volume can be flexibly controlled.

[0025] Step 4: After the first tertiary FIFO writes the first part of the data, the write control logic of the quaternary FIFO writes the first part of the data by judging the empty state of the first tertiary FIFO ( Figure 1 shown as empty3.1 in it). During this process, the second tertiary FIFO writes the second part of the data through the empty state of the secondary FIFO ( Figure 1 shown as empty2 in it). While the first tertiary FIFO reads out the first part of the data, it writes the third part of the data according to the empty state of the secondary FIFO until the third part of the data is completely written into the first tertiary FIFO and the first part of the data is completely written into the quaternary FIFO. Writing by judging the empty state of the first tertiary FIFO means that after the empty state of the first tertiary FIFO is not empty, the write enable of the quaternary FIFO takes effect and starts to receive data from the first tertiary FIFO.

[0026] In Step 4, the quaternary FIFO writes the first part of the data using the first tertiary FIFO, the second tertiary FIFO writes the second part of the data, and reads the first part of the data from the first tertiary FIFO, all at the same time. This can ensure that the first tertiary FIFO does not reach a full state when writing the third part of the data.

[0027] The first part of the data is cached in the quaternary FIFO and read out through the remote read control logic. When the quaternary FIFO has not completely read out the first part of the data, the second part of the data is cached in the second tertiary FIFO, the third part of the data is cached in the first tertiary FIFO, and the fourth part of the data is cached in the secondary FIFO.

[0028] Step 5: After the remote read control logic completely reads out the first part of the data, the quaternary FIFO writes the second part of the data through the empty state of the second tertiary FIFO. After the data is read out, the second tertiary FIFO writes the fourth part of the data from the secondary FIFO through its own empty state.

[0029] Step 6: After the remote read control logic completely reads out the second piece of data, the four-level FIFO writes the third and fourth pieces of data into the third-level FIFO in sequence according to the empty state of the second and third-level FIFO, and the data is read out by the remote control logic.

[0030] That is, when the second piece of data is completely written into the four-level FIFO, the second three-level FIFO writes the fourth piece of data from the two-level FIFO. After each complete readout of a piece of data from the four-level FIFO, the next piece of data is written into the three-level FIFO in sequence, and so on. Thus, the data caching and sending are completed.

[0031] Among them, the remote read control logic fully utilizes the blanking time to read out the data from the four-level FIFO in sequence. The remote read logic performs read operations according to the empty state of the four-level FIFO.

[0032] The so-called proximal end refers to the control logic close to the one-level FIFO, and the distal end refers to the control logic close to the four-level FIFO.

[0033] As Figure 2 shown, in this embodiment, the data needs to cross from the fast clock domain to the slow clock domain and be converted from a parallel signal to a serial signal. First, the one-level FIFO writes a 16-bit data signal ( Figure 2 shown as data (16 bits) in Figure 2 ) at a clock frequency of 125 MHz ( Figure 2 shown as wr_clk (125 MHz) in Figure 2 ), and reads out a 32-bit data signal ( Figure 2 shown as data (32 bits) in Figure 2 ) at a clock frequency of 125 MHz ( Figure 2 shown as rd_clk (125 MHz) in Figure 2 ). The two-level FIFO serves as a transition to implement partial cross-clock domain function. The data is input at a clock frequency of 125 MHz ( Figure 2 shown as wr_clk (125 MHz) in Figure 2 ) and outputs a 16-bit data signal ( Figure 2Shown in the middle is a 16-bit data signal of rd_clk (50MHz)) Figure 2 Shown in the middle is the data (16 bits)). Similarly for the second and third stage FIFO (FIFO3.2). At the same time, the fourth stage FIFO makes a conditional judgment based on the empty state of FIFO3.1 and writes the 1st to 200,000th bytes from FIFO3.1. The fourth stage FIFO (FIFO4) is input at a clock frequency of 50MHz Figure 2 Shown in the middle is wr_clk (50MHz)) and is output at a clock frequency of 50MHz Figure 2 Shown in the middle is a 16-bit data signal of rd_clk (50MHz)) Figure 2 Shown in the middle is the data (16 bits)). All the data output by the fourth stage FIFO (FIFO4) is processed by the remote read control logic. After the second stage FIFO sends the four hundred thousandth byte to FIFO3.2, it continues to send the 400,001st to 580,000th bytes to FIFO3.1, and the last 256,000 bytes are temporarily cached in the second stage FIFO. When data is written into the fourth stage FIFO, the remote read control logic reads the data from the fourth stage FIFO and performs parallel-to-serial conversion. After the first two hundred thousand bytes are completely read out by the remote control logic, the fourth stage FIFO makes a logical judgment through the empty state of FIFO3.2, writes the 200,001st to 400,000th bytes, and continues to be read by the remote control logic. And FIFO3.2 also makes a conditional judgment using its own empty state to read the last 256,000 bytes from the second stage FIFO. After each complete data is read out by the fourth stage FIFO, it sequentially receives subsequent data from the third stage FIFO, and the remote read control outputs and performs parallel-to-serial conversion, and finally outputs a 1-bit data signal externally.

[0034] The above description is only an embodiment of the present application and is not used to limit the present application. Those skilled in the art should clearly recognize that the present application can have various extensions and changes, and different implementation manners can be used within the scope of the present invention according to the actual application situation to achieve the described functions. These extensions, changes, and other implementation manners all fall within the scope of this disclosure.

Claims

1. A method for data caching and sending based on a multi-level FIFO, characterized in that, The method includes the following steps: Step 1: The primary FIFO acquires data; Step 2: The secondary FIFO reads data from the primary FIFO according to the empty status of the primary FIFO and realizes the decelerated output of the data; Step 3: The read control logic of the secondary FIFO divides the data into four approximately equal parts. The first part of the data is used to write into the first tertiary FIFO, and the second part of the data is used to write into the second tertiary FIFO. In this process, the decelerated output of the data is realized. Among the four parts of data, the third part of the data is less than the first part and the second part respectively, and the fourth part of the data is less than the third part. The data volume of the part with the least data is 70.3% of the part with the most data; Step 4: After the first tertiary FIFO writes the first part of the data, the write control logic of the quaternary FIFO writes the first part of the data by judging the empty status of the first tertiary FIFO. In this process, the second tertiary FIFO writes the second part of the data through the empty status of the secondary FIFO. While the first tertiary FIFO reads out the first part of the data, it writes the third part of the data according to the empty status of the secondary FIFO until the third part of the data is completely written into the first tertiary FIFO and the first part of the data is completely written into the quaternary FIFO; Step 5: After the remote read control logic completely reads out the first part of the data, the quaternary FIFO writes the second part of the data through the empty status of the second tertiary FIFO. After the data is read out, the second tertiary FIFO writes the fourth part of the data from the secondary FIFO through its own empty status; Step 6: After the remote read control logic completely reads out the second part of the data, the quaternary FIFO writes the third and fourth parts of the data in sequence through the empty status of the second tertiary FIFO and is read out by the remote control logic; Thus, the caching and sending of the data are completed.

2. The method for data caching and sending based on a multi-level FIFO according to claim 1, wherein Step 1 includes: The primary FIFO writes data through the proximal write control logic.

3. The method for data caching and sending based on a multi-level FIFO according to claim 2, characterized in that, The proximal refers to being close to the primary FIFO, and the remote refers to being close to the quaternary FIFO.

4. A method for data caching and sending based on a multi-level FIFO, as claimed in claim 1, wherein Step 2 includes: The deceleration ratio is that the read speed of the secondary FIFO is reduced to 64% of the write speed.

5. The method for data caching and sending based on a multi-level FIFO according to claim 1, characterized in that In Step 4, the quaternary FIFO writing the first part of the data by the first tertiary FIFO, the second tertiary FIFO writing the second part of the data, and reading the first part of the data from the first tertiary FIFO are carried out simultaneously.

6. The method for data caching and sending based on a multi-level FIFO according to claim 1, wherein After Step 4, the first part of the data is cached in the quaternary FIFO and read out by the remote read control logic, the second part of the data is cached in the second tertiary FIFO, the third part of the data is cached in the first tertiary FIFO, and the fourth part of the data is cached in the secondary FIFO.

7. A method for data caching and sending based on a multi-level FIFO, characterized in that, The remote read control logic reads out the data from the quaternary FIFO in sequence using the blanking time.

8. A method for data caching and sending based on a multi-level FIFO, characterized in that, In the processing from Step 1 to Step 6, the data crosses from the fast clock domain to the slow clock domain.

9. A method for data caching and sending based on a multi-level FIFO, as claimed in claim 8, wherein The secondary FIFO inputs at a clock frequency of 125 MHz and outputs at a clock frequency of 80 MHz. The first tertiary FIFO and the second tertiary FIFO input at a clock frequency of 80 MHz and output at a clock frequency of 50 MHz. The quaternary FIFO inputs at a clock frequency of 50 MHz and outputs at a clock frequency of 50 MHz.

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