Method and system for anti-radiation refreshing of internal program of FPGA (Field Programmable Gate Array) chip
By introducing radiation detectors and microprocessors into the FPGA chips of PET/CT equipment, refreshing and repairing the internal programs of the FPGA chips is solved, and the performance degradation of FPGA chips in the radiation environment is improved, reliability and service life are improved, while reducing costs and structural requirements.
Patent Information
- Application Number
- CN202411962421.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-06
AI Technical Summary
The performance of FPGA chips in PET/CT devices deteriorates or is damaged in the radiation environment, resulting in reliability and service life problems. The prior art mainly relies on expensive space-level FPGAs or shielding structures that increase the weight of the circuit board.
A method of refreshing the internal program of the FPGA chip against radiation is adopted. By setting a radiation detector and microprocessor on the printed circuit board, reading the radiation dose of the FPGA chip, comparing the pre-stored verification code, selecting the correct FPGA program to write to the chip, and realizing program refresh and repair.
It effectively enhances the reliability and service life of FPGA chips in radiation environments, avoids the disadvantages of expensive space-level FPGAs and increasing the weight of circuit boards, has low design cost and low requirements for equipment structure.
Smart Images
Figure CN119938093A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of medical device nuclear medicine technology, and in particular to a method and system for anti-radiation refreshing of internal programs of FPGA chips. Background Art
[0002] With the continuous development of medical technology, PET / CT is increasingly used in clinical diagnosis. The FPGA (Field Programmable Gate Array) in PET / CT equipment needs to work in a radiation environment for a long time, which will cause its performance to degrade or even be damaged. Therefore, it is of great significance to study how to enhance the reliability and service life of FPGA in a radiation environment. As an important component of the PET / CT system, how to improve the reliability and service life of FPGA in a radiation environment has become an urgent problem to be solved.
[0003] Current PET / CT devices either do not take any measures to address this problem, or mainly adopt shielding structures around FPGA chips, such as tungsten shells or lead shells, or use expensive space-grade FPGAs. The former increases the weight of the circuit board, making installation and maintenance more difficult and placing higher requirements on the structure and load-bearing design of the equipment. The latter greatly increases the production and maintenance costs of the product. Summary of the invention
[0004] Technical issues to be solved
[0005] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a method and system for refreshing the internal program of an FPGA chip with radiation resistance, which solves the technical problem of how to enhance the reliability and service life of the FPGA chip in a radiation environment.
[0006] Technical Solution
[0007] In order to achieve the above object, the main technical solutions adopted by the present invention include:
[0008] In a first aspect, the present invention provides a method for refreshing the internal program of an FPGA chip with radiation resistance, which is used in a system for refreshing the internal program of an FPGA chip with radiation resistance, the system comprising: a printed circuit board; an FPGA chip, which is arranged above the printed circuit board; a radiation detector, which is arranged below the printed circuit board and has a position corresponding to the FPGA chip; a microprocessor, which is connected to the FPGA chip and the radiation detector; the method comprises:
[0009] Read the radiation dose received by the FPGA chip according to a preset period;
[0010] When the radiation dose received by the FPGA chip is greater than a preset radiation value, the FPGA program pre-stored in the first flash memory and the second flash memory are read respectively, and the first check code and the second check code are calculated respectively;
[0011] Compare the pre-stored local verification code with the first verification code and the second verification code respectively;
[0012] The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip according to the comparison result.
[0013] Optionally, writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip according to the comparison result includes:
[0014] When the local check code is the same as the first check code and the second check code, writing the FPGA program stored in the first flash memory into the FPGA chip;
[0015] When the local verification code is only the same as the first verification code, writing the FPGA program stored in the first flash memory into the FPGA chip;
[0016] When the local verification code is identical to only the second verification code, writing the FPGA program stored in the second flash memory into the FPGA chip;
[0017] When the local verification code is different from the first verification code and the second verification code, the locally stored FPGA program is sent to the microprocessor, the microprocessor writes the FPGA program into the first flash memory and the second flash memory, and then writes the FPGA program into the FPGA chip by selecting the mapping interface.
[0018] Optionally, before writing the FPGA program into the FPGA chip by selecting the mapping interface, the method further includes:
[0019] Recalculate the first check code and the second check code;
[0020] Compare the pre-stored local verification code with the first verification code and the second verification code respectively;
[0021] The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip or reported as damaged according to the comparison result.
[0022] Optionally, writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip or reporting damage according to the comparison result includes:
[0023] When the local check code is the same as the first check code and the second check code, writing the FPGA program stored in the first flash memory into the FPGA chip;
[0024] When the local verification code is only the same as the first verification code, the FPGA program stored in the first flash memory is written into the FPGA chip, and a damage report is issued to the second flash memory;
[0025] When the local verification code is identical to the second verification code only, the FPGA program stored in the second flash memory is written into the FPGA chip, and a damage report is issued to the first flash memory;
[0026] When the local verification code is different from both the first verification code and the second verification code, a damage report is issued for the first flash memory and the second flash memory.
[0027] Optionally, the method further comprises:
[0028] When it is determined that the damaged first flash memory and / or the second flash memory has been replaced, respectively calculating a first check code and a second check code;
[0029] Compare the pre-stored local verification code with the first verification code and the second verification code respectively;
[0030] The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip according to the comparison result.
[0031] Optionally, the preset period is 1 hour.
[0032] Optionally, the preset radiation value is 500 mSv / day or 12000 mSv / 30 days.
[0033] In a second aspect, the present invention provides a radiation-resistant system for refreshing the internal program of an FPGA chip, using the method described in any of the above technical solutions, the system comprising:
[0034] Printed circuit boards;
[0035] An FPGA chip is disposed above the printed circuit board;
[0036] A radiation detector is disposed below the printed circuit board and is located corresponding to the FPGA chip;
[0037] A microprocessor is connected to the FPGA chip and the radiation detector.
[0038] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements a method for refreshing an internal program of an FPGA chip for radiation resistance as described in any one of the first aspects above.
[0039] In a fourth aspect, the present invention provides a storage device including a storage medium and a processor, wherein the storage medium stores a computer program, and when the program is executed by the processor, the method of refreshing the internal program of an FPGA chip with radiation resistance as described in any one of the above-mentioned first aspects is implemented.
[0040] Beneficial Effects
[0041] The beneficial effects of the present invention are as follows: a radiation-resistant method for refreshing the internal program of an FPGA chip of the present invention adds a radiation detector to the PET / CT device to count the radiation dose received by the FPGA chip, thereby accurately evaluating the possibility of damage to the internal program of the FPGA chip, and then refreshing the internal program of the FPGA chip. Because the radiation damage to the FPGA chip is mostly caused by the inversion of bits of certain data, and the hardware itself is not damaged, therefore, rewriting the correct program file into the FPGA chip can repair the damage caused by the inversion of data bits. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 A schematic diagram of the installation position of the radiation detector provided in an embodiment of the present invention;
[0043] Figure 2 A system structure block diagram of a radiation-resistant refreshing FPGA chip internal program provided by another embodiment of the present invention.
[0044] Description of Reference Numerals
[0045] 1: FPGA chip; 2: Printed circuit board; 3: Radiation detector. DETAILED DESCRIPTION
[0046] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation modes in conjunction with the accompanying drawings.
[0047] The present application provides a design method that uses a non-space-grade field programmable gate array chip and does not require the installation of a shielding structure around the field programmable gate array chip, thereby achieving the purpose of enhancing the reliability and service life of the field programmable gate array chip in a radiation environment.
[0048] Compared with traditional methods, only a radiation detector is added, the design and production costs are relatively low, and the requirements for equipment structure and load-bearing design are not high. It is a method based on the statistics of radiation doses received by field programmable gate array chips to more specifically repair the internal programs of field programmable gate array chips. This method is easy to design and implement, low-cost, and can effectively warn and alarm hardware damage to field programmable gate array chips.
[0049] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0050] In a first aspect, this embodiment provides a method for refreshing the internal program of an FPGA chip with radiation resistance, which is used in a system for refreshing the internal program of an FPGA chip with radiation resistance, the system comprising: a printed circuit board; an FPGA chip, which is arranged above the printed circuit board; a radiation detector, which is arranged below the printed circuit board and has a position corresponding to the FPGA chip; a microprocessor, which is connected to the FPGA chip and the radiation detector; the method comprises:
[0051] S1, reading the radiation dose received by the FPGA chip according to a preset period.
[0052] S2, when the radiation dose received by the FPGA chip is greater than a preset radiation value, respectively read the FPGA program pre-stored in the first flash memory and the second flash memory, and respectively calculate the first check code and the second check code.
[0053] The microprocessor will periodically read the radiation dose received by the field programmable gate array chip through the RS485 protocol. When the radiation dose exceeds the preset threshold, the microprocessor will read the FPGA chip program stored in the first flash memory and the second flash memory respectively, and then calculate the check code respectively and send it to the console computer via Ethernet.
[0054] Before the device leaves the factory, the console computer sends the program file of the FPGA chip to the microprocessor via Ethernet, and the microprocessor writes the program file into the first flash memory and the second flash memory respectively.
[0055] Because the flash memory chip itself is also in the radiation environment of PET / CT, it will inevitably be affected by radiation, and the program file data stored in it is also likely to be damaged. If two flash memories are used, although they are both affected by radiation, the probability of both being damaged at the same time will be much lower.
[0056] S3, comparing the pre-stored local verification code with the first verification code and the second verification code respectively.
[0057] In actual use, the console computer is outside the barium room and is not exposed to radiation. Therefore, the data files and checksums stored on it are likely to be correct, ensuring the correctness of the comparison results.
[0058] S4, writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip according to the comparison result.
[0059] The radiation detector will be installed directly below the FPGA chip on the printed circuit board to calculate the radiation dose to the FPGA chip as accurately as possible. Figure 1 As shown, its purpose is to more accurately evaluate the possibility of program damage inside the field programmable gate array chip and refresh the program inside the field programmable gate array chip more specifically to achieve the goal of radiation resistance.
[0060] Because most of the radiation damage to the FPGA chip is caused by the reversal of certain data bits, and the hardware itself is not damaged, rewriting the correct program file into the FPGA chip can repair the damage caused by the data bit reversal.
[0061] Optionally, writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip according to the comparison result includes:
[0062] When the local check code is the same as the first check code and the second check code, writing the FPGA program stored in the first flash memory into the FPGA chip;
[0063] When the local verification code is only the same as the first verification code, writing the FPGA program stored in the first flash memory into the FPGA chip;
[0064] When the local verification code is identical to only the second verification code, writing the FPGA program stored in the second flash memory into the FPGA chip;
[0065] When the local verification code is different from the first verification code and the second verification code, the locally stored FPGA program is sent to the microprocessor, the microprocessor writes the FPGA program into the first flash memory and the second flash memory, and then writes the FPGA program into the FPGA chip by selecting the mapping interface.
[0066] Optionally, before writing the FPGA program into the FPGA chip by selecting the mapping interface, the method further includes:
[0067] Recalculate the first check code and the second check code;
[0068] Compare the pre-stored local verification code with the first verification code and the second verification code respectively;
[0069] The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip or reported as damaged according to the comparison result.
[0070] Optionally, writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip or reporting damage according to the comparison result includes:
[0071] When the local check code is the same as the first check code and the second check code, writing the FPGA program stored in the first flash memory into the FPGA chip;
[0072] When the local verification code is only the same as the first verification code, the FPGA program stored in the first flash memory is written into the FPGA chip, and a damage report is issued to the second flash memory;
[0073] When the local verification code is identical to the second verification code only, the FPGA program stored in the second flash memory is written into the FPGA chip, and a damage report is issued to the first flash memory;
[0074] When the local verification code is different from both the first verification code and the second verification code, a damage report is issued for the first flash memory and the second flash memory.
[0075] Optionally, the method further comprises:
[0076] When it is determined that the damaged first flash memory and / or the second flash memory has been replaced, respectively calculating a first check code and a second check code;
[0077] Compare the pre-stored local verification code with the first verification code and the second verification code respectively;
[0078] The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip according to the comparison result.
[0079] The console computer receives two CRC check codes sent by the microprocessor and compares them with the locally stored CRC check codes. If the local check code is equal to the first check code, the console computer selects an appropriate time to notify the microprocessor through Ethernet to update the program file in the first flash memory to the field programmable gate array chip through the selection mapping interface, and then resets the radiation detector to restart the calculation of the radiation dose. Otherwise, if the local check code is equal to the second check code, the console computer selects an appropriate time to notify the microprocessor through Ethernet to update the program file in the second flash memory to the field programmable gate array chip through the selection mapping interface. If the local C check code is inconsistent with the first check code and the second check code, it means that the program file data in the two flash memories are damaged. The console computer will send the locally stored FPGA chip program file to the microprocessor through Ethernet, and the microprocessor will write it into the first flash memory and the second flash memory respectively, and then the microprocessor will write the program file into the field programmable gate array chip through the selection mapping interface.
[0080] The most likely reason for the corruption of program file data in the flash memory is that some data bits are reversed in a radiation environment, that is, from 0 to 1, or from 1 to 0, not because the flash memory chip itself is damaged. Therefore, after rewriting the correct program file into the flash memory, the data file damage caused by bit reversal can be repaired.
[0081] Each time the microprocessor writes a program file to the flash memory, it will read the file data from the flash memory and perform a verification comparison. If it fails, the program file will be written to the flash memory again and read and verified again. If it still fails, it can be confirmed that the flash memory hardware is damaged. At this time, the microprocessor will send this information to the console computer and display an alarm on the user interface, prompting the user to contact the after-sales engineer for repair.
[0082] The basic idea of CRC is to use linear coding theory to generate a check code (CRC code) of r bits according to certain rules based on the k-bit binary code sequence to be transmitted at the sending end, and attach it to the end of the information to form a new binary code sequence of (k+r) bits, which is finally sent out. At the receiving end, the information code and the CRC code are checked according to the rules followed to determine whether there is an error in the transmission.
[0083] Optionally, the preset period is 1 hour.
[0084] Optionally, the preset radiation value is 500 mSv / day or 12000 mSv / 30 days.
[0085] Second, as Figure 1 and Figure 2 As shown, this embodiment provides a system for refreshing the internal program of an FPGA chip with radiation resistance, adopting the method for refreshing the internal program of an FPGA chip with radiation resistance described in the above embodiment, the system includes: a printed circuit board 2; an FPGA chip 1, arranged above the printed circuit board; a radiation detector 3, arranged below the printed circuit board 2, and the position corresponds to the FPGA chip 1; a microprocessor, connected to the FPGA chip and the radiation detector. According to the system for refreshing the internal program of an FPGA chip with radiation resistance provided by this embodiment, since it is used to implement the steps of the method for refreshing the internal program of an FPGA chip with radiation resistance provided by the embodiment of the first aspect of the present invention, the system for refreshing the internal program of an FPGA chip with radiation resistance has all the technical effects of the method for refreshing the internal program of an FPGA chip with radiation resistance, which will not be repeated here.
[0086] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements a method for refreshing an internal program of an FPGA chip for radiation resistance as described in any one of the first aspects above.
[0087] In a fourth aspect, an embodiment of the present invention provides a storage device, including a storage medium and a processor, wherein the storage medium stores a computer program, and when the program is executed by the processor, the method of refreshing the internal program of an FPGA chip with radiation resistance as described in any one of the above-mentioned first aspects is implemented.
[0088] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0089] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention should also include these modifications and variations.
[0090] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may alter, modify, replace and modify the above embodiments within the scope of the present invention.
Claims
1. A method for refreshing the internal program of an FPGA chip with radiation resistance, characterized in that: A system for refreshing the internal program of an FPGA chip with radiation resistance, the system comprising: a printed circuit board; an FPGA chip arranged above the printed circuit board; a radiation detector arranged below the printed circuit board, the position of which corresponds to the FPGA chip; a microprocessor connected to the FPGA chip and the radiation detector; the method comprising: Read the radiation dose received by the FPGA chip according to a preset period; When the radiation dose received by the FPGA chip is greater than a preset radiation value, the FPGA program pre-stored in the first flash memory and the second flash memory are read respectively, and the first check code and the second check code are calculated respectively; Compare the pre-stored local verification code with the first verification code and the second verification code respectively; The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip according to the comparison result.
2. The method for refreshing the internal program of an FPGA chip with radiation resistance according to claim 1, characterized in that: Writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip according to the comparison result includes: When the local check code is the same as the first check code and the second check code, writing the FPGA program stored in the first flash memory into the FPGA chip; When the local verification code is only the same as the first verification code, writing the FPGA program stored in the first flash memory into the FPGA chip; When the local verification code is identical to only the second verification code, writing the FPGA program stored in the second flash memory into the FPGA chip; When the local verification code is different from the first verification code and the second verification code, the locally stored FPGA program is sent to the microprocessor, the microprocessor writes the FPGA program into the first flash memory and the second flash memory, and then writes the FPGA program into the FPGA chip by selecting the mapping interface.
3. The method for refreshing the internal program of an FPGA chip with radiation resistance according to claim 2, characterized in that: Before writing the FPGA program into the FPGA chip by selecting the mapping interface, the method further includes: Recalculate the first check code and the second check code; Compare the pre-stored local verification code with the first verification code and the second verification code respectively; The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip or reported as damaged according to the comparison result.
4. The method for refreshing the internal program of an FPGA chip with radiation resistance according to claim 3, characterized in that: Writing the FPGA program stored in the first flash memory or the second flash memory into the FPGA chip or reporting damage according to the comparison result includes: When the local check code is the same as the first check code and the second check code, writing the FPGA program stored in the first flash memory into the FPGA chip; When the local verification code is only the same as the first verification code, the FPGA program stored in the first flash memory is written into the FPGA chip, and a damage report is issued to the second flash memory; When the local verification code is identical to the second verification code only, the FPGA program stored in the second flash memory is written into the FPGA chip, and a damage report is issued to the first flash memory; When the local verification code is different from both the first verification code and the second verification code, a damage report is issued for the first flash memory and the second flash memory.
5. The method for refreshing the internal program of an FPGA chip with radiation resistance according to claim 4, characterized in that: The method further comprises: When it is determined that the damaged first flash memory and / or the second flash memory has been replaced, respectively calculating a first check code and a second check code; Compare the pre-stored local verification code with the first verification code and the second verification code respectively; The FPGA program stored in the first flash memory or the second flash memory is written into the FPGA chip according to the comparison result.
6. The method for refreshing the internal program of an FPGA chip with radiation resistance according to claim 5, characterized in that: The preset period is 1 hour.
7. The method for refreshing the internal program of an FPGA chip with radiation resistance according to claim 6, characterized in that: The preset radiation value is 500 mSv / day or 12000 mSv / 30 days.
8. A radiation-resistant system for refreshing the internal program of an FPGA chip, characterized in that: According to any one of claims 1 to 7, the system comprises: Printed circuit boards; An FPGA chip is arranged on top of a printed circuit board; A radiation detector is disposed below the printed circuit board and is located corresponding to the FPGA chip; A microprocessor is connected to the FPGA chip and the radiation detector.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for refreshing the internal program of an FPGA chip with radiation resistance as described in any one of claims 1 to 7 is implemented.
10. A storage device comprising a storage medium and a processor, wherein the storage medium stores a computer program, characterized in that: When the processor executes the computer program, the method for refreshing the internal program of an FPGA chip with radiation resistance as described in any one of claims 1 to 7 is implemented.