Bus data detection module and detection method

Abstract

The present invention discloses a bus data detection module and detection method, which processes bus data in a write mode or a read mode. Bus data information sent by a host M can only be written to a corresponding slave S when the target slave ID and M.ECC check code generated by the M.ECC generation module are compared and matched with the slave ID and S.ECC check code obtained by the S.ECC generation module. Bus data in slave S can only be transmitted to the host M and read by a client when the target slave ID, M.ECC check code, and M.Data ECC check code generated by the M.ECC generation module are matched with the slave ID, S.ECC check code, and S.Data ECC check code generated by the S.ECC generation module. The present invention transmits bus data information, check code, and address information separately, and incorporates a judgment and detection step during the transmission process. Any errors that occur during the transmission process are identified and reported in the different judgment steps, effectively addressing the problem of missed detection in traditional ECC technology.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a bus data detection module and a detection method. Background Art

[0002] In automotive microcontroller (MCU) designs, the address width of the bus within the computer system is shortened during transmission. This is because different modules require different address widths during digital data processing. For example, the CPU requires a larger address space, while memory controllers and devices may only need to process a limited address range. Furthermore, a wider address bus requires more signal lines, which can lead to signal integrity issues such as interference and latency. Therefore, an address decoder is typically included within the bus bridge module. This decoder generates control signals based on the complete address input by the host to determine the valid address. This decoder then generates a select signal for the designated slave and intercepts the required valid address width for each slave, sending it to the corresponding slave. The address width received by the slave only retains its own valid address space, without any high-order address information.

[0003] Bus data transmission mainly relies on ECC technology (Error Correcting Code) to detect and correct errors in data transmission. ECC technology is derived from parity check technology and has more powerful automatic identification and correction capabilities. It can identify and correct error bits that parity check technology cannot detect. In bus transmission, there are multiple bus protocol signals such as data signals, address signals, and control signals. These signals may cause errors during the transmission process. Therefore, bus bridges usually use ECC methods to check these signals. The flowchart of the traditional ECC verification method can be found in the attached figure. Figures 1 to 3 .

[0004] However, when the MCU host accesses a slave device through a bus bridge, if the address decoder is subject to electromagnetic or noise interference, an erroneous slave select signal may be generated, causing data to be mistakenly sent to an unintended slave or host. In this case, since the bus data itself is correct, the ECC check will still deem the data correct because the ECC cannot detect this incorrect slave select. This poses a potential safety hazard because the system cannot identify this error, which may cause data to be sent to the wrong component, leading to unpredictable behavior.

[0005] Furthermore, current ECC implementations do not support AXI (Advanced eXtenS1ble Interface) out-of-order mode. The AXI protocol allows transactions to arrive in a nonlinear order, thereby improving system efficiency. However, in out-of-order mode, ECC's error detection and correction capabilities may be limited because ECC typically assumes data is transmitted in a specific order. This mismatch can render traditional ECC techniques ineffective for out-of-order transmissions, reducing overall system reliability.

[0006] In summary, while ECC plays an important role in detecting and correcting errors in bus transmissions, its limitations in AXI out-of-order mode and its inability to detect slave select errors when the address decoder is disturbed indicate that existing technologies are still insufficient in ensuring system security and reliability.

[0007] The existing patent CN119149446A "A memory address generation method, storage control method and generation device" proposes a memory address generation method, storage control method and generation device. The generation method includes using a storage controller in the SOC system to obtain a data storage address based on the address signal from the bus of the SOC system, and storing the data from the bus in the data storage unit according to the access order from the lowest bit to the highest bit of the data storage address; based on the mode of the storage controller, obtaining the ECC memory address, and storing the obtained ECC check code in the ECC storage unit according to the access order from the highest bit to the lowest bit of the ECC memory address. However, this technical solution focuses on static address generation prevention. Bus data errors can only be discovered when they are read, that is, errors can only be detected after the bus data has completed transmission; and this technical solution requires a storage unit for the ECC of each address, and the number of storage units required is large, occupying a large storage space. Furthermore, this technical solution only includes the bus data ECC checksum, not the bus address. Instead, the bus address is indirectly checked by negating the checksum. Furthermore, the bus data ECC checksum and the bus data physical address are bound together and transmitted simultaneously. This transmission method carries the risk of storing the bus data ECC checksum in the wrong bus data physical address, and fails to address address decoding errors. Therefore, these limitations require further technical improvements and innovations to address. Summary of the Invention

[0008] The purpose of the present invention is to solve the above problems existing in the prior art and to provide a bus data detection module and a detection method.

[0009] The purpose of the present invention is achieved through the following technical solutions:

[0010] A bus data detection module is used to detect bus data transmitted between a host M and a slave S. When the host M issues an access request to the slave S, it generates bus information and corresponding host transaction IDs and slave transaction IDs. The bus information includes a bus address, a bus control signal, and bus data. The bus data detection module includes an address decoder, an M.ECC generation module, an M.ECC check module, and an S.ECC generation module.

[0011] The M.ECC generation module obtains the host transaction ID and generates a target slave ID and an M.ECC check code according to the bus information;

[0012] The S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating access and the ID of the slave currently to be accessed based on the bus information compiled by the address decoder, and calculates the S.ECC check code of the corresponding slave using the ECC algorithm;

[0013] The M.ECC check module is provided with a FIFO memory, and by comparing the target slave ID and the slave ID, as well as the M.ECC check code and the S.ECC check code, a comprehensive detection of data transmission and slave selection in bus information transmission is achieved, thereby blocking the transmission of erroneous data.

[0014] Preferably, it also includes a transmission sequence processing module, which determines whether the host transaction IDs corresponding to two or more of the bus information are consistent; when the host transaction IDs corresponding to two or more of the bus information are the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be consistent with the order in which the access requests are issued; when the host transaction IDs corresponding to two or more of the bus information are not the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be arbitrary.

[0015] When the detection method of the bus data detection module is in the bus data writing mode, the specific steps include:

[0016] S1, receiving an access request from a client for a host M to write bus data to a slave S, the host M generates a host transaction ID, a slave transaction ID, and corresponding bus information; and transmits the host transaction ID and the bus information to an M.ECC generation module corresponding to the host M; the bus information includes a bus address, a bus control signal, and bus data;

[0017] S2, the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information;

[0018] S3, the M.ECC generation module transmits the M.ECC check code, the target slave ID and the host transaction ID to the M.ECC check module corresponding to the host M; selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory;

[0019] S4, the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave;

[0020] S5, the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the ID of the slave currently to be accessed based on the compiled bus information, and calculates the S.ECC check code of the corresponding slave using the ECC algorithm;

[0021] S6, the S.ECC generation module transmits the slave ID, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID;

[0022] S7, selecting a corresponding FIFO memory according to the slave ID and the slave transaction ID, first determining whether the slave ID and the target slave ID are consistent, reporting an error if they are inconsistent, and retrieving the M.ECC check code stored therein from the FIFO memory; reporting an error if the M.ECC check code does not exist in the FIFO memory; and then determining whether the M.ECC check code is consistent with the S.ECC check code if the M.ECC check code exists in the FIFO memory, reporting an error if they are inconsistent, and outputting a "transmission correct" signal if they are consistent.

[0023] S8, feeding back the signal generated in step S7 to the S.ECC generation module;

[0024] S9, writing the compiled bus data in the bus information into the corresponding slave S.

[0025] Preferably, in step S2, the M.ECC check code includes a bus address check code, a bus control signal check code and a bus data ECC check code.

[0026] Preferably, in step S4, after the bus information is compiled by the address decoder, the address decoder first selects a slave S and then transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

[0027] Preferably, in step S5, the S.ECC check code includes a slave address check code, a slave control signal check code and a slave data ECC check code.

[0028] Preferably, in step S6, the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and the S.ECC check code, the slave ID and the slave transaction ID are sent to the M.ECC check module of the corresponding host based on the host address M.ID.

[0029] Preferably, if it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module; at this time, when continuing to step S7, it will be determined that the M.ECC check code does not exist in the FIFO memory, and an error will be reported.

[0030] As the detection method of the bus data detection module mentioned above, when in the bus data reading mode, the specific steps include:

[0031] S1', receiving an access request from a client to read bus data from a slave S by a host M, the host M generates a host transaction ID, a slave transaction ID, and corresponding bus information; and transmits the host transaction ID and the bus information to an M.ECC generation module corresponding to the host M; the bus information includes a bus address and a bus control signal;

[0032] S2', the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information;

[0033] S3′, the M.ECC generation module transmits the M.ECC check code, the target slave ID, and the host transaction ID to the M.ECC verification module of the host, selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory;

[0034] S4', the address decoder compiles the bus address and transmits the compiled bus information to the S.ECC generation module of the corresponding slave;

[0035] S5′, the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating access and the ID of the slave currently to be accessed based on the compiled bus information, and simultaneously calculates the S.ECC check code of the corresponding slave using the ECC algorithm;

[0036] S6′, the S.ECC generation module transmits the slave ID, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID;

[0037] S7', selecting a corresponding FIFO memory according to the slave ID and the slave transaction ID, first determining whether the slave ID is consistent with the target slave ID, and reporting an error if they are inconsistent; and retrieving the M.ECC check code stored therein from the FIFO memory; reporting an error if the M.ECC check code does not exist in the FIFO memory; and then determining whether the M.ECC check code is consistent with the S.ECC check code if the M.ECC check code exists in the FIFO memory, and reporting an error if they are inconsistent; and outputting a "transmission correct" signal if they are consistent.

[0038] S8', feeding back the signal generated in step S7 to the S.ECC generation module;

[0039] S9', the S.ECC generation module obtains the bus data to be read from the corresponding slave, calculates the S.Data ECC check code of the bus data using an ECC algorithm, and transmits the S.Data ECC check code together with the slave ID and the slave transaction ID to the M.ECC check module corresponding to the master address M.ID; the M.ECC check module selects a corresponding FIFO memory according to the slave ID and the slave transaction ID, and stores the S.Data ECC check code in the FIFO memory;

[0040] On the other hand, the bus data is transmitted to the M.ECC generation module after passing through the address decoder, and the M.ECC generation module generates an M.Data ECC check code according to the bus data;

[0041] S10′, the M.ECC generation module transmits the target slave ID, the M.Data ECC check code, and the acquired host transaction ID to the M.ECC verification module corresponding to the host address M.ID; selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and retrieves the S.Data ECC check code stored therein; reports an error if the S.Data ECC check code does not exist in the FIFO memory corresponding to the target slave ID and the host transaction ID; if the S.Data ECC check code exists in the FIFO memory, determines whether the M.Data ECC check code is consistent with the S.Data ECC check code, and reports an error if they are inconsistent; and outputs a "transmission successful" signal if they are consistent;

[0042] S11 ′ feeds back the signal generated in step S10 ′ to the M.ECC generation module; and feeds back the bus data in the bus information to the host M, which is finally read out by the client.

[0043] Preferably, in step S2', the M.ECC check code includes a bus address check code and a bus control signal check code.

[0044] Preferably, in step S4 ′, after the bus information is compiled by the address decoder, the address decoder selects a slave S and transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

[0045] Preferably, in step S5', the S.ECC check code includes a slave address check code and a slave control signal check code.

[0046] Preferably, in step S6', the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and the S.ECC check code, the slave ID and the slave transaction ID are sent to the M.ECC check module of the corresponding host based on the host address M.ID.

[0047] Preferably, if it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check modules corresponding to other hosts except the designated M.ECC check module; at this time, when step S7' is continued to be executed, it will be determined that there is no ECC check code in the FIFO memory, and an error will be reported.

[0048] Preferably, the S. data ECC check code in step S9' includes a slave data ECC check code; and the M. data ECC check code in step S9' includes a bus data ECC check code.

[0049] Preferably, in step S9', the S.data ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and the S.data ECC check code, the slave ID and the slave transaction ID are sent to the M.ECC check module of the corresponding host based on the host address M.ID.

[0050] Preferably, if the address decoder makes an error during the compilation process, an erroneous S.Data ECC check code will be generated in step S9'; and when continuing to step S10', it will be determined that the M.Data ECC check code is inconsistent with the S.Data ECC check code, and an error will be reported.

[0051] The advantages of the technical solution of the present invention are mainly reflected in:

[0052] (1) The present invention adds the host transaction ID and the slave transaction ID, thereby increasing the support for the AXI out-of-order mode in the traditional ECC technology. In the ECC technology, the target slave ID and the host transaction ID, as well as the slave ID and the slave transaction ID, can be used to effectively detect the problem that the data generated during the transmission process is mistakenly sent to an unintended slave or host, thereby improving the efficiency, security and reliability of data transmission.

[0053] (2) The present invention transmits bus information through an address decoder, while the M.ECC check code and the target slave ID other than the data information are generated by the M.ECC generation module, and the host transaction ID is generated by the host. The three are then directly transmitted to the M.ECC check module, that is, the data information, the check information and the ID information are transmitted separately, and a judgment program is added during the transmission process. If any error occurs during the transmission process, it will be identified and reported in different judgment programs, which effectively makes up for the problem of missed detection in traditional ECC technology;

[0054] (3) The present invention focuses on dynamic transmission error detection. During the read transmission process, the first step is to detect whether the transmission address is incorrect. The second step is to compare the consistency of the M.ECC check code with the Sn.ECC check code, and the M.Data ECC check code with the S.ECC check code to determine whether there is an error in the bus information transmission process. These two verification procedures enhance detection reliability. At the same time, the present invention requires fewer storage units and is more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1: Overall schematic diagram of bus data detection in the background technology of the present invention;

[0056] Figure 2 : Overall flow chart of bus data write transmission in the background technology of the present invention;

[0057] Figure 3 : Overall flow chart of bus data read transmission in the background technology of the present invention;

[0058] Figure 4 : Schematic diagram of the overall framework structure of bus data detection of the present invention;

[0059] Figure 5 : A specific flow chart of bus data write transmission according to a preferred embodiment of the present invention;

[0060] Figure 6 : Specific flow chart of bus data read transmission according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0061] The objects, advantages, and features of the present invention are illustrated and explained through the following non-limiting description of preferred embodiments. These embodiments are merely typical examples of the application of the technical solutions of the present invention, and any technical solutions formed by equivalent substitution or equivalent transformation fall within the scope of protection claimed by the present invention.

[0062] like Figures 4 to 6 As shown, the present invention discloses a bus data detection module for detecting bus data transmitted between a host M and a slave S. The bus data detection module can write bus data from the host M to the slave S in a write mode, or feed bus data from the slave S back to the host M in a read mode. Furthermore, the number of hosts in the bus data detection module can be determined based on usage requirements and is not specifically limited herein; that is, the hosts can be composed of host M1, host M2, host M3, to host Mn, where n represents a natural number. Similarly, the number of slaves is also determined based on usage requirements and is not specifically limited herein.

[0063] The present invention comprises a host M, a slave S, an address decoder, an M.ECC generating module, an M.ECC checking module and an S.ECC generating module.

[0064] When the host M sends an access request to the slave S, bus information, and corresponding host transaction ID and slave transaction ID are generated; the bus information includes a bus address, a bus control signal, and bus data.

[0065] The M.ECC generation module is located at the location where each host bus data enters the bus bridge module. The M.ECC generation module generates an M.ECC check code and a target slave ID based on the bus information generated by the host M. At the same time, the M.ECC generation module transmits the M.ECC check code, the target slave ID, and the acquired host transaction ID to the M.ECC verification module. Specifically, the M.ECC generation module has the functions of: 1. calculating the check code of the bus data according to the ECC algorithm; 2. calculating the check code of the bus address according to the ECC algorithm; 3. calculating the check code of the bus control signal according to the ECC algorithm; 4. decoding the address to determine the target slave ID; 5. obtaining the current host transaction ID from the bus information; and 6. transmitting all the aforementioned check codes, the target slave ID, and the host transaction ID to the M.ECC verification module.

[0066] The S.ECC generation module is located at the location where the bus information is sent to the corresponding slave after passing through the address decoder. Based on the bus information compiled by the address decoder, the S.ECC generation module obtains the host address M.ID of the current host and the ID of the currently accessed slave, and simultaneously calculates the S.ECC check code of the corresponding slave using the ECC algorithm. Simultaneously, the S.ECC generation module transmits the slave ID, the S.ECC check code, and the obtained slave transaction ID to the M.ECC check module corresponding to the host address M.ID. Specifically, the S.ECC generation module has the following steps: 1. Calculate the check code of the bus data using the ECC algorithm; 2. Calculate the check code of the address using the ECC algorithm; 3. Calculate the check code of the bus control signal using the ECC algorithm; 4. Calculate the host address M.ID of the currently accessing host from the bus information; 5. Calculate the current slave transaction ID; and 6. Transmit the aforementioned check code, the slave transaction ID, and the slave ID to the corresponding M.ECC check module based on the host address M.ID.

[0067] The M.ECC check module is provided with a FIFO memory, and by comparing the target slave ID and the slave ID, as well as the M.ECC check code and the S.ECC check code, a comprehensive detection of data errors and slave address selection errors in bus information transmission is achieved, thereby blocking the transmission of erroneous data.

[0068] Specifically, the number of FIFO memories in the M.ECC check module is determined by the number of slaves and the maximum number of out-of-order transactions supported by the bus. Each FIFO memory is bound to a unique transaction ID and slave ID to ensure the independence of the check code timing. The M.ECC check module has the following functions: 1. Receive and store the M.ECC check code, the target slave ID, and the host transaction ID corresponding to the M.ECC generation module; 2. Receive and store the check code, the slave ID, and the transaction ID of all S.ECC generation modules; 3. Check and handle errors on the check code based on the slave ID and slave transaction ID.

[0069] like Figure 2 or Figure 3 In the conventional bus data detection module using ECC technology, after data is transmitted to the address decoder, if the address decoder is interfered with by external signals or an error occurs, bus data that should have been written by master M1 to slave S1 is instead transmitted to slaves S2 or Sn. In this case, since the bus data itself is not erroneous, the corresponding ECC check module will not detect the error even after recalculating and comparing the data. Therefore, the conventional method cannot effectively detect the error. However, this error can cause unexpected system behavior and affect functional safety.

[0070] like Figures 5 and 6 As shown, the present invention also has the advantage of comprehensive detection of bus data. Specifically, the M.ECC check code and the S.ECC check code both cover the bus address, bus control signal, and bus data. The M.ECC check code module compares the host transaction ID and the slave transaction ID, the target slave ID and the slave ID, and the M.ECC check code and the S.ECC check code through three-layer verification, thereby achieving comprehensive detection of the bus information and full coverage of the bus signal, thereby improving the accuracy and reliability of bus data transmission.

[0071] like Figures 4 to 6 The figure shows the detection method of the bus data detection module disclosed by the present invention. Through this method, the bus information written by the host M to the slave S can be detected, and the bus data fed back from the slave S to the host M can also be detected. The present invention strengthens the inspection of the data distribution logic. Specifically, in addition to verifying the data, the present invention also adds the detection of the address decoding logic. The M.ECC check code and the target slave ID are generated on the host side according to the bus information, and the S.ECC check code and the slave ID are also generated on the slave side. The host ID of the transmission is sent to the detection module of the corresponding host for comparison. This can ensure the correctness of the transmission between the host and the slave, cover more abnormal scenarios in the bus transmission process, and improve the security and reliability of the system.

[0072] The present invention also adopts the AXI protocol to support out-of-order transmission. Specifically, each bus information sent by the host M corresponds to a host transaction ID and a slave transaction ID. All bus information is classified and distinguished by the host transaction ID and the slave transaction ID, and the bus information in the FIFO memory corresponding to the same host transaction ID or the slave transaction ID must be output in sequence; the bus information in the FIFO memory corresponding to different transaction IDs or the slave transaction IDs can be output in any order. That is, in the present invention, after sending a request to the slave S through the host transaction ID and the slave transaction ID, the slave S can identify whether the host transaction ID and the slave transaction ID of all bus information are consistent and select whether the bus data is written to the corresponding slave or returned to the corresponding host in sequence or out of order.

[0073] Specifically, the technical solution of the present invention includes a transmission sequence processing module, which is located in the host M and determines whether the host transaction IDs corresponding to two or more bus information are consistent. When the host transaction IDs corresponding to two or more bus information are the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be consistent with the order in which the access requests were issued. When the host transaction IDs corresponding to two or more bus information are different, the transmission sequence processing module controls the order in which the slave S writes or returns data to be arbitrary.

[0074] like Figure 5 The detection method of the bus data detection module shown in the figure performs detection when in the bus data write mode, and its specific steps include:

[0075] In step S1, host M receives an access request from a client to write bus data to slave S. Host M then generates a host transaction ID, a slave transaction ID, and corresponding bus information. Simultaneously, host M transmits the host transaction ID and bus information to its corresponding M.ECC generation module. In this mode, the bus information includes a bus address, bus control signals, and bus data. Furthermore, the bus address includes address data, the bus control signal includes at least a write signal and data transfer size information, and the bus data includes the data to be written.

[0076] S2: The M.ECC generation module transmits the bus information to the address decoder and generates the M.ECC check code of the corresponding host and the target slave ID based on the bus information. In this mode, the M.ECC check code includes the bus address check code, the bus control signal check code, and the bus data ECC check code.

[0077] S3, the M.ECC generation module transmits the M.ECC check code, the target slave ID, and the acquired host transaction ID to the M.ECC check module corresponding to the host M. At the same time, the M.ECC generation module selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory.

[0078] S4, the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave.

[0079] S5: The S.ECC generation module obtains the host address M.ID of the host currently initiating the access request and the ID of the slave currently being accessed based on the bus information, and simultaneously calculates the S.ECC check code of the corresponding slave using an ECC algorithm. In this case, the S.ECC check code includes a slave address check code, a slave control signal check code, and a slave data ECC check code.

[0080] S6: The S.ECC generation module transmits the slave ID, the S.ECC check code, and the obtained slave transaction ID to the M.ECC verification module corresponding to the host address M.ID. During this process, the S.ECC check code, the slave ID, and the slave transaction ID must determine the address of the host currently initiating the access request based on the host address M.ID before reaching the M.ECC verification module. The S.ECC check code, the slave ID, and the slave transaction ID are then sent to the M.ECC verification module of the corresponding host based on the host address M.ID.

[0081] In this step, if the host address M.ID determines that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to the host other than the designated M.ECC check module. In this case, when the process continues to step S7, it will be determined that the ECC check code does not exist in the FIFO memory, and an error will be reported.

[0082] Specifically, let's take the example of a client sending a write signal from host M1 to slave S1. If, during step S5, the address of the host currently issuing the access request (i.e., the host address M.ID) is incorrectly obtained, the host address that should have been M1.ID is mistakenly interpreted as the host address of M2.ID or Mn.ID. Then, the S1.ECC check code generated in step S5, the slave's S1.ID, and the slave's S1.Transaction ID will all be sent to the M2.ECC check module or the Mn.ECC check module. Furthermore, during step S7, it may be discovered that the ECC check code does not exist in the FIFO memory corresponding to the S1.ID and S1.Transaction ID, resulting in an error.

[0083] S7, select the corresponding FIFO memory according to the slave ID and the slave transaction ID, first determine the slave ID and the target slave ID, and when the two are consistent, retrieve the M.ECC check code stored therein; when the ECC check code does not exist in the FIFO memory, report an error; when the ECC check code exists in the FIFO memory, determine whether the M.ECC check code is consistent with the S.ECC check code, and when they are inconsistent, report an error; when they are consistent, output a "transmission correct" signal.

[0084] Furthermore, if the M.ECC check module reports an error to the controller during this step, the reasons could be: 1. The slave ID is incorrect; 2. The corresponding FIFO memory cannot be found; 3. The M.ECC check code does not exist in the FIFO memory. The root cause of the error is that the address decoder selected the wrong slave S in step S4.

[0085] If the address decoder fails during compilation or is affected by external interference, resulting in slave S2 or another slave Sn being selected instead of slave S1, bus information will be transmitted to the S2.ECC generation module or the Sn.ECC generation module in step S4. Then, in step S5, the S2.ECC check code, the address of slave S2 (i.e., S2.ID), and the transaction address of slave S2 (i.e., S2.Transaction ID) are generated. In step S6, the S2.ECC check code is sent to the M2.ECC check code module, or the Sn.ECC check code is sent to the Mn.ECC check code module. In step S7, the M1.ECC check code is retrieved from the FIFO memory corresponding to the S2.ID and S2.Transaction ID. At this point, it will be found that the slave ID (i.e., S2.ID) or the slave transaction ID (i.e., S2.Transaction ID) does not exist, or the corresponding FIFO memory cannot be found, or the ECC check code does not exist in the FIFO memory. Therefore, when the address decoder selects an incorrect slave, the detection method of the bus data detection module disclosed in the present invention will detect it, and the M1.ECC check module will report the error to the MCU controller.

[0086] In addition, the reason why the M.ECC check module reports an error to the controller during this step may also be because the M.ECC check code is determined to be inconsistent with the S.ECC check code. The fundamental reason for the inconsistency between the M.ECC check code and the S.ECC check code is that the bus information generates incorrect bus data during the process, causing the S.ECC generation module to generate an incorrect S.ECC check code.

[0087] Specifically, let's take the example of a client sending a write signal from master M1 to slave S1. If the address decoder experiences external interference and generates an error during the compilation process in step S4, resulting in incorrect or missing bus data in the bus information, an incorrect S1.ECC check code will be generated in step S5. This S1.ECC check code may be inconsistent when compared with the M1.ECC check code in step S7.

[0088] In addition, if after the above error is generated, it is found through investigation that the address decoder is correct during the compilation process, it means that the host address M.ID address obtained when executing step S5 is wrong.

[0089] S8, feeding back the signal generated in step S7 to the S.ECC generation module.

[0090] S9, writing the bus data in the compiled bus information to the corresponding slave S. Before writing the bus data to the slave S, the transmission sequence processing module first determines whether the host transaction IDs corresponding to two or more bus information are consistent. When the host transaction IDs corresponding to two or more bus information are the same, the transmission sequence processing module controls the order in which the slave S writes data to be consistent with the order in which the access requests are issued. When the host transaction IDs corresponding to two or more bus information are different, the transmission sequence processing module controls the order in which the slave S writes data to be arbitrary.

[0091] When the host M sends an access request to the slave S, it determines whether to perform write mode processing or read mode processing according to the bus control signal in the bus information. At the same time, the host M will generate the host transaction ID and the slave transaction ID.

[0092] Taking the bus control signal processing in write mode as an example: if the same slave S receives write signal requests from multiple masters M in succession, and the transmission order processing module determines that the host transaction IDs issued by each master M are different, then the order in which the data written to the slave S is controlled by the out-of-order transmission processing module may be different from the order of the host transaction IDs received by the slave S. That is, when slave S1 receives access requests from masters M1, M2, and M3 simultaneously or successively, where the host transaction ID of master M1 is 0, the corresponding bus information is X, bus data x, the host transaction ID of master M2 is 1, the corresponding bus information is Y, bus data y, and the host transaction ID of master M3 is 2, the corresponding bus information is Z, bus data z. The transmission sequence processing module determines that the host transaction IDs corresponding to the three bus information are different, and the slave S1 responds to bus data y faster than bus data x. Then the transmission sequence processing module controls the slave S1 to write in the order of bus data y, bus data x, and bus data z, or in the order of bus data y, bus data z, bus data x or other orders.

[0093] If the same slave S receives write signal requests from multiple masters M in succession, and the transmission sequence processing module determines that some of the master transaction IDs issued by the masters M are identical, the transmission sequence processing module controls the order in which data is written to the slave S to be different from the order of the master transaction IDs received by the slave S. That is, when slave S1 receives access requests from masters M1, M2, and M3 simultaneously or consecutively, where the master transaction ID of master M1 is 0, the corresponding bus information is X, bus data x; the master transaction ID of master M2 is 1, the corresponding bus information is Y, bus data y; and the master transaction ID of master M3 is 0, the corresponding bus information is Z, bus data z, the out-of-order transmission processing module determines that some of the master transaction IDs are identical and classifies them according to the master transaction IDs, dividing them into two types of master transaction IDs. The transmission sequence processing module controls slave S1 to write in the order of bus data y, bus data x, bus data z, or bus data x, bus data y, or bus data x, bus data z, bus data y. The bus data x and bus data z must be written in the order in which they are input.

[0094] If the same slave S receives write signal requests from multiple masters M in succession, and the out-of-order transmission processing module determines that the host transaction IDs issued by each master M are the same, then the out-of-order transmission processing module controls the order in which data is written to the slave S to be exactly the same as the order in which the host transaction IDs are received by the slave S. That is, when slave S1 receives access requests from masters M1, M2, and M3 simultaneously or successively, where the host transaction ID of master M1 is 0, the corresponding bus information is X, bus data x, the host transaction ID of master M2 is 0, the corresponding bus information is Y, bus data y, and the host transaction ID of master M3 is 0, the corresponding bus information is Z, bus data z, because the out-of-order transmission processing module determines that all the host transaction IDs are the same, the transmission sequence processing module controls slave S1 to write data only in the order in which they were received, and the write order is bus data x, bus data y, bus data z.

[0095] In addition, the same host M can also continuously send multiple access requests to the same slave S; that is, the same host M continuously sends multiple bus information to one of the slaves S in write mode, and at the same time sends the host transaction ID and slave transaction ID corresponding to each bus information to the corresponding slave S. The out-of-order transmission processing module controls the slave S to write the bus data in order or out of order based on whether the host transaction ID or the slave transaction ID is consistent. Figures 1 to 3The ECC technology used in the traditional bus data detection module shown above cannot handle out-of-order transmission in the AXI bus protocol. This is because the host cannot generate master and slave transaction IDs during transmission. Therefore, data transmission and write order must be transmitted in the input order. This results in long data transmission time and low system efficiency. If the AXI out-of-order mode is used in the traditional bus data detection module, false error messages will occur.

[0096] The present invention solves the problem that traditional ECC technology does not support out-of-order transmission of the AXI bus protocol by adding host transaction ID and slave transaction ID to support AXI processing. This enables traditional ECC technology to support out-of-order transmission of the AXI bus protocol, and data can be reliably verified and corrected, thereby improving system performance.

[0097] like Figure 5 As shown, taking the client sending a write signal from host M1 to slave S1 as an example, in the specific steps, all the host M refers to host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S1, S.ECC generation module refers to S1.ECC generation module, S.ECC check module refers to S1.ECC check module, S.ECC check code refers to S1.ECC check code, and S.data ECC check code refers to S1.data ECC check code.

[0098] Similarly, if the client sends a write signal from host M1 to slave S2 as an example, then in the above specific steps, all the host M refers to host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S2, S.ECC generation module refers to S2.ECC generation module, S.ECC check module refers to S2.ECC check module, S.ECC check code refers to S2.ECC check code, and S.data ECC check code refers to S2.data ECC check code.

[0099] By analogy, if the client sends a write signal from host M2 to slave S1 as an example, then all the host M in the above specific steps refers to host M2, M.ECC generation module refers to M2.ECC generation module, M.ECC check module refers to M2.ECC check module, M.ECC check code refers to M2.ECC check code, and M.data ECC check code refers to M2.data ECC check code. All the slaves S refer to slave 1, S.ECC generation module refers to S1.ECC generation module, S.ECC check module refers to S1.ECC check module, S.ECC check code refers to S1.ECC check code, and S.data ECC check code refers to S1.data ECC check code. Other embodiments can be inferred based on the above embodiments and will not be described in detail here.

[0100] Specific as Figure 6 The detection method of the bus data detection module shown in the figure performs detection when in the bus data write mode, and its specific steps include:

[0101] In step S1', host M receives a request from a client to read bus data from slave S. Host M then generates a host transaction ID, a slave transaction ID, and corresponding bus information. Host M then transmits the host transaction ID and bus information to its corresponding M.ECC generation module. In this mode, the bus information includes a bus address and bus control signals. Furthermore, the bus address includes address data, and the bus control signals include a read signal and data transfer size information.

[0102] S2', the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information. At the same time, the M.ECC check code in this mode includes the bus address check code and the bus control signal check code.

[0103] S3′: The M.ECC generation module transmits the M.ECC check code, the target slave ID, and the acquired host transaction ID to the M.ECC verification module of the host. The M.ECC generation module then selects a corresponding FIFO memory based on the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory.

[0104] S4', the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave.

[0105] S5': The S.ECC generation module obtains the host address M.ID of the host currently initiating the access request and the ID of the slave currently being accessed based on the bus information, and simultaneously calculates the S.ECC check code of the corresponding slave using the ECC algorithm. In this case, the S.ECC check code includes the bus address check code and the bus control signal check code.

[0106] S6': The S.ECC generation module transmits the slave ID, the S.ECC check code, and the obtained slave transaction ID to the M.ECC verification module corresponding to the master address M.ID. During this process, the S.ECC check code, the slave ID, and the slave transaction ID must be used to determine the host currently initiating the access request based on the master address M.ID before reaching the M.ECC verification module. The S.ECC check code, the slave ID, and the slave transaction ID are then sent to the M.ECC verification module of the corresponding master based on the master address M.ID.

[0107] In this step, if the host address M.ID determines that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to the host other than the designated M.ECC check module. At this time, when the process continues to step S7', it will be determined that the ECC check code does not exist in the FIFO memory, and an error will be reported.

[0108] Specifically, let's take the example of a client sending a read signal from host M1 to slave S1. If, during step S5', an error occurs in obtaining the address of the host currently issuing the access request (i.e., the host address M.ID), the host address that should have been obtained for M1.ID is mistakenly interpreted as the host address for M2.ID or Mn.ID. Then, the S1.ECC check code generated in step S5', the slave's S1.ID, and the slave's S1.Transaction ID will all be sent to the M2.ECC check module or the Mn.ECC check module. Furthermore, during step S7', it may be discovered that the ECC check code does not exist in the FIFO memory corresponding to the S1.ID and S1.Transaction ID, resulting in an error. Alternatively, when continuing to step S7', it may be determined that the M1.ECC check code is inconsistent with the S.ECC check code, resulting in an error. Based on the error information, it can be deduced that the cause of the error is that the incorrect host address was obtained (i.e., the host address M.ID was obtained incorrectly).

[0109] S7', select the corresponding FIFO memory according to the slave ID and the slave transaction ID, first determine whether the slave ID and the target slave ID are consistent, and when the two are consistent, retrieve the M.ECC check code stored therein; when the ECC check code does not exist in the FIFO memory, an error is reported; when the ECC check code exists in the FIFO memory, determine whether the M.ECC check code is consistent with the S.ECC check code, and when they are inconsistent, an error is reported; when they are consistent, a "transmission correct" signal is output.

[0110] The following reasons may cause the M.ECC check module to report an error to the controller during this step: 1. The slave ID is incorrect. 2. The corresponding FIFO memory cannot be found. 3. The M.ECC check code does not exist in the FIFO memory. The root cause of the error is that the address decoder in step S4' selected the wrong slave S.

[0111] Specifically, let's take the example of a client sending a read signal from host M1 to slave S1. If the address decoder fails during compilation or receives external interference, resulting in slave S2 or another slave Sn being selected instead of S1, the bus information will be transmitted to the S2.ECC generation module or the Sn.ECC generation module in step S4'. Then, in step S5', the S2.ECC check code, the address of slave S2 (i.e., S2.ID), and the transaction address of slave S2 (i.e., S2.Transaction ID) are generated. In step S6', the S2.ECC check code is sent to the M2.ECC check code module, or the Sn.ECC check code is sent to the Mn.ECC check code module. During step S7', the M1.ECC check module retrieves the M1.ECC check code from the FIFO memory corresponding to S2.ID and S2.Transaction ID. At this point, it is discovered that the slave ID (i.e., S2.ID) or the slave transaction ID (i.e., S2.Transaction ID) does not exist, or the FIFO memory corresponding to the slave ID and slave transaction ID cannot be found, or the ECC check code does not exist in the FIFO memory. Therefore, when the address decoder selects the wrong slave, the bus data detection module and detection method disclosed in the present invention will detect this, and the M1.ECC check module will report the error to the MCU controller.

[0112] In addition, the reason why the M.ECC check module reports an error to the controller during this step may also be because the M.ECC check code is determined to be inconsistent with the S.ECC check code. The fundamental reason for the inconsistency between the M.ECC check code and the S.ECC check code is that the bus information generates incorrect bus data during transmission, causing the S.ECC generation module to generate an incorrect S.ECC check code.

[0113] Specifically, let's take the example of a client sending a read signal from master M1 to slave S1. If the address decoder experiences external interference and generates an error during the compilation process in step S4, resulting in incorrect or missing bus data in the bus information, an incorrect S1.ECC check code will be generated in step S5. This S1.ECC check code may be inconsistent when compared with the M1.ECC check code in step S7, resulting in an error.

[0114] In addition, if it is found after the above error is generated that the address decoder is correct during the compilation process, it means that the host address M.ID address obtained when executing step S5' is wrong.

[0115] S8', feeding back the signal generated in step S7 to the S.ECC generation module.

[0116] S9', the S.ECC generation module obtains the bus data to be read from the corresponding slave. The bus data is the information in the bus information excluding the ECC check code, data ECC check code, ID, and transaction ID. That is, the bus data only contains the bus data to be transmitted and read. Furthermore, the bus data is bus information, so it can be directly obtained by extracting it from the bus information in the corresponding slave.

[0117] On the one hand, an ECC algorithm is used to calculate the S.Data ECC check code of the bus data. This S.Data ECC check code is then transmitted, along with the slave ID and the slave transaction ID, to the M.ECC check module corresponding to the master address M.ID. The M.ECC check module then selects a corresponding FIFO memory based on the slave ID and the slave transaction ID and stores the S.Data ECC check code in the FIFO memory. The S.Data ECC check code is generated based on the bus data in the slave S; it also includes the slave data ECC check code.

[0118] Furthermore, in this process, the S.data ECC check code, the slave ID, and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and send the S.data ECC check code, the slave ID, and the slave transaction ID to the corresponding M.ECC check module based on the host address M.ID.

[0119] If the address decoder makes an error during the compilation process, an erroneous S.Data ECC check code will be generated in this step. When the process continues to step S10', it will be determined that the M.Data ECC check code is inconsistent with the S.Data ECC check code, and an error will be reported.

[0120] On the other hand, the bus data is transmitted to the M.ECC generation module after passing through the address decoder. The M.ECC generation module generates an M.Data ECC check code based on the bus data. The M.Data ECC check code is a check code generated based on the data information in the host M; the M.Data ECC check code includes the bus data ECC check code.

[0121] S10': The M.ECC generation module transmits the target slave ID, the M.Data ECC check code, and the acquired host transaction ID to the M.ECC verification module corresponding to the host address M.ID. Based on the target slave ID and the host transaction ID, the corresponding FIFO memory is selected and the S.Data ECC check code stored therein is retrieved. An error message is generated if the S.Data ECC check code does not exist in the FIFO memory. If the S.Data ECC check code exists in the FIFO memory, the module determines whether the M.Data ECC check code is consistent with the S.Data ECC check code. If not, an error message is generated. If not, a "transmission successful" signal is output.

[0122] The reason why the M.ECC check module reports an error to the controller when executing this step is that the S.Data ECC check code does not exist in the FIFO memory corresponding to the target slave ID and the host transaction ID. The fundamental reason for the error is that the address decoder selects the wrong slave S.

[0123] Specifically, let's take the example of a client sending a read signal from host M1 to slave S1. If the address decoder encounters an error during compilation or is affected by external interference signals, resulting in the selection of slave S2 or another slave Sn when it should have selected slave S1, the bus data obtained in step S9' will be transmitted to the S2.ECC generation module or the Sn.ECC generation module. When executing step S10', the M1.ECC check module retrieves the S1.Data ECC check code from the FIFO memory corresponding to S2.ID and S2.Transaction ID. At this point, it will be found that the slave ID (i.e., S2.ID) or the slave transaction ID (i.e., S2.Transaction ID) does not exist, or the FIFO memory corresponding to the slave ID and slave transaction ID cannot be found, or the ECC check code does not exist in the FIFO memory. Therefore, when the address decoder selects the wrong slave, the bus data detection module and detection method disclosed in the present invention will detect this, and the M1.ECC check module will report the error to the MCU controller.

[0124] If it is determined during this step that the M.Data ECC check code is inconsistent with the S.Data ECC check code, the fundamental reason for the inconsistency between the M.Data ECC check code and the S.Data ECC check code is that the bus information in step S4' generated erroneous bus data during transmission, which in turn caused the S.Data ECC generation module in step S9' to generate an erroneous S.Data ECC check code.

[0125] Specifically, let's take the example of a client sending a read signal from master M1 to slave S1. If the address decoder experiences external interference and generates an error during the compilation process in step S4, resulting in incorrect or missing bus data in the bus information, an incorrect S1.ECC check code will be generated in step S5. This S1.ECC check code may be inconsistent when compared with the M1.ECC check code in step S7, resulting in an error.

[0126] S11' feeds back the signal generated in step S10' to the M.ECC generation module; and feeds back the bus data to the host M, which is ultimately read out by the client. Before feeding back the bus data to the host M, the transmission sequence processing module first determines whether the host transaction IDs corresponding to two or more bus information are consistent. When the host transaction IDs corresponding to two or more bus information are the same, the transmission sequence processing module controls the order in which the slave S returns data to be consistent with the order in which the access requests are issued. When the host transaction IDs corresponding to two or more bus information are different, the transmission sequence processing module controls the order in which the slave S returns data to be arbitrary.

[0127] When the host M sends an access request to the slave S, it determines whether to perform write mode processing or read mode processing according to the bus control signal in the bus information. At the same time, the host M will generate the host transaction ID and the slave transaction ID.

[0128] Taking the bus control signal processing in read mode as an example: if the same slave S receives read signal requests from multiple masters M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by each master M are different, the transmission sequence processing module can control the order of data returned from the slave S to be different from the order of the received host transaction IDs. That is, when slave S1 receives read data requests from masters M1, M2, and M3 simultaneously or successively, where the host transaction ID of master M1 is 0, the corresponding bus information is X, bus data x; the host transaction ID of master M2 is 1, the corresponding bus information is Y, bus data y; the host transaction ID of master M3 is 2, the corresponding bus information is Z, bus data z. Since the transmission sequence processing module determines that the host transaction ID corresponding to each bus information is different, and the slave S1 responds to bus data y faster than bus data x, the transmission sequence processing module controls the slave S1 to return data in the order of bus data y, bus data x, and bus data z, or to return data in the order of bus data y, bus data z, bus data x, or other orders.

[0129] If the same slave S receives read signal requests from multiple masters M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by some of the masters M are the same, the transmission sequence processing module controls the order in which the data returned from the slave S may not be exactly the same as the order of the received host transaction IDs. That is, when slave S1 receives read data requests from masters M1, M2, and M3 simultaneously or successively, where the host transaction ID of master M1 is 0, the corresponding bus information is X, bus data x; the host transaction ID of master M2 is 1, the corresponding bus information is Y, bus data y; and the host transaction ID of master M3 is 0, the corresponding bus information is Z, bus data z. In this case, the out-of-order transmission processing module determines that some of the host transaction IDs are the same and classifies them according to the host transaction IDs, dividing them into two types of host transaction IDs. The out-of-order transmission processing module controls slave S1 to write in the order of bus data y, bus data x, bus data z, or bus data x, bus data y, or bus data x, bus data z, bus data y. The bus data x and bus data z must return data in the order in which they are input.

[0130] If the same slave S receives read signal requests from multiple hosts M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by each host M are the same, then the transmission sequence processing module controls the order of data returned from the slave S to be exactly the same as the order of the host transaction IDs it receives. That is, when slave S1 receives access requests from hosts M1, M2, and M3 simultaneously or successively, where the host transaction ID of host M1 is 0, the corresponding bus information is X, bus data x; the host transaction ID of host M2 is 0, the corresponding bus information is Y, bus data y; the host transaction ID of host M3 is 0, the corresponding bus information is Z, bus data z. Because the transmission sequence processing module determines that all the host transaction IDs are the same, the transmission sequence processing module controls the slave S1 to write only in the order in which they are received, and the order of reading data is bus data x, bus data y, bus data z.

[0131] In addition, the same host M may also continuously issue multiple read signal requests to the same slave S. That is, the same host M continuously issues multiple bus information read data requests to one of the slaves S, performing read mode processing; simultaneously, the host transaction ID and slave transaction ID corresponding to each bus information are sent to the corresponding slave S. The transmission sequence processing module controls the slave S to feed the bus data back to the host M in sequential or random order based on whether the host transaction ID or the slave transaction ID is consistent.

[0132] like Figure 6 As shown, taking the example of a client sending a read signal from host M1 to slave S1, in the above specific steps, all the host M refers to host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S1, S.ECC generation module refers to S1.ECC generation module, S.ECC check module refers to S1.ECC check module, S.ECC check code refers to S1.ECC check code, and S.data ECC check code refers to S1.data ECC check code.

[0133] Similarly, if we take the example of a client sending a read signal from host M1 to slave S2, then in the above specific steps, all the host M refers to host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S2, S.ECC generation module refers to S2.ECC generation module, S.ECC check module refers to S2.ECC check module, S.ECC check code refers to S2.ECC check code, and S.data ECC check code refers to S2.data ECC check code.

[0134] By analogy, if the client sends a signal from host M2 to slave S1 as an example, then all the host M in the above specific steps refers to host M2, M.ECC generation module refers to M2.ECC generation module, M.ECC check module refers to M2.ECC check module, M.ECC check code refers to M2.ECC check code, and M.data ECC check code refers to M2.data ECC check code. All the slaves S refer to slave 1, S.ECC generation module refers to S1.ECC generation module, S.ECC check module refers to S1.ECC check module, S.ECC check code refers to S1.ECC check code, and S.data ECC check code refers to S1.data ECC check code. Other embodiments can be inferred based on the above embodiments and will not be described in detail here.

[0135] In summary, the number of the M.ECC generation modules and the M.ECC check modules in the present invention is determined by the number of the hosts M. The number of the S.ECC generation modules and the S.ECC check modules is determined by the number of the slaves S.

[0136] There are many implementation methods of the present invention, and all technical solutions formed by equivalent transformation or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A detection method for a bus data detection module, characterized in that: When in bus data write mode, the specific steps include: S1, receiving an access request from a client to write bus data from a host M to a slave S, the host M generates a host transaction ID, a slave transaction ID and corresponding bus information; and transmitting the host transaction ID and the bus information to the M.ECC generation module corresponding to the host M; the bus information includes a bus address, a bus control signal and bus data; S2, the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information; S3, the M.ECC generation module transmits the M.ECC check code, the target slave ID and the host transaction ID to the M.ECC check module corresponding to the host M; Select a corresponding FIFO memory according to the target slave ID and the host transaction ID, and store the M.ECC check code in the FIFO memory; S4, the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave; S5, the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the ID of the slave currently to be accessed based on the compiled bus information, and calculates the S.ECC check code of the corresponding slave using the ECC algorithm; S6, the S.ECC generation module transmits the slave ID to be accessed, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; S7, selecting a corresponding FIFO memory according to the slave ID currently to be accessed and the slave transaction ID, first determining whether the slave ID currently to be accessed is consistent with the target slave ID, reporting an error if they are inconsistent, and retrieving the M.ECC check code stored therein if they are consistent; When the M.ECC check code does not exist in the FIFO memory, an error is reported; when the M.ECC check code exists in the FIFO memory, it is determined whether the M.ECC check code is consistent with the S.ECC check code, and an error is reported if they are inconsistent; if they are consistent, a "transmission correct" signal is output; S8, feeding back the signal generated in step S7 to the S.ECC generation module; S9, writing the compiled bus data in the bus information into the corresponding slave S.

2. The detection method of the bus data detection module according to claim 1, characterized in that: In step S2, the M.ECC check code includes a bus address check code, a bus control signal check code and a bus data ECC check code.

3. The detection method of the bus data detection module according to claim 1, characterized in that: In step S4 , after the bus information is compiled by the address decoder, the address decoder first selects a slave S and then transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

4. The detection method of the bus data detection module according to claim 1, characterized in that: In step S5, the S.ECC check code includes a slave address check code, a slave control signal check code and a slave data ECC check code.

5. The detection method of the bus data detection module according to claim 1, characterized in that: In step S6, the S.ECC check code, the slave ID currently to be accessed, and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and the S.ECC check code, the slave ID currently to be accessed, and the slave transaction ID are sent to the M.ECC check module of the corresponding host based on the host address M.ID.

6. The detection method of the bus data detection module according to claim 5, characterized in that: If it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module; at this time, when continuing to step S7, it will be determined that the M.ECC check code does not exist in the FIFO memory, and an error will be reported.

7. A detection method for a bus data detection module, characterized in that: When in bus data reading mode, the specific steps include: S1', receiving an access request from a client to read bus data from a slave S by a host M, the host M generates a host transaction ID, a slave transaction ID and corresponding bus information; and transmitting the host transaction ID and the bus information to the M.ECC generation module corresponding to the host M; the bus information includes a bus address and a bus control signal; S2', the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information; S3′, the M.ECC generation module transmits the M.ECC check code, the target slave ID, and the host transaction ID to the M.ECC verification module of the host, selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory; S4', the address decoder compiles the bus address and transmits the compiled bus information to the S.ECC generation module of the corresponding slave; S5′, the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the ID of the slave currently to be accessed based on the compiled bus information, and calculates the S.ECC check code of the corresponding slave using the ECC algorithm; S6′, the S.ECC generation module transmits the slave ID to be currently accessed, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; S7′, selecting a corresponding FIFO memory according to the slave ID currently to be accessed and the slave transaction ID, first determining whether the slave ID currently to be accessed is consistent with the target slave ID, reporting an error if they are inconsistent, and retrieving the M.ECC check code stored therein if they are consistent; When the M.ECC check code does not exist in the FIFO memory, an error is reported; when the M.ECC check code exists in the FIFO memory, it is determined whether the M.ECC check code is consistent with the S.ECC check code, and an error is reported if they are inconsistent; if they are consistent, a "transmission correct" signal is output; S8', feeding back the signal generated in step S7 to the S.ECC generation module; S9', the S.ECC generation module obtains the bus data to be read from the corresponding slave, calculates the S.Data ECC check code of the bus data using an ECC algorithm, and transmits the S.Data ECC check code together with the slave ID currently to be accessed and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; the M.ECC check module selects a corresponding FIFO memory according to the slave ID currently to be accessed and the slave transaction ID, and stores the S.Data ECC check code in the FIFO memory; On the other hand, the bus data is transmitted to the M.ECC generation module after passing through the address decoder, and the M.ECC generation module generates an M.Data ECC check code according to the bus data; S10′, the M.ECC generation module transmits the target slave ID, the M.Data ECC check code, and the acquired host transaction ID to the M.ECC verification module corresponding to the host address M.ID; selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and retrieves the S.Data ECC check code stored therein; When the S. data ECC check code does not exist in the FIFO memory corresponding to the target slave ID and the host transaction ID, an error is reported; If the S. data ECC check code exists in the FIFO memory, determine whether the M. data ECC check code is consistent with the S. data ECC check code, and output an error message if they are inconsistent; if they are consistent, output a "transmission correct" signal; S11 ′ feeds back the signal generated in step S10 ′ to the M.ECC generation module; and feeds back the bus data in the bus information to the host M, which is finally read out by the client.

8. The detection method of the bus data detection module according to claim 7, characterized in that: In the step S2', the M.ECC check code includes a bus address check code and a bus control signal check code.

9. The detection method of the bus data detection module according to claim 7, characterized in that: In the step S4 ′, after the bus information is compiled by the address decoder, the address decoder selects a slave S and transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

10. The detection method of the bus data detection module according to claim 7, characterized in that: In the step S5', the S.ECC check code includes a slave address check code and a slave control signal check code.

11. The detection method of the bus data detection module according to claim 7, characterized in that: In step S6', the S.ECC check code, the ID of the slave currently to be accessed, and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and the S.ECC check code, the ID of the slave currently to be accessed, and the slave transaction ID are sent to the M.ECC check module of the corresponding host based on the host address M.ID.

12. The detection method of the bus data detection module according to claim 11, characterized in that: If it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check modules corresponding to other hosts except the designated M.ECC check module; At this time, when the process continues to execute step S7 ′, it will be determined that no ECC check code exists in the FIFO memory, and an error will be reported.

13. The detection method of the bus data detection module according to claim 7, characterized in that: The S. data ECC check code in step S9' includes the slave data ECC check code; the M. data ECC check code in step S9' includes the bus data ECC check code.

14. The detection method of the bus data detection module according to claim 7, characterized in that: In step S9', the S.data ECC check code, the ID of the slave currently to be accessed, and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and the S.data ECC check code, the ID of the slave currently to be accessed, and the slave transaction ID are sent to the M.ECC check module of the corresponding host based on the host address M.ID.

15. The detection method of the bus data detection module according to claim 14, characterized in that: If the address decoder makes an error during the compilation process, an erroneous S.Data ECC check code will be generated in step S9'; and when the process continues to step S10', it will determine that the M.Data ECC check code is inconsistent with the S.Data ECC check code, and an error will be reported.

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