Data forwarding module applied to processor, processor, equipment and method
By designing a data pre-delivery module that matches virtual addresses and physical addresses in parallel in the processor, the problem of long delay in the data pre-delivery pipeline in the prior art is solved, and a more efficient data pre-delivery process is achieved.
Patent Information
- Application Number
- CN202311452955.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-02
- Publication Date
- 2025-05-06
AI Technical Summary
The data pre-delivery pipeline in existing processors has a long delay, which affects overall performance.
A data pre-transfer module is designed, including an address conversion unit, a virtual address matching unit, a physical address matching unit and an address selection unit. By processing the matching tasks of virtual addresses and physical addresses in parallel, clock cycle delay is reduced.
By reducing the clock cycle delay between virtual address matching and physical address matching, the data loading process is shortened, the processing efficiency of data pre-delivery module is improved, and the efficiency of data pre-delivery is improved.
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Figure CN119938557A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a data forwarding module, processor, device and method applied to a processor. Background Art
[0002] Modern processors have introduced the mapping between virtual and real addresses. The addresses defined in the program are all virtual addresses. Under the mapping of TLB (Translation Lookaside Buffer), the conversion from virtual addresses to real addresses is completed. The program can be programmed only within the virtual address range. When it is ported to different systems, it can adapt to different systems by changing the virtual-to-real address mapping relationship, thereby greatly improving the portability of the program.
[0003] In the related technology, the data forward pipeline contains a total of 4 stages. The first stage is AGU (Address Generation Unit), which is used to calculate the virtual address. The second stage is the access to DTLB (Data Translation Lookaside Buffer) to complete the conversion of virtual and real addresses. The third stage is paddr compare (physical address comparison), which matches the physical address with the address of the data stored in the buffer. The fourth stage is paddrselect (physical address selection), which selects the hit data according to the matching result.
[0004] However, the delay in the above method is relatively long, which can easily have a significant impact on the overall performance of the processor. Summary of the invention
[0005] The embodiment of the present application provides a data forwarding module, processor, device and method applied to a processor. The technical solution is as follows:
[0006] According to one aspect of an embodiment of the present application, a data forwarding module applied to a processor is provided, the data forwarding module comprising: an address conversion unit, an address matching unit and an address selection unit, the address matching unit comprising a virtual address matching unit and a physical address matching unit;
[0007] The address conversion unit is used to determine a physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship; wherein the address mapping relationship refers to a mapping relationship between a virtual address and a physical address, and the first virtual address is a virtual address corresponding to the data to be read in the data read instruction responded by the data forwarding module;
[0008] The virtual address matching unit is used to match the first virtual address with at least one virtual address in a buffer to obtain a virtual matching result corresponding to the first virtual address, wherein the virtual matching result is used to indicate a virtual address in the buffer that matches the first virtual address, and the buffer is located in the processor;
[0009] The physical address matching unit is used to match the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address, wherein the physical matching result is used to indicate a physical address in the buffer that matches the first physical address, and the virtual address and the physical address in the buffer follow the address mapping relationship;
[0010] The address selection unit is used to obtain data in a target virtual address according to the virtual matching result when the virtual matching result matches the physical matching result, and the target virtual address refers to a virtual address in the buffer that matches the first virtual address.
[0011] According to one aspect of an embodiment of the present application, a processor is provided, the processor comprising the data forwarding module as described above.
[0012] According to one aspect of an embodiment of the present application, a computer device is provided, the computer device comprising a processor, and the processor comprising the data forwarding module as described above.
[0013] According to one aspect of an embodiment of the present application, a data forwarding method applied to a data forwarding module is provided, wherein the data forwarding module comprises: an address conversion unit, an address matching unit and an address selection unit, wherein the address matching unit comprises a virtual address matching unit and a physical address matching unit; the method comprises:
[0014] The address conversion unit determines a physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship; wherein the address mapping relationship refers to a mapping relationship between a virtual address and a physical address, and the first virtual address is a virtual address corresponding to the data to be read in the data read instruction responded by the data forwarding module;
[0015] The virtual address matching unit matches the first virtual address with at least one virtual address in a buffer to obtain a virtual matching result corresponding to the first virtual address, wherein the virtual matching result is used to indicate a virtual address in the buffer that matches the first virtual address, and the buffer is located in the processor;
[0016] The physical address matching unit matches the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address, wherein the physical matching result is used to indicate a physical address in the buffer that matches the first physical address, and the virtual address and the physical address in the buffer follow the address mapping relationship;
[0017] When the virtual matching result matches the physical matching result, the address selection unit obtains data in a target virtual address according to the virtual matching result, where the target virtual address refers to a virtual address in the buffer that matches the first virtual address.
[0018] The technical solution provided in the embodiments of the present application can bring the following beneficial effects:
[0019] By using a virtual address matching unit to match the first virtual address with at least one virtual address in the buffer, a virtual matching result is obtained, so that the acquisition of the virtual matching result does not need to go through the address conversion unit, and can be executed synchronously with the conversion process of the address conversion unit, thereby reducing the delay of one clock cycle. And by matching the virtual matching result with the physical matching result, when the virtual matching result and the physical matching result match, the address selection unit outputs the data in the target virtual address, so that the processing process of the address selection unit only needs to go through the output delay of the virtual address matching unit, and does not need to go through the output delay of the physical address matching unit. Compared with the solutions in the related art, the delay of one clock cycle is reduced in the overall data forwarding process, the data loading process is shortened, and the processing efficiency of the data forwarding module is improved, thereby improving the efficiency of data forwarding. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic diagram of a data forwarding module applied to a processor provided by the related art;
[0021] Figure 2 is a schematic diagram of a data forwarding module applied to a processor provided by an embodiment of the present application;
[0022] Figure 3 This is a schematic diagram of a one-to-one correspondence of address mapping relationships provided by an embodiment of the present application;
[0023] Figure 4 It is a structural diagram of a data forwarding module applied to a processor provided by an embodiment of the present application;
[0024] Figure 5 It is a schematic diagram of an address mapping relationship in which multiple virtual addresses are mapped to the same physical address provided by an embodiment of the present application;
[0025] Figure 6 It is a schematic diagram of a mismatch between a virtual matching result and a physical matching result provided by an embodiment of the present application;
[0026] Figure 7 It is a flowchart of a data forwarding method applied to a data forwarding module provided by an embodiment of the present application. DETAILED DESCRIPTION
[0027] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0028] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.
[0029] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.
[0030] With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless cars, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (Artificial Intelligence Generated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, virtual reality (Virtual Reality, VR), augmented reality (Augmented Reality, AR), etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.
[0031] The technical solution of this application mainly relates to the development and design of AI processors in artificial intelligence technology, and mainly to data forwarding modules applied to processors.
[0032] Data forwarding refers to passing data from the execution stage of the previous instruction to the current instruction for use, thereby reducing pipeline pauses and improving instruction execution efficiency.
[0033] In the embodiment of the present application, the program of the processor preferentially executes the data storage instruction, which is used to store the data in a certain register to a virtual address, such as the data storage instruction store X1, C, which is used to store the data in the X1 register to the C address, where C is a virtual address. The data storage instruction is followed by a data read instruction, which is used to read data from a certain virtual address to a register, such as the data read instruction load X2, A, which is used to read data from the A address to the X2 register, where A is a virtual address.
[0034] Since the data written by the data storage instruction has not yet entered the lower-level cache and is still staying in the processor's buffer, when the data read instruction is executed in the processor, the data can be read directly from the virtual address of the buffer, thereby reducing the pause between the execution of the data storage instruction and the execution of the data read instruction and improving the execution efficiency of the instruction.
[0035] In the related art, reference can be made to Figure 1 The schematic diagram of the data forwarding module shown in the figure includes an address generation unit, an address conversion unit, a physical address matching unit and an address selection unit. The address generation unit is used to generate a virtual address where the data to be read by the data read instruction is located according to the address information contained in the data read instruction; the address conversion unit is used to determine the physical address corresponding to the virtual address according to the mapping relationship between the virtual address and the physical address; the physical address matching unit is used to match the obtained physical address with each physical address in the buffer to obtain a physical address in the buffer that matches the physical address; the address selection unit is used to obtain the data stored in the buffer according to the matched physical address, that is, the forwarding data output by the data forwarding module.
[0036] However, in the above data forwarding process, after the S0 stage obtains the virtual address, it needs to be delayed by one clock cycle before being sent to the S1 stage. After the S1 stage obtains the converted physical address, it needs to be delayed by one clock cycle before being sent to the S2 stage. After the S2 stage obtains the matching result, it needs to be delayed by one clock cycle before being sent to the S3 stage, and finally the forwarded data is obtained. The delay of the data forwarding pipeline is relatively long, and the data read instruction is the core instruction executed by the processor. Any operation completed by the processor depends on the loading of external data by the data read instruction. The long pipeline delay has a greater impact on the overall performance of the processor.
[0037] Please refer to Figure 2 , which shows a schematic diagram of a data forwarding module applied to a processor provided by an embodiment of the present application. The data forwarding module can be a unit of a pure hardware structure, which can be set on the chip of the processor. The data forwarding module includes: an address conversion unit 20, an address matching unit and an address selection unit 40, and the address matching unit includes a virtual address matching unit 31 and a physical address matching unit 32.
[0038] In some embodiments, the data forwarding module further includes an address generation unit 10; the address generation unit 10 is used to generate a first virtual address according to address information contained in a data read instruction, and the data read instruction is used to read data from the first virtual address.
[0039] The data read instruction is used to read data from a certain virtual address into a register. The address information is information used to indicate the first virtual address. Exemplarily, the address generation unit may be an AGU, and the address generation unit is used to add the source operand indexed by the first virtual address in the register and the sign-bit extended immediate value to generate the first virtual address corresponding to the data read instruction.
[0040] The virtual address is not the actual memory address running on the processor, but a logical value. When writing a virtual address, you do not need to consider address allocation and it is decoupled from the specific ring. Each virtual address exists independently, so when writing a virtual address, you do not need to worry about the memory space being occupied or overwritten.
[0041] like Figure 2 As shown, after the first virtual address is generated in the S0 stage, it needs to be delayed by one clock cycle before being sent to the S1 stage.
[0042] The address conversion unit 20 is used to determine the physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship; wherein the address mapping relationship refers to the mapping relationship between the virtual address and the physical address, and the first virtual address is the virtual address corresponding to the data to be read in the data read instruction responded by the data forwarding module.
[0043] The physical address is the real address in the processor, which is also a data logically. The physical address is the storage unit on the processor.
[0044] Normally, there is a one-to-one mapping between virtual addresses and physical addresses. Figure 3 As shown, virtual address A corresponds to physical address B, virtual address B corresponds to physical address D, virtual address C corresponds to physical address C, and virtual address D corresponds to physical address A.
[0045] The address conversion unit determines a physical address corresponding to the first virtual address according to the address mapping relationship, which is referred to as a first physical address. The first physical address is a physical address corresponding to the first virtual address.
[0046] The data read instruction is used to read data from the first virtual address. The first virtual address is the virtual address corresponding to the storage of the data to be read in the data read instruction. It can also be understood as the processor reading data from the first physical address into a register.
[0047] Exemplarily, the address translation unit may be a DTLB or a TLB (Translation Lookaside Buffer).
[0048] like Figure 2 As shown, after the first physical address corresponding to the first virtual address is determined in the S1 stage, it needs to be delayed by one clock cycle before being sent to the S2 stage.
[0049] The virtual address matching unit 31 is used to match the first virtual address with at least one virtual address in the buffer to obtain a virtual matching result corresponding to the first virtual address. The virtual matching result is used to indicate a virtual address in the buffer that matches the first virtual address. The buffer is located in the processor.
[0050] Match the first virtual address with at least one virtual address in the buffer, specifically compare the first virtual address with at least one virtual address in the buffer, obtain a virtual address in the at least one virtual address in the buffer that is the same as the first virtual address, and use the same virtual address as the virtual matching result.
[0051] Exemplarily, a CAM (Content-addressable memory) may be used to compare the first virtual address with at least one virtual address in the buffer entry by entry to see if they match.
[0052] like Figure 2As shown, the virtual address matching unit 31 can be completed in the same stage as the address conversion unit 20. After obtaining the first virtual address output in the S0 stage, the address conversion unit 20 determines the first physical address corresponding to the first virtual address according to the address mapping relationship. At the same time, the virtual address matching unit 31 matches the first virtual address with at least one virtual address in the buffer to obtain a virtual matching result corresponding to the first virtual address. After the first physical address is determined in the S1 stage, and the virtual matching result is determined, it needs to be delayed by one clock cycle before being sent to the S2 stage.
[0053] By processing two tasks in parallel in one stage, the task of the virtual address matching unit is placed in the S1 stage, avoiding the pipeline structure from generating a delay of another clock cycle and improving the efficiency of data forwarding.
[0054] The physical address matching unit 32 is used to match the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address. The physical matching result is used to indicate the physical address in the buffer that matches the first physical address. The virtual address and the physical address in the buffer follow an address mapping relationship.
[0055] Match the first physical address and at least one physical address in the buffer, specifically compare the first physical address and at least one physical address in the buffer, obtain the physical address in the at least one physical address in the buffer that is the same as the first physical address, and use the same physical address as the physical matching result.
[0056] The virtual address and the physical address in the buffer follow an address mapping relationship. In some embodiments, the processor stores at least one virtual address in the buffer. It is necessary to first convert the at least one virtual address in the buffer into corresponding physical addresses according to the address mapping relationship, and then match the first physical address with the physical addresses in the buffer to obtain a physical matching result.
[0057] Exemplarily, the CAM may compare the first physical address with at least one physical address in the buffer entry by entry to see whether they match.
[0058] like Figure 2As shown, in the S1 stage, the virtual matching result and the physical matching result are matched to determine whether the virtual matching result and the physical matching result match each other. If the virtual matching result and the physical matching result match each other, it means that the virtual address indicated by the virtual matching result and the physical address indicated by the physical matching result follow the address mapping relationship, that is, the virtual address indicated by the virtual matching result and the physical address indicated by the physical matching result indicate the same address. If the virtual matching result and the physical matching result do not match each other, it means that the virtual address indicated by the virtual matching result and the physical address indicated by the physical matching result do not follow the address mapping relationship, that is, the virtual address indicated by the virtual matching result and the physical address indicated by the physical matching result do not indicate the same address.
[0059] The address selection unit 40 is used to obtain data in a target virtual address according to the virtual matching result when the virtual matching result matches the physical matching result, where the target virtual address refers to a virtual address in the buffer that matches the first virtual address.
[0060] The target virtual address is the virtual address indicated by the virtual matching result when the virtual matching result matches the physical matching result, that is, the virtual address in the at least one virtual address in the buffer that matches the first virtual address.
[0061] like Figure 2 As shown, the address selection unit 40 can be completed in the same stage as the physical address matching unit 32. In the S2 stage, after obtaining the first physical address output by the address conversion unit 20 in the S1 stage, the physical address matching unit 32 matches the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address. Then, in the S2 stage, according to the virtual matching result output by the virtual address matching unit 31 in the S1 stage, the virtual matching result and the physical matching result are matched to determine whether the virtual address indicated by the virtual matching result and the physical address indicated by the physical matching result indicate the same address. In the case where the virtual matching result and the physical matching result match, the address selection unit 40 obtains the data in the target virtual address as the output data of the data forwarding module.
[0062] By processing multiple tasks in one stage, the processing process of the address selection unit and the processing process of the physical address matching unit are placed in the same stage, avoiding the delay of one clock cycle for the processing process of the address selection unit after the processing process of the physical address matching unit is completed, thereby reducing the delay of one clock cycle and improving the efficiency of data forwarding.
[0063] The technical solution provided by the embodiment of the present application uses a virtual address matching unit to match the first virtual address and at least one virtual address in the buffer to obtain a virtual matching result, so that the acquisition of the virtual matching result does not need to go through the address conversion unit, and can be executed synchronously with the conversion process of the address conversion unit, reducing the delay of one clock cycle. And by matching the virtual matching result with the physical matching result, when the virtual matching result and the physical matching result match, the address selection unit outputs the data in the target virtual address, so that the processing process of the address selection unit only needs to go through the output delay of the virtual address matching unit, and does not need to go through the output delay of the physical address matching unit. Compared with the solution in the related art, the delay of one clock cycle is reduced in the overall data forward delivery process, the data loading process is shortened, and the processing efficiency of the data forward delivery module is improved, thereby improving the efficiency of data forward delivery.
[0064] Please refer to Figure 4 , which shows a schematic diagram of the structure of a data forwarding module applied to a processor provided by an embodiment of the present application. The data forwarding module can be a unit of a pure hardware structure, which can be set on the chip of the processor. The data forwarding module includes: an address conversion unit, an address matching unit and an address selection unit, and the address matching unit includes a virtual address matching unit and a physical address matching unit.
[0065] In the S1 stage, the address conversion unit is used to determine a physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship.
[0066] In the S1 stage, the virtual address matching unit is used to match the first virtual address with at least one virtual address in the buffer to obtain a virtual matching result corresponding to the first virtual address.
[0067] In some embodiments, the status information of the virtual address in the buffer includes: a valid state, an invalid state, and a flight state; the valid state means that data is stored in the entry of the virtual address, and the entry refers to a storage unit in the virtual address; the invalid state means that no data is stored in the entry of the virtual address; the flight state means that the data in the entry of the virtual address is in a state of requesting a lower-level cache.
[0068] Each virtual address contains at least one entry, and each entry is a storage unit in the virtual address. For example, a virtual address may contain entry0, entry1, entry2, etc. The status information of the virtual address in the buffer refers to the status information of each entry in the virtual address in the buffer, including valid status, invalid status, and inflight status, wherein the valid status means that data is stored in the entry, the invalid status means that no data is stored in the entry, and the inflight status means that the data in the entry is requesting the lower-level cache.
[0069] The virtual address matching unit is used to perform a bitwise AND operation on the target virtual address and the state information of the target virtual address to obtain a state matching result, and the state matching result is used to indicate the storage entry corresponding to the data to be read in the target virtual address.
[0070] Among them, the state matching results include valid matching results corresponding to the valid state and in-flight matching results corresponding to the in-flight state. The valid matching results are used to indicate the hit status of each entry in the target virtual address in the valid state, and the in-flight matching results are used to indicate the hit status of each entry in the target virtual address in the in-flight state.
[0071] The target virtual address here refers to the virtual address indicated by the virtual matching result. The virtual address matching unit is used to perform bitwise AND operations on the target virtual address and each entry in the target virtual address to obtain a state matching effect, so that entries in a valid state and entries in a flying state can be selected from the target virtual address.
[0072] Exemplarily, the valid state may be marked as 1 and other states may be marked as 0, and then a bitwise AND operation may be performed on the target virtual address and the state information of the target virtual address to obtain a valid matching result, which may indicate an entry in the target virtual address that is in a valid state.
[0073] Exemplarily, the flight status can be marked as 1 and other statuses can be marked as 0. Then, after a bitwise AND operation is performed on the target virtual address and the status information of the target virtual address, a flight matching result can be obtained, which can indicate the entries in the target virtual address that are in the flight status.
[0074] The valid matching results and the flying matching results may be in vector form.
[0075] In the S2 stage, the physical address matching unit is used to match the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address.
[0076] In the S2 stage, the address selection unit is used to use a multiplexer to obtain data in entries in a valid state and data in entries in a flying state in the target virtual address according to the virtual matching result and the state matching result when the virtual matching result and the physical matching result match.
[0077] A multiplexer is used to obtain data in an entry in a valid state in the target virtual address according to a virtual match result and a valid match result, and to obtain data in an entry in a flying state in the target virtual address according to a virtual match result and a flying match result.
[0078] Exemplarily, the multiplexer may be a mux-oh (multiplixer onehot, a multiplexer based on one-hot code).
[0079] Then the multiplexer outputs a valid signal according to the virtual match result and the valid match result, and the valid signal is used to indicate the entry in the target virtual address that is in a valid state. According to the valid signal, valid data is obtained, that is, data in the entry in the target virtual address that is in a valid state is obtained. And the multiplexer outputs a flight signal according to the virtual match result and the flight match result, and the flight signal is used to indicate the entry in the target virtual address that is in a flight state. According to the flight signal, flight data is obtained, that is, data in the entry in the target virtual address that is in a flight state is obtained.
[0080] In some embodiments, if there is no entry in the target virtual address that is in a valid state, the output data of the address selection unit includes data in the entry in the target virtual address that is in a flying state.
[0081] If there is no entry in a valid state in the target virtual address, but there is an entry in a flying state, it means that the data in the entry in the valid state in the target virtual address cannot be obtained, so the output data of the address selection unit only includes the data in the entry in the flying state in the target virtual address.
[0082] In some embodiments, if there is no entry in the target virtual address that is in the in-flight state, the output data of the address selection unit includes data in the entry in the target virtual address that is in the valid state.
[0083] If there is no entry in the in-flight state in the target virtual address, but there is an entry in the valid state, it means that the data in the entry in the in-flight state in the target virtual address cannot be obtained, so the output data of the address selection unit only includes the data in the entry in the valid state in the target virtual address.
[0084] In some embodiments, if there are entries in a valid state and entries in a flight state in the target virtual address, the output data of the address selection unit is merged data, which includes data in the entry in the flight state in the target virtual address and data in the entry in the valid state in the target virtual address, wherein the data in the entry in the valid state has a higher priority than the data in the entry in the flight state.
[0085] If there are entries in a valid state and entries in a flying state in the target virtual address, the output data of the address selection unit includes the data in the entry in the flying state in the target virtual address and the data in the entry in the valid state in the target virtual address. And because the priority of the data in the entry in the valid state is higher than the data in the flying state, the data in the entry in the valid state will be in front of the merged data, that is, the structure of the merged data is: the data in the entry in the valid state + the data in the entry in the flying state, and the data in the entry in the valid state will be output first.
[0086] like Figure 4 As shown, in the S0 stage, according to the data read instruction, a first virtual address (forward.req.vaddr) is generated, that is, the query address of the forward data. In the S1 stage, the first virtual address is matched with at least one virtual address (buffer.vtag) in the buffer to obtain a virtual matching result (vtag_match_bmap), that is, which entries (entries) the first virtual address matches. The status information (buffer.status) of the virtual address has three states: valid state, invalid state and flight state, wherein the valid state and the flight state are stored with data. The target virtual address and the status information of the valid state of the target virtual address, as well as the status information of the flight state are respectively subjected to a bitwise and operation to obtain a valid matching result and a flight matching result. The valid matching result indicates the hit of the entry in the valid state, and the flight matching result indicates the hit of the entry in the flight state.
[0087] In the S2 stage, mux-oh is used to select data and obtain selection signals, including valid signals (valid_mask) and inflight signals (inflght_mask). Valid data (valid_data) is obtained according to the valid signals, and inflight data (inflight_data) is obtained according to the inflight signals. The valid data and inflight data are merged to obtain merged data (bytebased merge), that is, a byte-based merge unit. Since the entry data in the valid state is the latest stored, the data in the entry in the valid state in the merged data has a higher priority than the data in the entry in the inflight state, and finally the output data (forward.resp) is obtained.
[0088] In the S2 stage, the first physical address (forward.req.paddr) is matched with at least one physical address (buffer.ptag) in the buffer to obtain a physical matching result (ptag_match_bmap). The virtual matching result and the physical matching result are compared. If the two follow the address mapping relationship, it means that the address indicated by the virtual matching result and the physical matching result is the same address, and the address selection unit outputs the forward data. If the two do not follow the address mapping relationship, it means that the address indicated by the virtual matching result and the physical matching result is not the same address, indicating that the reading of the forward data indicated by the first virtual address is incorrect, and redirection is required to flush the entire pipeline.
[0089] like Figure 5 The example shows a situation where multiple virtual addresses are mapped to the same physical address. Both virtual address A and virtual address C have a mapping relationship with physical address B. In this case, the virtual matching result and the physical matching result do not match. Figure 6 As shown, the data storage instruction is store X1,C, and the data read instruction is load X2,A. Store X1,C needs to store the value of the X1 register to the C address, and load X2,A needs to read data from the A address to the X2 register. Figure 5 In the address mapping table shown, both virtual address A and virtual address C are mapped to physical address B, which means that the data read by the data read instruction is the data written by the data storage instruction.
[0090] The data storage module responds to the data storage instruction. If the data written by the data storage instruction has not entered the lower-level cache at this time and is still staying in the processor's buffer, then the virtual address of the stored data in the buffer is C, and the corresponding physical address is B. The data forwarding module responds to the data read instruction, and first uses the virtual address A in the data read instruction and the virtual address C in the buffer for matching. The result is that A and C do not match, indicating that the data forwarding module will not generate data forwarding. The corresponding physical address B in the data read instruction is matched with the physical address B in the buffer. The result is that the physical addresses match, indicating that the data forwarding module needs to generate data forwarding. As a result, the virtual matching result and the physical matching result do not match, and redirection is required to flush the entire pipeline.
[0091] Redirection means that the data forwarding module re-responds to the data read instruction, that is, after a period of time, the data forwarding module re-forwards the data according to the data read instruction. At this time, if the virtual matching result and the physical matching result still do not match, the redirection will continue. It is also possible that the data stored in the entry in the virtual address has entered the lower-level cache within the interval time period, and the entry in the target virtual address matched by the first virtual address in the buffer is in an invalid state, indicating that the data forwarding module cannot respond to the data read instruction, that is, it is impossible to obtain the data to be read by the data read instruction through data forwarding.
[0092] In some embodiments, when the virtual matching result and the physical matching result do not match, if the entry in the target virtual address is in an invalid state, the data forwarding module cannot forward the data.
[0093] like Figure 6 As shown, if after redirection, the data stored in the virtual address B in the buffer has entered the lower-level cache within the interval time period, the entry in the target virtual address is in an invalid state, and the data read instruction cannot obtain data from the buffer, indicating that the data forward delivery module cannot perform data forward delivery.
[0094] The following is an embodiment of the method of the present application. For details not described in detail in the embodiment of the method of the present application, please refer to the above embodiment of the data forwarding module.
[0095] Please refer to Figure 7 , which shows a flow chart of a data forwarding method applied to a data forwarding module provided by an embodiment of the present application, the method is applied to the data forwarding module applied to the processor introduced above, the data forwarding module includes: an address conversion unit, an address matching unit and an address selection unit, the address matching unit includes a virtual address matching unit and a physical address matching unit. The method may include at least one of the following steps 710 to 740.
[0096] In step 710, the address conversion unit determines the physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship; wherein the address mapping relationship refers to the mapping relationship between the virtual address and the physical address, and the first virtual address is the virtual address corresponding to the data to be read in the data read instruction responded by the data forwarding module.
[0097] In some embodiments, the data forwarding module further includes an address generating unit; the address generating unit generates a first virtual address according to address information contained in a data read instruction, and the data read instruction is used to read data from the first virtual address.
[0098] Step 720, the virtual address matching unit matches the first virtual address with at least one virtual address in the buffer to obtain a virtual matching result corresponding to the first virtual address, the virtual matching result is used to indicate a virtual address in the buffer that matches the first virtual address, and the buffer is located in the processor.
[0099] In some embodiments, the status information of the virtual address in the buffer includes: a valid state, an invalid state, and a flight state; the valid state means that data is stored in the entry of the virtual address, and the entry refers to a storage unit in the virtual address; the invalid state means that no data is stored in the entry of the virtual address; the flight state means that the data in the entry of the virtual address is in a state of requesting a lower-level cache.
[0100] In some embodiments, the virtual address matching unit performs a bitwise AND operation on the target virtual address and the state information of the target virtual address to obtain a state matching result, and the state matching result is used to indicate the entry stored corresponding to the data to be read in the target virtual address. The state matching result includes a valid matching result corresponding to the valid state and a flying matching result corresponding to the flying state, and the valid matching result is used to indicate the hit situation of each entry in the target virtual address in the valid state, and the flying matching result is used to indicate the hit situation of each entry in the target virtual address in the flying state.
[0101] Step 730, the physical address matching unit matches the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address. The physical matching result is used to indicate a physical address in the buffer that matches the first physical address. The virtual address and the physical address in the buffer follow an address mapping relationship.
[0102] Step 740 , when the virtual matching result matches the physical matching result, the address selection unit obtains data in the target virtual address according to the virtual matching result, where the target virtual address refers to a virtual address in the buffer that matches the first virtual address.
[0103] In some embodiments, when the virtual matching result and the physical matching result match, the address selection unit uses a multiplexer to obtain data in the entry in the target virtual address that is in a valid state and data in the entry in the target virtual address that is in a flying state according to the virtual matching result and the state matching result.
[0104] In some embodiments, if there is no entry in a valid state in the target virtual address, the output data of the address selection unit includes the data in the entry in the target virtual address in the in-flight state; if there is no entry in the in-flight state in the target virtual address, the output data of the address selection unit includes the data in the entry in the target virtual address in the valid state; if there are entries in a valid state and entries in the in-flight state in the target virtual address, the output data of the address selection unit is merged data, and the merged data includes the data in the entry in the in-flight state in the target virtual address and the data in the entry in the valid state in the target virtual address, wherein the data in the entry in the valid state has a higher priority than the data in the entry in the in-flight state.
[0105] In some embodiments, when the virtual matching result and the physical matching result do not match, if the entry in the target virtual address is in an invalid state, the data forwarding module cannot forward the data.
[0106] The technical solution provided by the embodiment of the present application uses a virtual address matching unit to match the first virtual address and at least one virtual address in the buffer to obtain a virtual matching result, so that the acquisition of the virtual matching result does not need to go through the address conversion unit, and can be executed synchronously with the conversion process of the address conversion unit, reducing the delay of one clock cycle. And by matching the virtual matching result with the physical matching result, when the virtual matching result and the physical matching result match, the address selection unit outputs the data in the target virtual address, so that the processing process of the address selection unit only needs to go through the output delay of the virtual address matching unit, and does not need to go through the output delay of the physical address matching unit. Compared with the solution in the related art, the delay of one clock cycle is reduced in the overall data forward delivery process, the data loading process is shortened, and the processing efficiency of the data forward delivery module is improved, thereby improving the efficiency of data forward delivery.
[0107] An exemplary embodiment of the present application further provides a processor, which includes the data forwarding module introduced in the above embodiment.
[0108] An exemplary embodiment of the present application further provides a computer device, the computer device comprising a processor, and the processor comprising the data forwarding module introduced in the above embodiment.
[0109] Optionally, the processor is an AI processor, or other processor that requires data forwarding operations, which is not limited in this application.
[0110] Optionally, the computer device can be a server, or a terminal device such as a mobile phone, a tablet computer, a vehicle-mounted terminal, a wearable device, a smart home device, or any device that is applied to a processor, such as a robot or a base station, and this application does not limit this.
[0111] It should be noted that, before collecting the relevant data of the user and during the process of collecting the relevant data of the user, the present application can display a prompt interface, a pop-up window or output a voice prompt information, and the prompt interface, pop-up window or voice prompt information is used to prompt the user that the relevant data is currently being collected, so that the present application only starts to execute the relevant steps of obtaining the relevant data of the user after obtaining the confirmation operation issued by the user to the prompt interface or pop-up window, otherwise (that is, when the confirmation operation issued by the user to the prompt interface or pop-up window is not obtained), the relevant steps of obtaining the relevant data of the user are terminated, that is, the relevant data of the user is not obtained. In other words, all user data collected by the present application (including data stored in the buffer) are processed strictly in accordance with the requirements of the laws and regulations of the relevant countries, and the informed consent or separate consent of the subject of personal information is obtained with the consent and authorization of the user. The subsequent data use and processing behavior is carried out within the scope of authorization of laws and regulations and the subject of personal information, and the collection, use and processing of relevant user data shall comply with the relevant laws, regulations and standards of the relevant countries and regions.
[0112] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.
[0113] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A data forwarding module applied to a processor, characterized in that: The data forwarding module includes: an address conversion unit, an address matching unit and an address selection unit, wherein the address matching unit includes a virtual address matching unit and a physical address matching unit; The address conversion unit is used to determine a physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship; wherein the address mapping relationship refers to a mapping relationship between a virtual address and a physical address, and the first virtual address is a virtual address corresponding to the data to be read in the data read instruction responded by the data forwarding module; The virtual address matching unit is used to match the first virtual address with at least one virtual address in a buffer to obtain a virtual matching result corresponding to the first virtual address, wherein the virtual matching result is used to indicate a virtual address in the buffer that matches the first virtual address, and the buffer is located in the processor; The physical address matching unit is used to match the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address, wherein the physical matching result is used to indicate a physical address in the buffer that matches the first physical address, and the virtual address and the physical address in the buffer follow the address mapping relationship; The address selection unit is used to obtain data in a target virtual address according to the virtual matching result when the virtual matching result matches the physical matching result, and the target virtual address refers to a virtual address in the buffer that matches the first virtual address.
2. The data forwarding module according to claim 1, characterized in that: The state information of the virtual address in the buffer includes: valid state, invalid state and flying state; The valid state means that data is stored in the entry of the virtual address, and the entry refers to a storage unit in the virtual address; The invalid state means that no data is stored in the entry of the virtual address; The in-flight state refers to a state in which the data in the entry of the virtual address is in a requesting lower-level cache.
3. The data forwarding module according to claim 2, characterized in that: The virtual address matching unit is used to perform a bitwise AND operation on the target virtual address and the state information of the target virtual address to obtain a state matching result, wherein the state matching result is used to indicate an entry stored corresponding to the data to be read in the target virtual address; Among them, the state matching result includes a valid matching result corresponding to the valid state and a flight matching result corresponding to the flight state, the valid matching result is used to indicate the hit status of each entry in the target virtual address in the valid state, and the flight matching result is used to indicate the hit status of each entry in the target virtual address in the flight state.
4. The data forwarding module according to claim 3, characterized in that: The address selection unit is used to use a multiplexer to respectively obtain data in an entry in a valid state and data in an entry in a flying state in the target virtual address according to the virtual matching result and the state matching result when the virtual matching result and the physical matching result match.
5. The data forwarding module according to claim 4, characterized in that: If there is no entry in the target virtual address that is in a valid state, the output data of the address selection unit includes data in the entry in the target virtual address that is in a flying state; If there is no entry in the in-flight state in the target virtual address, the output data of the address selection unit includes data in the entry in the valid state in the target virtual address; If there are entries in a valid state and entries in a flight state in the target virtual address, the output data of the address selection unit is merged data, and the merged data includes data in the entry in the flight state in the target virtual address and data in the entry in the valid state in the target virtual address, wherein the data in the entry in the valid state has a higher priority than the data in the entry in the flight state.
6. The data forwarding module according to claim 1, characterized in that: The data forwarding module also includes an address generating unit; The address generation unit is used to generate the first virtual address according to the address information contained in the data read instruction, and the data read instruction is used to read data from the first virtual address.
7. The data forwarding module according to any one of claims 1 to 6, characterized in that: In the case where the virtual matching result does not match the physical matching result, if the entry in the target virtual address is in an invalid state, the data forwarding module cannot perform data forwarding.
8. A processor, characterized in that: The processor comprises a data forwarding module as described in any one of claims 1 to 7.
9. A computer device, characterized in that: The computer device comprises a processor, and the processor comprises the data forwarding module as described in any one of claims 1 to 7.
10. A data forwarding method applied to a data forwarding module, characterized in that: The data forwarding module includes: an address conversion unit, an address matching unit and an address selection unit, wherein the address matching unit includes a virtual address matching unit and a physical address matching unit; the method includes: The address conversion unit determines a physical address corresponding to the first virtual address as the first physical address according to the address mapping relationship; wherein the address mapping relationship refers to a mapping relationship between a virtual address and a physical address, and the first virtual address is a virtual address corresponding to the data to be read in the data read instruction responded by the data forwarding module; The virtual address matching unit matches the first virtual address with at least one virtual address in a buffer to obtain a virtual matching result corresponding to the first virtual address, wherein the virtual matching result is used to indicate a virtual address in the buffer that matches the first virtual address, and the buffer is located in the processor; The physical address matching unit matches the first physical address with at least one physical address in the buffer to obtain a physical matching result corresponding to the first physical address, wherein the physical matching result is used to indicate a physical address in the buffer that matches the first physical address, and the virtual address and the physical address in the buffer follow the address mapping relationship; When the virtual matching result matches the physical matching result, the address selection unit obtains data in a target virtual address according to the virtual matching result, where the target virtual address refers to a virtual address in the buffer that matches the first virtual address.
11. The method according to claim 10, characterized in that The state information of the virtual address in the buffer includes: valid state, invalid state and flying state; The valid state means that data is stored in the entry of the virtual address, and the entry refers to a storage unit in the virtual address; The invalid state means that no data is stored in the entry of the virtual address; The in-flight state refers to a state in which the data in the entry of the virtual address is in a requesting lower-level cache.
12. The method according to claim 11, characterized in that The method further comprises: The virtual address matching unit performs a bitwise AND operation on the target virtual address and the state information of the target virtual address to obtain a state matching result, wherein the state matching result is used to indicate an entry stored corresponding to the data to be read in the target virtual address; Among them, the state matching result includes a valid matching result corresponding to the valid state and a flight matching result corresponding to the flight state, the valid matching result is used to indicate the hit status of each entry in the target virtual address in the valid state, and the flight matching result is used to indicate the hit status of each entry in the target virtual address in the flight state.
13. The method according to claim 12, characterized in that The address selection unit, when the virtual matching result matches the physical matching result, acquires data in the target virtual address according to the virtual matching result, including: When the virtual matching result and the physical matching result match, the address selection unit uses a multiplexer to obtain the data in the entry in the valid state and the data in the entry in the in-flight state in the target virtual address according to the virtual matching result and the state matching result.
14. The method according to claim 13, characterized in that If there is no entry in the target virtual address that is in a valid state, the output data of the address selection unit includes data in the entry in the target virtual address that is in a flying state; If there is no entry in the in-flight state in the target virtual address, the output data of the address selection unit includes data in the entry in the valid state in the target virtual address; If there are entries in a valid state and entries in a flight state in the target virtual address, the output data of the address selection unit is merged data, and the merged data includes data in the entry in the flight state in the target virtual address and data in the entry in the valid state in the target virtual address, wherein the data in the entry in the valid state has a higher priority than the data in the entry in the flight state.
15. The method according to claim 10, characterized in that The data forwarding module further includes an address generating unit; the method further includes: The address generation unit generates the first virtual address according to the address information included in the data read instruction, and the data read instruction is used to read data from the first virtual address.
16. The method according to any one of claims 10 to 15, characterized in that In the case where the virtual matching result does not match the physical matching result, if the entry in the target virtual address is in an invalid state, the data forwarding module cannot perform data forwarding.