A Chip with a Many-Core Architecture of Network-on-Chip and Its Data Processing Method

Abstract

The present invention provides a many-core architecture chip on a chip and its data processing method, which relates to the technical field of data communication and is used to solve the technical problem of limited ability to support service characteristics based on the many-core architecture on a chip. The present invention virtualizes multiple physical firmware micro-cores into a logical firmware micro-core, and each physical firmware micro-core is equivalent to a hardware thread of the logical firmware micro-core. The instruction codes of multiple service characteristics to be run on the logical firmware micro-core are divided into multiple task groups, and each physical firmware micro-core only runs the instruction codes in one task group among the multiple task groups, so that the codes of different task groups are distributed on different physical firmware micro-cores in the logical firmware micro-core, thereby realizing the support for multiple service characteristics while reducing the resource requirements of each firmware micro-core for IRAM and DRAM.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular, to a many-core architecture chip on a chip network and a data processing method thereof. Background Art

[0002] How to achieve higher forwarding performance at lower cost (smaller chip area, lower power consumption) is a persistent problem faced by data communication chips used in data communication devices such as routers and switches. With the accelerating development of network technology, the processing performance requirements for data communication chips are getting higher and higher. It has become difficult to keep up with the requirements of network applications by simply increasing the hardware clock frequency and improving the chip performance in a scale-out manner.

[0003] The Network on Chip (NOC) architecture, with its good scalability, has become a technical means for chip designers to improve the performance of data communication chips in a scale-out manner when it is difficult to continuously improve the hardware performance in a scale-up manner.

[0004] The application document with the application number 201510507293.7, the application publication date of December 30, 2015, the publication number of CN105207957A, and the title of "A Multi-core Architecture on a Chip Network" is the closest prior art to the present invention. This prior art discloses a multi-core architecture on a chip network, including a multi-core architecture ontology on a chip network. The multi-core architecture ontology on a chip network includes multiple computing units, routers, and network interfaces. The multiple computing units are connected through routers and network interfaces to achieve parallel data processing and data interaction. One of the computing units serves as the main control core node, and the remaining computing units serve as operation core nodes. The main control core node is responsible for data exchange with the outside of the chip, and the operation core nodes transmit data to the main control core node, and the main control core node completes data exchange with the outside of the chip; the storage spaces in the multiple computing units adopt unified addressing, so that the cores in each computing unit can access the storage spaces in any other computing unit.

[0005] The above closest prior art has the following technical defects:

[0006] In order to control the power consumption and cost of the entire chip, only a small amount of IRAM and DRAM are integrated in the computing units / firmware micro-cores in the NOC architecture. The limited memory resources result in a great limitation on the ability of the data communication chip based on the many-core architecture on a chip network to support different service characteristics. Summary of the Invention

[0007] In view of this, the present invention provides a many-core architecture chip on a chip network and a data processing method thereof, which are used to solve the technical problem that the ability of the many-core architecture on a chip network to support service characteristics is limited.

[0008] On one aspect of the embodiments of the present invention, the present invention provides a many-core architecture chip for network-on-chip, comprising:

[0009] A logical firmware microkernel, which includes a plurality of physical firmware microkernels (Firmware microkernel, FW), and the plurality of physical firmware microkernels respectively support the service characteristics in different task groups (task_group), one task group includes one or more service characteristics, and different task groups include different service characteristics;

[0010] A logical multi-homed task engine, which includes a plurality of physical task engines (Task Engine, TE), and the physical task engine hardware solidifies the basic packet processing (PP) action, which is used to perform hardware acceleration on the message processing process of the service characteristics orchestrated by the physical firmware microkernel; each physical task engine is controlled by each physical firmware microkernel in the logical firmware microkernel;

[0011] In the network-on-chip, the physical firmware microkernel and the physical task engine are connected to the network-on-chip router through the local port (LocalPort) of the network-on-chip router (NOCRouter).

[0012] Further, the total amount of instruction codes and the total amount of required data random access memory of the service characteristics in the task group do not exceed the capacity of the instruction random access memory (IRAM) and the data random access memory (DRAM) in the physical firmware microkernel;

[0013] The number of physical firmware microkernels included in the logical firmware microkernel is determined by the total amount of instruction random access memory and the total amount of data random access memory required for the service characteristics supported by the logical firmware microkernel and the capacity of the instruction random access memory and the data random access memory of the physical firmware microkernel.

[0014] Further, each network-on-chip router (NOC Router) in the network-on-chip is connected to a physical firmware microkernel and a physical task engine through a local port;

[0015] The logical firmware microkernel and the logical multi-homed task engine are respectively composed of multiple pairs of physical firmware microkernels and physical task engines connected to the same network-on-chip router;

[0016] Each physical task engine in the logical multi-homed task engine is fully connected to each physical firmware microkernel in the logical firmware microkernel through the network-on-chip.

[0017] Further, the physical firmware microkernels in the logical firmware microkernel use a pipeline model to transmit commands to the physical task engines in the logical multi-homed task engine.

[0018] Further, the many-core architecture of the network-on-chip provides an orchestration and configuration interface for users. Through the orchestration and configuration interface, the message processing processes with different service characteristics in the task group are orchestrated, and several basic hardware-solidified basic packet processing (PP) actions are orchestrated and combined to achieve support for the service characteristics in the task group; and the service characteristics supported by each physical firmware microkernel in the logical firmware microkernel are configured (such as adding, deleting, modifying, etc.).

[0019] Further, the physical firmware microkernels in the logical firmware microkernel are a group of adjacent firmware microkernels in the network-on-chip. When configuring the logical firmware microkernel, the adjacent-nearest principle is adopted, and a group of adjacent physical firmware microkernels are configured as a logical firmware microkernel.

[0020] On the other hand based on the embodiments of the present invention, the present invention further provides a data processing method, which is applied to the network-on-chip many-core architecture chip provided by the present invention. The method includes:

[0021] When receiving a service request or service message of a certain service characteristic, route the service request or service message to the physical firmware microkernel that binds the service characteristic in the logical firmware microkernel that supports the service characteristic in the network-on-chip many-core architecture;

[0022] The physical firmware microkernel invokes one or more physical task engines in the logical multi-homing task engine based on the orchestrated service control logic to perform hardware acceleration on the message processing process of the service characteristic.

[0023] Further, the physical firmware microkernels in the logical firmware microkernel use a pipeline model to transfer commands to the physical task engines in the logical multi-homing task engine.

[0024] Further, receive the orchestration instructions sent by the user through the orchestration and configuration interface, and orchestrate the message processing process of the service characteristics supported by the physical firmware microkernel;

[0025] Receive the configuration instructions sent by the user through the orchestration and configuration interface, and configure the service characteristics supported by each physical firmware microkernel in the logical firmware microkernel.

[0026] Further, when the network-on-chip router receives a service request or service message of a certain service characteristic, use the position identifier of the network-on-chip router in the router matrix as the network address, and adopt a deterministic routing algorithm or an adaptive routing algorithm to route the service request or service message to the physical firmware microkernel that supports the service characteristic.

[0027] Based on the network-on-chip, the present invention virtualizes multiple physical firmware microkernels into one logical firmware microkernel, enabling the division of labor and cooperation among the physical firmware microkernels within the logical firmware microkernel group, and converting the one-to-one mapping between the physical firmware microkernel and the hardware acceleration module it manages, i.e., the physical task engine TE, into a many-to-many mapping relationship. Thus, when supporting the same number of service features, the demand of the physical firmware microkernel FW for the built-in IRAM and DRAM resources is effectively reduced, the power consumption of the chip is significantly reduced, and the chip area and cost are saved.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.

[0030] Figure 1 Schematic diagram of a many-core architecture of a network-on-chip with 4*4 router nodes adopted in an embodiment of the present invention;

[0031] Figure 2 Example diagram of routing based on the router position coordinates in a network-on-chip in an embodiment of the present invention;

[0032] Figure 3 Schematic diagram of the basic structure of a router in a many-core architecture of a network-on-chip used in an embodiment of the present invention;

[0033] Figure 4 Schematic diagram of a logical firmware microkernel in a many-core architecture of a network-on-chip in an embodiment of the present invention;

[0034] Figure 5 Schematic diagram of the binding relationship between a logical firmware microkernel and a task group in an embodiment of the present invention;

[0035] Figure 6 Schematic diagram of the binding relationship between a logical firmware microkernel and a task group in another embodiment of the present invention;

[0036] Figure 7 Schematic diagram of the step flow of a data processing method based on a many-core architecture of a network-on-chip provided in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0038] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit this specification. The singular forms "a", "the", and "that" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0039] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0040] For data communication chips, with the accelerating iteration and development of network technologies (user-level bandwidth guarantee, fine-grained network traffic profiling to support intelligent optimization of network parameters by AI artificial intelligence controllers), it is no longer sufficient to merely support the most basic L2 / L3 layer packet forwarding actions from a hardware perspective. Instead, more complex packet processing behaviors (packetprocess) need to be offloaded to the chip as much as possible to provide acceleration capabilities for more complex packet processing. For example: large-scale high-precision (3.3ms * 3) BFD (Bidirectional Forwarding Detection) / CFD (Connectivity Fault Detection) detection capabilities, millisecond-level telemetry information acquisition capabilities, high-performance SRV6 (Segment Routing over IPv6) tunnel processing capabilities, etc. If these capabilities are implemented by the host central processor (host CPU), the bottleneck is very obvious, while based on the NOC architecture and combined with the firmware microkernel (Firmware microkernel) technology, this bottleneck can be broken.

[0041] Figure 1 Schematic diagram of a many-core architecture of a network-on-chip containing 4*4 router nodes adopted in an embodiment of the present invention. In Figure 1 In the example 4*4 router matrix of the network-on-chip, each network-on-chip router (R) is connected to a physical FW (Firmware microkernel, firmware microkernel) and a physical TE (Task Engine, task engine) through a local interface (LocalPort). Assuming that each FW in the data communication chip based on this many-core architecture provides the processing capacity of 10 BFD sessions of 3.3ms*3, then the entire data communication chip can provide the processing capacity of 160 BFD sessions of 3.3ms*3. If the NOC scale is expanded to 10*10, it can provide the processing capacity of 1000 BFD sessions of 3.3ms*3, which far exceeds the maximum processing capacity that the host CPU can provide.

[0042] Figure 1 In the example network-on-chip many-core architecture, each physical firmware microkernel FW has programmable capabilities. Users can customize complex control logic, combine several basic hardware-solidified PP (Packet Process, packet processing) actions, and realize the support for the processing of more complex service characteristic messages. The physical task engine TE is used for the basic packet processing PP actions abstracted from the hardware solidification, such as implementing packet header encapsulation or lookup table algorithms and other PP actions at the RTL (Register Transfer Level, register transfer layer). That is, the FW realizes the control of the message processing process of the supported service characteristics based on the arranged control logic, and the TE, as a worker, executes the basic PP actions to realize the hardware acceleration of the message processing process of specific service characteristics.

[0043] For example, assume that the basic PP actions abstracted by the TE module include PP1, PP2, PP3, PP4, and PP5. Among them, the message processing flow of service characteristic 1 includes the packet processing actions of PP1->PP3->PP5. Then, the control logic of the message processing process of service characteristic 1 can be arranged on the FW, and TE is called in sequence to execute PP1, PP3, and PP5 to accelerate the message service processing process of service characteristic 1. The message processing flow of service characteristic 2 includes the packet processing actions of PP2->PP3->PP4. Then, the control logic of the message processing process of service characteristic 2 can be arranged on the FW, and TE is called in sequence to execute PP2, PP3, and PP4 to accelerate the message service processing process of service characteristic 2. Subsequently, if it is necessary to expand the support for more service characteristics, the message processing flow on the FW can be dynamically arranged and configured to realize the support for more services.

[0044] The programmable attributes of the FW can support the dynamic orchestration of processing flows for different service characteristics, enhancing the service scalability of data communication chips. TE can accelerate the packet processing performance by hardware-curing the PP actions. Therefore, Figure 1 The exemplary NOC-based many-core architecture can achieve a good balance between service flexibility and processing performance for the chip.

[0045] Figure 2 This is an example diagram of routing based on the position coordinates of an on-chip network router in an embodiment of the present invention. The routers in the on-chip network form a router matrix. The position identifier {X, Y} of the on-chip network router (NOC Router, abbreviated as Router) in the matrix can be used as the address of the router and the FW and TE attached to the router to achieve addressing and routing. Assume that the router in the lower left corner is the origin of the coordinate axis. The router position identifiers along the X-axis are 0, 1, 2, 3 respectively, and the router position identifiers along the Y-axis are 0, 1, 2, 3 respectively; then the position identifier of the router at the coordinate origin position in the lower left corner is {0, 0}, the position identifier of the leftmost upper router is {0, 3}, and the position identifier of the router in the lower right corner is {3, 0}. If a packet needs to be sent to the FW / TE attached to the router at the {0, 3} position, the destination address of the packet can be filled with {0, 3}. When the router at the {0, 3} position receives the packet, it can forward the packet to the locally attached FW / TE through the local port.

[0046] The routing algorithm adopted by the on-chip network many-core architecture provided by the embodiment of the present invention can be selected according to specific service scenarios, and the present invention does not make specific limitations. For example, the dimension-order routing algorithm, shortest path routing algorithm, etc. in the deterministic routing algorithm can be adopted. The fully adaptive routing algorithm, minimal adaptive routing algorithm, etc. in the adaptive routing algorithm can also be used to implement the routing of packets between routers.

[0047] Such as Figure 2For an example, if the source router {0,1} of the Network on Chip needs to send a packet of BFD service type to the destination router {0,3} according to the configuration of the logic firmware microkernel, the location identifiers of the source / destination routers can be used as the addresses of the source / destination routers in the Network on Chip, and the adaptive routing algorithm can be adopted to send the packet from node {0,1} to router {0,3}. When the direct connection paths between router {0,1} -> router {0,2} and router {0,2} to node {0,3} are unobstructed, the shortest path can be directly selected: router {0,1} -> router {0,2} -> router {0,3}. If the direct connection path between router {0,1} -> router {0,2} is blocked, based on the routing path calculated by the adaptive routing algorithm, the path of router {0,1} -> router {1,1} -> router {1,2} -> router {1,3} -> router {0,3} may also be selected.

[0048] Figure 3 It is a schematic diagram of the basic structure of a router in the many-core architecture of the Network on Chip used in an embodiment of the present invention. Four pairs of input / output ports are provided in the four directions of North / East / South / West in the Network on Chip router, which are used to realize the interconnection between routers in four directions in the NOC matrix. In addition, a LocalPort (local port) is also provided, which is used to connect the physical firmware microkernel FW and the local physical task engine TE of this node.

[0049] The Network on Chip router adopts the Credit-FIFO (credit-based first in first out) mechanism for flow control. Each input port in each direction is configured with a FIFO queue. The destination node provides credit to the source node, and the source node determines the number of packets to be sent to the destination node based on the size of the credit value. The source node can only send data to the downstream node when there is credit.

[0050] In the Network on Chip, in order to improve the data transmission efficiency, reduce the transmission delay, and enhance the routing flexibility, packets are usually segmented into smaller packet slices (flits) according to the physical link bandwidth, and then combined with the pipelined transmission technology to achieve the efficient transmission of packets between the source and destination routers. When the physical link bandwidth is wide enough or the packet itself is small, packets can also be transmitted between Network on Chip routers in the unit of packets. The present invention does not make specific limitations. For the sake of convenience of expression, the "packet" in the present invention can be understood as "packet" or "packet slice" according to the specific environment.

[0051] The access requests generated by FW or TE enter the on-chip network router through the local port of localport. After several hops of routing, at the on-chip network router corresponding to the target address, they leave the on-chip network NOC through the local port of localport and reach the destination FW or TE.

[0052] In each clock cycle, the arbiter module of the on-chip network router arbitrates among the data coming in from the five directions of N / E / S / W and localport, selects one for processing, and sends it to the next hop according to its destination address. FIFO queues are set at the input ports in the five directions to cache the packets sent by the sender. The credit manager module calculates the credit value based on the caching situation of the packets in the FIFO queue and feeds back the available credit value in the reverse direction to the sender. For example, when the router retrieves 1 packet from the FIFO queue in a certain direction, the credit manager module increments the credit value in the corresponding direction by 1, and then feeds back the current credit value in the reverse direction to the sender. The sender can then continue sending according to the available credit value fed back.

[0053] The crossbar switch (xBAR switch) in the on-chip network router is a key switching structure for realizing data exchange and routing selection between different input ports and output ports.

[0054] The on-chip network many-core architecture chip provided by the present invention integrates numerous cores. If each core is equipped with a large-capacity instruction random access memory IRAM and a data random access memory DRAM, the chip's cost, power consumption, design complexity, and other indicators will increase significantly. Therefore, the numerous cores must be sufficiently streamlined. For example, only a small amount of SRAM (Static Random Access Memory) is used to implement the instruction random access memory for storing instructions (Instruction), i.e., IRAM, and the data random access memory for storing data (Data), i.e., DRAM. In addition, no other memory (memory) is set up, and there is no complex cache (cache) system. However, the small amount of IRAM and DRAM will limit the types of service characteristics supported by the firmware microkernel, which creates a contradiction. To control costs and power consumption, the types of supported service characteristics have to be sacrificed.

[0055] Based on the on-chip network many-core architecture provided by the present invention, in order to reduce the resource requirements of the instruction codes of the service characteristics running on the FW firmware microkernel for IRAM and DRAM, so that the FW firmware microkernel has less resource requirements for the built-in random access memory when supporting the same number of service characteristics, thereby reducing the power consumption and cost of the data communication chip, the present invention further proposes the following improvement solutions:

[0056] Multiple physical firmware microkernels are virtualized into a logical firmware microkernel, and each physical firmware microkernel is equivalent to a hardware thread of the logical firmware microkernel. Then, the instruction codes of multiple service features to be run on the logical firmware microkernel are divided into multiple task groups (task_group). Each physical firmware microkernel only runs the instruction codes in one of the multiple task groups, that is, only runs a subset rather than the entire set of the service feature instruction codes, so that the codes of different task groups are distributed on different physical firmware microkernels in the logical firmware microkernel, thereby realizing the support for multiple service features while reducing the resource requirements of each firmware microkernel for IRAM and DRAM.

[0057] Figure 4 It is a schematic diagram of a logical firmware microkernel in the many-core architecture of the network-on-chip in an embodiment of the present invention. In this example, each firmware microkernel FW and task engine TE on the hardware are connected to a router matrix composed of network-on-chip routers (noc router). Any FW in the logical firmware microkernel can access any TE belonging to the logical firmware microkernel through the network-on-chip. The user plans the logical firmware microkernel for the numerous firmware microkernels mounted on the network-on-chip based on the quantity of the IRAM and DRAM resources of the firmware microkernel FW and the quantity of the instruction codes and data space requirements of the service features to be supported, divides the codes running on the firmware microkernel into multiple task groups (task_group), so that the quantity of the instruction codes of the service features included in each task group (corresponding to the demand for IRAM) and the quantity of the required data random access memory (corresponding to the demand for DRAM) do not exceed the resource quantity of the instruction random access memory IRAM and data random access memory DRAM built in the firmware microkernel.

[0058] Assume that the many-core architecture of the example needs to support the packet processing of four service features: Bidirectional Forwarding Detection BFD / Connectivity Fault Detection CFD packet generation, Deep Packet Inspection (DPI), Telemetry, and Netstream. The IRAM and DRAM of each firmware microkernel are 8KB respectively. The user plans these types of services into two service groups, namely Task_group1 and Task_group2, according to the quantity of the instruction codes of these types of service features and the quantity of the required data random access memory space, as shown in the example of Table 1.

[0059] Table 1:

[0060]

[0061] The IRAM and DRAM required for the BFD / CFD service feature are 2KB and 1.5KB respectively, the IRAM and DRAM required for the DPI service feature are 6KB and 6.5KB respectively, the IRAM and DRAM required for the Telemetry service feature are 3KB and 4KB respectively, and the IRAM and DRAM required for the traffic statistics analysis Netstream service feature are 5KB and 4KB respectively. The total amounts of IRAM and DRAM required for the four services are both 16KB. Assuming that the amounts of IRAM and DRAM for each firmware microcore in the many-core architecture of the on-chip network are both 8KB, without using the technical solution provided by the present invention, the many-core architecture of the on-chip network cannot support the packet processing of so many types of service features.

[0062] Based on the technical solution provided by the present invention, in this embodiment, the four service features are divided into two service groups, namely Task_group1 and Task_group2, according to the instruction code amount and data amount required for each service feature. Task_group1 includes the BFD / CFD service feature and the DPI service feature, and Task_group2 includes the Telemetry service feature and the Netstream service feature. Through such division, the instruction code amount and data amount required for the service features in each service group do not exceed the amounts of IRAM and DRAM built in each firmware microcore FW.

[0063] On the basis of completing the above planning, combined with Figure 4 the example of, two firmware microcores FW_A and FW_B directly connected by the on-chip network router nodes {0, 3} and router nodes {1, 3} are bound through the chip configuration interface, virtualized into a logical firmware microcore, the Task_group1 task group is bound to FW_A, and the Task_group2 task group is bound to FW_B, that is, the service features in the two task groups are distributed to two different firmware microcores in the logical firmware microcore. Each firmware microcore in the logical firmware microcore only needs to support the packet processing process of the service features in the bound task group. In this way, a logical firmware microcore can support the above four service features at the same time.

[0064] Figure 5 It is a schematic diagram of the binding relationship between the logical firmware microcore and the task group in an embodiment of the present invention.

[0065] FW_A and TE_A are the firmware microkernel and task engine directly connected to the same on-chip network router {0,3}; FW_B and TE_B are the firmware microkernel FW and task engine TE directly connected to the same on-chip network router {1,3}. After FW_A and FW_B are virtualized into a logical firmware microkernel, FW_A and FW_B are equivalent to being fully connected to TE_A and TE_B through the on-chip network respectively, and FW_A and FW_B can respectively call TE_A and / or TE_B to execute the basic packet processing PP actions required for the service characteristics in their respective bound task groups. For example, FW_A can dispatch the PP actions required for the packet processing processes of service characteristics BFD / CFD and / or DPI in Task_group1 to TE_A and / or TE_B for execution; FW_B can also dispatch the PP actions required for the packet processing processes of service characteristics Telemetry and / or Netstream in Task_group2 to TE_A and / or TE_B for execution.

[0066] Multiple physical task engines directly connected to the same on-chip network router as the physical firmware microkernel in the logical firmware microkernel form a logical multi-homed task engine. For example, TE_A and TE_B are the logical multi-homed task engine Logic TE1 {TE_A, TE_B} of the logical firmware microkernel Logic FW1 {FW_A, FW_B}. Any physical firmware microkernel FW in the logical firmware microkernel can manage and call one or more physical task engines TE in the logical multi-homed task engine.

[0067] There is a binding relationship between the logical firmware microkernel (Logic FW1) and the logical multi-homed task engine (Logic TE1) in the present invention. Any firmware microkernel in the logical firmware microkernel can manage and call one or more task engines in the logical multi-homed task engine.

[0068] Suppose FW_A in the logical firmware microkernel Logic FW1 needs to process the packet processing of 20 BFD session packet transmissions. FW_A can allocate the PP actions required for these packet processing PP actions to one or more task engines of the logical multi-homed task engine Logic TE1 based on a preset load balancing algorithm for execution. For example, the packet processing actions required for the first 10 BFD session packet transmissions are sent to TE_A in Logic TE1 for processing through source address {0,3} and destination address {0,3}, and the packet processing actions required for the last 10 BFD session packet transmissions are sent to TE_B in Logic TE1 for processing through source address {0,3} and destination address {1,3}. The on-chip network router noc router can correctly send the packet to the TE under the router corresponding to the destination address according to the destination address of the data packet.

[0069] As can be seen from the above embodiments, although the total requirements for the instruction code and data space of the business characteristics running on the FW are both 16 KB, by the method of using one FW to manage two TEs, each FW only requires 8 KB of code and 8 KB of data space to achieve the same function. That is to say, the required random access memory resources of each FW are halved to meet the requirements. Thus, under the condition of supporting the same number of business characteristics, the power consumption and cost of the firmware microkernel in the many-core architecture of the on-chip network are reduced.

[0070] Figure 6 This is a schematic diagram showing the binding relationship between the logical firmware microkernel and the task group in another embodiment of the present invention.

[0071] In this embodiment, the firmware microkernels FW_A, FW_B, FW_C, and FW_D respectively connected to 4 on-chip network routers are virtualized into a large logical firmware microkernel Virtual FW{FW_A, FW_B, FW_C, FW_D}. The 4 firmware microkernels are fully connected to 4 task engines TE_A, TE_B, TE_C, and TE_D which are respectively and commonly connected to the same on-chip network router node as the 4 firmware microkernels through the on-chip network. The 4 task engines form a logical multi-homed task engine Virtual TE{TE_A, TE_B, TE_C, TE_D}. Any one of the 4 firmware microkernels in the logical firmware microkernel can manage and call one or more task engines TE in the logical multi-homed task engine Virtual TE. It is equivalent to each firmware microkernel in the logical firmware microkernel Virtual FW can manage and call the 4 task engines TE in the logical multi-homed task engine Virtual TE.

[0072] Assume that each of the 4 firmware microkernels only has 8 KB of IRAM and 8 KB of DRAM, and each firmware microkernel can support 2 different business characteristics. Then, without increasing the IRAM and DRAM resources of each firmware microkernel, the number of business characteristics that the chip can support is increased from 2 to 8, achieving the effect of 32 KB of IRAM and 32 KB of DRAM.

[0073] Furthermore, when any firmware microkernel FW in a logical firmware microkernel manages multiple task engines TE through a network-on-chip, compared with the case where each firmware microkernel FW only manages local TEs, the latency inevitably increases when the cmd (command) sent by the physical firmware microkernel FW reaches other destination TEs in the logical multi-homed task engine except the local TE. For example, the clock delay may increase by several clock cycles. In an embodiment of the present invention, in order to reduce the latency, when the physical firmware microkernel FW in the logical firmware microkernel sends a (cmd) command to the physical task engine in the logical multi-homed task engine, a pipeline model is adopted to transmit the cmd, so as to try to avoid the performance degradation caused by the latency.

[0074] In the case where the physical firmware microkernel uses the pipeline model to send cmd to the TE, assume that FW_A needs to send commands for executing the PP action to TE_A and TE_B. After FW_A sends the cmd to TE_A, it can start to continue processing the cmd sent to TE_B without waiting for the response returned by TE_A to FW_A, and then return to process the response returned by TE_A, and then process the response returned by TE_B. That is, by parallelizing the action of FW processing the next destination TE and the action of transmitting the cmd for the previous destination TE on the NOC, the impact of the latency generated by transmitting the cmd on the NOC when one FW controls multiple TEs on the performance is offset as much as possible.

[0075] Based on the above embodiments, it can be seen that the present invention is based on the network-on-chip, and by virtualizing multiple physical firmware microkernels into a logical firmware microkernel, the division of labor and cooperation of the physical firmware microkernels within the logical firmware microkernel group is realized, and the one-to-one mapping between the physical firmware microkernel and the hardware acceleration module it manages, that is, the physical task engine TE, is converted into a many-to-many mapping relationship, so as to effectively reduce the demand of the physical firmware microkernel FW for the built-in IRAM and DRAM resources while supporting the same number of service characteristics, greatly reducing the power consumption of the chip and saving the chip area and cost.

[0076] Furthermore, the logical firmware microkernel and the task group Task_group can be designed in a dynamic configuration mode, and the user can dynamically configure the physical firmware microkernels included in the logical firmware microkernel, the task groups supported by each firmware microkernel, and the message processing process of the service characteristics supported by the physical firmware microkernels through the orchestration configuration interface of the chip, enabling the user to flexibly customize and expand the functions of the chip according to the actual application scenario.

[0077] Further, in order to reduce the latency of transmitting the cmd between the FW and the non-local TE through the on-chip network, when configuring the logic firmware microkernel, the adjacent proximity principle can be adopted to configure a group of adjacent physical firmware microkernels as a logic firmware microkernel.

[0078] Based on the on-chip network many-core architecture provided by the embodiments of the present invention, the present invention also proposes a data processing method, which is applied to a chip adopting the on-chip network many-core architecture provided by the present invention.

[0079] Figure 7 FIG. 7 is a schematic flowchart of the steps of a data processing method based on an on-chip network many-core architecture provided by an embodiment of the present invention. In this embodiment, it is assumed that in the on-chip network, two adjacent physical firmware microkernels 1 and physical firmware microkernel 2 are bound and virtualized into a logic firmware microkernel, and the physical task engine 1 co-located with the physical firmware microkernel 1 and the physical task engine 2 co-located with the physical firmware microkernel 2 are bound and virtualized into a logic multi-homing task engine. The physical firmware microkernel 1 in the logic firmware microkernel is bound to task group 1, and the physical firmware microkernel 2 is bound to task group 2. Task group 1 includes two service characteristics, namely service characteristic 1 and service characteristic 2. When any on-chip network router in the on-chip network receives a service packet with service characteristic 1, according to the binding relationship between the logic firmware microkernel and the service characteristic and the physical firmware microkernel in the chip configuration, based on a preset routing algorithm, the service request or service packet with service characteristic 1 is routed to the on-chip network router directly connected to the physical firmware microkernel 1, and then the router forwards it to the physical firmware microkernel 1 through a local port. The physical firmware microkernel 1 can call one or more physical task engines in the logic multi-homing task engine to accelerate the service processing process according to the configuration of the logic firmware microkernel. Based on the above example of the application environment, the steps of the method include:

[0080] Step 701. When receiving a service request or service packet of a certain service characteristic, route the service request or service packet to the physical firmware microkernel that binds the service characteristic in the logic firmware microkernel that supports the service characteristic in the on-chip network many-core architecture;

[0081] For example, when receiving a service request or service packet with service characteristic 1, route the service request or service packet with service characteristic 1 to the physical firmware microkernel 1 that binds the service characteristic 1 in the logic firmware microkernel that supports the service characteristic 1 in the on-chip network many-core architecture.

[0082] Step 702. The physical firmware microkernel calls one or more physical task engines in the logic multi-homing task engine to perform hardware acceleration on the message processing process of the service characteristic based on the orchestrated service control logic.

[0083] For example, after the physical firmware microkernel 1 receives the service message of service feature 1, it invokes one or more physical task engines in the logical multi-homing task engine based on the orchestrated service control logic to perform hardware acceleration on the message processing process of service feature 1.

[0084] Furthermore, the physical firmware microkernel in the logical firmware microkernel uses a pipeline model to transfer commands to the physical task engines in the logical multi-homing task engine.

[0085] Furthermore, the on-chip network many-core architecture provides an orchestration configuration interface. When the chip receives the orchestration instruction sent by the user through the orchestration configuration interface, it orchestrates the message processing process of the service features supported by the physical firmware microkernel according to the orchestration instruction. When receiving the configuration instruction sent by the user through the orchestration configuration interface, it configures the service features supported by each physical firmware microkernel in the logical firmware microkernel according to the configuration instruction.

[0086] Furthermore, when the on-chip network router receives a service request or service message of a certain type of service feature, it uses the position identifier of the on-chip network router in the router matrix as the network address, and adopts a deterministic routing algorithm or an adaptive routing algorithm to route the service request or service message to the physical firmware microkernel that supports this type of service feature.

[0087] The above describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0088] Those skilled in the art will readily conceive of other implementations of this specification after considering the specification and practicing the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of this specification that follow the general principles of this specification and include common general knowledge or conventional technical means in the technical field not claimed in this application. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this specification are pointed out by the claims.

[0089] It should be understood that this specification is not limited to the precise structures described above and shown in the figures, and various modifications and changes can be made without departing from its scope. The scope of this specification is only limited by the appended claims.

[0090] The above are only the preferred embodiments of this specification and are not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of protection of this specification.

Claims

1. A many-core architecture chip with a network-on-chip, characterized in that Comprising: A logical firmware microkernel, which includes a plurality of physical firmware microkernels, and the plurality of physical firmware microkernels respectively support service characteristics in different task groups, and one task group includes one or more service characteristics; A logical multi-homing task engine, which includes a plurality of physical task engines, and the physical task engines are hardware-cured with basic packet processing actions for hardware acceleration of the packet processing process of the service characteristics orchestrated by the physical firmware microkernels; each physical task engine is controlled by each physical firmware microkernel in the logical firmware microkernel; In the on-chip network, the physical firmware microkernel and the physical task engine are connected to the on-chip network router through the local ports of the on-chip network router.

2. The on-chip network many-core architecture chip according to claim 1, wherein: The total amount of instruction codes and the total amount of required data random access memory of the service characteristics in the task group do not exceed the instruction random access memory capacity and the data random access memory capacity in the physical firmware microkernel; The number of physical firmware microkernels included in the logical firmware microkernel is determined by the total amount of instruction random access memory and the total amount of data random access memory required for the service characteristics supported by the logical firmware microkernel and the instruction random access memory capacity and the data random access memory capacity of the physical firmware microkernel.

3. The on-chip network many-core architecture chip according to claim 1, wherein: Each on-chip network router in the on-chip network is connected to a physical firmware microkernel and a physical task engine through local ports; The logical firmware microkernel and the logical multi-homing task engine are respectively composed of multiple pairs of physical firmware microkernels and physical task engines connected to the same on-chip network router; Each physical task engine in the logical multi-homing task engine is fully connected to each physical firmware microkernel in the logical firmware microkernel through the on-chip network.

4. The on-chip network many-core architecture chip according to claim 3, wherein: The physical firmware microkernels in the logical firmware microkernel use a pipeline model to transmit commands to the physical task engines in the logical multi-homing task engine.

5. The on-chip network many-core architecture chip according to claim 1, wherein: The on-chip network many-core architecture provides an orchestration configuration interface for the user to orchestrate the packet processing processes of different service characteristics in the task group, combine a number of basic hardware-cured basic packet processing actions, and realize the support for the service characteristics in the task group; and configure the service characteristics supported by each physical firmware microkernel in the logical firmware microkernel.

6. The on-chip network many-core architecture chip according to claim 5, wherein: The physical firmware microkernels in the logical firmware microkernel are a group of adjacent firmware microkernels in the on-chip network. When configuring the logical firmware microkernel, the adjacent-nearest principle is adopted, and a group of adjacent physical firmware microkernels are configured as a logical firmware microkernel.

7. A data processing method, characterized in that, This method is applied to an on-chip network many-core architecture chip as described in any one of claims 1-6, and this method includes: When receiving a service request or service message of a certain type of service feature, route the service request or service message to the physical firmware microkernel that binds the service feature in the logic firmware microkernel that supports the service feature in the many-core architecture of the on-chip network; The physical firmware microkernel calls one or more physical task engines in the logic multi-homing task engine based on the orchestrated service control logic to perform hardware acceleration on the message processing process of the service feature of this type.

8. The data processing method according to claim 7, wherein The physical firmware microkernel in the logic firmware microkernel uses a pipeline model to send commands to the physical task engine in the logic multi-homing task engine.

9. The data processing method according to claim 7, wherein Receive the orchestration instruction sent by the user through the orchestration configuration interface, and orchestrate the message processing process of the service feature supported by the physical firmware microkernel; Receive the configuration instruction sent by the user through the orchestration configuration interface, and configure the service features supported by each physical firmware microkernel in the logic firmware microkernel.

10. The data processing method according to claim 7, wherein When the on-chip network router receives a service request or service message of a certain type of service feature, use the position identifier of the on-chip network router in the router matrix as the network address, and use a deterministic routing algorithm or an adaptive routing algorithm to route the service request or service message to the physical firmware microkernel that supports the service feature of this type.

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