RDMA queue asynchronous processing method and device based on hardware multithreading
By creating an independent hardware thread context in the RDMA network card to process the submission and completion queues in parallel, and dynamically adjusting event priorities and resource allocation, the problem of the ineffective release of the hardware multi-threaded parallel potential under high-concurrency and low-latency services was solved, and the performance of ultra-high-speed networks was improved.
Patent Information
- Application Number
- CN202510893644.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-11-21
AI Technical Summary
In high-concurrency, low-latency service scenarios, the hardware multi-threaded parallel potential of traditional RDMA network cards has not been effectively released, resulting in performance bottlenecks in ultra-high-speed networks. In particular, in the 100GbE+ era, the processing latency of a single work queue element has become the main performance bottleneck.
Two independent hardware thread contexts are created in the hardware multi-threading engine of the RDMA network card. Asynchronous events are triggered independently through the hardware event scheduler to achieve parallel processing of the submission queue and the completion queue. Combined with the hardware-level queue management unit, RDMA protocol operations are directly executed, and the completion queue elements are written to the host memory after the operation is completed. Event priority and resource allocation are dynamically adjusted to optimize the processing flow.
It improves resource utilization, solves the problems of serialization processing latency and resource utilization imbalance in high-concurrency scenarios, and enhances the throughput and performance of ultra-high-speed networks.
Smart Images
Figure CN120994322A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-threaded queue processing technology, and in particular to an asynchronous RDMA queue processing method and apparatus based on hardware multi-threading. Background Technology
[0002] As data center network bandwidth evolves from 40GbE to 400GbE and even 800GbE, Remote Direct Memory Access (RDMA) technology, based on features such as zero-copy and kernel bypass, has become a core interconnection solution for high-performance computing and distributed storage. Traditional RDMA network cards use a single-threaded polling architecture to process work queues, which can meet latency requirements in low-load scenarios. However, when networks enter the 100GbE+ era, the processing latency of a single work queue element has dropped to the microsecond level, at which point queue management overhead becomes the main performance bottleneck.
[0003] In existing technologies, hardware multi-threaded engines improve throughput by processing the submission queue and completion queue in parallel. Most implementations use static priority scheduling; when the submission queue is under sustained high load, completion queue elements cannot be written to host memory in a timely manner, causing application-layer blocking. Furthermore, existing architectures use a line-by-line parsing execution mode for consecutive individual work queue elements, failing to fully utilize data locality. These shortcomings prevent RDMA network cards from effectively unleashing the parallel potential of hardware multi-threading when dealing with high-concurrency, low-latency services, severely limiting the performance realization of ultra-high-speed networks. Summary of the Invention
[0004] This invention provides an asynchronous processing method and apparatus for RDMA queues based on hardware multithreading, which solves the problem that the parallel potential of hardware multithreading cannot be effectively released when RDMA network cards deal with high concurrency and low latency services, which seriously restricts the performance realization of ultra-high-speed networks.
[0005] The first aspect of this invention provides an asynchronous processing method for RDMA queues based on hardware multithreading, comprising:
[0006] Create a first hardware thread context and a second hardware thread context in the hardware multithreading engine of the RDMA network card;
[0007] The first hardware thread context is triggered to access the submission queue based on the first asynchronous event, and the first work queue element is parsed.
[0008] The second hardware thread context is triggered by the second asynchronous event to access the completion queue and generate completion queue elements;
[0009] The hardware-level queue management unit executes the RDMA protocol operation corresponding to the first work queue element, and after the operation is completed, the second hardware thread context writes the completed queue element into the host memory.
[0010] The first asynchronous event and the second asynchronous event are triggered independently by the hardware event scheduler, and the execution processes of the first hardware thread context and the second hardware thread context overlap in timing.
[0011] Furthermore, during the execution of the first hardware thread context, the depth status information of the submission queue is monitored; based on the depth status information of the submission queue and the status of the completed queue elements, the arbitration priority of the hardware event scheduler for the first asynchronous event is adjusted.
[0012] Furthermore, during execution in the first hardware thread context, monitoring the depth status information of the submission queue and adjusting the arbitration priority of the hardware event scheduler for the first asynchronous event based on the depth status information of the submission queue and the status of the completed queue elements includes:
[0013] Read the current submission queue depth value from the submission queue depth register of the hardware multithreaded engine;
[0014] Compare the depth value of the current submission queue with a preset depth threshold;
[0015] If the depth value of the current submission queue is greater than or equal to the depth threshold, then the arbitration priority of the first asynchronous event in the hardware event scheduler is increased.
[0016] If the depth value of the current submission queue is less than the depth threshold, the arbitration priority of the first asynchronous event in the hardware event scheduler is dynamically reduced to the baseline priority or maintained at the current priority.
[0017] Furthermore, the first asynchronous event includes the queue tail pointer update event of the submission queue; the second asynchronous event includes the queue head pointer consumption event of the completion queue.
[0018] Furthermore, the hardware event scheduler triggers the first asynchronous event and the second asynchronous event according to a preset configurable priority strategy, wherein the first asynchronous event has a higher priority than the second asynchronous event.
[0019] Furthermore, the method also includes:
[0020] The hardware event scheduler records the trigger timestamps of the first asynchronous event and the second asynchronous event;
[0021] If the timestamp difference between two events is less than a preset overlap threshold within N consecutive scheduling cycles, then the instruction issuance slot and cache resource allocation ratio of the hardware thread in the second hardware thread context will be increased.
[0022] Furthermore, the step of directly executing the RDMA operation corresponding to the first work queue element through the hardware-level queue management unit includes:
[0023] Obtain the depth status information of the submission queue;
[0024] When the depth state information meets the preset batch processing trigger conditions, the hardware-level batch processing execution mode is started to merge and process multiple consecutive work queue elements and generate an aggregated completion queue element.
[0025] Furthermore, the preset batch processing triggering conditions include: the depth value of the submission queue is lower than the first threshold for N consecutive periods; and the available cache space of the completion queue is higher than the second threshold.
[0026] Furthermore, the method also includes: when the queue management unit of the hardware multi-threaded engine is in batch execution mode, merging and parsing consecutive work queue elements with the same operation type and performing batch RDMA operations.
[0027] A second aspect of the present invention provides an asynchronous processing apparatus for RDMA queues based on hardware multithreading, comprising:
[0028] The hardware thread context creation unit is used to create a first hardware thread context and a second hardware thread context in the hardware multithreading engine of the RDMA network card.
[0029] The first work queue element parsing unit is used to trigger the first hardware thread context to access the submission queue according to the first asynchronous event, and parse the first work queue element.
[0030] The completion queue element generation unit is used to trigger the second hardware thread context to access the completion queue according to the second asynchronous event and generate completion queue elements;
[0031] The hardware-level queue management unit execution unit is used to execute the RDMA protocol operation corresponding to the first work queue element through the hardware-level queue management unit, and write the completed queue element into the host memory by the second hardware thread context after the operation is completed; wherein, the first asynchronous event and the second asynchronous event are triggered independently by the hardware event scheduler, and the execution processes of the first hardware thread context and the second hardware thread context overlap in timing.
[0032] As can be seen from the above technical solutions, the present invention has the following advantages:
[0033] This invention creates a first hardware thread context and a second hardware thread context within the hardware multithreading engine of an RDMA network card. A hardware thread allocator provides independent execution environments for submission queue processing and completion queue processing. Based on a first asynchronous event, the first hardware thread context accesses the submission queue and parses the first work queue element, enabling immediate response to high-priority requests. Based on a second asynchronous event, the second hardware thread context accesses the completion queue and generates completion queue elements, ensuring low-latency submission of completion notifications. The hardware-level queue management unit directly executes the RDMA protocol operation corresponding to the first work queue element, offloading the host computing load. After the operation is completed, the second hardware thread context writes the completion queue element to the host memory, thereby converting the hardware multithreading parallel potential into actual throughput gain. This solves the performance bottleneck problem of ultra-high-speed networks caused by serialization processing latency, resource utilization imbalance, and atomic operation efficiency loss in high-concurrency scenarios, effectively improving resource utilization. Attached Figure Description
[0034] Figure 1 This is a schematic flowchart of an embodiment of an asynchronous processing method for RDMA queues based on hardware multithreading in this invention. Detailed Implementation
[0035] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “corresponding to,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0036] Example 1
[0037] The implementation method in this embodiment can be implemented in a system, on a server, or on a terminal; no specific limitation is made. The following section will describe the hardware multithreaded RDMA queue asynchronous processing method in this application from a system implementation perspective. Please refer to... Figure 1 The method provided in this application includes the following steps:
[0038] S11. Create a first hardware thread context and a second hardware thread context in the hardware multithreading engine of the RDMA network card;
[0039] In the hardware multithreading engine of the RDMA network card, two independent hardware thread contexts are created through a hardware thread allocator. The first hardware thread context is dedicated to handling the Submission Queue (SQ), and its hardware resources include a dedicated instruction cache, a queue tail pointer register, and a Work Queue Element (WQE) parsing logic unit. The second hardware thread context is dedicated to handling the Completion Queue (CQ), and its hardware resources include a Completion Queue cache, a Completion Queue Element (CQE) generation engine, and a host memory write interface. The two thread contexts share the hardware multithreading engine's event response bus but have independent program counters and register files, ensuring execution state isolation.
[0040] S12. Trigger the first hardware thread context to access the submission queue based on the first asynchronous event, and parse the elements of the first work queue;
[0041] In this embodiment, the first asynchronous event includes the queue tail pointer update event of the submission queue. When the hardware event scheduler detects the first asynchronous event (i.e., the submission queue tail pointer update event), it triggers the first hardware thread context to perform the following operations:
[0042] 1. Accessing the Submission Queue and Parsing WQE: The first hardware thread context obtains the physical address of the submission queue through the Send Queue Direct Memory Access (SQDMA) engine, accesses the submission queue in host memory, reads and parses the first work queue element, and extracts key information such as opcode and memory address descriptor.
[0043] 2. During WQE resolution in the first hardware thread context, the depth value of the current submission queue is read in real time from the submission queue depth register of the hardware multithreaded engine via the depth monitoring coprocessor, for example, if the depth value is 32. The current depth value is compared with preset depth thresholds (including a high threshold of 28 and a low threshold of 10). If the current depth value is greater than or equal to the high threshold (e.g., 32 ≥ 28), the arbitration priority of the first asynchronous event in the hardware event scheduler is increased to the highest level (e.g., from priority 2 to 0) to ensure that new requests are processed first under high load. If the current depth value is less than the low threshold (e.g., 8 < 10), the arbitration priority of the first asynchronous event is dynamically reduced to the base priority (e.g., from priority 2 to 3) to release scheduling resources for use by the second asynchronous event. If the depth value is between the high and low thresholds (e.g., 15), the current priority remains unchanged. Simultaneously monitor the available cache space of the completed queue (e.g., via the CQ space status register). If the available space is detected to be lower than the safety threshold (e.g., remaining slots < 16), the priority of the second asynchronous event is forcibly increased to avoid CQ overflow, even if the submission queue depth is not exceeded. The adjusted priority is written to the arbitration table of the hardware event scheduler in real time through the priority encoder and takes effect in the next scheduling cycle.
[0044] After priority adjustment is completed, the parsed WQE operation instructions are passed to the hardware-level queue management unit for execution. During this process, the first hardware thread context continuously monitors the queue status to ensure that dynamic arbitration is completed within a single WQE parsing cycle, thereby maintaining high throughput while avoiding queue congestion.
[0045] S13. Trigger the second hardware thread context to access the completion queue based on the second asynchronous event, and generate completion queue elements;
[0046] In this embodiment, the second asynchronous event includes the queue head pointer consumption event of the completed queue; when the hardware event scheduler detects the second asynchronous event, namely the queue head pointer consumption event, the following processing flow is triggered:
[0047] 1. The hardware event scheduler adopts a preset configurable priority strategy, and its core design is based on the queue processing latency model. The default priority strategy is configured so that the first asynchronous event has a higher priority than the second asynchronous event, that is, SQ priority = 1, CQ priority = 2, and the smaller value takes precedence. This setting is based on quantitative analysis, that is, in high throughput scenarios, the SQ processing latency accounts for 68% of the weight of the end-to-end performance.
[0048] 2. The event scheduler integrates a 48-bit high-precision timer, recording a timestamp T1 when the first asynchronous event is triggered and T2 when the second asynchronous event is triggered. When (T2-T1) < 100ns for eight consecutive scheduling cycles (this threshold was determined through silicon verification), it indicates a high degree of overlap between the execution windows of the two thread contexts. Dynamic resource allocation here expands the instruction issuance slots of the second hardware thread context from the base value of 4 slots to 6 slots, improving parallel instruction processing capabilities; and increases its L2 cache share from 25% to 40% through a cache partitioning controller, reducing memory access conflicts.
[0049] 3. Second hardware thread context execution: Obtain the current write pointer address from the completion queue head pointer register; the QE generation engine parses the RDMA operation status; (successful operation: fill with 0x0000 status code; failed operation: fill with error code); temporarily store the generated CQE in the on-chip double buffer queue (capacity of 64 entries) to avoid the impact of host memory access latency.
[0050] S14. The RDMA protocol operation corresponding to the first work queue element is executed through the hardware-level queue management unit, and the completed queue element is written to the host memory by the second hardware thread context after the operation is completed; wherein, the first asynchronous event and the second asynchronous event are triggered independently by the hardware event scheduler, and the execution processes of the first hardware thread context and the second hardware thread context overlap in timing.
[0051] In this embodiment, before executing the RDMA operation corresponding to the first work queue element, the hardware-level queue management unit first obtains the current submission queue depth value in real time through the hardware latch of the submission queue depth status register. When it is detected that the depth value continuously meets the preset batch processing triggering conditions, the mode switching signal of the batch processing state machine is immediately activated to start the hardware-level batch processing execution mode. In this mode, the queue management unit will merge and parse multiple consecutive work queue elements in the submission queue at one time, and map the scattered data access requests into consecutive physical blocks to perform batch data transmission through the DMA aggregation engine. After all operations are completed, the CQE generation engine creates a single aggregated completion queue element. This element contains the composite status code of the batch operation and the address identifier of the first operation. Finally, it is atomically submitted to the completion queue area through the host memory writing unit.
[0052] The aforementioned preset batch processing triggering conditions are based on the dual guarantee principle of queue state stability and resource security. Among them, the submission queue depth value must be lower than the first threshold of 12 for four consecutive hardware clock cycles (N=4). This value is derived from the Poisson distribution model of typical data center load to ensure that the queue is in a stable and low-fluctuation state (probability of 92%) when the depth value is less than 12. At the same time, the available cache space for completing the queue must be higher than the second threshold of 48 slots. This threshold is calculated based on 1.5 times the redundancy of the space required for the maximum batch processing volume of 32 entries. Real-time monitoring is achieved through periodic sampling of the CQ space counter. Both conditions need to be verified synchronously by hardware and logic gates. The batch processing enable signal will only be triggered when the low threshold flag bit of the depth status register and the high threshold flag bit of the CQ space are set at the same time, thereby avoiding the risk of batch processing failure due to queue congestion or cache overflow.
[0053] In this embodiment, during the batch execution mode activation, the instruction parser of the queue management unit strictly follows the operation type consistency principle, only merging and parsing consecutive work queue elements with identical opcodes in the submission queue, such as 8 consecutive RDMA_WRITE operations or 6 consecutive RDMA_READ operations. This restriction is implemented by the opcode comparator hardware. If non-continuity or opcode difference is detected, the current merging window is immediately terminated and the process reverts to single-element processing. For a sequence of operations of the same type that meets the conditions, the DMA aggregation engine merges the memory descriptions of multiple WQEs into a single DMA request, converts the scattered logical addresses into contiguous physical blocks through the address mapping table, and performs a batch data transfer of up to 128KB. At the same time, the protocol offloading engine maintains atomic semantics, ensuring that batch operations are equivalent to sequential independent execution, and finally generates an aggregation completion queue element containing a unified status code.
[0054] During batch processing, the operation status monitoring unit captures the execution result of each sub-operation in real time through a 32-bit status code register. The hardware error counter accumulates the count of consecutive failed operations. When the counter value reaches the preset circuit breaker threshold 3, which covers 99.7% of instantaneous error scenarios, a three-level circuit breaker mechanism is immediately triggered: First, the batch processing state machine clears the mode flag to force exit the batch processing state; second, it switches to single-element processing mode to ensure that subsequent work queue elements are parsed and executed independently; finally, the interrupt signal line is pulled high to notify the host driver to perform error diagnosis. This process is completed within 10 clock cycles. At the same time, the error counter is automatically cleared to zero when any successful operation is detected. In this way, a hardware-level elastic protection layer is built while maintaining batch processing efficiency, avoiding the avalanche of batch operations caused by the spread of single-point failures.
[0055] The following section provides a detailed verification and explanation of the methods in steps S13 and S14 above, using a scenario involving NVMe over Fabrics storage services to handle 8KB data writes:
[0056] The host driver first submits four consecutive RDMA_WRITE work queue elements to the submission queue, triggering a submission queue tail pointer update event. The hardware event scheduler captures this first asynchronous event at timestamp 125,600 nanoseconds and triggers the first hardware thread context. This thread reads the opcode and memory descriptor of the first WQE through the SQ DMA engine. Simultaneously, the depth monitoring coprocessor detects that the submission queue depth is 8 and has been below the preset threshold of 12 for four consecutive cycles, and the available space in the completion queue is 52 slots, which is above the threshold of 48. After meeting the batch processing trigger conditions, the queue management unit starts the batch processing execution mode. At this time, the protocol offloading engine recognizes that all four WQEs are RDMA_WRITE operations. The DMA aggregation engine maps the four groups of 8KB scattered addresses into contiguous physical blocks and merges them into a single 32KB data transfer to improve efficiency. During execution, the operation status register detects that the first write fails due to a target memory protection error, and the error counter increments to 1. However, the subsequent three operations succeed, clearing the counter. If three consecutive failures occur, the circuit breaker mechanism is triggered, automatically switching to single-element processing mode. After data transmission is complete, the second hardware thread context responds to the queue head pointer consumption event at timestamp 125,750 nanoseconds, generating an aggregated completion queue element containing the composite status code 0xA001. This element is then submitted to the host memory mapping area via the host memory write unit, and the head pointer register is atomically updated. Notably, the event scheduler records that the timestamp difference between this first asynchronous event and the historical second asynchronous event is only 20 nanoseconds, far less than the 100-nanosecond overlap threshold. Therefore, the dynamic allocator expands the instruction issuance slots of the second hardware thread context from 4 slots to 6 slots, and increases the L2 cache share from 25% to 40%. This ensures that the hardware execution windows for submitting queue parsing and completing queue writing completely overlap, ultimately achieving completion of all operations within 150 nanoseconds in a single batch processing cycle, increasing throughput to 98.7% of the theoretical line rate.
[0057] Example 2
[0058] An embodiment of the hardware multithreaded RDMA queue asynchronous processing device of the present invention includes the following steps:
[0059] The hardware thread context creation unit is used to create a first hardware thread context and a second hardware thread context in the hardware multithreading engine of the RDMA network card.
[0060] The first work queue element parsing unit is used to trigger the first hardware thread context to access the submission queue and parse the first work queue element according to the first asynchronous event.
[0061] The completion queue element generation unit is used to trigger the second hardware thread context to access the completion queue and generate completion queue elements based on the second asynchronous event.
[0062] The hardware-level queue management unit execution unit is used to execute the RDMA protocol operation corresponding to the first work queue element through the hardware-level queue management unit, and after the operation is completed, the second hardware thread context writes the completed queue element into the host memory; wherein, the first asynchronous event and the second asynchronous event are triggered independently by the hardware event scheduler, and the execution processes of the first hardware thread context and the second hardware thread context overlap in timing.
[0063] For specific limitations regarding the device, please refer to the limitations of the method above, which will not be repeated here. Each module in the above device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0064] It is understood that those skilled in the art can combine various implementation methods in the above embodiments under the guidance of the above examples to obtain technical solutions with multiple implementation methods.
[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An asynchronous processing method for RDMA queues based on hardware multithreading, characterized in that, include: Create a first hardware thread context and a second hardware thread context in the hardware multithreading engine of the RDMA network card; The first hardware thread context is triggered to access the submission queue based on the first asynchronous event, and the first work queue element is parsed. The second hardware thread context is triggered by the second asynchronous event to access the completion queue and generate completion queue elements; The hardware-level queue management unit executes the RDMA protocol operation corresponding to the first work queue element, and after the operation is completed, the second hardware thread context writes the completed queue element into the host memory. The first asynchronous event and the second asynchronous event are triggered independently by the hardware event scheduler, and the execution processes of the first hardware thread context and the second hardware thread context overlap in timing.
2. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 1, characterized in that, The method further includes: During execution in the first hardware thread context, the depth status information of the submission queue is monitored; Based on the depth status information of the submission queue and the status of the completed queue elements, the arbitration priority of the hardware event scheduler for the first asynchronous event is adjusted.
3. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 2, characterized in that, During execution in the first hardware thread context, monitoring the depth status information of the submission queue and adjusting the arbitration priority of the hardware event scheduler for the first asynchronous event based on the depth status information of the submission queue and the status of the completion queue includes: Read the current submission queue depth value from the submission queue depth register of the hardware multithreaded engine; Compare the depth value of the current submission queue with a preset depth threshold; If the depth value of the current submission queue is greater than or equal to the depth threshold, then the arbitration priority of the first asynchronous event in the hardware event scheduler is increased. If the depth value of the current submission queue is less than the depth threshold, the arbitration priority of the first asynchronous event in the hardware event scheduler is dynamically reduced to the baseline priority or maintained at the current priority.
4. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 1, characterized in that, The first asynchronous event includes the queue tail pointer update event of the submission queue; the second asynchronous event includes the queue head pointer consumption event of the completion queue.
5. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 4, characterized in that, The hardware event scheduler triggers the first asynchronous event and the second asynchronous event according to a preset configurable priority strategy, wherein the first asynchronous event has a higher priority than the second asynchronous event.
6. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 5, characterized in that, The method further includes: The hardware event scheduler records the trigger timestamps of the first asynchronous event and the second asynchronous event; If the timestamp difference between two events is less than a preset overlap threshold within N consecutive scheduling cycles, then the instruction issuance slot and cache resource allocation ratio of the hardware thread in the second hardware thread context will be increased.
7. The asynchronous processing method for RDMA queues based on hardware multithreading according to any one of claims 1-6, characterized in that, The step of directly executing the RDMA operation corresponding to the first work queue element through the hardware-level queue management unit includes: Obtain the depth status information of the submission queue; When the depth state information meets the preset batch processing trigger conditions, the hardware-level batch processing execution mode is started to merge and process multiple consecutive work queue elements and generate an aggregated completion queue element.
8. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 7, characterized in that, The preset batch processing triggering conditions include: the depth value of the submission queue is lower than the first threshold for N consecutive periods; and the available cache space of the completion queue is higher than the second threshold.
9. The asynchronous processing method for RDMA queues based on hardware multithreading according to claim 7, characterized in that, The method further includes: when the queue management unit of the hardware multi-threaded engine is in batch execution mode, merging and parsing consecutive work queue elements with the same operation type and performing batch RDMA operations.
10. An asynchronous processing device for RDMA queues based on hardware multithreading, characterized in that, The method described by any one of claims 1-9 comprises: The hardware thread context creation unit is used to create a first hardware thread context and a second hardware thread context in the hardware multithreading engine of the RDMA network card. The first work queue element parsing unit is used to trigger the first hardware thread context to access the submission queue according to the first asynchronous event, and parse the first work queue element. The completion queue element generation unit is used to trigger the second hardware thread context to access the completion queue according to the second asynchronous event and generate completion queue elements; The hardware-level queue management unit execution unit is used to execute the RDMA protocol operation corresponding to the first work queue element through the hardware-level queue management unit, and write the completed queue element into the host memory by the second hardware thread context after the operation is completed; wherein, the first asynchronous event and the second asynchronous event are triggered independently by the hardware event scheduler, and the execution processes of the first hardware thread context and the second hardware thread context overlap in timing.