Integrated system of post quantum cryptography chip and terminal equipment

Abstract

The invention relates to the technical field of computers, in particular to a post quantum cryptography chip integration system and terminal equipment, and the system comprises a main processor which is used for transmitting a post quantum cryptography calculation task; the power consumption detection module is used for receiving the current data provided by the post quantum cryptography chip and the execution state of the post quantum cryptography calculation task, and calculating the power consumption of the post quantum cryptography chip according to the current data; the clock management unit is used for adjusting the clock signal frequency required by the post quantum cryptography chip according to the power consumption and the execution state; the voltage management unit is used for adjusting the voltage required by the post quantum cryptography chip according to the power consumption and the execution state; by flexibly adjusting the clock signal frequency and voltage required by the post quantum cryptography chip, the requirement of terminal equipment for low power consumption is met, reasonable utilization of resources is realized, and long-time standby work is realized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an integrated system and terminal equipment of a post-quantum cryptographic chip. Background Art

[0002] Quantum computers are developing rapidly. In the next 10 to 30 years, quantum computing power that can crack the existing public key encryption system may appear. Post-quantum migration is already a problem that many countries and companies are solving. At present, the global Internet of Things is developing rapidly, not only covering daily life areas such as smart cities, smart medical care, Internet of Vehicles, and smart homes, but also developing rapidly in smart manufacturing, military and other fields. Most of the Internet of Things is connected by small terminal devices. These terminal devices have high power consumption, resulting in unreasonable waste of resources. Therefore, how to achieve low power consumption to save resources is a technical problem that needs to be solved urgently. At the same time, the terminal devices do not have the ability to resist quantum computer attacks, resulting in poor data transmission security of terminal devices, which greatly affects the entire Internet of Things ecosystem. Summary of the invention

[0003] The present invention provides an integrated system of a post-quantum cryptographic chip and a terminal device, which are used to solve the problem in the prior art that the Internet of Things is mostly composed of small terminal devices connected together, and these terminal devices have high power consumption, resulting in unreasonable waste of resources.

[0004] The embodiment of this specification provides an integrated system of a post-quantum cryptographic chip, including:

[0005] A main processor for sending post-quantum cryptographic computing tasks;

[0006] A power consumption detection module, used to receive current data provided by the post-quantum cryptographic chip and the execution status of the post-quantum cryptographic computing task, and calculate the power consumption of the post-quantum cryptographic chip according to the current data;

[0007] A clock management unit, used for adjusting the clock signal frequency required by the post-quantum cryptographic chip according to the power consumption and the execution state;

[0008] A voltage management unit is used to adjust the voltage required by the post-quantum cryptographic chip according to the power consumption and the execution state.

[0009] Optionally, the system further includes:

[0010] The current acquisition circuit is used to collect current data of the post-quantum cryptographic chip and transmit the current data to the power consumption detection module.

[0011] Optionally, the system further comprises: a phase locked loop, a voltage regulator and a power supply;

[0012] The clock management unit adjusts the frequency of the clock signal generated by the phase-locked loop according to the power consumption and the execution state;

[0013] The voltage management unit controls the voltage regulator to adjust the voltage generated by the power supply according to the power consumption and the execution state.

[0014] Optionally, the execution status is any one of task execution start, task execution in progress, and task execution completion. When the execution status is in the task execution start, the clock management unit is also used to control the phase-locked loop to produce the first preset clock signal frequency according to a first preset clock signal frequency and transmit it to the post-quantum cryptographic chip; the voltage management unit is also used to control the voltage regulator to adjust the power supply to produce the first preset voltage according to a first preset voltage and transmit it to the post-quantum cryptographic chip.

[0015] Optionally, when the execution state is in task execution, the clock management unit is further used to determine the change value of the clock signal frequency according to the current power consumption of the post-quantum cryptographic chip, the current clock signal frequency of the post-quantum cryptographic chip, and the clock signal frequency of the post-quantum cryptographic chip in the previous cycle, and adjust the current clock signal frequency produced by the phase-locked loop based on the change value of the clock signal frequency; the voltage management unit is further used to determine the change value of the voltage according to the current power consumption of the post-quantum cryptographic chip, the current voltage of the post-quantum cryptographic chip, and the voltage of the post-quantum cryptographic chip in the previous cycle, and control the voltage regulator to adjust the current voltage produced by the power supply based on the change value of the voltage.

[0016] Optionally, when the execution state is in the task execution completion state, the power consumption detection unit is also used to time the time after the task execution is completed, compare the time with the first preset time, and control the clock management unit and the voltage management unit based on the comparison result.

[0017] Optionally, when the time is greater than a first preset time and less than a second preset time, the clock management unit is further used to control the phase-locked loop to produce the second preset clock signal frequency according to a second preset clock signal frequency and transmit it to the post-quantum cryptographic chip; the voltage management unit is further used to control the voltage regulator to adjust the power supply to produce the second preset voltage according to a second preset voltage and transmit it to the post-quantum cryptographic chip; wherein the second preset clock signal frequency is less than the first preset clock signal frequency, and the second preset voltage is less than the first preset voltage.

[0018] Optionally, when the time is greater than a second preset time, the clock management unit is further used to control closing of the phase-locked loop; the voltage management unit is further used to control the voltage regulator to close the power supply.

[0019] Optionally, the power consumption detection module is also used to control the clock management unit to shut down the phase-locked loop when the power consumption of the post-quantum cryptographic chip is greater than a preset safety power consumption, and to control the voltage regulator to shut down the power supply by controlling the voltage management unit.

[0020] A terminal device includes an integrated system using the post-quantum cryptographic chip described above.

[0021] Its beneficial effects are: this application flexibly adjusts the clock signal frequency and voltage required by the post-quantum cryptographic chip to meet the terminal equipment's requirements for low power consumption, achieves rational use of resources, and achieves long-term standby operation. At the same time, the post-quantum cryptographic chip with post-quantum cryptographic algorithm function is integrated into the terminal equipment, so that the terminal equipment can run the post-quantum cryptographic algorithm during the communication process, ensuring that the communication process between terminals can resist quantum computer attacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0023] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0024] Figure 1 An integrated system structure diagram of a post-quantum cryptographic chip provided in an embodiment of this specification;

[0025] Figure 2 A schematic diagram of the principle of a terminal device provided in an embodiment of this specification. DETAILED DESCRIPTION

[0026] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0027] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0028] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0029] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0030] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0031] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0032] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0033] Reference Figure 1 An integrated system structure diagram of a post-quantum cryptographic chip provided for an embodiment of this specification includes: a main processor 1, used to send a post-quantum cryptographic computing task; a power consumption detection module 2, used to receive the current data provided by the post-quantum cryptographic chip 5 and the execution status of the post-quantum cryptographic computing task, and calculate the power consumption of the post-quantum cryptographic chip 5 according to the current data; a clock management unit 3, used to adjust the clock signal frequency required by the post-quantum cryptographic chip 5 according to the power consumption and the execution status; a voltage management unit 4, used to adjust the voltage required by the post-quantum cryptographic chip 5 according to the power consumption and the execution status. The system also includes: a phase-locked loop 6, a voltage regulator 7 and a power supply 8; the clock management unit 3 adjusts the clock signal frequency produced by the phase-locked loop 6 according to the power consumption and the execution status; the voltage management unit 4 controls the voltage regulator 7 to adjust the voltage produced by the power supply 8 according to the power consumption and the execution status.

[0034] In an optional embodiment, after the terminal device is integrated with the post-quantum cryptographic chip 5, the clock signal frequency and voltage required by the post-quantum cryptographic chip for different post-quantum cryptographic computing tasks are different. In order to ensure that the power consumption of the post-quantum cryptographic chip 5 is minimized when executing the post-quantum cryptographic computing task, it is necessary to adaptively adjust the clock signal frequency and voltage required by the post-quantum cryptographic chip 5. For this reason, the present application proposes an integrated system of post-quantum cryptographic chips. First, the main processor 1 sends a post-quantum cryptographic computing task to the post-quantum cryptographic chip 5. After the post-quantum cryptographic chip 5 confirms that it has received the post-quantum cryptographic computing task, when the post-quantum cryptographic computing task does not require the main processor 1 to provide data, such as the post-quantum cryptographic computing task is post-quantum key generation, at this time, the post-quantum cryptographic chip 5 only needs to run the internal post-quantum key algorithm. Taking the post-quantum cryptographic computing task as post-quantum key generation as an example, in the process of the post-quantum cryptographic chip 5 running the internal post-quantum key algorithm, that is, when the power consumption detection module 2 receives the execution state of the post-quantum key generation and is at the beginning of the task execution, the power consumption detection module 2 will transmit a control signal to the clock management unit 3, so that the clock management unit 3 controls the phase-locked loop 6 according to the first preset clock signal frequency to produce the first preset clock signal frequency and transmit it to the post-quantum cryptographic chip 5. At the same time, the power consumption detection module 2 will transmit a control signal to the voltage management unit 4, so that the voltage management unit 4 controls the voltage regulator 7 according to the first preset voltage to adjust the power supply 8 to produce the first preset voltage and transmit it to the post-quantum cryptographic chip 5. Then, the post-quantum cryptographic chip 5 starts to execute the post-quantum key algorithm based on the first preset clock signal frequency and the first preset voltage to generate the post-quantum key. Among them, the first preset clock signal frequency and the first preset voltage are the initial required clock signal frequency and voltage for the post-quantum cryptographic chip 5 to perform the post-quantum cryptographic computing task. It should be noted that the clock signal frequency is not limited to the phase-locked loop 6, and can also be other devices that can generate clock signal frequencies, which are not limited here.

[0035] Afterwards, the power consumption detection module 2 receives that the execution state of the post-quantum key generation has changed from the start of task execution to the task execution, and the power consumption detection module 2 starts to collect the current data of the post-quantum cryptographic chip 5 in real time, and calculates the current power consumption of the post-quantum cryptographic chip 5 in real time based on the current data; the clock management unit 3 determines the change value of the clock signal frequency based on the current power consumption of the post-quantum cryptographic chip 5, the current clock signal frequency of the post-quantum cryptographic chip 5, and the clock signal frequency of the post-quantum cryptographic chip in the previous cycle, and adjusts the current clock signal frequency produced by the phase-locked loop 6 based on the change value of the clock signal frequency, and applies the adjusted current clock signal frequency to the next cycle of the post-quantum cryptographic chip 5 running the post-quantum key generation task; at the same time, the voltage management unit 4 determines the change value of the current voltage based on the current power consumption of the post-quantum cryptographic chip 5, the current voltage of the post-quantum cryptographic chip 5, and the voltage of the post-quantum cryptographic chip 5 in the previous cycle, and controls the voltage regulator 7 to adjust the current voltage produced by the power supply 8 based on the change value of the voltage, and applies the adjusted current voltage to the next cycle of the post-quantum cryptographic chip 5 running the post-quantum key generation task. The power consumption detection module 2 collects the current data of the post-quantum cryptographic chip 5 in real time to calculate the power consumption, and adjusts the clock signal frequency and voltage acting on the post-quantum cryptographic chip 5 in real time according to the calculation results. This satisfies the terminal device's requirements for low power consumption, realizes the rational use of resources, and achieves long-term standby work. At the same time, the post-quantum cryptographic chip with post-quantum cryptographic algorithm function is integrated into the terminal device, so that the terminal device can run the post-quantum cryptographic algorithm in the communication process, and ensures that the communication process between terminals can resist quantum computer attacks. Among them, the post-quantum cryptographic chip 5 runs the post-quantum cryptographic calculation task periodically, and each process executed in the post-quantum cryptographic chip 5 according to the post-quantum cryptographic calculation task can also be regarded as a time node, and each time node is used instead of the period to adjust the clock signal frequency and voltage of the post-quantum cryptographic chip 5.

[0036] Finally, when the post-quantum cryptographic chip 5 completes the post-quantum key generation task, the post-quantum cryptographic chip 5 will send a task completion signal to the main processor 1 and the power consumption detection module 2. The main processor 1 will issue a post-quantum key storage instruction to the post-quantum cryptographic chip 5 based on the task completion signal, so that the post-quantum key generated by the post-quantum cryptographic chip 5 when performing the post-quantum key generation task is stored in the key storage area for subsequent use in data signing, data encryption, etc.

[0037] At the same time, the power consumption detection module 2 will time the time after the task is executed, and compare the time with the first preset time, and control the clock management unit 3 and the voltage management unit 3 based on the comparison result. Specifically, when the time is greater than the first preset time and less than the second preset time, the clock management unit 3 controls the phase-locked loop 6 to produce the second preset clock signal frequency according to the second preset clock signal frequency and transmits it to the post-quantum cryptographic chip 5; at the same time, the voltage management unit 4 controls the voltage regulator 7 to adjust the power supply 8 to produce the second preset voltage according to the second preset voltage and transmit it to the post-quantum cryptographic chip 5; wherein the second preset clock signal frequency is less than the first preset clock signal frequency, and the second preset voltage is less than the first preset voltage.

[0038] For example, assuming that the first preset time is 10ms, the second preset time is 20ms, the timing time is 15ms, and the timing time is between the first preset time and the second preset time, it can be determined that the post-quantum cryptographic chip 5 does not need to continue working, and the post-quantum cryptographic chip 5 can be adjusted to a dormant state. Specifically, the clock management unit 3 controls the phase-locked loop 6 to produce a second preset clock signal frequency according to the second preset clock signal frequency and transmits it to the post-quantum cryptographic chip 5; at the same time, the voltage management unit 4 controls the voltage regulator 7 to adjust the power supply 8 according to the second preset voltage to produce the second preset voltage and transmit it to the post-quantum cryptographic chip 5. The post-quantum cryptographic chip 5 runs the post-quantum cryptographic chip 5 based on the second preset clock signal frequency and the second preset voltage, so that the post-quantum cryptographic chip 5 is in a dormant state, wherein the second preset clock signal frequency is less than the first preset clock signal frequency, and the second preset voltage is less than the first preset voltage, which indicates that the clock signal frequency and voltage in the dormant state are lower than the clock signal frequency and voltage required for the post-quantum cryptographic chip 5 to perform the post-quantum cryptographic computing task. By using the above method, it is determined whether the post-quantum cryptographic chip 5 has entered a dormant state and the clock signal frequency and voltage are adjusted, thereby achieving rational utilization of resources and long-term standby operation.

[0039] In an optional embodiment, when the time is greater than a second preset time, the clock management unit 3 is further used to control the phase-locked loop 6 to be turned off; the voltage management unit 4 is further used to control the voltage regulator 7 to turn off the power supply 8.

[0040] In an optional embodiment, for example, assuming that the first preset time is 10ms, the second preset time is 20ms, and the timing time is 21ms, and the timing time is greater than the second preset time, it can be determined that the post-quantum cryptographic chip 5 does not need to continue to sleep, and the post-quantum cryptographic chip 5 can be adjusted to a closed state. Specifically, the clock management unit 3 controls the phase-locked loop 6 to turn off; at the same time, the voltage management unit 4 controls the voltage regulator 7 to turn off the power supply 8, so as to achieve the effect of turning off the post-quantum cryptographic chip 5. By the above method, it is determined whether the post-quantum cryptographic chip 5 enters the closed state and adjusts the clock signal frequency and voltage to achieve reasonable use of resources.

[0041] Optionally, the system further includes: a current acquisition circuit 9, which is used to collect current data of the post-quantum cryptographic chip and transmit the current data to the power consumption detection module.

[0042] In an optional embodiment, in order to realize the collection of current data of the post-quantum cryptographic chip 5 by the power consumption detection module, the current data of the post-quantum cryptographic chip is collected by using the current collection circuit 9, so as to facilitate the subsequent power consumption calculation of the post-quantum cryptographic chip. It should be noted that the collection of current data of the post-quantum cryptographic chip is not limited to the current collection circuit 9, but can also be other devices or circuits capable of current collection, which is not limited here; and the current collection circuit 9 is a conventional circuit in the prior art, which will not be described in detail here.

[0043] In an optional embodiment, when the power consumption of the post-quantum cryptographic chip 5 is greater than the preset safety power consumption, the power consumption detection module 2 controls the clock management unit 3 to turn off the phase-locked loop 6 and controls the voltage regulator 7 to turn off the power supply 8 by controlling the voltage management unit 4. The preset safety power consumption is the maximum value of the power consumption of the post-quantum cryptographic chip 5 when it is running. When the power consumption of the post-quantum cryptographic chip 5 calculated by the power consumption detection module 2 is greater than the preset safety power consumption, it indicates that the post-quantum cryptographic chip 5 is abnormal, and the post-quantum cryptographic chip 5 is directly turned off. At the same time, the power consumption detection module 2 reports the abnormal information of the post-quantum cryptographic chip 5 to the main processor 1, and the main processor 1 records the abnormal information and notifies the management personnel to perform abnormal inspection of the post-quantum cryptographic chip 5 to prevent the post-quantum cryptographic chip 5 from giving wrong results of the post-quantum cryptographic calculation task when it is running.

[0044] In an optional embodiment, when the post-quantum cryptographic computing task is to encrypt or sign a certain data using the post-quantum cryptographic chip 5, the post-quantum cryptographic chip 5 sends a signal that the post-quantum cryptographic chip 5 is ready, i.e., a ready signal, to the main processor 1 through the communication interface; thereafter, the main processor 1 sends the data to be encrypted or the data to be signed to the post-quantum cryptographic chip 5 through the communication interface, and finally, the post-quantum cryptographic chip 5 performs the post-quantum cryptographic computing task to encrypt the encrypted data or sign the signed data, and sends a done signal to the main processor 1 after completing the post-quantum cryptographic computing task; finally, the main processor 1 sends a data storage instruction to the post-quantum cryptographic chip 5 based on the done signal, and stores the encrypted data or signed data in the data storage area through the communication interface. This application integrates the post-quantum cryptographic chip 5 with the post-quantum cryptographic algorithm function into the terminal device, so that the terminal device can run the post-quantum cryptographic algorithm in the communication process, and ensures that the communication process between the terminals can resist quantum computer attacks.

[0045] A terminal device 01 includes an integrated system 02 using the post-quantum cryptographic chip as described above.

[0046] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the present invention is not inherently related to any specific computer, virtual device or electronic device, and various general devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0047] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0048] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. An integrated system of a post-quantum cryptographic chip, characterized in that: include: A main processor for sending post-quantum cryptographic computing tasks; A power consumption detection module, used to receive current data provided by the post-quantum cryptographic chip and the execution status of the post-quantum cryptographic computing task, and calculate the power consumption of the post-quantum cryptographic chip according to the current data; A clock management unit, used for adjusting the clock signal frequency required by the post-quantum cryptographic chip according to the power consumption and the execution state; A voltage management unit is used to adjust the voltage required by the post-quantum cryptographic chip according to the power consumption and the execution state.

2. The system according to claim 1, characterized in that The system further comprises: The current acquisition circuit is used to collect current data of the post-quantum cryptographic chip and transmit the current data to the power consumption detection module.

3. The system according to claim 1, characterized in that The system also includes: a phase locked loop, a voltage regulator and a power supply; The clock management unit adjusts the frequency of the clock signal generated by the phase-locked loop according to the power consumption and the execution state; The voltage management unit controls the voltage regulator to adjust the voltage generated by the power supply according to the power consumption and the execution state.

4. The system according to claim 3, characterized in that The execution state is any one of task execution start, task execution in progress, and task execution completion. When the execution state is at the task execution start, the clock management unit is also used to control the phase-locked loop to produce the first preset clock signal frequency according to the first preset clock signal frequency and transmit it to the post-quantum cryptographic chip; the voltage management unit is also used to control the voltage regulator to adjust the power supply to produce the first preset voltage according to the first preset voltage and transmit it to the post-quantum cryptographic chip.

5. The system according to claim 4, characterized in that When the execution state is in task execution, the clock management unit is further used to determine the change value of the clock signal frequency according to the current power consumption of the post-quantum cryptographic chip, the current clock signal frequency of the post-quantum cryptographic chip, and the clock signal frequency of the post-quantum cryptographic chip in the previous cycle, and adjust the current clock signal frequency produced by the phase-locked loop based on the change value of the clock signal frequency; the voltage management unit is further used to determine the change value of the voltage according to the current power consumption of the post-quantum cryptographic chip, the current voltage of the post-quantum cryptographic chip, and the voltage of the post-quantum cryptographic chip in the previous cycle, and control the voltage regulator to adjust the current voltage produced by the power supply based on the change value of the voltage.

6. The system according to claim 4, characterized in that When the execution state is in the task execution completion state, the power consumption detection unit is further used to time the time after the task execution is completed, compare the time with the first preset time, and control the clock management unit and the voltage management unit based on the comparison result.

7. The system according to claim 6, characterized in that When the time is greater than the first preset time and less than the second preset time, the clock management unit is further used to control the phase-locked loop to produce the second preset clock signal frequency according to the second preset clock signal frequency and transmit it to the post-quantum cryptographic chip; the voltage management unit is further used to control the voltage regulator to adjust the power supply to produce the second preset voltage according to the second preset voltage and transmit it to the post-quantum cryptographic chip; wherein the second preset clock signal frequency is less than the first preset clock signal frequency, and the second preset voltage is less than the first preset voltage.

8. The system according to claim 6, characterized in that When the time is greater than a second preset time, the clock management unit is further used to control closing of the phase-locked loop; the voltage management unit is further used to control the voltage regulator to close the power supply.

9. The system according to claim 8, characterized in that The power consumption detection module is also used to control the clock management unit to shut down the phase-locked loop when the power consumption of the post-quantum cryptographic chip is greater than the preset safety power consumption, and to control the voltage regulator to shut down the power supply by controlling the voltage management unit.

10. A terminal device, characterized in that: An integrated system comprising the post-quantum cryptographic chip as described in claims 1-9.

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