Electronic circuit simulation model acquisition method and electronic equipment

Abstract

The invention provides an electronic circuit simulation model obtaining method, and relates to the technical field of semiconductor device simulation. The electronic circuit simulation method comprises the following steps: generating a graph data structure according to a netlist file of an electronic circuit, and acquiring a prediction performance index of the electronic circuit by utilizing a graph attention neural network and the graph data structure; and obtaining the deviation between the predicted performance index and the simulation result of the electronic circuit, and updating the parameters of the graph attention neural network based on the deviation and a back propagation algorithm to obtain a simulation model of the electronic circuit. According to the embodiment of the invention, circuit simulation data can be efficiently fitted through the simulation model, the simulation time and the simulation cost of the electronic circuit are greatly reduced, the simulation efficiency is improved, accurate and rapid performance evaluation and simulation time can be provided for circuit design, the rapid convergence of a DTCO process is effectively met, and the simulation efficiency is improved. The design iteration period is shortened; and the trial and error cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device simulation technology, and more specifically, to an electronic circuit simulation model acquisition method and an electronic device. Background Art

[0002] DTCO (Decign Technology Co Optimization) is an emerging design and process collaborative optimization paradigm. By building a bridge between devices, processes and designs, it achieves global optimization of parameter space at a higher level. It is expected to break through the performance upgrade bottleneck of Moore's Law and continue the development of the semiconductor industry.

[0003] Electronic circuit simulation is one of the key links in the DTCO process. Its goal is to establish a high-fidelity mapping relationship between device structure, process parameters and performance indicators. Accurate and efficient simulation models can accelerate the convergence of the DTCO process, shorten the design iteration cycle, and reduce the cost of trial and error. However, traditional circuit simulation methods are mainly based on SPICE (Simulation Program with Integrated Circuit Emphasis) and its variant tools. SPICE uses an improved node analysis method to simulate the dynamic behavior of the circuit by solving the differential algebraic equations of the circuit in detail at each time step. The dynamic characteristics of the circuit are simulated by calculating the voltage and branch current at each node. This method has high accuracy, but the computational complexity is also very high, and the time and space complexity increases linearly with the circuit scale. However, today's circuits are becoming more and more complex, resulting in a lot of time and time required for calculation when using this method for circuit simulation, which is time-consuming and costly, greatly reducing the efficiency of simulation, and it is difficult to effectively meet the needs of rapid convergence of the DTCO process, shortening the design iteration cycle, and reducing the cost of trial and error. Summary of the invention

[0004] The embodiments of the present application provide a method for obtaining an electronic circuit simulation model and an electronic device, which can solve the problem that electronic circuit simulation requires a lot of time to calculate, is time-consuming, costly, has low simulation efficiency, and is difficult to meet DTCO process requirements.

[0005] In order to achieve this purpose, the embodiments of the present application provide the following solutions.

[0006] According to one aspect of an embodiment of the present application, a method for obtaining an electronic circuit simulation model is provided, wherein a graph data structure is generated according to a netlist file of the electronic circuit, and a predicted performance index of the electronic circuit is obtained using a graph attention neural network and the graph data structure;

[0007] Obtain a deviation between the prediction performance index and a simulation result of the electronic circuit, update the parameters of the graph attention neural network based on the deviation and a back propagation algorithm, and obtain a simulation model of the electronic circuit.

[0008] In a possible implementation, the graph data structure includes a feature vector of a node, and obtaining the feature vector includes:

[0009] Obtaining node characteristics through the netlist file, wherein the node characteristics include a device type code, a device physical parameter, and a device DC operating point;

[0010] The node features are concatenated to obtain the feature vector.

[0011] In a possible implementation, the graph attention neural network includes a graph attention layer, a graph convolution layer, a gated recurrent unit, a transposed convolution layer, a pooling layer, and a fully connected layer. The use of the graph attention neural network and the graph data structure to obtain the predicted performance index of the electronic circuit includes:

[0012] Using the graph attention layer to update the feature vector of the node and updating the feature of the node through the graph convolution layer, the updating of the feature vector is achieved based on the attention weight;

[0013] Acquire the node state of the node at the last time step by using the gated recurrent unit and the feature vector;

[0014] The transposed convolution layer, the pooling layer, and the fully connected layer are used to obtain the prediction performance index corresponding to the node state of the last time step.

[0015] In a possible implementation, the updating the feature vector of a node by using the graph attention layer includes:

[0016] Calculating the attention weights between the nodes, and updating the feature vector according to the attention weights;

[0017] The attention weight is calculated based on the query-key, and the calculation formula of the attention weight is:

[0018]

[0019] In the formula, α ij For node v i To node v j The attention weight, W Q , W k are the linear transformation matrices of query and key respectively, a is the attention vector, N i For node v iThe set of neighboring nodes, x i For node v i The eigenvector of j For node v j The eigenvector of k For node v k The eigenvector of T is the transpose of the attention vector a, vert represents concatenation, and LeakyReLU is the leakage correction linear unit activation function;

[0020] The updating formula of the feature vector is:

[0021]

[0022] Among them, W V ∈R F′×F is the value transformation matrix, R F′×F represents a real matrix of F′×F, x′ i is node v i The updated feature vector, x j For node v j The eigenvector of ij For node v i To node v j The attention weight.

[0023] In a possible implementation, updating the feature of the node through the graph convolution layer includes:

[0024] Based on the formula Update the feature vector of the node, where W k ∈R F′×F is the weight matrix of the k-th order polynomial, K is the polynomial order, v i The k-order neighborhood of For node v i The normalized degree, A ij is the adjacency matrix element, Represents node v j The normalization degree of .

[0025] In a possible implementation, the acquiring the node state of the node at the last time step by using the gated recurrent unit and the feature vector includes:

[0026] The node state is updated using the time step, the updated feature vector and the gated recurrent unit, and the node state of the last time step is determined based on the update result of the node state. The update formula of the node state is:

[0027]

[0028]

[0029]

[0030]

[0031] in, is the node v at time t i The node status, is the node v at time t i Candidate status, is the node v aggregated by the graph attention layer and graph convolution layer at time t i The eigenvector of r , W z , W h ∈R F′×2F′ Reset Gate Update Gate and candidate status The corresponding weight matrix, b r , b z , b h ∈R F′ To reset the gate Update Gate and candidate status The corresponding bias vector, σ(·) is the sigmoid activation function, tanh(·) is the hyperbolic tangent activation function, and ⊙ represents the Hadamard product.

[0032] In a possible implementation, the using the transposed convolution layer, the pooling layer, and the fully connected layer to obtain the prediction performance index corresponding to the node state at the last time step includes:

[0033] By formula Obtain the prediction performance index corresponding to the node state, where: is the prediction performance index, H (T) ∈R N×F′ is the final state matrix of all nodes, which includes the node states of all nodes in the last time step, TransConv(·) is the transposed convolution operation, AvgPool(·) is the average pooling operation, and f out (·) indicates a fully connected operation.

[0034] In a possible implementation, the calculation formula of the deviation is:

[0035]

[0036] Among them, L(θ) represents the mean square error function, θ is the network parameter of the graph attention neural network, and y pred is the prediction performance indicator, y true is the actual performance indicator corresponding to the predicted performance indicator, and N is the number of training samples.

[0037] In a possible implementation, updating the parameters of the graph attention neural network based on the deviation and the back propagation algorithm includes:

[0038] Calculating an update result of the network parameter, and updating the network parameter based on the update result and the back propagation algorithm;

[0039] The calculation formula of the network parameters is:

[0040]

[0041] Among them, θ * is the update result of the network parameter θ, α is the learning rate, is the gradient.

[0042] According to one aspect of an embodiment of the present application, there is provided an electronic device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0043] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0044] The layout file generation method provided by the present application includes generating a graph data structure according to the netlist file of the electronic circuit, obtaining the predicted performance index of the electronic circuit by using the graph attention neural network and the graph data structure; obtaining the deviation between the predicted performance index and the simulation result of the electronic circuit, updating the parameters of the graph attention neural network based on the deviation and the back propagation algorithm, and obtaining the simulation model of the electronic circuit. The present application implements the use of the graph attention neural network to learn the dynamic performance of the electronic circuit from the netlist file of the electronic circuit and focus on the key signal characteristics in the circuit to construct a simulation model of the electronic circuit. It can efficiently fit the circuit simulation data through the simulation model, greatly reduce the simulation time and simulation cost of the electronic circuit, improve the simulation efficiency, and provide accurate and fast performance evaluation for circuit design, simulation time, effectively meet the needs of fast convergence of the DTCO process, shorten the design iteration cycle, and reduce the cost of trial and error. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in describing the embodiments of the present application.

[0046] Figure 1A flowchart of a method for obtaining an electronic circuit simulation model provided in an embodiment of the present application;

[0047] Figure 2 A flowchart of the electronic circuit simulation method provided in the embodiment of the present application;

[0048] Figure 3 A schematic diagram of the generation of a graph data structure provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of a graph attention neural network provided in an embodiment of the present application;

[0050] Figure 5 A structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0052] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" indicates that it is implemented as "A", or is implemented as "A", or is implemented as "A and B".

[0053] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0054] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present invention and the technical effects produced by the technical solutions of the present invention. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0055] The electronic circuit simulation model acquisition method and electronic device provided in the present application are intended to solve at least one technical problem existing in the prior art.

[0056] A method for obtaining an electronic circuit simulation model is provided in an embodiment of the present application, wherein the graph attention neural network includes a graph attention layer, a graph convolution layer, a gated recurrent unit, a transposed convolution layer, a pooling layer and a fully connected layer, and the graph attention neural network is used to obtain a simulation model of the electronic circuit.

[0057] Alternatively, if Figure 1-Figure 4 As shown, the electronic circuit simulation model acquisition method includes:

[0058] S101: Generate a graph data structure according to a netlist file of the electronic circuit, and use the graph attention neural network and the graph data structure to obtain a predicted performance indicator of the electronic circuit.

[0059] Optionally, the netlist file includes information such as the encoding of the device type, the physical parameters of the device, and the DC operating point of the device. The netlist file is converted into a graph data structure. During the conversion process, information such as devices, nodes, and connection relationships in the electronic circuit is obtained. The devices and nodes in the circuit are mapped to nodes of the graph data structure, and the connection relationships are mapped to edges of the graph data structure. The feature vector of each node in the graph data structure incorporates attribute information such as device type, physical parameters, and bias conditions.

[0060] Optionally, the graph data structure includes a feature vector of a node, and obtaining the feature vector includes: obtaining node features through a netlist file, the node features include a device type encoding, device physical parameters, and a device DC operating point, and splicing the node features to obtain a feature vector.

[0061] Optionally, the node features may also include topological properties such as the degree and betweenness centrality of the node, and the topological properties are determined as additional structural features.

[0062] In one embodiment, the feature vector of a node is x i ∈R F , R F represents the feature vector x i belongs to an F-dimensional real number space, namely R F The dimension of the feature vector is F, which is composed of all node features, including:

[0063] (1) One-hot encoding of device type Among them, N dis the number of device types. The device types of semiconductor devices used in electronic circuits include NMOS (N-channel Metal-Oxide-Semiconductor), PMOS (P-channel Metal-Oxide-Semiconductor), resistors, capacitors, etc.;

[0064] (2) Physical parameters of the device N p It is the dimension of physical parameters, representing the number of physical parameters. The physical parameters include the channel length L, gate width W of the transistor, the resistance R, the capacitance C of the capacitor, etc.

[0065] (3) The DC (Direct Current) operating point of the device N b is the dimension of the DC operating point, which includes the gate voltage V GS , drain current I DS wait.

[0066] By concatenating the above node features, we can get node v i The eigenvector x i :

[0067]

[0068] Among them, the total dimension of the feature vector F = N d +N p +N b The feature vector can also introduce the topological properties of the node, such as the degree of the node deg(v i ), betweenness centrality bc(v i ) etc. as additional structural features.

[0069] Optionally, multiple netlist files of electronic circuits can be obtained, multiple graph data structures can be generated using the netlist files, and circuit data sets can be established using these graph data structures. The circuit data sets are used as training sets, validation sets, and test sets required for graph attention neural network training. The training set is used for parameter learning of the graph attention neural network, the validation set is used for hyperparameter tuning and model selection, and the test set is used to evaluate the generalization performance of the simulation model.

[0070] Optionally, after obtaining the graph data structure, it is used for training a graph attention neural network. During the training process, predictive performance indicators of electronic circuits are obtained based on the graph attention neural network and the graph data structure, including: using the graph attention layer to update the feature vector of the node and updating the features of the node through the graph convolution layer, and the update of the feature vector is based on the attention weight; using the gated recurrent unit and the feature vector to obtain the node state of the node in the last time step; using the transposed convolution layer, the pooling layer and the fully connected layer to obtain the predictive performance indicator corresponding to the node state in the last time step.

[0071] Optionally, the graph attention layer can use scaled dot-product attention to update the feature vector. And the update of attention weight can be obtained by query-key similarity calculation. The graph attention layer calculates the attention weights between nodes through the self-attention mechanism, thereby learning the information transfer and interaction within the circuit.

[0072] Optionally, the feature vector of the node is updated using the graph attention layer, including: calculating the attention weights between the nodes, and updating the feature vector according to the attention weights; the attention weights are calculated based on the query-key, and the calculation formula of the attention weights is:

[0073]

[0074] In the formula, α ij For node v i To node v j The attention weight, W Q , W k are the linear transformation matrices of query and key respectively, a is the attention vector, N i For node v i The set of neighboring nodes, x i For node v i The eigenvector of j For node v j The eigenvector of k For node v k The eigenvector of T is the transpose of the attention vector a, vert represents concatenation, and LeakyReLU is the leakage correction linear unit activation function;

[0075] The update formula of the feature vector is:

[0076]

[0077] Among them, W V ∈R F′×Fis the value transformation matrix, which is used to transform the feature vector x of the domain node j Transform to node x i The eigenvector of F′×F represents a real matrix of F′×F, where F′ represents x′ i The dimension of x′ i is node v i The updated feature vector, x j For node v j The eigenvector of ij For node v i To node v j The attention weight.

[0078] Optionally, Among them, γ is a small constant, and x represents the concatenation result obtained by concatenating Vert when calculating similarity. Q x i With each key W in the neighborhood K x j The concatenation is multiplied with the transpose of the attention vector a, and the scalar attention score is obtained by LeakyReLU activation. Then the scalar attention scores of all neighboring nodes are normalized by softmax to obtain the attention weight α ij The larger the weight, the better the node v j v i The greater the impact.

[0079] Optionally, when the feature vector of a node is updated using the graph attention layer, the feature vector can also be updated using the graph convolution layer. The graph convolution layer can use the spectral domain convolution of the Chebyshev polynomial expansion to update the feature vector of the node v i Update the features. Specifically, update the features of the nodes through the graph convolution layer, including:

[0080] Based on the formula Update the node's feature vector, where W k ∈R F′×F is the weight matrix of the k-th order polynomial, K is the polynomial order, v i The k-order neighborhood of node v i The set of nodes whose distance does not exceed k, For node v i The normalized degree, A ij is the adjacency matrix element, Represents node v jThe normalization degree is used to balance the aggregation weights of different nodes. Spectral domain convolution avoids Fourier transform and can be defined directly in the graph space, making the calculation efficient. K-order polynomial convolution is equivalent to aggregating K-hop neighborhood information. Convolution kernel parameter W k It can learn the multi-scale features of graph signals to obtain the feature representation of the local structure of the circuit. Compared with GCN, ChebNet can capture higher-order structural information.

[0081] In one embodiment, the updated feature vector is transmitted to the gated recurrent unit, the gated recurrent unit introduces the time step t, and updates the node state based on the time step t and the updated feature vector. The node state of the node at the last time step is obtained by using the gated recurrent unit and the feature vector, including:

[0082] The node state is updated using the time step, the updated feature vector and the gated recurrent unit. The node state of the last time step is determined based on the updated node state. The update formula of the node state is:

[0083]

[0084]

[0085]

[0086]

[0087] in, is the node v at time t i The node status, is the node v at time t i Candidate status, is the node v aggregated by the graph attention layer and graph convolution layer at time t i The eigenvector of r , W z , W h ∈R F′×2F′ Reset Gate Update Gate and candidate status The corresponding weight matrix, b r , b z , b h ∈R F′ To reset the gate Update Gate and candidate status The corresponding bias vector, σ(·) is the sigmoid activation function, tanh(·) is the hyperbolic tangent activation function, and ⊙ represents the Hadamard product.

[0088] Specifically, reset the gate Control the node status at the previous moment For the current candidate status The influence of the update gate Control the node status at the previous moment and the current candidate status To the new state Through iterative calculation, GRU (Gated Recurrent Unit) can model the temporal evolution of circuit states and capture the dynamic behavior of circuits.

[0089] Optionally, the transposed convolution layer, the pooling layer, and the fully connected layer are used to obtain the prediction performance indicators corresponding to the node state at the last time step, including:

[0090] By formula Get the prediction performance index corresponding to the node status, where H (T) ∈R N×F′ is the final state matrix of all nodes, which includes the node states of all nodes in the last time step, TransConv(·) is the transposed convolution operation of the transposed convolution layer, AvgPool(·) is the average pooling operation of the pooling layer, and f out (·) represents the fully connected operation of the fully connected layer. The node state of the last time step is converted into a prediction performance indicator through the operations of the transposed convolution layer, the pooling layer, and the fully connected layer.

[0091] Optionally, the predicted performance indicator may be a circuit performance indicator, which includes gain, bandwidth, power consumption, and other indicators related to circuit performance.

[0092] S102: Obtain the deviation between the predicted performance index and the simulation result of the electronic circuit, update the parameters of the graph attention neural network based on the deviation and the back propagation algorithm, and obtain the simulation model of the electronic circuit.

[0093] Optionally, the deviation can be measured by a loss function. Specifically, the loss function can be a mean square error loss function, which is used to measure the deviation between the performance index predicted by the graph attention neural network and the actual performance index.

[0094] Optionally, the deviation is calculated as:

[0095]

[0096] Among them, L(θ) represents the mean square error function, θ is the network parameter of the graph attention neural network, and y pred is the prediction performance indicator, y trueis the actual performance indicator corresponding to the predicted performance indicator, and N is the number of training samples when training the graph attention neural network. The trained graph attention neural network can be verified using the validation set, and the deviation can be obtained based on the actual performance indicator in the validation set.

[0097] Optionally, after obtaining the calculation result of the loss function, the network parameter θ can be updated by minimizing the loss function using an optimization algorithm such as gradient descent to achieve end-to-end training of the model. The updating of the parameters of the graph attention neural network based on the deviation and back propagation algorithm includes: calculating the update result of the network parameters, and updating the network parameters based on the update result and the back propagation algorithm; the calculation formula of the network parameters is:

[0098]

[0099] Among them, θ * is the update result of the network parameter θ, α is the learning rate, The back propagation algorithm combines deviation calculation with parameter update to achieve rapid update of the simulation model and improve the consistency between the output of the simulation model and the actual performance of the electronic circuit.

[0100] Optionally, multiple rounds of iterative optimization are implemented in the graph attention neural network training process through deviation calculation and parameter update, and the deviation between the predicted performance index and the true value is continuously reduced. After the number of iterations reaches a preset value or the deviation is less than a preset value, the training is completed and the trained graph attention neural network is determined as a simulation model of the electronic circuit.

[0101] By combining the above methods, this application constructs an end-to-end graph attention neural network that can learn its dynamic performance from the original circuit topology based on the netlist file. The attention mechanism focuses on the key signal paths in the circuit, enhancing the interpretability of the model. Graph convolution and GRU model the structural and timing characteristics of the circuit, expanding the scope of application of the model. Transposed convolution, pooling, and fully connected operations ensure the consistency of the output with the physical meaning. Through back-propagation optimization, the model can efficiently fit circuit simulation data and provide accurate and fast performance evaluation for circuit design.

[0102] In one embodiment, Figure 2-Figure 4As shown, the electronic circuit is a CMOS operational amplifier, and the netlist file stores the device and connection information in SPICE format. The netlist file is parsed into a graph data structure, and the graph data structure is used to obtain a data set for graph attention neural network training. The graph data structure includes an adjacency matrix (such as the adjacency matrix of nodes M1-M5) and node features (node ​​features of nodes M1-M5). The adjacency matrix is ​​obtained by extracting the device connection relationship, and the node features are obtained by extracting the device attribute features. 1 in the adjacency matrix indicates that there is a connection between the two nodes, and 0 indicates that there is no connection between the two nodes. At the same time, the key features of each device node are extracted from the netlist file, such as device type, gate length and width, gate connection, source connection, drain connection, substrate connection, port connection object, bias operating point and other features, and these features are used to form the feature vector of the node. The adjacency matrix and node features together constitute the graph data structure of the circuit as the input of the graph attention neural network.

[0103] After the graph data structure is input into the graph attention neural network, such as Figure 4 As shown in the figure, the graph data structure of the circuit is mapped to the input tensor of the neural network. The graph attention layer aggregates the information of the neighboring nodes through scaled dot-product attention. Calculate the query-key similarity, generate the attention weight matrix, weight the sum of the value vectors, and update the node representation (such as updating the feature vectors A and B to A′ and B′ respectively). The graph convolution layer uses K-order Chebyshev polynomials to approximate the spectral domain convolution to aggregate the neighborhood information at multiple scales. The convolution kernel parameter w k Learn the local structural features of graph signals. The gated recurrent unit introduces time step t to model the temporal evolution of the circuit state. Reset gate r t and update gate z t Control the influence of previous state on current state, candidate state The node representation is updated through nonlinear transformation. The output layer restores the graph data to performance indicators through transposed convolution, pooling operation and fully connected layer. The transposed convolution maps the graph representation back to the grid structure, the average pooling extracts the global features, and the fully connected layer maps to the prediction performance indicators. The predicted performance index may include key performance indicators such as gain and bandwidth of the operational amplifier. Based on the deviation between the predicted performance index and the actual performance index, it is detected whether the simulation accuracy reaches a threshold. If so, it is determined that a simulation model is obtained. If not, training is performed again.

[0104] The electronic circuit simulation model acquisition method of the present application has the following advantages:

[0105] (1) The circuit is considered as a dynamic graph structure that evolves over time. Nodes represent the devices and nodes of the circuit, and edges represent the connections between devices. By passing time step information in the graph attention neural network, the model can capture the change process of the circuit state over time and more accurately simulate the transient response characteristics of the circuit in the time domain.

[0106] (2) In addition to encoding the device type as a node feature, the physical parameters of the device (such as the channel length and gate width of the transistor) and the DC operating point of the device (such as bias voltage and current) are also incorporated into the node representation. The model can adaptively adjust the attention weights to focus on the impact of different device properties on circuit performance, enhancing the model's adaptability to device diversity.

[0107] (3) The attention mechanism is used to enhance the interpretability of the model. The graph attention layer learns the interaction strength between circuit nodes, and the distribution of attention weights reflects the importance of different devices and connections to the circuit function. By visualizing the attention weights of key nodes and edges, we can gain insight into the signal propagation path and bottlenecks of the circuit, which provides an important reference for optimizing circuit topology and parameters.

[0108] In an optional embodiment, an electronic device is provided, such as Figure 5 As shown, Figure 5 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0109] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0110] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0111] Memory 4003 can be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disc, optical disk, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium, other magnetic storage devices or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation here.

[0112] The memory 4003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0113] Among them, the electronic device can be any electronic product that can interact with an object, such as a personal computer, a tablet computer, a smart phone, a personal digital assistant (PDA), a game console, an interactive network television (IPTV), a smart wearable device, etc.

[0114] The electronic device may also include a network device and / or an object device, wherein the network device includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud consisting of a large number of hosts or network servers based on cloud computing.

[0115] The network where the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (Virtual Private Network, VPN), etc.

[0116] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0117] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0118] The above is only an optional implementation method for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A method for obtaining an electronic circuit simulation model, characterized in that: The method comprises: Generate a graph data structure according to a netlist file of an electronic circuit, and obtain a predicted performance indicator of the electronic circuit using a graph attention neural network and the graph data structure; Obtain a deviation between the prediction performance index and a simulation result of the electronic circuit, update the parameters of the graph attention neural network based on the deviation and a back propagation algorithm, and obtain a simulation model of the electronic circuit.

2. The method for obtaining an electronic circuit simulation model according to claim 1, characterized in that: The graph data structure includes a feature vector of a node, and obtaining the feature vector includes: Obtaining node characteristics through the netlist file, wherein the node characteristics include a device type code, a device physical parameter, and a device DC operating point; The node features are concatenated to obtain the feature vector.

3. The method for obtaining an electronic circuit simulation model according to claim 2, characterized in that: The graph attention neural network includes a graph attention layer, a graph convolution layer, a gated recurrent unit, a transposed convolution layer, a pooling layer, and a fully connected layer. The use of the graph attention neural network and the graph data structure to obtain the prediction performance index of the electronic circuit includes: Using the graph attention layer to update the feature vector of the node and updating the feature of the node through the graph convolution layer, the updating of the feature vector is achieved based on the attention weight; Acquire the node state of the node at the last time step by using the gated recurrent unit and the feature vector; The transposed convolution layer, the pooling layer, and the fully connected layer are used to obtain the prediction performance index corresponding to the node state of the last time step.

4. The method for obtaining an electronic circuit simulation model according to claim 3, characterized in that: The updating of the feature vector of the node by using the graph attention layer includes: Calculating the attention weights between the nodes, and updating the feature vector according to the attention weights; The attention weight is calculated based on the query-key, and the calculation formula of the attention weight is: In the formula, α ij For node v i To node v j The attention weight, W Q , W k are the linear transformation matrices of query and key respectively, a is the attention vector, N i For node v i The set of neighboring nodes, x i For node v i The eigenvector of j For node v j The eigenvector of k For node v k The eigenvector of T is the transpose of the attention vector a, vert represents concatenation, and LeakyReLY is the leakage correction linear unit activation function; The updating formula of the feature vector is: Among them, W v ∈R F′×F is the value transformation matrix, R F′×F represents a real matrix of F′×F, x′ i is node v i The updated feature vector, x j For node v j The eigenvector of ij For node v i To node v j The attention weight.

5. The method for obtaining an electronic circuit simulation model according to claim 4, characterized in that: The updating of the feature of the node through the graph convolution layer includes: Based on the formula Update the feature vector of the node, where W k ∈R F′×F is the weight matrix of the k-th order polynomial, K is the polynomial order, v i The k-order neighborhood of For node v i The normalized degree, A ij is the adjacency matrix element, Represents node v j The normalization degree of .

6. The method for acquiring an electronic circuit simulation model according to claim 3, characterized in that: The obtaining the node state of the node at the last time step by using the gated recurrent unit and the feature vector includes: The node state is updated using the time step, the updated feature vector and the gated recurrent unit, and the node state of the last time step is determined based on the update result of the node state. The update formula of the node state is: in, is the node v at time t i The node status, is the node v at time t i Candidate status, is the node v aggregated by the graph attention layer and graph convolution layer at time t i The eigenvector of r , W z , W h ∈R F′×2F′ Reset Gate Update Gate and candidate status The corresponding weight matrix, b r , b z , b h ∈R F′ Reset Gate Update Gate and candidate status The corresponding bias vector, σ(·) is the sigmoid activation function, tanh(·) is the hyperbolic tangent activation function, and ⊙ represents the Hadamard product.

7. The method for acquiring an electronic circuit simulation model according to claim 3, characterized in that: The step of obtaining the prediction performance index corresponding to the node state at the last time step by using the transposed convolution layer, the pooling layer, and the fully connected layer includes: By formula Obtain the prediction performance index corresponding to the node state, where: is the prediction performance index, H (T) ∈R N×F′ is the final state matrix of all nodes, which includes the node states of all nodes in the last time step, TransConv(·) is the transposed convolution operation, AvgPool(·) is the average pooling operation, and f out (·) indicates a fully connected operation.

8. The method for acquiring an electronic circuit simulation model according to claim 1, characterized in that: The calculation formula of the deviation is: Among them, L(θ) represents the mean square error function, θ is the network parameter of the graph attention neural network, and y pred is the prediction performance indicator, y true is the actual performance indicator corresponding to the predicted performance indicator, and N is the number of training samples.

9. The method for acquiring an electronic circuit simulation model according to claim 8, characterized in that: The updating of the parameters of the graph attention neural network based on the deviation and the back propagation algorithm includes: Calculating an update result of the network parameter, and updating the network parameter based on the update result and the back propagation algorithm; The calculation formula of the network parameters is: Among them, θ * is the update result of the network parameter θ, α is the learning rate, is the gradient.

10. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1-9.

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