PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library

Abstract

The invention provides a development method of a heterogeneous integrated PCB (Printed Circuit Board) device library based on a silicon-based CMOS (Complementary Metal Oxide Semiconductor) under Cadence Virtuoso. The development method comprises the following steps: S1, compiling a tecfile.tf file, a display.drf file and a CMOS. Layermap file based on CMOS process information; s2, creating a heterogeneous integration library; s3, in the heterogeneous integrated library, creating a view symbol corresponding to the device according to the type of the device, and setting a CDF parameter attribute of the corresponding device according to a parameter file of the device; s4, creating a callback.il file of a callback function of the device, and carrying out abnormal value detection; s5, creating a layout Pcell of the device; 6, developing a design rule check file based on an interconnection process between the CMOS device and the PCB device by using a skill language; by means of the method, the application range of the PDK is widened, and heterogeneous integration of the silicon-based CMOS technology and the PCB library is completed; and a method for checking the design rule of the interconnection process between the CMOS device and the PCB device is provided, so that the PDK can be used for drawing and developing a board-level circuit, and the limitation of development under different platforms is broken through.

Description

Technical Field

[0001] The present invention relates to the field of PDK development in semiconductor technology, and in particular to a PDK development method based on a silicon-based CMOS heterogeneous integrated PCB device library. Background Art

[0002] PDK (Process Design Kit) is a complete semiconductor process kit, which is a bridge between design and process. At present, the tools used for PDK library design and the tools used for PCB library design may come from different suppliers' platforms, or have different file structures and data formats. Secondly, there are also significant differences in the design rules of integrated circuit design and board-level circuit design. The PDK library has detailed definitions of the width and spacing of the layer structure, which are somewhat different from the board-level process parameters. If these problems can be solved and the two can be combined, the limitations of the original semiconductor process kit can be broken, thereby breaking through some unsolvable problems in the field of integrated circuit design.

[0003] Currently, there is a complete PDK development method under a single process. However, when heterogeneously integrating PDK library devices and PCB library devices, how to deal with the differences in design rules between the two and newly develop the physical verification rules of the interconnection process between devices is the difficulty of this heterogeneous integration PDK. Providing a complete set of PDK development methods for heterogeneous integration under the Virtuoso tool is an issue that needs to be solved urgently. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a PDK development method based on a silicon-based CMOS heterogeneous integrated PCB device library under the Cadence Virtuoso tool. The method adds board-level components on the basis of the PDK device library under the silicon-based CMOS process. The method enables heterogeneous integration of silicon-based CMOS and PCB devices, avoids repeated development and wastes time, improves the efficiency of integrated circuit design, and opens up the design of board-level circuits under the Virtuoso tool. The heterogeneous integration of silicon-based CMOS process devices and PCB devices requires the completion of the semiconductor process kit of the silicon-based CMOS process device first, then considers the development of PCB devices, and finally checks the interconnection process between devices through the design rule check file. Through the above method, the present invention improves the scope of application of PDK, completes the heterogeneous integration of silicon-based CMOS process and PCB library, and provides a method for design rule checking of the interconnection process between CMOS devices and PCB devices, successfully improves the richness of the process kit library, so that this PDK can also perform board-level circuit drawing and development, breaks through the limitations of development under different platforms, improves the work efficiency of developers, and also adds a selectivity for developers.

[0005] In order to achieve the above object, the present invention provides a PDK development method based on a silicon-based CMOS heterogeneous integrated PCB device library, which comprises the following steps:

[0006] S1: Based on the PDK development requirements, a semiconductor process information file is developed using process information; the semiconductor process information file includes: a techfile.tf file, a display.drf file, and a CMOS.layermap file;

[0007] S2: Use the Cadence Virtuoso tool to create a heterogeneous integrated library, create a TF folder under the heterogeneous integrated library, and load the techfile.tf file and display.drf into the heterogeneous integrated library;

[0008] S3: In the heterogeneous integrated library, create a view symbol corresponding to the device according to the device category, and then set the CDF parameter attributes of the corresponding device according to the device parameter file; so that the parameters set in the CDF are reflected in the device view symbol;

[0009] S4: Create a callback function callback.il file of the device to detect whether the input parameter value is abnormal. If the input parameter value is abnormal, the correct parameter value is fed back;

[0010] S5: creating a layout Pcell of a single device, wherein the created layout Pcell includes the layout Pcell of the PCB device;

[0011] S6: Develop design rule checking files for the interconnection process between CMOS devices and PCB devices.

[0012] Preferably, the techfile.tf file defines the name, serial number, abbreviation and purpose of the process layer, and the purposes mainly include drawing, label, marking, etc.; the display.drf file is used to define the display color, display pattern, display border and filling method of the process layer; the CMOS.layermap file defines the layer mapping relationship of the process layer.

[0013] Preferably, in step S2, the step of establishing a heterogeneous integrated library includes:

[0014] Open the Virtuoso tool, select the "Compile an ASCII technology file" button in the interface of the new heterogeneous integrated library, and connect to the techfile.tf file in step S1 to associate the ASCII format process technology file and the heterogeneous integrated library after the first compilation.

[0015] Preferably, in step S3, the step of creating a view symbol includes:

[0016] In the heterogeneous integrated library, create the schematicSymbol of the device; open the Symbol file, use lines to draw the device symbol at a certain size, add relevant pins according to the device manual, save the Symbol file, and set the device CDF parameter properties.

[0017] Preferably, the step of setting the device CDF parameter attributes includes:

[0018] Open the CDF Editor window in the CIW interface of the virtuoso tool and set the CDF parameters for the corresponding device in the window; CDF parameters include: device parameter name, device parameter default value, device parameter type, callback function name and netlist design information.

[0019] Preferably, in step S4, the callback function callback.il is developed using skill language; the function name in the callback function callback.il is consistent with the name of the Callback function defined in CDF; when the parameter value input does not meet the device size and process information requirements under the current process, the callback function callback.il determines that the current parameter value is abnormal and returns the parameter that meets the process information requirements. The Callback function will issue a corresponding warning for the abnormal parameter and modify the abnormal parameter so that its parameter is within the range required by the process information.

[0020] Preferably, in step S5, the step of creating a layout Pcell of the device includes:

[0021] According to the device layout gds file, the skill language is used to reproduce the size scaling, graphic parity change, copy translation, and stretching change rules of the device layout level;

[0022] Combined with the device layout gds file, determine the relative position between the layers of the device, and gradually write the skill code based on a certain layer to fully reproduce the device layout gds file;

[0023] After the device code is written, in the CIW window of the virtuoso software, the skill file of the Pcell is imported into the heterogeneous integrated library through the load function.

[0024] Preferably, in step S6, the specific steps of developing the design rule check file include:

[0025] Obtain the design rule file in the semiconductor process information file, determine the layer name of the shape and the rules it specifies, the main rules include: shape width width and spacing space;

[0026] Get the layout information that needs DRC check, and get all shapes, shape layer information and shape coordinate points in the layout;

[0027] Calculate the width of all shapes through the coordinate points; for the spacing space, first determine the positional relationship between layers, and then calculate the spacing between graphics.

[0028] Preferably, the design rule checking file of the device interconnection process is developed using skill language.

[0029] Preferably, the development data of each device view symbol, CDF parameter attributes and the development data of the device layout Pcell are integrated in the same library file.

[0030] The present invention provides a PDK development method based on a silicon-based CMOS heterogeneous integrated PCB device library, which has the following beneficial effects compared with the prior art:

[0031] The present invention provides a PDK development method based on a silicon-based CMOS heterogeneous integrated PCB device library under the Virtuoso tool, which heterogeneously integrates the PDK under a single process and adds board-level devices; based on the heterogeneous integrated library, a design rule check file DRC_check.il for the interconnection process is developed, which successfully improves the richness of the process kit library, so that this PDK can be used to draw and develop board-level schematics and layouts, thereby increasing the categories of heterogeneous integrated PDKs and improving the work efficiency of engineers. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the development process of a heterogeneous integrated PDK provided in the first embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the design rule checking development process for the interconnection process in the heterogeneous integrated PDK provided in the first embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0035] like Figure 1 As shown, the present invention provides a PDK development method based on a silicon-based CMOS heterogeneous integrated PCB device library. To better explain and verify the feasibility of the method, the present invention provides an embodiment, which is as follows:

[0036] Step 1: Obtain process technology files: Organize the semiconductor process information files required for PDK development, and develop techfile.tf files, display.drf files, and CMOS.layermap files through process information.

[0037] Obtain semiconductor process files related to silicon-based CMOS processes, and develop techfile.tf files, display.drf files, and CMOS.layermap files in semiconductor process information for embodiments of the present invention. The techfile.tf file defines the name, serial number, abbreviation, and purpose of the process layer, and the purposes mainly include drawing, label, marking, etc. The display.drf file is used to define the display color, display pattern, display border, and filling method of the process layer. The CMOS.layermap file defines the layer mapping relationship of the process layer.

[0038] Step 2: Create a heterogeneous integrated library: Create a heterogeneous integrated library under the Cadence Virtuoso tool, create a TF folder under the heterogeneous integrated library, and load the techfile.tf file and display.drf into the heterogeneous integrated library.

[0039] When using the Virtuoso tool to create a heterogeneous integrated library, select the "Complie an ASCII techology file" button in the "Technology File for New Library" window that pops up, and associate it with the developed techfile.tf file to connect the ASCII format process technology file compiled for the first time with the heterogeneous integrated library.

[0040] Step 3: Create a device symbol view: Create a device view symbol based on the device category.

[0041] The device symbol is a view that represents the characteristic properties of the device, and is mainly used in the design of schematics. Open the built heterogeneous integrated library, add the corresponding device name cell file to this library, and select schematicSymbol for the corresponding device view. Draw it in a certain size ratio in the Symbol Editor interface; after completion, add parameter labels to the symbol view. The device view contains the instance name cdsName, important parameter information cdsParam, and port information cdsTerm.

[0042] Step 4: Set CDF parameters: Set the CDF parameter attributes of the corresponding device according to the device parameter file; reflect the set CDF parameters in the device view symbol; the development data of the PCB device view symbol and CDF parameter attributes are integrated in the same library file.

[0043] CDF (Component Description Format) is a component description format that contains the basic characteristic attribute parameters of a standard device. Open the CDF Editor window in the CIW interface of the Virtuoso tool and set the CDF parameters for the corresponding device in the window. CDF parameters mainly include device parameter name, device parameter type, device parameter callback function name, whether the device parameter is displayed in the schematic diagram, and whether the device parameter is editable in the schematic diagram.

[0044] Step 5: Set the Callback function.

[0045] Callback is a parameter callback, which is used to characterize the functional relationship between CDF parameters. When the parameter value input does not meet the requirements of the process for the device size and process information, the Callback function will automatically determine that the parameter value is abnormal and return a reasonable parameter value. The callback.il file is mainly developed in the skill language. The function name in the code needs to be consistent with the Callback function name defined in CDF to implement the function call. The first function of the Callback function is to limit the range of parameters. Parameter values ​​that exceed the range are called back to the maximum (minimum) value; the second function is the calculation of certain parameter values. In some devices, the parameter value needs to be calculated through other parameters.

[0046] Step 6: Layout Pcell.

[0047] The parameterized cell (Pcell) reflects the layout structure of the device, turning the device into a programmable unit. The device structure is controlled by some parameters (width W, length L, etc.). The layout Pcell mainly uses the skill language to develop the device. According to the device layout gds file, the skill language is used to reproduce the size scaling, graphic parity change, copy translation, and stretching change rules of the device layout level. Combined with the device layout gds file, the relative position between the layers of the device is determined, and the skill code is gradually written based on a certain layer to achieve the reproduction of the complete device layout gds file. After the device code is written, in the CIW window of the virtuoso software, the skill file of the Pcell is imported into the heterogeneous integrated library through the load function. Among them, the created layout Pcell includes the layout Pcell of the PCB device.

[0048] The advantages of developing device layout structure through layout Pcell are: high efficiency in generating layout, covering various situations of device parameters changing, reducing a lot of repetitive work; Pcell parameterization method, in the subsequent device update and optimization, only some modifications to the code are needed to update and maintain the device, which is also conducive to future upgrade optimization and secondary development.

[0049] Step 7: Development of design rule checking files.

[0050] DRC mainly checks the designed layout according to the rules required by the process manufacturing. The embodiment of the present application is mainly about the development method of the design rule checking file of the interconnection process between CMOS devices and PCB devices. The method is as follows:

[0051] Get the design rule file in the semiconductor process information file, determine the layer name of the shape and the rules related to this layer in its design rule file, mainly about the width width and spacing space rules of the shape. The design rule checking file of the device interconnection process is developed in the skill language.

[0052] Get the layout information that needs DRC check, and further get all shapes, shape layer information and shape coordinate points in the layout.

[0053] Through the coordinate points, the width of all shapes can be calculated; for the spacing space, first determine the positional relationship between layers, and then calculate the spacing between graphics.

[0054] After the above steps, the PDK development of silicon-based CMOS heterogeneous integrated PCB device library under the virutoso tool is realized. The flow chart is as follows Figure 2 shown.

[0055] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

Claims

1. A PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library, characterized in that: The steps include: S1: Based on the PDK development requirements, a semiconductor process information file is developed using process information; the semiconductor process information file includes: a techfile.tf file, a display.drf file, and a CMOS.layermap file; S2: Use the Cadence Virtuoso tool to create a heterogeneous integrated library, create a TF folder under the heterogeneous integrated library, and load the techfile.tf file and display.drf into the heterogeneous integrated library; S3: In the heterogeneous integrated library, create a view symbol corresponding to the device according to the device category, and then set the CDF parameter attributes of the corresponding device according to the device parameter file; so that the parameters set in the CDF are reflected in the device view symbol; S4: Create a callback function callback.il file of the device to detect whether the input parameter value is abnormal. If the input parameter value is abnormal, the correct parameter value is returned; S5: creating a layout Pcell of a single device, wherein the created layout Pcell includes the layout Pcell of the PCB device; S6: Develop design rule checking files for the interconnection process between CMOS devices and PCB devices.

2. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 1, characterized in that: In step S2, the step of establishing a heterogeneous integrated library includes: Open the Virtuoso tool, select the "Compile an ASCII technologyfile" button in the interface of the new heterogeneous integrated library, and connect to the techfile.tf file in step S1 to associate the ASCII format process technology file and the heterogeneous integrated library after the first compilation.

3. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 1, characterized in that: In step S3, the step of creating a view symbol includes: In the heterogeneous integrated library, create the schematicSymbol of the device; open the Symbol file, use lines to draw the device symbol at a certain size, add relevant pins according to the device manual, save the Symbol file, and set the device CDF parameter properties.

4. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 3, characterized in that: The steps of setting the device CDF parameter attributes include: Open the CDF Editor window in the CIW interface of the virtuoso tool and set the CDF parameters for the corresponding device in the window; CDF parameters include: device parameter name, device parameter default value, device parameter type, callback function name and netlist design information.

5. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 1, characterized in that: In step S4, the callback function callback.il is developed using the skill language; the function name in the callback function callback.il is consistent with the name of the Callback function defined in the CDF; When the parameter value input does not meet the device size and process information requirements under the current process, the callback function callback.il determines that the current parameter value is abnormal and returns the parameter that meets the process information requirements.

6. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 1, characterized in that: In step S5, the step of creating a layout Pcell of the device includes: According to the device layout gds file, the skill language is used to reproduce the size scaling, graphic parity change, copy translation, and stretching change rules of the device layout level; Combined with the device layout gds file, determine the relative position between the layers of the device, and gradually write the skill code based on a certain layer to fully reproduce the device layout gds file; After the device code is written, in the CIW window of the virtuoso software, the skill file of the Pcell is imported into the heterogeneous integrated library through the load function.

7. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 1, characterized in that: In step S6, the specific steps of developing the design rule check file include: Obtain the design rule file in the semiconductor process information file, determine the layer name of the shape and the rules it specifies, the main rules include: shape width width and spacing space; Get the layout information that needs DRC check, and get all shapes, shape layer information and shape coordinate points in the layout; Calculate the width of all shapes through the coordinate points; for the spacing space, first determine the positional relationship between layers, and then calculate the spacing between graphics.

8. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 7, characterized in that: The design rule checking file of the device interconnection process is developed using skill language.

9. The PDK development method based on silicon-based CMOS heterogeneous integrated PCB device library according to claim 1, characterized in that: The devices under the CMOS process and each PCB device view symbol, the development data of CDF parameter attributes and the development data of the PCB device layout Pcell are all integrated in the same library file.

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