Clock distribution method, device, computer device, storage medium and program product

Abstract

The present invention relates to the field of integrated circuit technology, and discloses a clock distribution method, apparatus, computer device, storage medium, and program product. The method includes: obtaining the clock distribution of each device in a target field programmable gate array; respectively determining the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array; constructing an undirected graph with each clock of the target field programmable gate array as vertices based on the bounding boxes corresponding to each clock; processing the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph; and respectively allocating the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane. The above solution ensures the accuracy and effectiveness of clock distribution.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a clock distribution method, apparatus, computer device, storage medium, and program product. Background Art

[0002] A Field Programmable Gate Array (FPGA) can be programmed to implement various complex digital logic functions, and includes a more complex clock architecture logic on the basis of being configurable to implement synchronous operations, control timing, optimize performance, and simplify design, etc. In the FPGA clock network architecture, a plane composed of clock wires of the same model is called a clock plane, and a clock signal can only be transmitted on the same clock plane and cannot be transmitted across planes. Since the physical structure of the clock network in the field programmable gate array is pre-manufactured and cannot be modified later, the implemented functions cannot be adjusted for different application scenarios. Moreover, for high-utilization designs, clock routing resources are usually limited. In the related art, the clock distribution method for field programmable gate arrays has been difficult to support large-scale clock structures, and it is easy to cause congestion problems in layout and routing resources due to unreasonable clock distribution, resulting in low resource utilization.

[0003] Therefore, there is an urgent need for a solution that can accurately and effectively perform clock distribution. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a clock distribution method, apparatus, computer device, storage medium, and program product to solve the problem of inaccurate and ineffective clock distribution.

[0005] In a first aspect, the present invention provides a clock distribution method, and the method includes:

[0006] Obtain the clock distribution of each device in the target field programmable gate array;

[0007] Based on the clock distribution of each device in the target field programmable gate array, respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array;

[0008] Taking each clock of the target field programmable gate array as a vertex, construct an undirected graph based on the bounding boxes corresponding to each clock;

[0009] Process the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph;

[0010] Respectively assign the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0011] In an alternative embodiment, obtaining the clock distribution of each device in the target field programmable gate array includes:

[0012] Establishing a grid coordinate system based on the target field programmable gate array;

[0013] Obtaining the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0014] In an alternative embodiment, determining the bounding box corresponding to each clock of the target field programmable gate array respectively based on the clock distribution of each device in the target field programmable gate array includes:

[0015] Calculating the bounding box corresponding to each clock based on the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0016] In an alternative embodiment, constructing an undirected graph based on the bounding boxes corresponding to each clock includes:

[0017] If there is a position overlap between the bounding boxes corresponding to any two clocks, adding an undirected edge between the vertices corresponding to the two clocks.

[0018] In an alternative embodiment, processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph includes:

[0019] Determining the degree of each vertex in the undirected graph;

[0020] Arranging all vertices in descending order of degree to obtain the vertex arrangement order;

[0021] Coloring each vertex according to the vertex arrangement order.

[0022] In an alternative embodiment, coloring each vertex according to the vertex arrangement order includes:

[0023] Coloring the first vertex in the vertex arrangement order with the first color;

[0024] Judging whether the second vertex is connected to the colored vertex through an undirected edge; if not, coloring the second vertex with the first color; if so, coloring the second vertex with the second color;

[0025] Repeating the above steps so that each pair of adjacent vertices connected by an undirected edge are colored with different colors until all vertices are colored.

[0026] In a second aspect, the present invention provides a clock distribution device, and the device includes:

[0027] An acquisition module, configured to acquire the clock distribution of each device in a target field programmable gate array;

[0028] A bounding box module, configured to respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array;

[0029] An undirected graph module, configured to use each clock of the target field programmable gate array as a vertex and construct an undirected graph based on the bounding boxes corresponding to each clock;

[0030] A graph coloring module, configured to process the undirected graph through a graph coloring algorithm and color each vertex in the undirected graph;

[0031] A clock distribution module, configured to respectively assign the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0032] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the clock distribution method according to the first aspect or any corresponding embodiment thereof.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the clock distribution method according to the first aspect or any corresponding embodiment thereof.

[0034] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the clock distribution method according to the first aspect or any corresponding embodiment thereof.

[0035] The technical solution provided by the present invention may include the following beneficial effects:

[0036] The clock distribution method provided by the present invention first obtains the clock distribution of each device in the target field programmable gate array, then determines the bounding box corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock of the target field programmable gate array as vertices based on the bounding box corresponding to each clock, then processes the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph, and finally assigns the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane. In the above solution, the bounding box corresponding to each clock is determined based on the clock distribution of each device in the target field programmable gate array, then an undirected graph is constructed with each clock as vertices and graph coloring is performed, and then the clock plane is assigned, which can reasonably allocate the clock plane resources occupied by each clock in the target field programmable gate array in a targeted manner, alleviate the congestion problem of layout and routing resources caused by ultra-large-scale clocks, set the minimum number of clock planes on the premise of ensuring that there is no clock conflict between the devices corresponding to each clock, improve the resource utilization rate, and ensure the accuracy and effectiveness of clock distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 is a schematic flowchart of the clock distribution method according to an embodiment of the present invention;

[0039] Figure 2 is a schematic flowchart of another clock distribution method according to an embodiment of the present invention;

[0040] Figure 3 is a clock distribution diagram according to an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram of the clock bounding box according to an embodiment of the present invention;

[0042] Figure 5 is an undirected graph according to an embodiment of the present invention;

[0043] Figure 6 is a graph coloring result diagram according to an embodiment of the present invention;

[0044] Figure 7 is a clock plane allocation result diagram according to an embodiment of the present invention;

[0045] Figure 8 is a structural block diagram of a clock distribution device according to an embodiment of the present invention;

[0046] Figure 9 is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0048] A Field Programmable Gate Array (FPGA) can be programmed to implement various complex digital logic functions. On a configurable basis, it includes a more complex clock architecture logic for implementing synchronous operations, controlling timing, optimizing performance, and simplifying designs, etc. In the FPGA clock network architecture, a plane composed of clock wires of the same model is called a clock plane. A clock signal can only be transmitted on the same clock plane and cannot be transmitted across planes. Since the physical structure of the clock network in the field programmable gate array is pre-manufactured and cannot be modified later, the implemented functions cannot be adjusted for different application scenarios. Moreover, for high-utilization designs, clock routing resources are usually limited, and the FPGA placement and routing methods in the related art are difficult to support large-scale clock structures.

[0049] Therefore, the embodiments of the present invention provide a clock distribution method. By determining the bounding boxes corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, and then constructing an undirected graph with each clock as a vertex and performing graph coloring, the clock plane is allocated, ensuring the accuracy and effectiveness of clock distribution.

[0050] According to an embodiment of the present invention, an embodiment of a clock distribution method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0051] In this embodiment, a clock distribution method is provided, which can be used in desktop computers, laptop computers, servers, etc. Figure 1is a flowchart of a clock distribution method according to an embodiment of the present invention. As Figure 1 shown, the process includes the following steps:

[0052] Step S101, obtain the clock distribution of each device in the target field programmable gate array.

[0053] The target field programmable gate array is the field programmable gate array that needs to be clock-distributed by the clock distribution method provided in this embodiment. When clock-distributing the target field programmable gate array, first, it is necessary to obtain the clock distribution of each device in the target field programmable gate array. The clocks of each device can be obtained through the configuration tool built in the target field programmable gate array, and the coordinates of each device can be obtained through the placement tool, so as to obtain the clock distribution of each device.

[0054] Step S102, based on the clock distribution of each device in the target field programmable gate array, respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array.

[0055] Based on the clocks and coordinates of each device in the target field programmable gate array, using the clock as the classification criterion, the devices belonging to the same clock are classified into one category, and the bounding box corresponding to the clock is determined according to the coordinates of the devices belonging to the same clock. For example, the upper left coordinate among the coordinates of the devices belonging to the same clock is used as the upper left coordinate of the bounding box, and the lower right coordinate among the coordinates of the devices belonging to the same clock is used as the lower right coordinate of the bounding box, and so on, to obtain the bounding boxes corresponding to each clock.

[0056] Step S103, using each clock of the target field programmable gate array as a vertex, construct an undirected graph based on the bounding boxes corresponding to each clock.

[0057] An undirected graph is a set of vertices and a set of edges. In this embodiment, each clock of the target field programmable gate array is set as a vertex of the undirected graph, and a preset rule is used to judge whether there is an undirected edge between each vertex. The undirected edge has no direction, and the relationship between the vertices at both ends of the undirected edge is bidirectional and symmetric. The preset rule can be set according to actual needs. For example, if there is an overlap between the bounding boxes corresponding to two clocks, it indicates that these two clocks may conflict if they are in the same clock plane. Therefore, an undirected edge is added between the vertices corresponding to these two clocks, indicating that these two clocks are not assigned to the same clock plane.

[0058] Step S104, process the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph.

[0059] The graph coloring algorithm marks the vertices or edges of a graph with different colors so that adjacent vertices have different colors. After coloring the vertices of the undirected graph through the graph coloring algorithm, the vertices at both ends of an undirected edge have different colors and the total number of colors used for coloring is the least. That is to say, there are no conflicts between the bounding boxes corresponding to each clock and the total number of colors used for coloring is the least. Exemplarily, graph coloring algorithms such as the greedy coloring algorithm, the Welch-Powell algorithm, and the backtracking algorithm can be used to color the vertices in the undirected graph.

[0060] Step S105: Assign the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0061] Since there are no conflicts between the bounding boxes corresponding to each clock and the total number of colors used for coloring is the least after coloring the vertices in the undirected graph, grouping the vertices with the same color into one group can ensure the least number of groups on the premise that there are no conflicts between the bounding boxes corresponding to each clock, ensure the least number of clock planes to be set, and accurately and effectively implement clock allocation.

[0062] The clock allocation method provided in this embodiment first obtains the clock distribution of each device in the target field programmable gate array, then determines the bounding box corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock of the target field programmable gate array as vertices based on the bounding box corresponding to each clock, then processes the undirected graph through a graph coloring algorithm to color the vertices in the undirected graph, and finally assigns the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane. The above solution determines the bounding box corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock as vertices and performs graph coloring, and then allocates the clock plane, which can reasonably allocate the clock plane resources occupied by each clock in the target field programmable gate array in a targeted manner, alleviate the congestion problem of layout and routing resources brought by ultra-large-scale clocks, set the least number of clock planes on the premise that there are no clock conflicts between the devices corresponding to each clock, improve resource utilization, and ensure the accuracy and effectiveness of clock allocation.

[0063] In this embodiment, a clock allocation method is provided, which can be used in desktop computers, laptop computers, servers, etc. Figure 2 It is a flowchart of the clock allocation method according to the embodiment of the present invention. As Figure 2 shown, the process includes the following steps:

[0064] Step S201: Obtain the clock distribution of each device in the target field-programmable gate array.

[0065] Specifically, the above step S201 includes:

[0066] Step S2011: Establish a grid coordinate system based on the target field-programmable gate array.

[0067] Establish a grid coordinate system based on the physical structure of the target field-programmable gate array, so as to determine the positions of each device in the target thread programmable gate array through the coordinates corresponding to each device in the grid coordinate system. Exemplarily, the grid coordinate system in the layout tool of the target field-programmable gate array can be adopted.

[0068] Step S2012: Obtain the clocks of each device in the target field-programmable gate array and the coordinates of each device in the grid coordinate system.

[0069] Each device in the target field-programmable gate array includes a clock buffer and other functional devices. The clock buffer includes a global clock buffer, a semi-global clock buffer, a regional clock buffer, an I / O clock buffer, etc. The distribution position and quantity of the clock buffer determine the propagation range and manner of each clock signal in the target field-programmable gate array. Other functional devices rely on the corresponding clock buffer to allocate clock signals. Then, obtain the coordinates of each clock buffer and each functional device in the grid coordinate system, the coverage range of each clock buffer, and the clocks corresponding to each functional device as the clock distribution of each device in the target field-programmable gate array.

[0070] Step S202: Based on the clock distribution of each device in the target field-programmable gate array, respectively determine the bounding boxes corresponding to each clock of the target field-programmable gate array.

[0071] Specifically, based on the clocks of each device in the target field-programmable gate array and the coordinates of each device in the grid coordinate system, calculate the bounding boxes corresponding to each clock. Determine the upper left corner coordinates and the lower right corner coordinates of the bounding boxes corresponding to each clock based on the clocks of each device and the coordinates of each device in the grid coordinate system, and calculate the center point coordinates corresponding to the bounding boxes according to the upper left corner coordinates and the lower right corner coordinates for convenient positioning. It is also possible to combine geometric algorithms to obtain the minimum circumscribed rectangle corresponding to each clock as the bounding box to improve the accuracy of the bounding box.

[0072] Optionally, it is also possible to obtain the clock distribution map of each device in the target field-programmable gate array. The clock distribution map is used to indicate the positions of each device in the target field-programmable gate array and the corresponding clocks, and distinguish the devices corresponding to each clock through different identifiers or colors.

[0073] Exemplarily, Figure 3 is a clock distribution diagram according to an embodiment of the present invention. As shown in Figure 3 , taking the example that there are 6 clocks in the target field programmable gate array, each device corresponding to each clock is marked with dots of 6 colors respectively. Then, the bounding box corresponding to each clock can be determined based on the clock distribution diagram. For example, a deep learning model with a bounding box prediction function is used to process the clock distribution diagram to predict the bounding box corresponding to each clock. Figure 4 is a schematic diagram of a clock bounding box according to an embodiment of the present invention. As shown in Figure 4 , the rectangular bounding box is filled with the color corresponding to each clock, and the rectangular bounding box is used to indicate the distribution position of the corresponding clock.

[0074] Step S203: Taking each clock of the target field programmable gate array as a vertex, construct an undirected graph based on the bounding box corresponding to each clock.

[0075] Specifically, if there is an overlap in the positions between the bounding boxes corresponding to any two clocks, an undirected edge is added between the vertices corresponding to the two clocks. For example, if there is an overlap in the positions between the bounding box corresponding to the first clock and the bounding box corresponding to the second clock, it indicates that there is a conflict between the first clock and the second clock, and an undirected edge is added between the vertex corresponding to the first clock and the vertex corresponding to the second clock. And so on, by exhaustive enumeration, it is determined whether an undirected edge needs to be added between any two of the clocks.

[0076] Exemplarily, Figure 5 is an undirected graph according to an embodiment of the present invention. As shown in Figure 5 , among the 6 clocks, there are undirected edges between the first clock and the third clock, the fourth clock, the fifth clock, and the sixth clock, there are undirected edges between the second clock and the third clock and the fourth clock, there is also an undirected edge between the third clock and the sixth clock, and there is also an undirected edge between the fourth clock and the fifth clock.

[0077] Step S204: Process the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph.

[0078] Specifically, the above step S204 includes:

[0079] Step S2041: Determine the degree of each vertex in the undirected graph.

[0080] The degree of a vertex is the number of undirected edges connected to the vertex. When coloring each vertex in the undirected graph, first identify each vertex in the undirected graph and the number of undirected edges connected to each vertex.

[0081] Step S2042: Arrange each vertex in descending order of degree to obtain the vertex arrangement order.

[0082] Dyeing the vertices with larger degrees first helps improve the dyeing efficiency. Therefore, first arrange all the vertices in descending order of degrees to obtain the vertex arrangement order for determining the dyeing order.

[0083] Step S2043: Dye each vertex according to this vertex arrangement order.

[0084] Specifically, dye the vertex in the first position in the vertex arrangement order with the first color, and then determine whether the vertex in the second position is connected to the dyed vertex through an undirected edge, that is, whether it is connected to the vertex in the first position through an undirected edge. If not, dye the vertex in the second position with the first color; if so, dye the vertex in the second position with the second color. Then, determine whether the vertex in the third position is connected to the vertex in the first position through an undirected edge. If not, dye the vertex in the third position with the first color; if so, determine whether the vertex in the third position is connected to the vertex in the second position through an undirected edge. If so, dye the vertex in the third position with the third color; if not, dye the vertex in the third position with the second color. Repeat the above steps so that adjacent vertices connected by undirected edges are dyed with different colors until all vertices are dyed. Iteration can also be performed. For example, if there are multiple colors available for a certain vertex in the above steps, during iteration, this vertex is dyed with another color. After all vertices are dyed, count the total number of colors dyed in this round and compare it with the total number of colors dyed in the previous rounds until the round with the least total number of dyed colors is selected as the optimal solution and used as the final graph dyeing result.

[0085] Exemplarily, Figure 6 is the graph dyeing result diagram according to the embodiment of the present invention. As Figure 6 shown, the first vertex and the second vertex are dyed with the first color, the third vertex and the fifth vertex are dyed with the second color, the fourth vertex and the sixth vertex are dyed with the third color, and the final total number of colors is 3. The dyeing colors between any two vertices connected by undirected edges are different.

[0086] Step S205: Assign the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0087] There is no conflict in the clocks corresponding to the vertices with the same color. Therefore, the devices in the target field programmable gate array corresponding to the vertices with the same color can be assigned to the same clock plane, that is, the devices in the target field programmable gate array corresponding to the clocks without conflict are assigned to the same clock plane, and clock assignment can be achieved. Since the total number of colors is guaranteed to be the least in step S204, the number of clock planes to be set is also the least, ensuring the accuracy and effectiveness of clock assignment.

[0088] Exemplarily,Figure 7 It is a clock plane allocation result diagram according to an embodiment of the present invention. As Figure 7 shown, the devices corresponding to the third clock and the devices corresponding to the fifth clock are allocated to clock plane 1, the devices corresponding to the sixth clock and the devices corresponding to the fourth clock are allocated to clock plane 2, and the devices corresponding to the first clock and the devices corresponding to the second clock are allocated to clock plane 3.

[0089] The clock allocation method provided in this embodiment first obtains the clock distribution of each device in the target field programmable gate array, and then, based on the clock distribution of each device in the target field programmable gate array, respectively determines the bounding boxes corresponding to each clock of the target field programmable gate array. Then, taking each clock of the target field programmable gate array as a vertex, an undirected graph is constructed based on the bounding boxes corresponding to each clock. Next, the undirected graph is processed by a graph coloring algorithm to color each vertex in the undirected graph. Finally, the devices in the target field programmable gate array corresponding to the vertices with the same color are respectively allocated to the same clock plane. The above solution determines the bounding boxes corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock as a vertex and performs graph coloring, and then allocates the clock plane, which can reasonably allocate the clock plane resources occupied by each clock in the target field programmable gate array in a targeted manner, relieve the congestion of layout and wiring resources caused by ultra-large-scale clocks, set the minimum number of clock planes on the premise that there is no clock conflict between the devices corresponding to each clock, improve the resource utilization rate, and ensure the accuracy and effectiveness of clock allocation.

[0090] In this embodiment, a clock allocation device is also provided. This device is used to implement the above embodiments and preferred implementation manners, and those that have been described will not be repeated. As used hereinafter, the term "module" may be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0091] This embodiment provides a clock allocation device. As Figure 8 [[ID=I4]]shown, it includes:

[0092] An acquisition module 801, configured to acquire the clock distribution of each device in the target field programmable gate array;

[0093] A bounding box module 802, configured to respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array;

[0094] The undirected graph module 803 is used to construct an undirected graph with each clock of the target field programmable gate array as vertices, based on the bounding boxes corresponding to each clock;

[0095] The graph coloring module 804 is used to process the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph;

[0096] The clock allocation module 805 is used to respectively allocate the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0097] In an alternative embodiment, the acquisition module is further used to: establish a grid coordinate system based on the target field programmable gate array; acquire the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0098] In an alternative embodiment, the bounding box module is further used to: calculate the bounding boxes corresponding to each clock based on the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0099] In an alternative embodiment, the undirected graph module is further used to: if there is a position overlap between the bounding boxes corresponding to any two clocks, add an undirected edge between the vertices corresponding to the two clocks.

[0100] In an alternative embodiment, the graph coloring module is further used to: determine the degrees of each vertex in the undirected graph; sort each vertex in descending order of degree to obtain the vertex arrangement order; color each vertex according to the vertex arrangement order.

[0101] In an alternative embodiment, the graph coloring module is further used to: color the first vertex in the vertex arrangement order with a first color; determine whether the second vertex is connected to the colored vertex through an undirected edge; if not, color the second vertex with the first color; if so, color the second vertex with a second color; repeat the above steps so that each pair of adjacent vertices connected by an undirected edge are colored with different colors until all vertices are colored.

[0102] The further function descriptions of the above-mentioned modules and units are the same as those in the corresponding embodiments above, and will not be elaborated here.

[0103] The clock allocation device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0104] An embodiment of the present invention further provides a computer device having the above Figure 8 clock distribution device shown.

[0105] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a computer device provided by an optional embodiment of the present invention. As Figure 9 shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 9 In

[0106] FIG., a single processor 10 is taken as an example.

[0107] The processor 10 may be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 may further include a hardware chip. The above hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device may be a complex programmable logic device, a field programmable gate array, a general array logic, or any combination thereof.

[0108] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0109] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory 20 may further include a combination of the above types of memories.

[0110] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected by a bus or other means. Figure 9 Taking connection by bus as an example.

[0111] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function control of the computer device, such as touch screen, keypad, mouse, trackpad, touchpad, pointing stick, one or more mouse buttons, trackball, joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (such as an LED), and a tactile feedback device (such as a vibration motor), etc. The above display device includes but is not limited to liquid crystal display, light emitting diode, display and plasma display. In some alternative embodiments, the display device may be a touch screen.

[0112] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented by downloading through a network the original computer code stored in a remote storage medium or a non-transitory machine-readable storage medium and to be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state drive, etc.; further, the storage medium may further include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor or the hardware, the method shown in the above embodiment is implemented.

[0113] A part of the present invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operations of the computer. Those skilled in the art should understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0114] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the protection scope of the present invention.

Claims

1. A clock distribution method, characterized in that, The method includes: Obtaining the clock distribution of each device in the target field programmable gate array; Based on the clock distribution of each device in the target field programmable gate array, respectively determining the bounding boxes corresponding to each clock of the target field programmable gate array; Taking each clock of the target field programmable gate array as a vertex, constructing an undirected graph based on the bounding boxes corresponding to each clock; Processing the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph; Respectively allocating the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

2. The method according to claim 1, wherein The obtaining the clock distribution of each device in the target field programmable gate array includes: Establishing a grid coordinate system based on the target field programmable gate array; Obtaining the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

3. The method according to claim 2, wherein The respectively determining the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array includes: Calculating the bounding boxes corresponding to each clock based on the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

4. The method according to any one of claims 1 to 3, characterized in that, The constructing an undirected graph based on the bounding boxes corresponding to each clock includes: If there is a position overlap between the bounding boxes corresponding to any two clocks, adding an undirected edge between the vertices corresponding to the two clocks.

5. The method according to claim 4, wherein Processing the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph includes: Determining the degrees of each vertex in the undirected graph; Arranging each vertex in descending order of degree to obtain a vertex arrangement order; Coloring each vertex according to the vertex arrangement order.

6. The method according to claim 5, wherein The coloring each vertex according to the vertex arrangement order includes: Coloring the first vertex in the vertex arrangement order with the first color; Judging whether the second vertex is connected to the colored vertex through an undirected edge; if not, coloring the second vertex with the first color; if so, coloring the second vertex with the second color; Repeating the above steps so that each pair of adjacent vertices connected by an undirected edge are colored with different colors until all vertices are colored.

7. A clock distribution device, characterized in that, The device includes: An obtaining module, configured to obtain the clock distribution of each device in the target field programmable gate array; A bounding box module, configured to respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array; An undirected graph module, configured to construct an undirected graph with each clock of the target field programmable gate array as a vertex based on the bounding boxes corresponding to each clock; A graph coloring module, configured to process the undirected graph through a graph coloring algorithm to color each vertex in the undirected graph; A clock allocation module, configured to respectively allocate the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

8. A computer device, characterized in that, including: A memory and a processor, which are communicatively connected to each other. Computer instructions are stored in the memory, and the processor executes the computer instructions to execute the clock distribution method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Computer instructions are stored on the computer-readable storage medium, and the computer instructions are used to cause a computer to execute the clock distribution method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, It includes computer instructions, and the computer instructions are used to cause a computer to execute the clock distribution method according to any one of claims 1 to 6.

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