Transistor detection image correction and optimization method based on multiple dimensions

Abstract

The invention provides a transistor detection image correction and optimization method based on multiple dimensions. The method comprises the steps that stable feature points in a transistor detection image are selected, a transformation matrix is calculated through a geometric correction model based on the stable feature points, geometric distortion in the image is eliminated through the transformation matrix, and a corrected image is obtained. Based on the corrected image, using a dark field illumination method to obtain a dark field image highlighting surface defects and textures of the transistor, using a bright field illumination method to obtain a bright field image of overall form and structure information of the transistor, and fusing the dark field image and the bright field image to generate a detection image; detecting time domain noise in the detection image, and smoothing the detected time domain noise by using a filtering algorithm; and performing high-speed parallel processing on the processed detection image based on the FPGA. The high-speed parallel processing capability of the FPGA is utilized, the detection image can be quickly processed, and the processing speed and efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of image correction technology, and in particular to a multi-dimensional transistor detection image correction and optimization method, device and storage medium. Background Art

[0002] In the field of semiconductor manufacturing, the quality and performance of transistors directly determine the quality and reliability of the entire electronic product. Therefore, accurate and efficient detection of transistors is an indispensable part of the semiconductor manufacturing process. However, traditional transistor detection image correction and optimization methods have many shortcomings and cannot meet the high-precision and high-efficiency requirements of modern semiconductor manufacturing.

[0003] Traditional transistor detection image correction methods usually rely on manually selecting feature points for geometric correction. This method is not only time-consuming and labor-intensive, but also easily affected by human factors, resulting in unstable correction accuracy. In addition, traditional image correction methods often only focus on the overall deformation of the image, while ignoring the detailed features of the transistor surface, thus affecting subsequent detection and analysis. In terms of noise processing, traditional time domain noise detection methods usually analyze based on the spatial domain features of the image. This method is not effective in removing high-frequency noise and interference, and is likely to affect subsequent edge detection and image enhancement processing. In addition, traditional noise processing methods often use serial processing, which has a slow processing speed and cannot meet the needs of real-time detection. Summary of the invention

[0004] The present invention aims to at least solve the technical problem of low efficiency of traditional transistor detection image correction methods in the prior art, and particularly innovatively proposes a multi-dimensional transistor detection image correction and optimization method, device and storage medium.

[0005] In order to achieve the above-mentioned object of the present invention, the present invention provides a transistor detection image correction and optimization method based on multi-dimensionality, the method comprising: S1, selecting a transistor to detect stable feature points in an image, calculating a transformation matrix based on the stable feature points using a geometric correction model, and using the transformation matrix to eliminate geometric distortion in the image to obtain a corrected image; S2, based on the corrected image, using a dark field illumination method to obtain a dark field image that highlights the surface defects and texture of the transistor, using a bright field illumination method to obtain a bright field image of the overall morphology and structural information of the transistor, and fusing the dark field image and the bright field image to generate a detection image; S3, detecting the time domain noise in the detection image, smoothing the detected time domain noise using a filtering algorithm, and enhancing the edge of the detection image; S4. Perform high-speed parallel processing on the processed detection image based on FPGA to optimize the detection image.

[0006] As an optional embodiment of the present invention, optionally, selecting stable feature points in the transistor detection image in step S1 includes: S101, converting the transistor detection image into a grayscale image, and performing smoothing filtering on the grayscale image to obtain; S102, using a corner detection algorithm to identify corner points or extreme points in the grayscale image; S103, sorting the corner points and extreme value points based on the response values, and obtaining the point with the highest response value as a feature point; S104 , calculating a descriptor of the feature point, and verifying the feature point based on the descriptor to obtain a stable feature point.

[0007] As an optional embodiment of the present invention, optionally, in step S1, calculating a transformation matrix based on the stable feature points using a geometric correction model, and eliminating geometric distortion in the image using the transformation matrix includes: S105, matching feature points in different transistor detection images based on the descriptors of the feature points, and obtaining corresponding relationships between the feature points in different transistor detection images; S106, using a geometric correction model based on the matched feature points to evaluate the correspondence between different transistor detection images, and calculating a transformation matrix based on the correspondence; S107 , transforming the original transistor detection image based on the transformation matrix, eliminating geometric distortion in the original transistor detection image, and obtaining a corrected image.

[0008] As an optional embodiment of the present invention, optionally, the expression for calculating the transformation matrix is: ; in, Represents the horizontal coordinate of the midpoint of the detected image after transformation, Represents the ordinate of the midpoint of the detected image after transformation, represents the weight in homogeneous coordinates, , , , , , , , and represent the elements of the transformation matrix, Represents the horizontal coordinate of the midpoint of the original transistor detection image, Represents the vertical coordinate of the midpoint of the original transistor detection image.

[0009] As an optional embodiment of the present invention, optionally, fusing the dark field image and the bright field image in step S2 includes: S201, preprocessing the dark field image and the bright field image; S202, registering the dark field image and the bright field image; S203, using a fusion algorithm to fuse the dark field image and the bright field image to obtain an initial detection image; S204: Perform color correction and brightness adjustment on the initial detection image to obtain a detection image.

[0010] As an optional embodiment of the present invention, optionally, the expression of the fusion algorithm is: ; ; in, Indicates scale levels, coordinates The weight map at Indicates that the dark field image is scale levels, coordinates The contrast measurement at Indicates the bright field image at scale levels, coordinates The contrast measurement at After fusion, images at different scales, Indicates that the dark field image is images at different scales, Indicates the bright field image at images at different scales.

[0011] As an optional embodiment of the present invention, optionally, detecting the time domain noise in the detection image in step S3 includes: S301, performing noise filtering and image enhancement processing on the detection image in sequence; S302, converting the detected image into a frequency domain image, and analyzing the intensity of different frequency components based on the frequency domain image to obtain an intensity distribution map; S303: Setting a noise threshold based on the intensity distribution graph, determining frequency components above the noise threshold as time domain noise, and locating the time domain noise in the detection image.

[0012] As an optional embodiment of the present invention, optionally, in step S4, performing high-speed parallel processing on the processed detection image based on FPGA includes: S401, loading the detection image into the internal memory of the FPGA, and preprocessing the detection image through the FPGA; S402, dividing the FPGA into a filtering module, an edge detection module and an image enhancement module, and configuring corresponding processing algorithms for the filtering module, the edge detection module and the image enhancement module respectively, so as to realize parallel processing of the detected image; S403, filtering the detection image by the filtering module to remove high-frequency noise and interference in the detection image; S404, performing edge detection on the filtered image by the edge detection module, and extracting edge information in the detected image; S405, based on the edge information, performing enhancement processing on the detected image after edge detection by the image enhancement module; S406: Output the processed detection image to an external storage device or a display device.

[0013] In another aspect, the present invention further provides an electronic device, comprising: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the multi-dimensional based transistor detection image correction and optimization method when executing the executable instructions.

[0014] In another aspect, the present invention further provides a computer-readable storage medium, comprising: a memory having a computer program stored thereon; A processor is used to execute the program in the memory to implement the multi-dimensional transistor detection image correction and optimization method.

[0015] Beneficial effects of the present invention: The present invention can accurately eliminate geometric distortion in the image and obtain a high-quality corrected image by automatically selecting stable feature points in the transistor detection image and calculating the transformation matrix using the geometric correction model. This method reduces the interference of human factors and improves the accuracy and stability of the correction. Combining the dark field illumination method and the bright field illumination method, the present invention can obtain a dark field image that highlights the surface defects and textures of the transistor and a bright field image that reflects the overall morphology and structural information of the transistor. By fusing these two images, a detection image containing more useful information can be obtained, providing strong support for subsequent analysis and detection. The present invention adopts an advanced time domain noise detection method, which can accurately identify and locate high-frequency noise and interference in the detection image. The noise is smoothed by a filtering algorithm, and the edge information of the image is enhanced, thereby improving the clarity and readability of the image. The present invention also utilizes the high-speed parallel processing capability of the FPGA, and the present invention can realize rapid processing of the detection image. By dividing the FPGA into multiple processing modules and configuring corresponding processing algorithms, parallel processing of images is realized, which significantly improves the processing speed and efficiency.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 It is a flow chart of a transistor detection image correction and optimization method based on multi-dimensionality of the present invention; Figure 2 It is a structural schematic diagram of an electronic device of the present invention. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] Example 1 like Figure 1 As shown, a transistor detection image correction and optimization method based on multi-dimensionality, the method includes: S1, selecting a transistor to detect stable feature points in an image, calculating a transformation matrix based on the stable feature points using a geometric correction model, and using the transformation matrix to eliminate geometric distortion in the image to obtain a corrected image; It should be noted that in step S1, when selecting stable feature points in the transistor detection image, this embodiment adopts a series of fine steps to ensure the stability and reliability of the feature points. First, the transistor detection image is converted into a grayscale image. This step helps to reduce the interference of color information in the image, making the subsequent feature point detection more accurate. Next, the grayscale image is smoothed and filtered, which can further reduce image noise and improve the accuracy of feature point detection. Then, a corner point detection algorithm is used to identify corner points or extreme points in the grayscale image. These points usually have higher image gradients and edge responses, and are therefore regarded as potential stable feature points. In order to screen out the most stable feature points, the present invention sorts the identified corner points and extreme points based on the response value, and selects the point with the highest response value as the final feature point. Finally, the descriptors of these feature points are calculated. The descriptors usually contain local image information of the feature points, which can be used for subsequent feature point matching and verification. By verifying the feature points based on the descriptors, the present invention can eliminate those unstable or misidentified feature points, thereby obtaining a more accurate and stable feature point set. These stable feature points will serve as the basis for subsequent geometric correction to ensure the accuracy and stability of image correction.

[0020] S2, based on the corrected image, using a dark field illumination method to obtain a dark field image that highlights the surface defects and texture of the transistor, using a bright field illumination method to obtain a bright field image of the overall morphology and structural information of the transistor, and fusing the dark field image and the bright field image to generate a detection image; It should be noted that in step S2, in order to generate high-quality detection images, the present embodiment adopts a combination of dark field illumination and bright field illumination. The dark field illumination method uses a specific illumination angle to make the light mainly shine on the surface defects and textures of the transistor, thereby highlighting these subtle features. The bright field illumination method provides comprehensive illumination, so that the overall morphology and structural information of the transistor can be clearly presented. By fusing these two images, not only can the detailed features of the transistor surface be obtained, but also its overall structural information can be retained, providing more comprehensive and accurate data support for subsequent analysis and detection. In the fusion process, the present embodiment also uses an advanced fusion algorithm to ensure that the dark field image and the bright field image can be seamlessly combined to avoid information loss or overlap, thereby generating a detection image with optimal visual effects and detection accuracy.

[0021] S3, detecting the time domain noise in the detection image, smoothing the detected time domain noise using a filtering algorithm, and enhancing the edge of the detection image; It should be noted that, in step S3, the present embodiment adopts the time domain noise detection technology. The technology first performs a detailed preprocessing on the detection image, including noise filtering and image enhancement processing, to improve the accuracy of noise detection and image quality. Subsequently, the processed detection image is converted into a frequency domain image, and the intensity distribution of different frequency components can be clearly observed through the frequency domain analysis technology. Based on this intensity distribution diagram, the present embodiment sets a reasonable noise threshold, and the frequency components above this threshold are determined as time domain noise, and the positions of these noises in the detection image are accurately located. Once the noise is accurately identified, the present embodiment uses an efficient filtering algorithm to smooth it, effectively reducing the impact of high-frequency noise and interference on image quality. At the same time, in order to further improve the clarity and readability of the image, the present invention also enhances the edge information of the detection image, so that the edge features of the transistor are more distinct. The implementation of this series of steps not only improves the visual effect of the image, but also ensures the accuracy and reliability of the detection results.

[0022] S4. Perform high-speed parallel processing on the processed detection image based on FPGA to optimize the detection image.

[0023] It should be noted that this embodiment uses the high-speed parallel processing capability of FPGA (field programmable gate array) to further optimize the processed detection image. As a high-performance hardware platform, FPGA has powerful parallel computing capabilities and high flexibility, and is very suitable for intensive computing tasks such as image processing. In step S4, the processed detection image is first loaded into the internal memory of FPGA to ensure that the image data can be quickly accessed and processed. Subsequently, FPGA is divided into multiple processing modules, including a filtering module, an edge detection module and an image enhancement module. Each module is configured with a corresponding processing algorithm to achieve parallel processing of the detection image. This parallel processing method can significantly improve the processing speed and efficiency, making the image optimization process faster and more efficient. In the filtering module, the detection image is further filtered by an advanced filtering algorithm to remove high-frequency noise and interference that may remain in the image. Then, in the edge detection module, the edge detection algorithm is used to perform edge detection on the filtered image to extract edge information in the image. In order to further enhance the visual effect and readability of the image, the image enhancement module performs enhancement processing on the detection image after edge detection. By adjusting the image's contrast, brightness, and color, the features in the image are made more distinct and prominent. Finally, the processed detection image is output to an external storage device or display device for subsequent analysis and detection. Through the high-speed parallel processing of FPGA, this embodiment can achieve rapid optimization of the detection image, significantly improve the processing speed and efficiency, and provide powerful technical support for the detection and analysis of transistors.

[0024] This embodiment is based on the principle of a multi-dimensional transistor detection image correction and optimization method: First, the transistor detection image is converted into a grayscale image and smoothed and filtered to reduce noise interference. Next, the corner detection algorithm is used to identify the corner points or extreme points in the grayscale image, which usually have stable structures and obvious features. Then, the corner points and extreme points are sorted according to their response values, and the points with the highest response values ​​are selected as feature points. Finally, the descriptors of the feature points are calculated to describe the local features of the feature points so that they can be matched in different images.

[0025] The descriptors of feature points are used to match feature points in different transistor detection images to obtain the corresponding relationship between feature points in different images. Based on the matched feature points, a geometric correction model (such as affine transformation, perspective transformation, etc.) is used to evaluate the corresponding relationship between different images. The transformation matrix is ​​calculated based on the corresponding relationship, which describes the geometric transformation relationship between the images. The original transistor detection image is transformed using the transformation matrix to eliminate the geometric distortion in the image and obtain the corrected image.

[0026] Preprocess the dark field image and the bright field image, such as denoising and enhancement, to improve the image quality. Register the preprocessed images, that is, adjust the position and angle of the images so that they are aligned in the same coordinate system. Use appropriate fusion algorithms (such as weighted average, multi-scale fusion, etc.) to fuse the dark field image and the bright field image. The fusion algorithm assigns weights according to the image's contrast, brightness and other features to obtain the fused image. Perform color correction and brightness adjustment on the fused image to obtain the final detection image.

[0027] Perform frequency domain analysis on the detected image to identify and locate frequency components above the noise threshold as time domain noise. Use filtering algorithms to smooth the detected noise to reduce the impact of noise on image quality. Perform edge detection on the filtered image to extract edge information in the image. Perform image enhancement based on edge information, such as sharpening and contrast enhancement, to improve image clarity and readability.

[0028] The detected image is loaded into the internal memory of the FPGA for subsequent processing. The detected image is preprocessed by the FPGA, such as denoising and enhancement, to improve processing efficiency and accuracy. The FPGA is divided into multiple parallel processing modules, such as filtering module, edge detection module and image enhancement module. Each module is configured with corresponding processing algorithms and hardware resources to achieve parallel processing. Each parallel processing module works simultaneously to filter, detect edges and enhance images. The processed image is transmitted to an external storage device or display device through the output interface of the FPGA.

[0029] To sum up, the overall principle of this solution is to achieve image correction through feature point selection and description, geometric correction and transformation; to achieve image fusion through image preprocessing, registration and fusion algorithms; to achieve image noise processing and enhancement through noise detection and filtering, edge detection and image enhancement; and finally to achieve efficient image processing through the high-speed parallel processing capability of FPGA.

[0030] As an optional embodiment of the present invention, optionally, selecting stable feature points in the transistor detection image in step S1 includes: S101, converting the transistor detection image into a grayscale image, and performing smoothing filtering on the grayscale image to obtain; It should be noted that in step S101, converting the transistor detection image into a grayscale image can simplify the image information and reduce the amount of calculation for subsequent processing. The grayscale image only contains brightness information, but not color information, which makes the detection of feature points more efficient and accurate. Smoothing filtering is used to further reduce noise and interference in the image and improve the stability of feature point detection. By adopting appropriate smoothing filtering algorithms, such as Gaussian filtering, mean filtering, etc., high-frequency noise and small fluctuations in the image can be removed, making the feature points more prominent and easy to detect.

[0031] S102, using a corner detection algorithm to identify corner points or extreme points in the grayscale image; It should be noted that, in step S102, the corner detection algorithm identifies corner points or extreme points by calculating the gradient change of each pixel in the image. These points are usually located at the edge of the image or in the area with rich texture, and have high gradient values ​​and obvious features. In the transistor detection image, the corner detection algorithm can effectively identify the subtle features and structural changes on the surface of the transistor. Through the corner detection algorithm, this embodiment can accurately identify the corner points and extreme points in the grayscale image.

[0032] S103, sorting the corner points and extreme value points based on the response values, and obtaining the point with the highest response value as a feature point; It should be noted that in step S103, the response value reflects the stability and significance of the corner points and extreme points in the image. A higher response value usually means that the feature point is more stable and reliable and can better represent the characteristics of the image. Therefore, this embodiment selects the point with the highest response value as the feature point to ensure the accuracy and stability of subsequent geometric correction. These feature points will serve as the basis of the geometric correction model to calculate the transformation matrix, thereby achieving accurate correction of the transistor detection image.

[0033] S104 , calculating a descriptor of the feature point, and verifying the feature point based on the descriptor to obtain a stable feature point.

[0034] It should be noted that in step S104, the descriptor is a mathematical representation for describing the local image information of the feature point, which contains key information such as the pixel intensity distribution and gradient direction around the feature point. These descriptors can be used in the subsequent feature point matching and verification process to ensure the stability and accuracy of the feature points. By calculating the descriptors of the feature points, the present embodiment can further screen out those feature points that are unique and stable. In the feature point verification process, the present embodiment adopts a verification algorithm, which eliminates those feature points with high similarity or instability by comparing the similarity between the descriptors of different feature points. The implementation of this step can further improve the stability and reliability of the feature points, and provide a more accurate and reliable basis for subsequent geometric correction and image correction.

[0035] As an optional embodiment of the present invention, optionally, in step S1, calculating a transformation matrix based on the stable feature points using a geometric correction model, and eliminating geometric distortion in the image using the transformation matrix includes: S105, matching feature points in different transistor detection images based on the descriptors of the feature points, and obtaining corresponding relationships between the feature points in different transistor detection images; It should be noted that in step S105, this embodiment uses the descriptor of the feature point to search for similar feature points in different transistor detection images, thereby establishing a correspondence between the feature points. This step uses a matching algorithm and a search strategy to ensure the accuracy and efficiency of the matching results. Through feature point matching, this embodiment can obtain the position information of the same or similar feature points in different images.

[0036] S106, using a geometric correction model based on the matched feature points to evaluate the correspondence between different transistor detection images, and calculating a transformation matrix based on the correspondence; It should be noted that in step S106, geometric correction models such as affine transformation, perspective transformation, etc. are used to evaluate the correspondence between different transistor detection images. These models accurately describe the geometric transformation relationship between images by considering information such as the position, direction and distance of feature points. Based on the matched feature points, this embodiment uses an appropriate geometric correction model to calculate the transformation matrix. The transformation matrix describes the geometric transformation relationship between images, including transformations such as translation, rotation, scaling and tilt. By using the transformation matrix, this embodiment can transform the original transistor detection image to eliminate the geometric distortion in the image, thereby obtaining a corrected image and improving the accuracy and readability of the image.

[0037] S107 , transforming the original transistor detection image based on the transformation matrix, eliminating geometric distortion in the original transistor detection image, and obtaining a corrected image.

[0038] It should be noted that in step S107, by applying the transformation matrix to the original transistor detection image, accurate correction of geometric distortion in the image can be achieved. In this step, the present embodiment uses an image processing algorithm to ensure the accuracy and efficiency of the transformation process. Through the transformation, geometric distortions such as distortion, tilt and scaling in the image are effectively eliminated, thereby obtaining a corrected image. The corrected image has higher accuracy and readability, providing a more reliable basis for subsequent analysis and detection.

[0039] As an optional embodiment of the present invention, optionally, the expression for calculating the transformation matrix is: ; in, Represents the horizontal coordinate of the midpoint of the detected image after transformation; Represents the ordinate of the midpoint of the detected image after transformation; represents the weight under homogeneous coordinates; , , , , , , , and All represent elements of the transformation matrix; Represents the horizontal coordinate of the midpoint of the original transistor detection image, Represents the vertical coordinate of the midpoint of the original transistor detection image.

[0040] As an optional embodiment of the present invention, optionally, fusing the dark field image and the bright field image in step S2 includes: S201, preprocessing the dark field image and the bright field image; It should be noted that in step S201, preprocessing is a key step in the fusion process, which aims to improve the quality and consistency of the image. For dark field images and bright field images, preprocessing includes operations such as denoising, contrast enhancement, and brightness adjustment. These operations help reduce noise and interference in the image and improve the clarity and readability of the image. Through preprocessing, the dark field image and the bright field image can have better matching and consistency when fused, thereby improving the quality of the fused image.

[0041] S202, registering the dark field image and the bright field image; It should be noted that in step S202, registration is the process of aligning the same or similar features in different images. Since dark field images and bright field images differ in shooting conditions and lighting conditions, registration is required to ensure that they can be accurately aligned when fused. The registration process includes calculating the transformation relationship between images and adjusting the position and angle of the images so that they are aligned in the same coordinate system. By adopting appropriate registration algorithms, such as feature point matching, phase correlation, etc., high-precision image registration can be achieved.

[0042] S203, using a fusion algorithm to fuse the dark field image and the bright field image to obtain an initial detection image; S204: Perform color correction and brightness adjustment on the initial detection image to obtain a detection image.

[0043] It should be noted that in step S204, due to the differences in illumination and color between the dark field image and the bright field image, direct fusion may cause color distortion and uneven brightness. Therefore, it is necessary to perform color correction and brightness adjustment on the fused initial detection image. Color correction aims to eliminate color deviation in the image so that the color of the image is more realistic and accurate. Brightness adjustment is used to optimize the brightness distribution of the image and improve the clarity and readability of the image. Through color correction and brightness adjustment, a transistor detection image with higher quality and easier analysis and detection can be obtained.

[0044] As an optional embodiment of the present invention, optionally, the expression of the fusion algorithm is: ; ; in, Indicates scale levels, coordinates The weight mapping at ; Indicates that the dark field image is scale levels, coordinates Contrast measurement at ; Indicates the bright field image at scale levels, coordinates Contrast measurement at ; After fusion, images at different scales; Indicates that the dark field image is images at different scales; Indicates the bright field image at images at different scales.

[0045] As an optional embodiment of the present invention, optionally, detecting the time domain noise in the detection image in step S3 includes: S301, performing noise filtering and image enhancement processing on the detection image in sequence; S302, converting the detected image into a frequency domain image, and analyzing the intensity of different frequency components based on the frequency domain image to obtain an intensity distribution map; It should be noted that in step S302, the detection image is converted from the spatial domain to the frequency domain using mathematical tools such as Fourier transform. The frequency domain image shows the information of different frequency components in the image, where the low-frequency components usually represent the general structure and background of the image, while the high-frequency components reflect the details and edge information of the image. By analyzing the intensity of different frequency components in the frequency domain image, an intensity distribution map can be obtained, which reveals the distribution characteristics of noise and signals in the image at different frequencies. This step helps to identify the manifestation of time domain noise in the frequency domain, providing key information for subsequent time domain noise detection and processing.

[0046] S303: Setting a noise threshold based on the intensity distribution graph, determining frequency components above the noise threshold as time domain noise, and locating the time domain noise in the detection image.

[0047] It should be noted that, in step S303, the setting of the noise threshold is determined based on the statistical characteristics and empirical values ​​of the intensity distribution diagram. By comparing the intensity of the frequency component with the noise threshold, the frequency components above the threshold can be identified, and these components are regarded as time domain noise. In order to accurately locate these noises in the detection image, the present embodiment uses mathematical tools such as inverse Fourier transform to convert the frequency domain image back to the spatial domain, thereby marking the position of the noise in the original detection image. The implementation of this step helps to carry out targeted processing of the time domain noise in the follow-up and improve the clarity and quality of the image.

[0048] As an optional embodiment of the present invention, optionally, in step S4, performing high-speed parallel processing on the processed detection image based on FPGA includes: S401, loading the detection image into the internal memory of the FPGA, and preprocessing the detection image through the FPGA; S402, dividing the FPGA into a filtering module, an edge detection module and an image enhancement module, and configuring corresponding processing algorithms for the filtering module, the edge detection module and the image enhancement module respectively, so as to realize parallel processing of the detected image; It should be noted that in step S402, by loading the detection image into the internal memory of the FPGA, rapid access and processing of the image data can be achieved. On the FPGA platform, this embodiment divides the image processing process into multiple modules, including a filtering module, an edge detection module, and an image enhancement module. These modules each undertake different image processing tasks, and by configuring corresponding processing algorithms, parallel processing of the detection image is achieved. The filtering module is used to smooth the image and reduce noise interference; the edge detection module is used to identify edge features in the image and improve the clarity of the image; the image enhancement module is used to enhance the contrast and brightness of the image, making the image easier to analyze and detect. Through parallel processing, this embodiment can significantly improve the efficiency and quality of image processing.

[0049] S403, filtering the detection image by the filtering module to remove high-frequency noise and interference in the detection image; It should be noted that in step S403, on the FPGA platform, the filtering module can implement filtering processing on the detection image by configuring different filtering algorithms, such as mean filtering, Gaussian filtering, etc. These filtering algorithms calculate new pixel values ​​by considering the neighborhood information around the pixel, thereby achieving noise suppression and smoothing processing. Through filtering processing, high-frequency noise and interference in the image are effectively removed, and the clarity and quality of the image are improved.

[0050] S404, performing edge detection on the filtered image by the edge detection module, and extracting edge information in the detected image; It should be noted that in step S404, edge detection is an important step in image processing, which aims to identify edge features in the image, which usually represent important information and structure in the image. On the FPGA platform, the edge detection module can implement edge detection of the detected image by configuring different edge detection algorithms, such as Sobel operator, Canny operator, etc. These algorithms identify edge features in the image by calculating pixel gradients or intensity changes. Through edge detection, the edge information in the image is clearly extracted.

[0051] S405, based on the edge information, performing enhancement processing on the detected image after edge detection by the image enhancement module; It should be noted that in step S405, by enhancing the edge features in the image, the edge of the image is made clearer and more prominent, thereby improving the contrast and readability of the image. On the FPGA platform, the image enhancement module can implement enhanced processing of the detection image by configuring different enhancement algorithms, such as histogram equalization, adaptive contrast enhancement, etc. These algorithms adjust the pixel value of the image according to the statistical characteristics and edge information of the image, thereby achieving an enhanced effect on the image. Through image enhancement processing, the quality and clarity of the detection image are significantly improved.

[0052] S406: Output the processed detection image to an external storage device or a display device.

[0053] It should be noted that, in step S406, the detected image after processing is transferred to an external storage device, such as a hard disk, a solid state drive or a network storage device, through the output interface of FPGA, to realize long-term preservation and backup of data. Meanwhile, the detected image after processing can also be directly output to a display device, such as a liquid crystal display, an LED display, etc., for real-time viewing and analysis by an operator. The implementation of this step not only ensures the reliability and security of the detected image data, but also provides convenience for subsequent image analysis and detection. By the high-speed parallel processing of FPGA, the present embodiment can realize the fast and accurate processing of transistor detection images, and improves the efficiency and quality of image processing.

[0054] Example 2 like Figure 2 As shown, an electronic device includes: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the multi-dimensional transistor detection image correction and optimization method in Example 1 when executing the executable instructions.

[0055] It should be noted that the electronic device includes: a processor, a memory, and the electronic device may also include one or more of a multimedia component, an input / output (I / O) interface, and a communication component.

[0056] Among them, the processor is used to control the overall operation of the electronic device to complete all or part of the steps in the above-mentioned big data-based factory equipment automated testing method.

[0057] The memory is used to store various types of data to support operations on the electronic device, which data may include, for example, instructions for any application or method operating on the electronic device, as well as application-related data; the memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0058] The multimedia component may include a screen and an audio component, wherein the screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals; for example, the audio component may include a microphone for receiving external audio signals, and the received audio signals may be further stored in a memory or sent via a communication component; the audio component also includes at least one speaker for outputting audio signals.

[0059] The I / O interface provides an interface between the processor and other interface modules, which may be a keyboard, a mouse, buttons, etc.; these buttons may be virtual buttons or physical buttons.

[0060] The communication component is used for wired or wireless communication between the electronic device and other devices; wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G or 5G, or a combination of one or more of them, so the corresponding communication component may include: Wi-Fi module, Bluetooth module, NFC module, mobile phone communication module.

[0061] As a preferred solution of this embodiment, the electronic device can be implemented by one or more application specific integrated circuits (Application Specific Integrated Circuit, ASIC), digital signal processors (Digital Signal Processor, DSP), digital signal processing devices (Digital Signal Processing Device, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field Programmable Gate Array, FPGA), controllers, microcontrollers, microprocessors or other electronic components to execute the above-mentioned big data-based factory equipment automated testing method.

[0062] Example 3 A computer-readable storage medium, comprising: a memory having a computer program stored thereon; A processor is used to execute the program in the memory to implement the multi-dimensional transistor detection image correction and optimization method in Example 1.

[0063] It should be noted that the electronic device according to the embodiment of the present disclosure includes a processor and a memory for storing processor executable instructions. The processor is configured to implement any of the above-mentioned transistor detection image correction and optimization methods based on multi-dimensionality when executing the executable instructions.

[0064] Here, it should be noted that the number of processors can be one or more. At the same time, the electronic device in the embodiment of the present disclosure may also include an input device and an output device. Among them, the processor, memory, input device and output device may be connected through a bus or in other ways, which are not specifically limited here.

[0065] As a computer-readable storage medium, the memory can be used to store software programs, computer executable programs and various modules, such as the program or module corresponding to the multi-dimensional transistor detection image correction and optimization method in the embodiment of the present disclosure. The processor executes various functional applications and data processing of the electronic device by running the software programs or modules stored in the memory.

[0066] The input device can be used to receive input numbers or signals. The signal can be a key signal related to user settings and function control of the device / terminal / server. The output device can include a display device such as a display screen.

[0067] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A transistor detection image correction and optimization method based on multi-dimensionality, characterized in that: The method comprises: S1, selecting a transistor to detect stable feature points in an image, calculating a transformation matrix based on the stable feature points using a geometric correction model, and using the transformation matrix to eliminate geometric distortion in the image to obtain a corrected image; S2, based on the corrected image, using a dark field illumination method to obtain a dark field image that highlights the surface defects and texture of the transistor, using a bright field illumination method to obtain a bright field image of the overall morphology and structural information of the transistor, and fusing the dark field image and the bright field image to generate a detection image; S3, detecting the time domain noise in the detection image, smoothing the detected time domain noise using a filtering algorithm, and enhancing the edge of the detection image; S4. Perform high-speed parallel processing on the processed detection image based on FPGA to optimize the detection image.

2. A transistor detection image correction and optimization method based on multi-dimensionality as claimed in claim 1, characterized in that: Selecting stable feature points in the transistor detection image in step S1 includes: S101, converting the transistor detection image into a grayscale image, and performing smoothing filtering on the grayscale image to obtain; S102, using a corner detection algorithm to identify corner points or extreme points in the grayscale image; S103, sorting the corner points and extreme value points based on the response values, and obtaining the point with the highest response value as a feature point; S104 , calculating a descriptor of the feature point, and verifying the feature point based on the descriptor to obtain a stable feature point.

3. A transistor detection image correction and optimization method based on multi-dimensionality as claimed in claim 2, characterized in that: In step S1, a transformation matrix is ​​calculated based on the stable feature points using a geometric correction model, and using the transformation matrix to eliminate geometric distortion in the image includes: S105, matching feature points in different transistor detection images based on the descriptors of the feature points, and obtaining corresponding relationships between the feature points in different transistor detection images; S106, using a geometric correction model based on the matched feature points to evaluate the correspondence between different transistor detection images, and calculating a transformation matrix based on the correspondence; S107 , transforming the original transistor detection image based on the transformation matrix, eliminating geometric distortion in the original transistor detection image, and obtaining a corrected image.

4. A transistor detection image correction and optimization method based on multi-dimensionality as claimed in claim 2, characterized in that: The expression for calculating the transformation matrix is: ； in, Represents the horizontal coordinate of the midpoint of the detected image after transformation, Represents the ordinate of the midpoint of the detected image after transformation, represents the weight in homogeneous coordinates, , , , , , , , and represent the elements of the transformation matrix, Represents the horizontal coordinate of the midpoint of the original transistor detection image, Represents the vertical coordinate of the midpoint of the original transistor detection image.

5. The multi-dimensional transistor detection image correction and optimization method according to claim 1, characterized in that: In step S2, fusing the dark field image and the bright field image comprises: S201, preprocessing the dark field image and the bright field image; S202, registering the dark field image and the bright field image; S203, using a fusion algorithm to fuse the dark field image and the bright field image to obtain an initial detection image; S204: Perform color correction and brightness adjustment on the initial detection image to obtain a detection image.

6. A transistor detection image correction and optimization method based on multi-dimensionality as claimed in claim 5, characterized in that: The expression of the fusion algorithm is: ； ； in, Indicates scale levels, coordinates The weight map at Indicates that the dark field image is scale levels, coordinates The contrast measurement at Indicates the bright field image at scale levels, coordinates The contrast measurement at After fusion, images at different scales, Indicates that the dark field image is images at different scales, Indicates the bright field image at images at different scales.

7. The multi-dimensional transistor detection image correction and optimization method according to claim 1, characterized in that: Detecting the temporal noise in the detection image in step S3 includes: S301, performing noise filtering and image enhancement processing on the detection image in sequence; S302, converting the detected image into a frequency domain image, and analyzing the intensity of different frequency components based on the frequency domain image to obtain an intensity distribution map; S303: Setting a noise threshold based on the intensity distribution graph, determining frequency components above the noise threshold as time domain noise, and locating the time domain noise in the detection image.

8. The multi-dimensional transistor detection image correction and optimization method according to claim 1, characterized in that: In step S4, high-speed parallel processing of the processed detection image based on FPGA includes: S401, loading the detection image into the internal memory of the FPGA, and preprocessing the detection image through the FPGA; S402, dividing the FPGA into a filtering module, an edge detection module and an image enhancement module, and configuring corresponding processing algorithms for the filtering module, the edge detection module and the image enhancement module respectively, so as to realize parallel processing of the detected image; S403, filtering the detection image by the filtering module to remove high-frequency noise and interference in the detection image; S404, performing edge detection on the filtered image by the edge detection module, and extracting edge information in the detected image; S405, based on the edge information, performing enhancement processing on the detected image after edge detection by the image enhancement module; S406: Output the processed detection image to an external storage device or a display device.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the multi-dimensional transistor detection image correction and optimization method according to any one of claims 1 to 8 when executing the executable instructions.

10. A computer-readable storage medium, characterized in that: include: a memory having a computer program stored thereon; A processor, used to execute the program in the memory to implement the multi-dimensional transistor detection image correction and optimization method according to any one of claims 1 to 8.

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