Gate driving circuit and driving method for realizing panel frequency division display

Abstract

The application discloses a kind of grid driving circuit for realizing panel frequency division display, including cascaded multiple GOA units and multiple frequency division control units, frequency division control unit is evenly distributed between GOA unit, frequency division control unit is opened by frequency division control signal control, multiple clock signals are respectively accessed GOA unit, the gate drive signal of upper GOA unit and the frequency division display signal of frequency division control unit are input lower GOA unit, GOA unit includes pull-up unit, pull-up control unit, pull-down control unit, inverter, pull-down maintenance unit, Reset unit, common terminal Q, gate drive signal output end, pull-up unit controls gate drive signal output end output signal, inverter and pull-down maintenance unit maintain common terminal Q and gate drive signal output end potential, pull-up control unit pulls up common terminal Q potential and opens pull-up unit, pull-down control unit pulls down common terminal Q potential and closes pull-up unit, Reset unit maintains common terminal and gate drive signal output end potential.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular, to a gate driving circuit and a driving method for display panel frequency division display. BACKGROUND

[0002] The gate driving circuit applied to display panel driving comprises a plurality of cascaded GOA (Gate Driver on Array) units, and the output signal generated by each GOA unit is not only used for display panel driving, but also opens the next-level GOA unit through level transmission. Due to the characteristics of GOA unit level transmission, all GOA units output signals in turn, and the refresh frequency of the entire display panel remains consistent.

[0003] The GOA unit uses a thin film transistor (TFT) circuit to output a gate driving signal row by row, and the opening and closing of the Gate signal of the common GOA level transmission circuit is affected by the upper and lower gate driving signals. Within a frame of time, all Gate signals complete a potential rising and falling action through the gate driving signal, and during the potential rising period, the thin film transistor of the corresponding row of pixels is opened to complete the charging of the pixels.

[0004] In actual use, users usually watch videos, games, etc. in a part of the screen area, and this part of the area has a higher requirement for refresh frequency, while the other part of the area is a comment area or an area not effectively used, and has a lower requirement for refresh frequency. Therefore, the high refresh frequency requirement area such as video and game and the comment area and the area not effectively used work at different refresh frequencies, which not only meets the user's demand, but also reduces the power consumption of the display panel. SUMMARY

[0005] The purpose of the present application is to overcome the defects and deficiencies of the prior art, and to provide a gate driving circuit and a driving method for realizing panel frequency division display, which increases the frequency division control unit and the input frequency division control signal, realizes the work of different display areas at different refresh frequencies, and the display frequencies can be independent of each other, thereby reducing the display power consumption.

[0006] In order to achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0007] A gate driving circuit for realizing panel frequency division display, comprising a plurality of cascaded GOA units, and a plurality of frequency division control units uniformly distributed between the GOA units, a plurality of clock signals are connected to the plurality of GOA units, and the frequency division control unit is connected to the upper GOA unit and the lower GOA unit, the upper GOA unit is used to open the lower GOA unit during normal display, and the frequency division control unit is used to open the lower GOA unit during frequency division display;

[0008] The GOA unit includes a pull-up unit, a pull-up control unit, a pull-down control unit, an inverter, a pull-down maintaining unit, a reset unit, a common terminal Q, and a gate drive signal output terminal. The pull-up unit is used to control the gate drive signal output terminal to output a square wave signal to drive display and upper and lower stage transmission. The inverter and the pull-down maintaining unit are used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during the non-stage transmission period. The pull-up control unit is used to pull up the potential of the common terminal Q and turn on the pull-up unit. The pull-down control unit is used to pull down the potential of the common terminal Q and turn off the pull-up unit. The reset unit is used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during the non-display period.

[0009] Multiple frequency division control units are turned on by frequency division control signals. By setting a specific clock signal, the turned-on frequency division control unit drives the lower-level GOA unit connected to it. The gate drive signal output by the upper-level GOA unit and the frequency division display signal output by the frequency division control unit are simultaneously input into the lower-level GOA unit to drive the frequency division display.

[0010] Furthermore, the frequency division control unit includes a frequency division control signal input terminal, an open position signal input terminal, a first thin film transistor T1, a level transfer control signal input terminal, n second thin film transistors T2(1) to T2(n) and n frequency division display signal output terminals F(1) to F(n);

[0011] The gate of the first thin film transistor T1 is connected to the frequency division control signal input terminal, the drain of the first thin film transistor T1 is connected to the open bit signal input terminal, the source of the first thin film transistor T1 is connected to the level transfer control signal input terminal, and the gates and drains of the n second thin film transistors T2(1) to T2(n) are respectively connected to the level transfer control signal input terminal;

[0012] The source and drain electrodes of n second thin film transistors T2(1) to T2(n) are connected to form a common terminal S1, the source electrode of the second thin film transistor T2(i) is connected to the frequency division display signal output terminal F(i), and the frequency division display signal output terminal F(i) is connected to the common terminal Q(i) of the i-th level GOA unit after the frequency division control unit, where n≥1, and i is a positive integer less than or equal to n.

[0013] Furthermore, the GOA unit also includes an upper gate drive signal input terminal, a lower gate drive signal input terminal, a clock signal input terminal, a low potential signal input terminal, a high potential signal input terminal and a reset signal input terminal, the upper gate drive signal input terminal is connected to the pull-up control unit, the lower gate drive signal input terminal is connected to the pull-down control unit, the clock signal input terminal is connected to the pull-up unit, the reset signal input terminal is connected to the reset unit, and the high potential signal input terminal is connected to the inverter;

[0014] The common terminal Q is connected with the pull-up unit, the pull-up control unit, the pull-down control unit, the inverter, the pull-down maintaining unit and the Reset unit respectively, the gate drive signal output terminal is connected with the pull-up unit, the pull-down maintaining unit and the Reset unit respectively, the low potential signal input terminal is connected with the pull-down control unit, the inverter, the Reset unit and the pull-down maintaining unit respectively, the pull-down control unit, the inverter and the Reset unit are connected with the pull-up control unit respectively, and the pull-down maintaining unit is connected with the inverter and the Reset unit respectively.

[0015] Further, the frequency division control signal input terminal is used for receiving a frequency division control signal STVD, the start bit signal input terminal is used for receiving a clock signal, the frequency division display signal output terminal is used for outputting a frequency division display signal to start a lower GOA unit, and the frequency division control units at different positions are connected with different clock signals to realize the control of the different frequency division control units by using different clock signals.

[0016] Further, when the frequency division control signal STVD is at a low potential, the first thin film transistor T1 is closed by the low potential frequency division control signal STVD, the common terminal S1 point is at a low potential, and the low potential common terminal S1 point is connected with the gate of the second thin film transistor T2(1) to T2(n) and closes the second thin film transistor T2(1) to T2(n).

[0017] When the frequency division control signal STVD is at a high potential, the first thin film transistor T1 is opened by the high potential frequency division control signal STVD, the high potential clock signal pulls up the potential of the common terminal S1 point through the first thin film transistor T1, and the high potential common terminal S1 opens the second thin film transistor T2(1) to T2(n).

[0018] Further, the number of clock signals connected with the GOA unit is even, the number of frequency division control units is less than or equal to the number of clock signals, and the number of second thin film transistors T2 and the number of frequency division display signal output terminals are half of the number of clock signals.

[0019] A driving method for realizing panel frequency division display is applied to the gate drive circuit for realizing panel frequency division display in any one of claims 1 to 5, and the driving method comprises the following steps.

[0020] Before the frequency division control signal is output, the clock signals CK(1) to CK(2n) become low potential after the display of the upper GOA unit of the frequency division control unit ends, the Reset signal becomes high potential after the clock signal is reduced to low potential, the high potential Reset signal opens the Reset unit of all GOA units, and the Reset unit of the GOA unit reduces the gate drive signal of the GOA unit and the potential of the common terminal Q point to low potential.

[0021] After that, the Reset signal becomes a low level. After the Reset signal becomes a low level, the frequency division control signal outputs a high level signal. By setting the specific clock signal CK(m) to a high level, the corresponding frequency division control unit is turned on. The turned-on frequency division control unit drives the lower-level GOA unit connected to it, and sets the display frequency of the corresponding panel by setting the clock signal and data signal.

[0022] Furthermore, when frequency division display is not performed, the method includes:

[0023] The frequency division control signal STVD is at a low potential, the control signal input terminal of the frequency division control unit inputs a low potential to the gate of the first thin film transistor T1, the first thin film transistor T1 is in a closed state, the common terminal S1 connected to the gate of the second thin film transistor T2 is at a low potential, the second thin film transistor T2 is closed, the frequency division display signal output terminal has no output signal, all GOA units of the gate drive circuit are normally transmitted, and the display area is displayed at the same frequency.

[0024] Furthermore, when performing frequency division display, it includes:

[0025] After the upper GOA unit of the frequency division control unit outputs the gate drive signal, all clock signals CK(1) to CK(2n) output low potential, and the Reset signal outputs high potential, pulling down the common terminal Q and the gate drive signal output terminal potential in the GOA unit;

[0026] After the Reset signal changes from high potential to low potential, the frequency division control signal STVD and the specific clock signal CK(m) output high potential to the frequency division control unit, and the frequency division control unit outputs the frequency division display signal to turn on the lower-level GOA unit;

[0027] The frequency division control unit is connected to different clock signals, and controls the display of different areas by setting a specific clock signal with a high output potential. By matching the appropriate clock signal waveform and data signal waveform, the frequency division display of different parts can be realized.

[0028] A display panel includes a display area and a non-display area. The non-display area applies the gate drive circuit described in any one of the above items. When a driving method without frequency division display is used, the display panel displays at the same refresh frequency; when a driving method with frequency division display is used, the display refresh frequencies of different areas in the display panel are independent of each other.

[0029] Compared with the prior art, the present invention adds a frequency division control unit to the gate drive circuit of the display panel, and controls the refresh frequency of the gate drive signal output by the display area and the display area GOA unit through the frequency division control unit, so that the display panel operates at different refresh frequencies in different display areas separated by the frequency division control unit. When the frequency division control unit does not input the frequency division control signal, the gate drive signal of the upper-level GOA unit is normally input to the lower-level GOA unit, so that the entire display area operates at the same refresh frequency. The present invention realizes the display of different display areas at different refresh frequencies through level transmission control, reduces the power consumption of the display panel, and improves the market competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the structure of the display panel in Example 1.

[0031] Figure 2 Schematic diagram of the connection between the frequency division control unit and the GOA unit in Example 1.

[0032] Figure 3 Schematic diagram of the structure of the GOA unit in Example 1.

[0033] Figure 4 Schematic diagram of the connection between the frequency division control unit and the GOA unit in Example 1.

[0034] Figure 5 This is a schematic diagram of the signal waveform before the frequency division control unit in Example 1 works.

[0035] Figure 6 This is a schematic diagram of signal waveforms when the frequency division control unit in Example 1 is working.

[0036] Figure 7 Schematic diagram of the operation of the display panel in Example 2 with divided display frequencies of 60 Hz and 120 Hz.

[0037] Figure 8 Schematic diagram of the display panel operating at 60 Hz and 90 Hz frequency division display in Example 3. DETAILED DESCRIPTION

[0038] The gate driving circuit and driving method for realizing frequency division display of a panel according to the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0039] Example 1

[0040] See also Figure 1This embodiment provides a display panel capable of frequency-dividing display and its working method. The display panel includes a GOA driving circuit (gate driving circuit) and display areas ① to ④. The GOA driving circuit (gate driving circuit) includes multiple GOA units and frequency-dividing control units 1 to 3. The frequency-dividing control units 1 to 3 are respectively located at the intersection of the dividing lines of display areas ① to ④, and the frequency-dividing control units 1 to 3 are respectively used to control the activation of the GOA units corresponding to display areas ②-④.

[0041] See also Figure 2 The frequency division control unit is turned on by the frequency division control signal line outputting the frequency division control signal STVD. The frequency division display signal output by the frequency division control unit and the gate drive signal output by the upper-level GOA unit are simultaneously input into the lower-level GOA unit, wherein the frequency division control unit is used to turn on the lower-level GOA unit during frequency division display, and the upper-level GOA unit is used to turn on the lower-level GOA unit during normal display.

[0042] See also Figure 3 The GOA unit includes a pull-up unit, a pull-up control unit, a pull-down control unit, an inverter, a pull-down maintaining unit, a Reset unit, a common terminal Q(N), an upper gate drive signal G(N-1) input terminal, a lower gate drive signal G(N+1) input terminal, a gate drive signal G(N) output terminal, a clock signal CK(M) input terminal, a low potential signal VGL input terminal, a high potential signal VGH input terminal and a Reset signal input terminal. The upper gate drive signal G(N-1) input terminal is connected to the pull-up control unit, the lower gate drive signal G(N+1) input terminal is connected to the pull-down control unit, and the clock signal CK(M) input terminal is connected to the pull-up unit.

[0043] The Reset signal input end is connected to the Reset unit, the high potential signal VGH input end is connected to the inverter, the common end Q(N) is respectively connected to the pull-up unit, the pull-up control unit, the pull-down control unit, the inverter, the pull-down maintaining unit and the Reset unit, the gate drive signal G(N) output end is respectively connected to the pull-up unit, the pull-down maintaining unit and the Reset unit, the low potential signal VGL input end is respectively connected to the pull-down control unit, the inverter, the Reset unit and the pull-down maintaining unit, the pull-down control unit, the inverter and the Reset unit are respectively connected to the pull-up control unit, and the pull-down maintaining unit is respectively connected to the inverter and the Reset unit.

[0044] After the gate drive signal G(N-1) of the upper GOA unit is input into the GOA unit, the pull-up control unit pulls up the potential of the common end Q(N) and opens the pull-up unit, and then the square wave signal output by the clock signal CK(M) is input into the pull-up unit. The pull-up unit controls the gate drive signal G(N) output end to output a square wave signal for driving the panel display and the upper and lower level transmission. After the square wave signal is output by the gate drive signal G(N) output end, the gate drive signal G(N+1) of the lower GOA unit is input into the pull-down control unit, which pulls down the potential of the common end Q(N) and closes the pull-up unit. The inverter and the pull-down maintenance unit jointly act to maintain the common end Q(N) and the gate drive signal G(N) output end at a low potential during the non-level transmission. The reset unit is used to maintain the common end Q(N) and the gate drive signal G(N) output end at a low potential during the non-display period of each frame.

[0045] Please refer to Figure 4 The frequency division control unit comprises a frequency division control signal input end, an opening bit signal input end, a first thin film transistor T1, a level transmission control signal input end, n second thin film transistors T2(1) to T2(n), and n frequency division display signal output ends F(1) to F(n). The gate of the first thin film transistor T1 is connected with the frequency division control signal input end. The drain of the first thin film transistor T1 is connected with the opening bit signal input end. The source of the first thin film transistor T1 is connected with the level transmission control signal input end. The gates and drains of the n second thin film transistors T2(1) to T2(n) are respectively connected with the level transmission control signal input end.

[0046] The sources and drains of the n second thin film transistors T2(1) to T2(n) are connected to form a common end S1. The source of the second thin film transistor T2(i) is connected with the frequency division display signal output end F(i). The frequency division display signal output end F(i) is connected with the common end Q(i) of the i-th GOA unit after the frequency division control unit. n≥1, and i is a positive integer less than or equal to n. The number of clock signals connected to the GOA unit is even. The number of frequency division control units is less than or equal to the number of clock signals. The number of second thin film transistors T2 and frequency division display signal output ends is half of the number of clock signals.

[0047] The frequency division control signal input end is used to receive a frequency division control signal STVD. The opening bit signal input end is used to receive a specific clock signal CK(m). The first thin film transistor T1 and the second thin film transistors T2(1) to T2(n) are used to convert the received frequency division control signal and clock signal into a frequency division display signal. The frequency division display signal output end is used to output a frequency division display signal to start the lower GOA unit. The frequency division control units at different positions are connected with different clock signals to realize the control of different frequency division control units using different clock signals.

[0048] When the frequency division control signal STVD is at a low level, the low-level frequency division control signal STVD turns off the first thin film transistor T1, and the common terminal S1 is at a low level. The low-level common terminal S1 is connected to the gates of the second thin film transistors T2(1) to T2(n) and turns them off. When the frequency division control signal STVD is at a high level, the high-level frequency division control signal STVD turns on the first thin film transistor T1. The high-level clock signal pulls up the potential of the common terminal S1 through the first thin film transistor T1, and the high-level common terminal S1 turns on the second thin film transistors T2(1) to T2(n).

[0049] When the first thin-film transistor T1 of the frequency division control unit receives a high-level input signal of the frequency division control signal STVD, the source and drain of the first thin-film transistor T1 are turned on, and the common terminal S1 is connected to the clock signal CK(m) through the first thin-film transistor T1. When the clock signal CK(m) is at a low level, the common terminal S1 is at a low level, the gate and drain of the second thin-film transistor T2(i) are connected to the low-level common terminal S1, the source and drain of the second thin-film transistor T2(i) are not turned on, and the frequency division display signal output terminal F(i) is at a low level. When the clock signal CK(m) is set to a high level, the common terminal S1 is at a high level, the gate and drain of the second thin-film transistor T2(i) are connected to the high-level common terminal S1, the source and drain of the second thin-film transistor T2(i) are turned on, and the frequency division display signal output terminal F(i) outputs a high-level signal.

[0050] When the frequency division control signal STVD and the clock signal CK(m) output high-voltage signals at the same time, the frequency division display signal output terminal F(i) outputs a high-voltage signal to the Q(k+i) point of the connected GOA unit, and the connected GOA unit outputs a gate drive signal G(k+i), where k is a positive integer less than or equal to the number of GOA units.

[0051] When the gate drive circuit normally transmits power to the GOA unit connected to the frequency division control unit, the second thin-film transistor T2(i) is a diode structure with the gate and drain connected, and thus conducts unidirectionally. Therefore, fluctuations in the potential at the common terminal Q(N+i) of the GOA unit will not affect the frequency division control unit. The clock signal CK(m) input to the frequency division control unit and the clock signal CK(M) input to the GOA unit connected to the frequency division control unit are different clock signals, thereby preventing the connected GOA unit from prematurely outputting the gate drive signal G(N) during the operation of the frequency division control unit.

[0052] In this embodiment, when the display area is normally displayed, the circuit is normally transmitted, and the frequency division control signal STVD is low during the display period. Figure 5The figure shows the time-dependent changes in the potentials of the frequency division control signal STVD, the common terminal S1 in the frequency division control unit and the common terminal Q(N) of the GOA unit connected thereto, and the gate drive signal G(N). When the gate drive signal is transmitted to the GOA unit connected to the frequency division control unit, the frequency division control signal STVD always maintains a low potential; the first thin-film transistor T1 and the second thin-film transistor T2(i) are both in the off state, and the common terminal S1 maintains a low potential.

[0053] The potential of the common terminal Q(k+1) of the k+1th level GOA unit has two rising and two falling sections. The first rising section is driven by the gate drive signal of the upper level GOA unit. The second rising section and the first falling section come from the capacitive coupling effect of the rising and falling potential of the connected clock signal CK(m). The second falling section is pulled down by the gate drive signal of the lower level GOA unit. The high potential common terminal Q(k+1) turns on the pull-up unit of the GOA unit, and the gate drive signal G(k+1) is connected to the clock signal CK(m) through the pull-up unit and outputs Figure 5 Square wave signal; similarly, the potential change of the gate drive signal G(k+2)~G(k+n) is Figure 5 The square wave signal shown in FIG. 4 is a square wave signal, and the time difference between the rising edges of adjacent gate driving signals G(k+1) to G(k+n) is equal.

[0054] When the display area operates in a frequency division display mode: all clock signals CK(m) remain at a low level after the upper GOA unit of the frequency division control unit outputs a gate drive signal, and then the Reset signal outputs a high level signal to clear the charge of the common terminal Q(N) and the gate drive signal G(N) in all GOA units; after the Reset signal potential drops to a low level, the frequency division control signal STVD outputs a high level signal to turn on the first thin film transistor T1 in the frequency division control unit, and the corresponding frequency division control unit can be turned on by controlling different clock signals CK(m) to output high level signals; by setting the waveforms of the clock signal and data signal, it is possible to control different areas to operate at different refresh frequencies.

[0055] Figure 5The Reset signal outputs a high-potential signal to clear the waveform changes of the common terminal Q(k) and the gate drive signal G(k) in the k-th level GOA unit. The gate drive signal output by the k-1-th level GOA unit pulls the potential of the common terminal Q(k) higher. The clock signal CK(m) connected to the k-th level GOA unit pulls the voltage of the common terminal Q(k) higher for the second time through the capacitive coupling effect. At the same time, the gate drive signal G(k) is pulled higher through the pull-up unit of the GOA unit. After the potential of the clock signal CK(m) drops, the potential of the common terminal Q(k) is pulled lower by the clock signal CK(m) for the first time due to the capacitive coupling effect. The gate drive signal G(k) is pulled lower to the low potential of the clock signal CK(m) through the pull-up unit. When the potential of the Reset signal rises, the potential of the common terminal Q(k) is reduced to the low potential of the low potential signal through the Reset unit.

[0056] Figure 6 The figure shows the potential changes of each signal when the frequency division control unit is working. The frequency division control signal STVD and the clock signal CK(m) simultaneously output high-potential signals to the frequency division control unit. The frequency division control unit outputs high-potential signals to the frequency division display signal output terminals F(1) to F(n). The common terminals Q(k+1) to Q(k+n) of the k+1 to k+n-th GOA units are pulled to a high potential by being connected to the frequency division display signal output terminals F(1) to F(n). The clock signals CK(m+1) to CK(m+n) are connected to the k+1 to k+n-th GOA units respectively. The clock signals CK(m+1) to CK(m+n) sequentially output high-potential signals of the same width.

[0057] The gate drive signals G(k+1)~G(k+n) are connected to the clock signals CK(m+1)~CK(m+n) through the pull-up unit, and the gate drive signals G(k+1)~G(k+n) sequentially output high-potential signals with the same width as the high-potential signal width of the clock signal. Figure 6 Only the potential changes of the common terminals Q(k+1) and Q(k+2), the clock signals CK(m+1) and CK(m+2), and the gate drive signals G(k+1) and G(k+2) are reflected in the figure. The common terminals Q(N), the connected clock signals CK(M) and the gate drive signals G(N) of the k+3th to k+nth level GOA units are similar to the examples and are not described here.

[0058] Example 2

[0059] Based on the first embodiment, this embodiment provides a working mode of displaying at a refresh rate of 60 Hz and 120 Hz. The structure of the display panel is the same as that of the first embodiment. Figure 1The display panel shown has a similar structure, including three groups of frequency division control units 1 to 3, a frequency division control signal STVD and four clock signals CK(1) to CK(4), wherein the clock signals CK(1) to CK(3) are connected to the frequency division control units 1 to 3 respectively, the lower-level GOA unit of the frequency division control unit 1 is connected to the clock signal CK(2), the lower-level GOA unit of the frequency division control unit 2 is connected to the clock signal CK(3), and the lower-level GOA unit of the frequency division control unit 3 is connected to the clock signal CK(4).

[0060] Figure 7 The working sequence of the GOA units corresponding to display areas ① to ④ and the timing settings of some signal lines are shown. During the first frame display at 120 Hz, display areas ①, ③, and ④ are turned on in sequence. During the display period of display area ①, the width of the high-potential signal output by the clock signals CK(1) to CK(4) and the gate drive signal G(N) output by the GOA unit corresponding to display area ① match the refresh frequency of 60 Hz. During the display period of display areas ③ and ④, the width of the high-potential signal output by the clock signals CK(1) to CK(4) and the gate drive signal G(N) output by the GOA unit corresponding to display areas ③ and ④ match the refresh frequency of 120 Hz. After the display is completed, the blanking period at the end of the frame begins.

[0061] During the 120Hz display time of the second frame, display areas ②, ③, and ④ are turned on in sequence. During the display period of display area ②, the width of the high-potential signal output by the clock signals CK(1) to CK(4) and the gate drive signal G(N) output by the GOA unit corresponding to display area ② matches the refresh frequency of 60Hz. During the display period of display areas ③ and ④, the width of the high-potential signal output by the clock signals CK(1) to CK(4) and the gate drive signal G(N) output by the GOA unit corresponding to display areas ③ and ④ matches the refresh frequency of 120Hz. After the display ends, the blanking period at the end of the frame begins.

[0062] During the first frame of 120Hz display, after the display area ① finishes working, the Reset signal, the frequency division control signal STVD and the clock signal CK(2) are output as in Example 1. Figures 5 and 6 The same signal as in Example 1 clears the residual charge in the GOA unit and turns on the GOA unit corresponding to the display area ③. The reset signal clears the residual charge in the GOA unit during the blanking period at the end of the first frame. At the initial stage of the second frame 120Hz display, the frequency division control signal STVD and the clock signal CK (1) are output as in Example 1. Figure 6The same signal as in Example 1 turns on the GOA unit corresponding to display area ②. During the second frame 120Hz display time, after display area ② finishes working, the Reset signal, frequency division control signal STVD and clock signal CK(2) are output as in Example 1. Figures 5 and 6 The same signal in the display area ③ clears the residual charge in the GOA unit and turns on the GOA unit corresponding to the display area ③.

[0063] Example 3

[0064] This embodiment provides an operating mode for a display panel. This operating mode uses the same circuit structure as in Embodiment 2 to achieve display at refresh rates of 60 Hz and 90 Hz in different areas of the display panel. In this embodiment, display areas 1 and 2 of the display panel operate at a refresh rate of 90 Hz, and display areas 3 and 4 operate at a refresh rate of 60 Hz. Frequency division display in different display areas is achieved by setting the signal output of the frequency division control signal STVD and clock signals CK(1) to CK(4) in Embodiment 2.

[0065] Figure 8 The sequence of signal refresh times for different display areas in Example 3 is shown. In the first frame time calculated at 60Hz display, display areas ①, ③, ②, ④, and ① sequentially refresh the display signal, followed by a blanking period for non-display signal input. In the second frame time calculated at 60Hz display, display areas ②, ③, ①, ④, and ② sequentially refresh the display signal, followed by a blanking period for non-display signal input.

[0066] Using the 60Hz display frame time as a reference, set the signal refresh time for display areas ① and ② to 1 / 15 of the reference time, and the signal refresh time for display areas ③ and ④ to 1 / 10 of the reference time. With this signal refresh time setting, the signal refresh frequencies for display areas ① through ④ are identical to the normal display refresh rates of 60Hz and 90Hz, respectively.

[0067] In summary, the present invention adds a frequency division control unit to the gate drive circuit of the display panel, and controls the refresh frequency of the gate drive signal output by the display area and the display area GOA unit through the frequency division control unit, so that the display panel operates at different refresh frequencies in different display areas separated by the frequency division control unit. When the frequency division control unit does not input the frequency division control signal, the gate drive signal of the upper-level GOA unit is normally input to the lower-level GOA unit, so that the entire display area operates at the same refresh frequency. The present invention realizes the display of different display areas at different refresh frequencies through level transmission control, reduces the power consumption of the display panel, and improves the market competitiveness of the product.

[0068] The above description is a detailed description of the preferred embodiments of the present invention, but the embodiments are not intended to limit the scope of the patent application of the present invention. Any equivalent changes or modifications made under the technical spirit disclosed by the present invention should fall within the patent scope covered by the present invention.

Claims

1. A gate drive circuit for realizing frequency division display of a panel, characterized in that: It includes multiple cascaded GOA units and multiple frequency division control units evenly distributed between the GOA units. Multiple clock signals are respectively connected to the multiple GOA units. The frequency division control unit is connected to the upper-level GOA unit and the lower-level GOA unit. The upper-level GOA unit is used to turn on the lower-level GOA unit during normal display, and the frequency division control unit is used to turn on the lower-level GOA unit during frequency division display. The GOA unit includes a pull-up unit, a pull-up control unit, a pull-down control unit, an inverter, a pull-down maintaining unit, a Reset unit, a common terminal Q, a gate drive signal output terminal, a clock signal input terminal and a Reset signal input terminal, the clock signal input terminal is connected to the pull-up unit, the Reset signal input terminal is connected to the Reset unit, the pull-up unit is used to control the gate drive signal output terminal to output a square wave signal to drive display and upper and lower stage transmission, the inverter and the pull-down maintaining unit are used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during the non-stage transmission period, the pull-up control unit is used to pull the common terminal Q potential high and turn on the pull-up unit, the pull-down control unit is used to pull the common terminal Q potential low and turn off the pull-up unit, and the Reset unit is used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during the non-display period; Multiple frequency division control units are turned on by frequency division control signals. By setting a specific clock signal, the turned-on frequency division control unit drives the lower-level GOA unit connected to it. The gate drive signal output by the upper-level GOA unit and the frequency division display signal output by the frequency division control unit are simultaneously input into the lower-level GOA unit to drive the frequency division display; The frequency division control unit includes a frequency division control signal input terminal, an opening position signal input terminal, a first thin film transistor T1, a level transfer control signal input terminal, n second thin film transistors T2(1) to T2(n) and n frequency division display signal output terminals F(1) to F(n), wherein the opening position signal input terminal is used to receive a specific clock signal CK(m); The gate of the first thin film transistor T1 is connected to the frequency division control signal input terminal, the drain of the first thin film transistor T1 is connected to the open bit signal input terminal, the source of the first thin film transistor T1 is connected to the level transfer control signal input terminal, and the gates and drains of the n second thin film transistors T2(1) to T2(n) are respectively connected to the level transfer control signal input terminal; The source and drain electrodes of n second thin film transistors T2(1) to T2(n) are connected to form a common terminal S1, the source electrode of the second thin film transistor T2(i) is connected to the frequency division display signal output terminal F(i), and the frequency division display signal output terminal F(i) is connected to the common terminal Q(i) of the i-th level GOA unit after the frequency division control unit, where n≥1, and i is a positive integer less than or equal to n.

2. The gate driving circuit for realizing panel frequency division display according to claim 1, characterized in that: The GOA unit further includes an upper gate drive signal input terminal, a lower gate drive signal input terminal, a low potential signal input terminal, and a high potential signal input terminal, wherein the upper gate drive signal input terminal is connected to the pull-up control unit, the lower gate drive signal input terminal is connected to the pull-down control unit, and the high potential signal input terminal is connected to the inverter; The common end Q is respectively connected to the pull-up unit, the pull-up control unit, the pull-down control unit, the inverter, the pull-down maintaining unit and the Reset unit, the gate drive signal output end is respectively connected to the pull-up unit, the pull-down maintaining unit and the Reset unit, the low potential signal input end is respectively connected to the pull-down control unit, the inverter, the Reset unit and the pull-down maintaining unit, the pull-down control unit, the inverter and the Reset unit are respectively connected to the pull-up control unit, and the pull-down maintaining unit is respectively connected to the inverter and the Reset unit.

3. The gate driving circuit for realizing panel frequency division display according to claim 1, characterized in that: The frequency division control signal input end is used to receive the frequency division control signal STVD, and the frequency division display signal output end is used to output the frequency division display signal to start the lower-level GOA unit. The frequency division control units at different positions are connected to different clock signals to realize the use of different clock signals to control the operation of different frequency division control units.

4. The gate driving circuit for realizing panel frequency division display according to claim 3, characterized in that: When the frequency division control signal STVD is at a low level, the low-level frequency division control signal STVD turns off the first thin film transistor T1, and the common terminal S1 is at a low level. The low-level common terminal S1 is connected to the gates of the second thin film transistors T2(1) to T2(n) and turns them off. When the frequency division control signal STVD is at a high level, the high-level frequency division control signal STVD turns on the first thin film transistor T1, and the high-level clock signal pulls up the potential of the common terminal S1 through the first thin film transistor T1, and the high-level common terminal S1 turns on the second thin film transistors T2(1) to T2(n).

5. The gate driving circuit for realizing panel frequency division display according to claim 1, characterized in that: The number of clock signals connected to the GOA unit is an even number, the number of frequency division control units is less than or equal to the number of clock signals, and the number of second thin film transistors T2(1)~T2(n) and frequency division display signal output terminals is half the number of clock signals.

6. A driving method for realizing panel frequency division display, applied to the gate driving circuit for realizing panel frequency division display according to any one of claims 1 to 4, characterized in that: include: Before outputting the frequency division control signal, the clock signals CK(1) to CK(2n) become low potential after the upper level GOA unit of the frequency division control unit ends displaying. After the clock signal drops to low potential, the Reset signal becomes high potential. The high potential Reset signal turns on the Reset units of all GOA units, and the Reset units of the GOA units drop the gate drive signal of the GOA units and the potential of the common terminal Q point to low potential. After that, the Reset signal becomes a low level. After the Reset signal becomes a low level, the frequency division control signal outputs a high level signal. By setting the specific clock signal CK(m) to a high level, the corresponding frequency division control unit is turned on. The turned-on frequency division control unit drives the lower-level GOA unit connected to it, and sets the display frequency of the corresponding panel by setting the clock signal and data signal.

7. The driving method for realizing panel frequency division display according to claim 6, characterized in that: When no frequency division is performed, it includes: The frequency division control signal STVD is at a low potential, the control signal input terminal of the frequency division control unit inputs a low potential to the gate of the first thin film transistor T1, the first thin film transistor T1 is in a closed state, the common terminal S1 connected to the gate of the second thin film transistors T2(1)~T2(n) is at a low potential, the second thin film transistors T2(1)~T2(n) are closed, the frequency division display signal output terminal has no output signal, all GOA units of the gate drive circuit are normally transmitted, and the display area is displayed at the same frequency.

8. The driving method for realizing panel frequency division display according to claim 6, characterized in that: When frequency division is used, it includes: After the upper GOA unit of the frequency division control unit outputs the gate drive signal, all clock signals CK(1) to CK(2n) output low potential, and the Reset signal outputs high potential, pulling down the common terminal Q and the gate drive signal output terminal potential in the GOA unit; After the Reset signal changes from high potential to low potential, the frequency division control signal STVD and the specific clock signal CK(m) output high potential to the frequency division control unit, and the frequency division control unit outputs the frequency division display signal to turn on the lower-level GOA unit; The frequency division control unit is connected to different clock signals, and controls the display of different areas by setting a specific clock signal with a high output potential. By matching the appropriate clock signal waveform and data signal waveform, the frequency division display of different parts can be realized.

9. A display panel comprising a display area and a non-display area, characterized in that: The gate drive circuit described in any one of claims 1 to 5 is applied to the non-display area. When the driving method described in claim 7 is used, the display panel displays at the same refresh frequency; when the driving method described in claim 8 is used, the display refresh frequencies of different areas in the display panel are independent of each other.

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