Display device and electronic device

Abstract

A display device and an electronic device are disclosed. The display device includes: a power management circuit that generates a display driving voltage; the display driving circuit receives the display driving voltage; and a display panel for displaying an image. The power management circuit includes: a conversion circuit that converts an input voltage into a display driving voltage and outputs the display driving voltage through an output terminal; a load sensing circuit connected to the conversion circuit to sense a load current of the output terminal and output a sensing result signal; a resistance division circuit connected to the feedback terminal to receive a feedback voltage, and controlling a level of the feedback voltage in response to a feedback control signal; and a control circuit controlling an operation of the conversion circuit by providing a feedback control signal to the resistance division circuit based on the sensing result signal.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device and an electronic device, and more particularly, to a display device and an electronic device having a function for compensating for power loss. Background Art

[0002] An emission display device among various types of display devices displays an image by using a light emitting diode that generates light through recombination of electrons and holes. The emission display device generally has a fast response speed and is driven with low power consumption.

[0003] The emissive display device may include pixels connected to data lines and scan lines. Each of the pixels generally includes a light-emitting element and a pixel circuit unit (or pixel drive circuit) for controlling the amount of current flowing through the light-emitting element. In response to a data signal, the pixel circuit unit controls the amount of current flowing from a first drive voltage to a second drive voltage via a light-emitting diode. In this case, light with a specific brightness is generated corresponding to the amount of current flowing through the light-emitting element. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device and an electronic device for stably supplying power by compensating for power loss.

[0005] According to an embodiment of the present disclosure, a display device includes: a power management circuit receiving an input voltage to generate a display driving voltage; a display driving circuit receiving the display driving voltage to output a panel control signal; and a display panel receiving the panel control signal to display an image.

[0006] In such an embodiment, the power management circuit includes: a conversion circuit, which converts an input voltage into a display driving voltage and outputs the display driving voltage through an output terminal; a load sensing circuit, which is connected to the conversion circuit, wherein the load sensing circuit senses a load current of the output terminal and outputs a sensing result signal; a resistance division circuit, which is connected to the feedback terminal to receive a feedback voltage, wherein the resistance division circuit controls the level of the feedback voltage in response to a feedback control signal; and a control circuit, which controls the operation of the conversion circuit by providing a feedback control signal to the resistance division circuit based on the sensing result signal.

[0007] According to an embodiment of the present disclosure, a display device includes: a power management circuit receiving an input voltage to generate a display driving voltage; a display driving circuit receiving the display driving voltage and outputting a panel control signal; and a display panel receiving the panel control signal to display an image.

[0008] In such an embodiment, the power management circuit includes: a conversion circuit, which converts an input voltage into a display driving voltage in response to a pulse width modulation signal generated based on conversion information, and outputs the display driving voltage through an output terminal; a load sensing circuit, which is connected to the conversion circuit, wherein the load sensing circuit senses a load current of the output terminal and outputs a sensing result signal; and a control circuit, which provides the pulse width modulation signal to the conversion circuit and changes the conversion information based on the sensing result signal.

[0009] According to an embodiment of the present disclosure, the electronic device includes: a power management circuit, which receives an input voltage to generate a display drive voltage; a display drive circuit, which receives the display drive voltage and an image signal and outputs a panel control signal; a display panel, which receives the panel control signal to display an image; and a main processor, which provides the image signal to the display drive circuit.

[0010] In such an embodiment, the power management circuit includes: a conversion circuit, which converts an input voltage into a display driving voltage and outputs the display driving voltage through an output terminal; a load sensing circuit, which is connected to the conversion circuit, wherein the load sensing circuit senses a load current of the output terminal and outputs a sensing result signal; a resistance division circuit, which is connected to the feedback terminal to receive a feedback voltage, wherein the resistance division circuit controls the level of the feedback voltage in response to a feedback control signal; and a control circuit, which controls the operation of the conversion circuit by providing a feedback control signal to the resistance division circuit based on the sensing result signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of embodiments of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 2A is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0014] Figure 2B is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0015] Figure 3A is a plan view illustrating a display module and an electronic module according to an embodiment of the present disclosure.

[0016] Figure 3B It is a graphic Figure 3A 00140 - 00141 - 00142 - 00143 ...

[0017] Figure 4A is a plan view illustrating a display module and an electronic module according to an embodiment of the present disclosure.

[0018] Figure 4B It is a graphic Figure 4A 00140 - 00141 - 00142 - 00143 ...

[0019] Figure 5 is a block diagram of a load sensing circuit according to an embodiment of the present disclosure.

[0020] Figure 6 It is a graphic Figure 5 Graph showing the waveforms of the input and output signals of the median generation circuit shown in FIG.

[0021] Figure 7 It is a graphic Figure 5 Waveform diagram of the input signal and output signal of the multiplier circuit shown in FIG.

[0022] Figure 8 It is a graphic Figure 3B Schematic diagram of the resistance dividing circuit shown in FIG.

[0023] Fig. 9 is a block diagram illustrating a power management circuit and a display driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The present invention will now be more fully described with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0025] In the specification, the expression that a first component (or region, layer, portion, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is interposed therebetween.

[0026] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportion, and size of components may be exaggerated to effectively describe the technical features.

[0027] Although the terms "first," "second," etc. may be used to describe various components, these components should not be construed as being limited by these terms. These terms are only used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope and spirit of the present invention.

[0028] In addition, the terms "below", "at the lower part", "above", and "at the upper part" are used to describe the relationship between the components illustrated in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0029] The terms used in this article are only used to describe the purpose of specific embodiments, and are not intended to be limited. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and unless the context clearly indicates otherwise, it is intended to include both singular and plural. Therefore, the reference to "one" element in the claim (followed by the reference to "the (described)" element) includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used in this article, the term "and / or" includes any combination and all combinations of one or more related listed items. It will be further understood that the term "includes", "comprising" or "having" or its variants indicate the existence of stated features, quantities, steps, operations, parts, parts or combinations thereof, but does not exclude the existence or addition of one or more other features, quantities, steps, operations, parts, parts and / or combinations thereof.

[0030] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0031] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0032] In this article, embodiments are described with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the zones as illustrated herein, but will include deviations in shapes, for example, caused by manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. Moreover, the illustrated sharp corners may be rounded. Therefore, the zones illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones and are not intended to limit the scope of the invention.

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0035] Reference Figure 1 According to an embodiment of the present disclosure, the electronic device ED may have a rectangular shape having a shorter side parallel to the first direction DR1 and a longer side parallel to the second direction DR2 crossing the first direction DR1. However, the embodiment is not limited thereto, and the electronic device ED may have various shapes such as a circle or other polygons.

[0036] The electronic device ED may be a device activated in response to an electrical signal. The electronic device ED may include various types of devices. For example, the electronic device ED may be an electronic device including a display screen such as a smart phone, a smart watch, a computer (e.g., a personal computer (PC) such as a tablet or a laptop), a smart television (TV), or a navigation device.

[0037] Hereinafter, a direction substantially orthogonal to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 may be a thickness direction of the electronic device ED. In the specification, the meaning of "when viewed in a plan view" may refer to "when viewed in the third direction DR3".

[0038] A top surface of the electronic device ED may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the electronic device ED may be provided to a user through the display surface IS.

[0039] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area for displaying an image IM. A user observes the image IM through the transmission area TA. According to an embodiment, the transmission area TA may have a rectangular shape with rounded vertices. However, this shape is provided for illustrative purposes. In an embodiment, for example, the transmission area TA may have various shapes and is not limited to any one embodiment.

[0040] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a specific color. The border area BZA may surround the transmission area TA. Accordingly, the shape of the transmission area TA may be substantially defined by the border area BZA. However, the above-mentioned shape of the border area BZA is provided by way of example. In an embodiment, for example, the border area BZA may be disposed adjacent to only one side of the transmission area TA, or may be omitted.

[0041] The electronic device ED may detect an external input applied from the outside. The external input may include various types of input provided outside the electronic device ED. In an embodiment, for example, in addition to a touch of a part of the user's body such as a hand US_F or a touch by an additional device (e.g., an active pen or a digitizer), the external input may include an external input (e.g., a hovering input) applied when the user's hand approaches the electronic device ED or is close to the electronic device ED within a given distance. In addition, the external input may be of various types such as force, pressure, temperature, and light.

[0042] The electronic device ED may sense biometric information of a user applied from the outside. The display surface IS of the electronic device ED may have a biometric information sensing area for sensing biometric information of the user. The biometric information sensing area may be provided with respect to the entire area of ​​the transmission area TA or a partial area of ​​the transmission area TA.

[0043] Figure 2A is an exploded perspective view of an electronic device according to an embodiment of the present disclosure, and Figure 2B is a cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0044] Reference Figure 2A and Figure 2B , an embodiment of the electronic device ED may include a display device DD, an electronic module and a housing EDC. The display device DD may include a window WM and a display module DM, and may be disposed (received or accommodated) in the housing EDC. According to an embodiment, the window WM is coupled to the housing EDC to form the appearance of the electronic device ED.

[0045] The front surface of the window WM may define the display surface IS of the electronic device ED. The window WM may include an optically transparent insulating material. In an embodiment, for example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. In an embodiment, for example, the window WM may include a plurality of plastic films coupled to each other by an adhesive, or may include a glass substrate and a plastic film coupled to each other by an adhesive.

[0046] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image in response to an electrical signal (or by receiving a panel control signal), and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0047] According to an embodiment of the present disclosure, the display panel DP may be an emissive display panel, and the present disclosure is not limited thereto. In an embodiment, for example, the display panel DP may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, for ease of description, an embodiment in which the display panel DP is an organic light-emitting display panel will be described in detail, but is not limited thereto.

[0048] Reference Figure 2B In an embodiment, the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. In an embodiment, for example, the display panel DP may be a foldable display panel or a rigid display panel folded about a folding axis.

[0049] In an embodiment, the base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and the material of the polyimide-based resin layer is not particularly limited. In an embodiment, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0050] The circuit layer DP_CL is provided (arranged or formed) on the base layer BL. The circuit layer DP_CL is inserted between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL may be referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for identifying external information. The external information may be biometric information. According to an embodiment of the present disclosure, each of the sensors may include a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood measurement sensor, or an illumination sensor. In addition, each of the sensors may be an optical sensor for optically recognizing biometric information. The circuit layer DP_CL may further include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0051] The element layer DP_ED may include a light emitting element included in each pixel and a light receiving element included in each of the sensors. According to an embodiment of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor for sensing light reflected by a user's fingerprint or responding to light.

[0052] The encapsulation layer TFE encapsulates the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material for protecting the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but the present disclosure is not limited thereto. The organic layer may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0053] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to an embodiment of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a subsequent process. In other words, when the input sensing layer ISL is directly disposed on the display panel DP, the adhesive film is not interposed between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, the adhesive film may be interposed between the input sensing layer ISL and the display panel DP. In such an embodiment, the input sensing layer ISL and the display panel DP are not manufactured by a continuous process. In other words, after the input sensing layer ISL is manufactured by a process separate from the process of the display panel DP, the input sensing layer ISL may be fixed on the top surface of the display panel DP by an adhesive film.

[0054] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the sensed input into a specific input signal, and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense a capacitive type external input. The display panel DP may receive an input signal from the input sensing layer ISL, and may generate an image corresponding to the input signal.

[0055] The display module DM may further include a color filter layer CFL. According to an embodiment of the present disclosure, the color filter layer CFL may be disposed on the input sensing layer ISL. However, the present disclosure is not limited thereto. In an embodiment, for example, the color filter layer CFL may be interposed between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include a black matrix and a plurality of color filters.

[0056] According to an embodiment of the present disclosure, the display device DD may further include an adhesive layer AL. The window WM may be attached to the color filter layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure sensitive adhesive (PSA).

[0057] In an embodiment, Figure 2A As shown in , the display module DM may further include a display drive circuit DIC (or a display drive chip), a flexible circuit film FCB, a touch drive circuit TIC (or a touch drive chip) and a readout circuit ROIC (or a readout chip). According to an embodiment of the present disclosure, the display drive circuit DIC, the touch drive circuit TIC and the readout circuit ROIC may be provided in the form of a chip and may be mounted on the flexible circuit film FCB. However, the present disclosure is not limited thereto. Alternatively, the display drive circuit DIC may be provided on the display panel DP. The display drive circuit DIC may include a data drive circuit for providing a data signal to the display panel DP. Alternatively, the display drive circuit DIC may further include a drive control circuit for controlling the drive of the data drive circuit. In other words, the display drive circuit DIC may have the form of an integrated chip in which the data drive circuit and the drive control circuit are integrated.

[0058] The flexible circuit film FCB may be coupled to the display panel DP. The flexible circuit film FCB may be coupled to one end of the display panel DP to electrically connect the display driving circuit DIC to the display panel DP. The flexible circuit film FCB may electrically connect the touch driving circuit TIC to the input sensing layer ISL and electrically connect the readout circuit ROIC to the display panel DP.

[0059] although Figure 2AThe embodiment having a structure in which the touch driving circuit TIC and the readout circuit ROIC are separately provided is illustrated, but the present disclosure is not limited thereto. In the embodiment, for example, the touch driving circuit TIC and the readout circuit ROIC may be integrated in the form of one chip.

[0060] The electronic module may include a main circuit board MCB. According to an embodiment of the present disclosure, the main circuit board MCB may be electrically connected to the flexible circuit film FCB through a connector CNT. The electronic module may further include a main processor MCU and a power management circuit PMIC (or a power management chip). The main processor MCU and the power management circuit PMIC may be mounted on the main circuit board MCB. The main processor MCU and the power management circuit PMIC may be electrically connected to the display drive circuit DIC through a connector CNT.

[0061] The main processor MCU may control the overall operation of the electronic device ED. The main processor MCU may include at least one of a central processing unit (CPU) and an application processor (AP). The main processor MCU may include at least one selected from a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor MCU may provide an image signal for displaying an image and various control signals to the display driving circuit DIC.

[0062] The power management circuit PMIC may receive an external supply voltage (e.g., a battery voltage). In an embodiment, for example, the power management circuit PMIC may generate a voltage to be supplied to the display device DD based on the external supply voltage. The power management circuit PMIC may include at least one regulator. The at least one regulator may generate an output voltage having various voltage levels based on the external supply voltage.

[0063] although Figure 2A The embodiment having a structure in which the power management circuit PMIC is provided in the form of a chip mounted on the main circuit board MCB is illustrated, but the present disclosure is not limited thereto. In the embodiment, for example, the power management circuit PMIC may be provided as a component included in the display device DD such as a component mounted on a flexible circuit film FCB in the form of a chip.

[0064] In addition to the main circuit board MCB, the main processor MCU and the power management circuit PMIC, the electronic module may further include various functional modules such as a camera module or a sensor module.

[0065] The housing EDC is connected to the window WM. The housing EDC is connected to the window WM to provide a specific internal space. The display device DD and the electronic module can be accommodated in the internal space of the housing EDC. The housing EDC may include a material with relatively high rigidity. In an embodiment, for example, the housing EDC may include a plurality of frames and / or plates including glass, plastic or metal or a combination thereof. The housing EDC can stably protect the display device DD and the components of the electronic module accommodated in the internal space from external impacts.

[0066] Although not shown, a battery module for supplying an external supply voltage for overall operations of the display device DD may be interposed between the display module DM and the case EDC.

[0067] Figure 3A is a plan view of a display module and an electronic module according to an embodiment of the present disclosure, and Figure 3B It is a graphic Figure 3A 00140 - 00141 - 00142 - 00143 ...

[0068] Reference Figure 3A In an embodiment, the display panel DP includes a display area DA and a non-display area NDA. The display area DA is an area in which an image is substantially displayed, and the non-display area NDA is an area in which an image is not displayed. The display area DA may be aligned with the transmission area TA (see FIG. 1 ) of the electronic device ED. Figure 1 ), and the non-display area NDA may correspond to the frame area BZA (see Figure 1 According to an embodiment of the present disclosure, the non-display area NDA surrounds the display area DA.

[0069] The display panel DP includes a plurality of pixels PX disposed in a display area DA. The plurality of pixels PX are disposed in the entire portion of the display area DA. The display panel DP may further include a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, and a plurality of emission lines EL1 to ELm. In this case, "m" and "n" are natural numbers greater than 0. The pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm.

[0070] The scan lines SL1 to SLm may extend in the first direction DR1 and may be connected to the scan driving circuit. The light emitting lines EL1 to ELm may extend in the first direction DR1 and may be connected to the light emitting driving circuit. The scan driving circuit and the light emitting driving circuit may be provided in the non-display area NDA of the display panel DP by the same process as that for the pixel PX.

[0071] The data lines DL1 to DLn may extend in the second direction DR2 and may be electrically connected to the display driving circuit DIC. The display panel DP may further include power lines for supplying various driving voltages to the pixels PX.

[0072] Reference Figure 3B In an embodiment, the power management circuit PMIC may include a conversion circuit VCC, a load sensing circuit LSC, a resistance division circuit RDC, and a control circuit PCC. The control circuit PCC may be electrically connected to the conversion circuit VCC, the load sensing circuit LSC, and the resistance division circuit RDC.

[0073] The power management circuit PMIC may output a driving voltage VDD (or a display driving voltage) to be supplied to the display driving circuit DIC through the output terminal OT. The conversion circuit VCC may be connected to the output terminal OT of the power management circuit PMIC. The conversion circuit VCC includes a first switching transistor ST1 and a second switching transistor ST2. The first switching transistor ST1 and the second switching transistor ST2 may be transistors of different types from each other. In an embodiment, for example, the first switching transistor ST1 may be a P-type transistor, and the second switching transistor ST2 may be an N-type transistor. The conversion circuit VCC may convert the input voltage VIN into a driving voltage VDD, and output the driving voltage VDD through the output terminal OT.

[0074] The first switch transistor ST1 is connected between an input terminal receiving an input voltage VIN and a first node N1, and receives a pulse width modulation signal from a control circuit PCC. The second switch transistor ST2 is connected between the first node N1 and a ground terminal, and receives a pulse width modulation signal from a control circuit PCC. In response to the pulse width modulation signal, the first switch transistor ST1 and the second switch transistor ST2 may be alternately turned on. In an embodiment, for example, during an on-duty period of the pulse width modulation signal, the first switch transistor ST1 may be turned off, and the second switch transistor ST2 may be turned on. In such an embodiment, during an off-duty period of the pulse width modulation signal, the first switch transistor ST1 may be turned on, and the second switch transistor ST2 may be turned off.

[0075] The control circuit PCC may include a pulse width modulation circuit. The control circuit PCC may generate a pulse width modulation signal through the pulse width modulation circuit. The pulse width modulation signal includes a working period and a non-working period, and the control circuit PCC may control the level of the drive voltage VDD output from the conversion circuit VCC by adjusting the proportion of the period of the pulse width modulation signal occupied by the working period (i.e., the duty cycle).

[0076] The first node N1 of the conversion circuit VCC may be connected to the output terminal OT. The inductor L and the output capacitor C_OUT may be further connected to the output terminal OT of the power management circuit PMIC. The inductor L is connected between the output terminal OT and the second node N2, and the output capacitor C_OUT is connected between the second node N2 and the ground terminal.

[0077] In an embodiment, when the first switching transistor ST1 is turned on and the second switching transistor ST2 is turned off, charges may be stored in the output capacitor C_OUT while current is supplied to the inductor L. In such an embodiment, when the first switching transistor ST1 is turned off and the second switching transistor ST2 is turned on, current based on the charges stored in the output capacitor C_OUT may be output to the input terminal IT of the display driving circuit DIC. Therefore, the display driving circuit DIC may receive a driving voltage VDD corresponding to the current to output a panel control signal.

[0078] Connect the main circuit board MCB (see Figure 3A ) and flexible circuit film FCB (see Figure 3A ) can electrically connect the output terminal OT of the power management circuit PMIC to the input terminal IT of the display driving circuit DIC. The connector CNT may include a voltage pin for supplying the driving voltage VDD output from the power management circuit PMIC to the display driving circuit DIC. The voltage pin of the connector CNT may be connected between the output terminal OT of the power management circuit PMIC and the input terminal IT of the display driving circuit DIC. Therefore, the driving voltage VDD output from the output terminal OT of the power management circuit PMIC can be supplied to the input terminal IT of the display driving circuit DIC through the voltage pin of the connector CNT. In an embodiment, the parasitic capacitor C_VDD may be connected to the input terminal IT of the display driving circuit DIC.

[0079] The driving voltage VDD input through the input terminal IT of the display driving circuit DIC may be used as an oscillator voltage for operating the oscillator OSC or a logic voltage for controlling driving of the logic Lg in the display driving circuit DIC.

[0080] The load sensing circuit LSC can be connected to the conversion circuit VCC to sense the load current of the output terminal OT, and can generate a sensing result signal SRS by processing the load current. The sensing result signal SRS generated from the load sensing circuit LSC can be applied to the control circuit PCC. According to an embodiment of the present disclosure, the load sensing circuit LSC can be connected to the first node N1. However, the present disclosure is not limited thereto. In an embodiment, the load sensing circuit LSC can be directly connected to the output terminal OT.

[0081] The control circuit PCC may generate a feedback control signal FCS based on the sensing result signal SRS received from the load sensing circuit LSC, and may control the operation of the conversion circuit VCC by providing the feedback control signal FCS to the resistance dividing circuit RDC. The resistance dividing circuit RDC may control the level of the feedback voltage Vf in response to the feedback control signal FCS.

[0082] According to an embodiment of the present disclosure, the second node N2 may be electrically connected to a feedback terminal FT of the power management circuit PMIC. The resistance division circuit RDC may be connected to the feedback terminal FT. The power management circuit PMIC may receive feedback (ie, feedback voltage Vf) about the driving voltage VDD through the feedback terminal FT.

[0083] According to an embodiment of the present disclosure, the resistance division circuit RDC includes a first resistor R1, a second resistor R2, and a plurality of adjustment resistors (e.g., a first adjustment resistor Rc1 to an Nth adjustment resistor RcN). The first resistor R1 is connected between the feedback terminal FT and the division node N3, and the second resistor R2 is connected between the division node N3 and the ground terminal. The adjustment resistors Rc1 to RcN are connected in parallel to the first resistor R1. In this case, "N" is a natural number equal to or greater than 1.

[0084] According to an embodiment of the present disclosure, the first resistor R1 and the second resistor R2 may have resistances equal to each other, and each of the adjustment resistors Rc1 to RcN may have a resistance smaller than that of the first resistor R1 and the second resistor R2. In an embodiment, for example, each of the adjustment resistors Rc1 to RcN may have a resistance equal to 1 / 10 of the resistance of the first resistor R1 and the second resistor R2.

[0085] The resistance dividing circuit RDC may further include a switch control circuit SCC connected to the adjustment resistors Rc1 to RcN. The switch control circuit SCC may receive a feedback control signal FCS from the control circuit PCC and adjust the number of adjustment resistors Rc1 to RcN connected to the first resistor R1 in response to the feedback control signal FCS. Figure 8 The switch control circuit SCC is described in more detail.

[0086] The level of the actual feedback voltage A_Vf fed back to the control circuit PCC may vary depending on the number of adjustment resistors Rc1 to RcN connected to the first resistor R1 .

[0087] The control circuit PCC can adjust the number of adjustment resistors Rc1 to RcN connected in parallel with the first resistor R1 based on the load current, and thus control the degree of boosting of the driving voltage VDD by changing the level of the actual feedback voltage A_Vf. Accordingly, considering the reduction in the voltage level of the driving voltage VDD due to the wiring resistance (i.e., IR drop or voltage drop) in the process of supplying the driving voltage VDD to the display driving circuit DIC, the power management circuit PMIC can stably supply the driving voltage VDD having a desired level to the display driving circuit DIC by outputting the boosted driving voltage VDD.

[0088] Figure 4A is a plan view of a display module and an electronic module according to an embodiment of the present disclosure, and Figure 4B It is a graphic Figure 4A A block diagram of a power management circuit and a display driver circuit is shown in FIG. Figure 4A and Figure 4B In the Figure 3A and Figure 3B The same components as those illustrated in FIG. 1 are described below, and any repeated detailed description thereof will be omitted.

[0089] Reference Figure 4A and Figure 4B , the display module DM_1 according to an embodiment of the present disclosure may include a power management circuit PMIC_1. In an embodiment, the power management circuit PMIC_1 may be mounted on a flexible circuit film FCB_1 in the form of a chip. In an embodiment, the power management circuit PMIC_1 may be included in a component of the display device DD.

[0090] In an embodiment where the power management circuit PMIC_1 is mounted on the flexible circuit film FCB_1 together with the display driving circuit DIC, the connector CNT may not be provided between the power management circuit PMIC_1 and the display driving circuit DIC. Accordingly, a voltage pin for providing the driving voltage VDD output from the power management circuit PMIC_1 to the display driving circuit DIC may be omitted from the connector CNT, and accordingly, the total number of pins provided in the connector CNT may be reduced.

[0091] The signal line is inserted between the output terminal OT of the power management circuit PMIC_1 and the input terminal IT of the display driving circuit DIC to connect the output terminal OT of the power management circuit PMIC_1 to the input terminal IT of the display driving circuit DIC. In the process of supplying the driving voltage VDD output from the power management circuit PMIC_1 to the display driving circuit DIC, an IR drop may be caused (or occur) due to the signal line.

[0092] In such an embodiment, the control circuit PCC can adjust the number of adjustment resistors Rc1 to RcN connected in parallel with the first resistor R1 based on the load current, and thus control the degree of boosting of the driving voltage VDD by changing the level of the actual feedback voltage A_Vf. In other words, considering the reduction in the voltage level of the driving voltage VDD due to IR drop in the process of supplying the driving voltage VDD to the display driving circuit DIC, the power management circuit PMIC_1 can stably supply the driving voltage VDD having a desired level to the display driving circuit DIC by outputting the boosted driving voltage VDD.

[0093] Figure 5 is a block diagram of a load sensing circuit according to an embodiment of the present disclosure. Figure 6 It is a graphic Figure 5 The waveform diagram of the input signal and the output signal of the median generation circuit shown in FIG. Figure 7 It is a graphic Figure 5 Waveform diagram of the input signal and output signal of the multiplier circuit shown in FIG.

[0094] Reference Figure 5 and Figure 6 , in an embodiment, the load sensing circuit LSC includes a median generating circuit MGC and a multiplier circuit MC.

[0095] The median generation circuit MGC receives the load current LDC of the first node N1 and outputs the median of the load current LDC as the median load current MLC. The first node N1 outputs the first load current LDC1 during the first period SP in which the first switching transistor ST1 is turned on, and outputs the second load current LDC2 during the second period SN in which the second switching transistor ST2 is turned on. The median load current MLC may correspond to the median of the first load current LDC1 and the second load current LDC2.

[0096] Reference Figure 5 and Figure 7, the multiplier circuit MC can receive the median load current MLC from the median generation circuit MGC, and can receive the pulse width modulation signal from the control circuit PCC. In other words, the multiplier circuit MC can output the final load current FLC by reflecting the duty cycle of the pulse width modulation signal to the median load current MLC. Accordingly, the final load current FLC can have a low level during the first period SP and a high level during the second period SN. The duty cycle of the final load current FLC can be defined as the proportion of the period of the final load current FLC occupied by the second period SN, and can be determined by the duty cycle of the pulse width modulation signal. Alternatively, the final load current FLC can have a high level during the first period SP and a low level during the second period SN. In this case, the duty cycle of the final load current FLC can be defined as the proportion of the period of the final load current FLC occupied by the first period SP.

[0097] According to an embodiment of the present disclosure, the load sensing circuit LSC may provide the final load current FLC as a sensing result signal SRS to the control circuit PCC.

[0098] The control circuit PCC may adjust the number of adjustment resistors Rc1 to RcN based on the amplitude of the final load current FLC. In an embodiment, for example, when the amplitude of the final load current FLC during the second period SN is about 50 milliamperes (mA) or less, the control circuit PCC may set the number of adjustment resistors Rc1 to RcN to one. In such an embodiment, when the amplitude of the final load current FLC during the second period SN is about 50 mA or more and about 100 mA or less, the control circuit PCC may set the number of adjustment resistors Rc1 to RcN to two, and when the amplitude of the final load current FLC during the second period SN is about 100 mA or more and about 150 mA or less, the control circuit PCC may set the number of adjustment resistors Rc1 to RcN to three.

[0099] The correspondence between the amplitude of the final load current FLC and the number of adjustment resistors Rc1 to RcN can be stored in a lookup table, and the control circuit PCC can control the number of adjustment resistors Rc1 to RcN connected to the first resistor R1 by referring to the lookup table corresponding to the amplitude of the final load current FLC.

[0100] Figure 8 It is a graphic Figure 3B Schematic diagram of the resistance dividing circuit shown in FIG.

[0101] Reference Figure 8In an embodiment, the resistance division circuit RDC includes a first resistor R1, a second resistor R2, and a plurality of adjustment resistors Rc1 to RcN (e.g., a first adjustment resistor Rc1 to an Nth adjustment resistor RcN). The first resistor R1 is connected between the feedback terminal FT and the division node N3, and the second resistor R2 is connected between the division node N3 and the ground terminal. The adjustment resistors Rc1 to RcN are connected in parallel to the first resistor R1. In this case, "N" is a natural number equal to or greater than 1.

[0102] The resistance dividing circuit RDC may further include a switch control circuit SCC connected to the adjustment resistors Rc1 to RcN. The switch control circuit SCC includes a plurality of switch elements SW1 to SWN (or first to Nth switch elements SW1 to SWN) connected to the adjustment resistors Rc1 to RcN, respectively, to switch the connection between the adjustment resistors Rc1 to RcN and the division node N3 in response to feedback control signals FCS1 to FCSN (or first to Nth feedback control signals FCSN).

[0103] Control circuit PCC (see Figure 3B ) can control the activation state of each of the feedback control signals FCS1 to FCSN in response to the sensing result signal SRS to determine the number of adjustment resistors Rc1 to RcN connected in parallel with the first resistor R1. The feedback control signals FCS1 to FCSN can be applied to the plurality of switch elements SW1 to SWN, respectively. In an embodiment, for example, when only the first switch element SW1 is turned on in response to the first feedback control signal FCS1, and the remaining switch elements SW2 to SWN can be turned off in response to the second feedback control signal FCS2 to the Nth feedback control signal FCSN, only one adjustment resistor (e.g., the first adjustment resistor Rc1) among the adjustment resistors Rc1 to RcN is connected in parallel to the first resistor R1. When only the first switching element SW1 and the second switching element SW2 are turned on in response to the first feedback control signal FCS1 and the second feedback control signal FCS2, respectively, and the remaining switching elements SW3 to SWN can be turned off in response to the third feedback control signal FCS3 to the Nth feedback control signal FCSN, only two of the adjustment resistors Rc1 to RcN (for example, the first adjustment resistor Rc1 and the second adjustment resistor Rc2) are connected in parallel to the first resistor R1.

[0104] When the number of adjustment resistors Rc1 to RcN connected to the first resistor R1 increases, the level at which the actual feedback voltage A_Vf is lower than the feedback voltage Vf may decrease. In other words, as the final load current FLC increases and the number of adjustment resistors Rc1 to RcN connected in parallel to the first resistor R1 increases, the level at which the actual feedback voltage A_Vf is lower than the feedback voltage Vf may decrease. When the actual feedback voltage A_Vf is reduced, the control circuit PCC may perform a compensation operation to boost the drive voltage VDD by the reduced level of the actual feedback voltage A_Vf.

[0105] In an embodiment, for example, when the final load current FLC is sensed to be about 50mA and the wiring resistance is about 1 ohm (Ω), the drive voltage VDD can be expected to be reduced by about 50 millivolts (mV). In this case, when an adjustment resistor (e.g., a first adjustment resistor Rc1) is connected in parallel to the first resistor R1, the actual feedback voltage A_Vf is about 0.95V, which can be reduced by about 50mV from the feedback voltage Vf of about 1V. In this case, since the actual feedback voltage A_Vf is reduced by about 50mV from the feedback voltage Vf of about 1V, the control circuit PCC can control the duty cycle of the pulse width modulation signal to output the drive voltage VDD boosted by about 50mV.

[0106] In an embodiment, for example, when the final load current FLC is sensed to be about 100mA and the wiring resistance is about 1Ω, the drive voltage VDD can be expected to be reduced by about 100mV. In this case, when two adjustment resistors (e.g., the first adjustment resistor Rc1 and the second adjustment resistor Rc2) are connected in parallel to the first resistor R1, the actual feedback voltage A_Vf can be about 0.9V, which is about 100mV lower than the feedback voltage Vf of about 1V. Since the actual feedback voltage A_Vf is reduced by about 100mV from the feedback voltage Vf of about 1V, the control circuit PCC can control the duty cycle of the pulse width modulation signal to output the drive voltage VDD boosted by about 100mV.

[0107] In such an embodiment, by adjusting the number of adjustment resistors Rc1 to RcN connected in parallel with the first resistor R1 based on the sensed load current, the driving voltage VDD can be effectively prevented from being reduced by the wiring resistance (i.e., IR drop). Accordingly, the power management circuit PMIC can supply the driving voltage VDD stably maintained at a constant level to the display driving circuit DIC.

[0108] Fig. 9 is a block diagram illustrating a power management circuit and a display driving circuit according to an embodiment of the present disclosure. Fig. 9 In the Figure 3BThe same components as those illustrated in FIG. 1 are described below, and any repeated detailed description thereof will be omitted.

[0109] Reference Fig. 9 In an embodiment, the power management circuit PMIC_2 may include a conversion circuit VCC, a load sensing circuit LSC, a resistance division circuit RDC_a, and a control circuit PCC_a. The control circuit PCC_a may be electrically connected to the conversion circuit VCC, the load sensing circuit LSC, and the resistance division circuit RDC_a.

[0110] The control circuit PCC_a may include a pulse width modulation circuit PWMC and an offset control circuit OCC. The pulse width modulation circuit PWMC may generate a pulse width modulation signal based on the conversion information. In an embodiment, for example, the conversion information may be a digital signal. When the conversion information is a 5-bit signal, the duty cycle of the pulse width modulation signal may be represented as 32 5-bit signals. The pulse width modulation circuit PWMC may generate a pulse width modulation signal having a duty cycle corresponding to the conversion information.

[0111] In the embodiment, for example, it can be assumed that a pulse width modulation signal with a duty cycle of 64% is generated based on a signal of "00000", and a driving voltage VDD of 1V is generated based on the pulse width modulation signal with a duty cycle of 64%. When the signal of "00000" is input to the pulse width modulation circuit PWMC as conversion information, a pulse width modulation signal with a duty cycle of 64% is output, and the conversion circuit VCC can output a driving voltage VDD of 1V in response to the pulse width modulation signal.

[0112] When the final load current FLC is sensed as approximately 50mA and the wiring resistance is approximately 1Ω, an IR drop of approximately 50mV may be caused in the drive voltage VDD. In this case, in order to compensate for the IR drop of the drive voltage VDD, the offset control circuit OCC may receive the final load current FLC and change the conversion information based on the final load current FLC. In an embodiment, for example, a signal of "00000" may be converted into a signal of "00001" based on the final load current FLC. Accordingly, the pulse width modulation circuit PWMC may output a pulse width modulation signal having a duty cycle corresponding to the signal of "00001", and accordingly, the conversion circuit VCC may output a drive voltage VDD of approximately 1.05V.

[0113] In such an embodiment, when the final load current FLC is sensed as approximately 100mA and the wiring resistance is approximately 1Ω, an IR drop of approximately 100mV may be caused in the drive voltage VDD. In this case, the offset control circuit OCC may convert a signal of "00000" into a signal of "00010" based on the final load current FLC to compensate for the IR drop of the drive voltage VDD. Accordingly, the pulse width modulation circuit PWMC may output a pulse width modulation signal having a duty cycle corresponding to the signal of "00010", and accordingly, the conversion circuit VCC may output a drive voltage VDD of approximately 1.1V.

[0114] According to an embodiment of the present disclosure, the second node N2 may be electrically connected to a feedback terminal FT of the power management circuit PMIC_2. The resistance division circuit RDC_a may be connected to the feedback terminal FT. The power management circuit PMIC_2 may receive feedback (ie, feedback voltage Vf) regarding the driving voltage VDD through the feedback terminal FT.

[0115] According to an embodiment of the present disclosure, the resistance division circuit RDC_a includes a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the feedback terminal FT and the division node N3, and the second resistor R2 is connected between the division node N3 and the ground terminal. According to an embodiment of the present disclosure, the first resistor R1 and the second resistor R2 may have equal resistance to each other.

[0116] In such an embodiment, when the offset control circuit OCC is provided in the control circuit PCC_a, the level of the drive voltage VDD can be changed by directly changing the conversion information based on the final load current FLC. Figure 3B The configuration of the adjustment resistors Rc1 to RcN and the switch control circuit SCC shown in FIG. Fig. 9 It is omitted in the resistance dividing circuit RDC_a shown in the figure.

[0117] According to an embodiment of the present disclosure, the power management circuit can change the level of the actual feedback voltage actually fed back to the power management circuit by sensing the load current at the output terminal by the load sensing circuit and adjusting the number of adjustment resistors connected in parallel to the first resistor depending on the load current.

[0118] Accordingly, the degree of boosting of the driving voltage can be controlled depending on the load current reflected by the wiring resistance, so that in the process of supplying the driving voltage to the display driving circuit, even if the voltage level is reduced due to the wiring resistance, the power management circuit will supply the driving voltage with the desired voltage level to the display driving circuit.

[0119] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the concept of the present invention to those skilled in the art.

[0120] While the present invention has been described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes and modifications in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: A power management circuit receives an input voltage to generate a display driving voltage; A display driving circuit receives the display driving voltage to output a panel control signal; as well as A display panel receives the panel control signal to display an image, Wherein, the power management circuit includes: a conversion circuit, which converts the input voltage into the display driving voltage and outputs the display driving voltage through an output terminal; a load sensing circuit, which is connected to the conversion circuit, wherein the load sensing circuit senses the load current of the output terminal and outputs a sensing result signal; a resistance division circuit, which is connected to a feedback terminal to receive a feedback voltage, wherein the resistance division circuit controls the level of the feedback voltage in response to a feedback control signal; and a control circuit, which controls the operation of the conversion circuit by providing the feedback control signal to the resistance division circuit based on the sensing result signal.

2. The display device according to claim 1, wherein: The conversion circuit comprises: A first switch transistor connected between an input terminal receiving the input voltage and a first node; and a second switch transistor connected between the first node and a ground terminal, wherein the first node is connected to the output terminal, and The load sensing circuit is connected to the first node to sense the load current.

3. The display device according to claim 2, further comprising: an inductor connected between the output terminal and the second node; as well as an output capacitor connected between the second node and the ground terminal, Wherein, the feedback terminal is connected to the second node.

4. The display device according to claim 2, wherein: The first switching transistor and the second switching transistor are transistors of different types from each other, and The first switching transistor and the second switching transistor receive a pulse width modulation signal from the control circuit, and are alternately turned on in response to the pulse width modulation signal.

5. The display device according to claim 4, wherein: The load sensing circuit comprises: a median generating circuit that outputs a median value of a first load current during a first period in which the first switching transistor is turned on and a second load current during a second period in which the second switching transistor is turned on as a median load current; and A multiplier circuit receives the median load current and the pulse width modulation signal, and outputs a final load current generated by reflecting a duty ratio of the pulse width modulation signal to the median load current as the sensing result signal.

6. The display device according to claim 1, wherein: The resistance dividing circuit comprises: a first resistor connected between the feedback terminal and a division node; a second resistor connected between the division node and a ground terminal; and A plurality of adjustment resistors are connected in parallel to the first resistor.

7. The display device according to claim 6, wherein: The first resistor and the second resistor have resistances equal to each other, and wherein each of the adjustment resistors has a resistance smaller than the resistance of the first resistor and the second resistor.

8. The display device according to claim 6, wherein: The resistance dividing circuit further includes a switch control circuit including a plurality of switch elements respectively connected to the plurality of adjustment resistors and performing a switching operation for connection between the plurality of adjustment resistors and the dividing node in response to the feedback control signal.

9. The display device according to claim 8, wherein: The feedback control signal includes: A plurality of feedback control signals are applied to the plurality of switch elements, respectively, and The control circuit determines the number of the adjustment resistors connected in parallel to the first resistor by controlling an activation state of each of the feedback control signals in response to the sensing result signal.

10. A display device, comprising: A power management circuit receives an input voltage to generate a display driving voltage; A display driving circuit receives the display driving voltage and outputs a panel control signal; as well as A display panel receives the panel control signal to display an image, Wherein, the power management circuit includes: a conversion circuit, which converts the input voltage into the display drive voltage in response to a pulse width modulation signal generated based on conversion information, and outputs the display drive voltage through an output terminal; a load sensing circuit, connected to the conversion circuit, wherein the load sensing circuit senses the load current of the output terminal and outputs a sensing result signal; and a control circuit, which provides the pulse width modulation signal to the conversion circuit and changes the conversion information based on the sensing result signal.

11. The display device according to claim 10, wherein: The conversion circuit comprises: A first switch transistor connected between an input terminal receiving the input voltage and a first node; and a second switch transistor connected between the first node and a ground terminal, wherein the first node is connected to the output terminal, and The load sensing circuit is connected to the first node to sense the load current.

12. The display device according to claim 11, wherein: The first switching transistor and the second switching transistor are transistors of different types from each other, and The first switching transistor and the second switching transistor receive the pulse width modulation signal from the control circuit, and are alternately turned on in response to the pulse width modulation signal.

13. The display device according to claim 12, wherein: The load sensing circuit comprises: a median generating circuit that outputs a median value of a first load current during a first period in which the first switching transistor is turned on and a second load current during a second period in which the second switching transistor is turned on as a median load current; and A multiplier circuit receives the median load current and the pulse width modulation signal, and outputs a final load current generated by reflecting a duty ratio of the pulse width modulation signal to the median load current as the sensing result signal.

14. The display device according to claim 11, wherein: The power management circuit further comprises: a resistance dividing circuit connected to a feedback terminal receiving a feedback voltage, and The resistance dividing circuit includes: a first resistor connected between the feedback terminal and a dividing node; and a second resistor connected between the dividing node and the ground terminal.

15. The display device according to claim 14, further comprising: an inductor connected between the output terminal and the second node; as well as an output capacitor connected between the second node and the ground terminal, and Wherein, the feedback terminal is connected to the second node.

16. The display device according to any one of claims 10 to 12, 14 and 15, wherein: The control circuit comprises: a pulse width modulation circuit, controlling a duty cycle of the pulse width modulation signal based on the conversion information; and The offset control circuit receives the sensing result signal and changes the conversion information based on the sensing result signal.

17. An electronic device comprising: A power management circuit receives an input voltage to generate a display driving voltage; A display driving circuit receives the display driving voltage and the image signal and outputs a panel control signal; A display panel, receiving the panel control signal to display an image; as well as A main processor provides the image signal to the display driving circuit, Wherein, the power management circuit includes: a conversion circuit, which converts the input voltage into the display driving voltage and outputs the display driving voltage through an output terminal; a load sensing circuit, which is connected to the conversion circuit, wherein the load sensing circuit senses the load current of the output terminal and outputs a sensing result signal; a resistance division circuit, which is connected to a feedback terminal to receive a feedback voltage, wherein the resistance division circuit controls the level of the feedback voltage in response to a feedback control signal; and a control circuit, which controls the operation of the conversion circuit by providing the feedback control signal to the resistance division circuit based on the sensing result signal.

18. The electronic device according to claim 17, further comprising: a first circuit board on which the main processor and the power management circuit are mounted; a second circuit board on which the display driving circuit is mounted; as well as A connector is connected to the first circuit board and the second circuit board.

19. The electronic device according to claim 18, wherein: The connector comprises: A voltage pin is connected between the output terminal of the power management circuit and the input terminal of the display driving circuit.

20. The electronic device according to any one of claims 17 to 19, wherein: The resistance dividing circuit comprises: a first resistor connected between the feedback terminal and a division node; a second resistor connected between the division node and a ground terminal; and A plurality of adjustment resistors are connected in parallel to the first resistor.

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