Array substrate and display panel

Abstract

The application provides an array substrate and a display panel, and realizes the purpose that the actual size of a driving transistor and the actual area of a capacitor meet design requirements. The array substrate comprises a substrate semiconductor layer and a plurality of conductive layers, the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate; the plurality of conductive layers comprise a pixel circuit and a plurality of signal lines, the pixel circuit comprises a driving transistor and a first transistor, and the plurality of signal lines comprise a power signal line and a first power connection line arranged in different layers; the first electrode of the first transistor is connected with the first electrode of the driving transistor, and the second electrode of the first transistor is electrically connected with the power signal line through the first power connection line; the power signal line extends along a first direction parallel to the substrate, the first power connection line extends along a second direction parallel to the substrate, and the second direction intersects with the first direction; in the first direction, the driving transistor and the first power connection line are respectively located on the two sides of the first transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] In recent years, organic light-emitting display panels have gradually become mainstream products in the display field, and are widely used in mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range.

[0003] However, in the array substrate of the current display panel, the actual size of the driving transistor and the actual area of the capacitor cannot meet the design requirements. SUMMARY

[0004] In order to solve the above technical problems, the present application is proposed. The array substrate and the display panel provided by the embodiments of the present application achieve the purpose that the actual size of the driving transistor and the actual area of the capacitor meet the design requirements.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, which comprises a substrate, a semiconductor layer and a plurality of conductive layers. The semiconductor layer is located on one side of the substrate, and the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate. The plurality of conductive layers comprise a pixel circuit and a plurality of signal lines. The pixel circuit comprises a driving transistor and a first transistor. The plurality of signal lines comprise a power signal line and a first power connection line arranged in different layers. The first electrode of the first transistor is connected to the first electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the power signal line through the first power connection line. The power signal line extends along a first direction parallel to the substrate, the first power connection line extends along a second direction parallel to the substrate, and the second direction intersects the first direction. In the first direction, the driving transistor and the first power connection line are respectively located on the two sides of the first transistor.

[0006] In combination with the first aspect, in some implementations of the first aspect, the first electrode of the first transistor is connected to the first electrode of the driving transistor through a first conductive via, and the orthographic projection of the first conductive via on the substrate and the orthographic projection of the semiconductor layer on the substrate overlap. Preferably, the active part of the driving transistor is located in the semiconductor layer, and the active part has a symmetry axis in the first direction. Preferably, the distance between the orthographic projection of the control electrode of the driving transistor on the substrate and the orthographic projection of the first conductive via on the substrate is greater than or equal to 0.9 microns.

[0007] In combination with the first aspect, in some implementations of the first aspect, the second electrode of the first transistor is connected to the first power connection line through a second conductive via, the first power connection line is connected to the power signal line through a third conductive via, and the second conductive via and the third conductive via are arranged along the second direction.

[0008] Preferably, the second electrode comprises a source electrode and the first electrode comprises a drain electrode.

[0009] Preferably, the second direction is perpendicular to the first direction.

[0010] With reference to the first aspect, in some implementations of the first aspect, the plurality of signal lines further comprise a cross-connection line, and the pixel circuit further comprises a second transistor, a first electrode of the second transistor being electrically connected to the first electrode of the first transistor through the cross-connection line.

[0011] Preferably, the cross-connection line and the first power connection line are located in the same conductive layer.

[0012] Preferably, the first electrode of the second transistor is connected to the cross-connection line through a fourth conductive via.

[0013] Preferably, the plurality of signal lines further comprise a reference voltage signal line, and the reference voltage signal line is connected to a second electrode of the second transistor.

[0014] With reference to the first aspect, in some implementations of the first aspect, the plurality of signal lines further comprise a second power connection line, and the pixel circuit further comprises a capacitor, a first plate of the capacitor sharing the control electrode of the driving transistor, and a second plate of the capacitor being connected to the second power connection line, the second power connection line being connected to the power signal line.

[0015] Preferably, the second plate and the second power connection line are located in different layers, and the second plate is connected to the second power connection line through a fifth conductive via and a sixth conductive via.

[0016] Preferably, in the first direction, the second power connection line and the first power connection line are respectively located on two sides of the first transistor.

[0017] Preferably, the second power connection line extends along the second direction.

[0018] With reference to the first aspect, in some implementations of the first aspect, the second power connection line and the first power connection line are located in the same conductive layer.

[0019] Preferably, the first power connection line and the second power connection line are arranged at intervals in the same conductive layer.

[0020] With reference to the first aspect, in some implementations of the first aspect, the plurality of signal lines further comprise a data signal line, and a projection of the data signal line on the substrate substrate and a projection of the first power connection line and the second power connection line on the substrate substrate at least partially overlap.

[0021] In some embodiments of the first aspect, the semiconductor layer and the plurality of conductive layers comprise a plurality of pixel circuits, the plurality of pixel circuits are arranged along a second direction, and at least one of the first power connection line and the second power connection line is located between adjacent pixel circuits in the second direction. Preferably, at least one of the first power connection line and the second power connection line has an axis of symmetry in the first direction. Preferably, at least one of the first power connection line and the second power connection line connects the second electrodes of the capacitors in adjacent pixel circuits.

[0022] In some embodiments of the first aspect, the same second power connection line connects the second electrodes of the capacitors in adjacent pixel circuits, and / or the same first power connection line connects the second electrodes of the first transistors in adjacent pixel circuits. Preferably, the pixel circuit comprises an 8T1C pixel circuit.

[0023] In a second aspect, an embodiment of the present application provides a display panel, comprising the array substrate provided in any of the above embodiments.

[0024] The array substrate provided by the embodiments of the present application comprises a substrate, a semiconductor layer and a plurality of conductive layers. The semiconductor layer is located on one side of the substrate, and the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate. The plurality of conductive layers comprise pixel circuits and a plurality of signal lines. The pixel circuit comprises a driving transistor and a first transistor. The plurality of signal lines comprise a power signal line and a first power connection line arranged in different layers. The first electrode of the first transistor is connected to the first electrode of the driving transistor, the second electrode of the first transistor is connected to the first power connection line, and the first power connection line is connected to the power signal line. The power signal line extends along a first direction parallel to the substrate, the first power connection line extends along a second direction parallel to the substrate, and the second direction intersects the first direction. In the first direction, the driving transistor and the first power connection line are respectively located on the two sides of the first transistor. The first power connection line is used to connect the power signal line and the second electrode of the first transistor. The driving transistor and the first power connection line are respectively located on the two sides of the first transistor, that is, the position of the first power connection line does not limit the spacing between the first electrode of the first transistor and the driving transistor. That is, the spacing between the first electrode of the first transistor and the driving transistor is large enough, so that the actual size of the driving transistor and the actual area of the capacitor can meet the design requirements. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description thereof taken in conjunction with the accompanying drawings, in which: The accompanying drawings provide a further understanding of the present application and constitute a part of this specification, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0026] Figure 1 A top view structural schematic diagram of an array substrate provided by the related art is shown.

[0027] Figure 2 A top view structural schematic diagram of an array substrate provided by the related art is shown. Figure 1 A zoomed-in structural schematic diagram of the A region is shown.

[0028] Figure 3 A top view structural schematic diagram of an array substrate provided by an embodiment of the present application is shown.

[0029] Figure 4 A top view structural schematic diagram of an array substrate provided by the related art is shown. Figure 3 A zoomed-in structural schematic diagram of the B region is shown.

[0030] Figure 5 A circuit schematic diagram of a pixel circuit provided by an embodiment of the present application is shown.

[0031] Figure 6 A top view structural schematic diagram of an array substrate provided by another embodiment of the present application is shown.

[0032] Figure 7 A top view structural schematic diagram of an array substrate provided by another embodiment of the present application is shown.

[0033] Figure 8 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown.

[0034] Reference signs: array substrate 100; pixel circuit 110; driving transistor DTFT; first transistor T1; second transistor T2; capacitor C; power supply signal line elvdd; first power supply connection line Line1; second power supply connection line Line2; cross-connection line Line3; reference voltage signal line Vref; data signal line Data; first direction F1; second direction F2; first conductive via K1; second conductive via K2; third conductive via K3; fourth conductive via K4; fifth conductive via K5; sixth conductive via K6; first connection line L1; active part a; display panel 10. DETAILED DESCRIPTION

[0035] Figure 1 A top view structural schematic diagram of an array substrate provided by the related art is shown. As shown in FIG. 1, the array substrate 100 includes a plurality of pixel circuits 110 arranged in a matrix form. Each pixel circuit 110 includes a driving transistor DTFT, a first transistor T1, a second transistor T2, and a capacitor C. Figure 1As shown in the array substrate 100 provided by the related art, in order to realize the connection between the power signal line elvdd and the second electrode (such as the source) of the first transistor T1, a first connection line L1 located in the third metal layer is usually used to connect the power signal line elvdd and the second electrode of the first transistor T1, and the first connection line L1 is vertically arranged. The first electrode (such as the drain) of the first transistor T1 is located between the control electrode (such as the gate) of the driving transistor DTFT and the first connection line L1, and the first connection line L1 and the first electrode of the first transistor T1 are both located in the third metal layer. In order to ensure the safe distance between different elements in the third metal layer, the first electrode of the first transistor T1 needs to be arranged close to the control electrode of the driving transistor DTFT. This results in a small distance between the first electrode of the first transistor T1 and the control electrode of the driving transistor DTFT, and further results in that the actual size of the control electrode of the driving transistor DTFT is smaller than the design requirement size, and the actual area of the capacitor C is smaller than the design requirement area, that is, the actual size of the driving transistor DTFT and the actual area of the capacitor C cannot meet the design requirements.

[0036] For example, the width design requirement of the driving transistor DTFT is 2.7 microns, the length design requirement of the driving transistor DTFT is 18 microns, and the area design requirement of the capacitor C is 67 square microns. In the array substrate 100 provided by the related art, the actual width of the driving transistor DTFT is 2.7 microns, the actual length of the driving transistor DTFT is 16 microns, and the actual area of the capacitor C is 58 square microns. Therefore, the actual size of the driving transistor DTFT and the actual area of the capacitor C cannot meet the design requirements.

[0037] Figure 2 As shown in the enlarged structure diagram of the local area in FIG. 1C. Figure 1 As shown in FIG. 1D, the driving transistor in the array substrate 100 provided by the related art is shown. Figure 2 As shown in FIG. 1D, the driving transistor in the array substrate 100 provided by the related art is shown. Figure 1 As shown in FIG. 1D, the driving transistor in the array substrate 100 provided by the related art is shown. Figure 2 As shown in FIG. 1D, the driving transistor in the array substrate 100 provided by the related art is shown.

[0038] To solve the above technical problems, the array substrate provided by the present application comprises a substrate substrate, a semiconductor layer and a plurality of conductive layers, the semiconductor layer is located on one side of the substrate substrate, and the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate substrate; wherein the plurality of conductive layers comprise a pixel circuit and a plurality of signal lines, the pixel circuit comprises a driving transistor and a first transistor, and the plurality of signal lines comprise a power supply signal line and a first power supply connection line arranged in different layers; the first electrode of the first transistor is connected to the first electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the power supply signal line through the first power supply connection line; the power supply signal line extends along a first direction parallel to the substrate substrate, the first power supply connection line extends along a second direction parallel to the substrate substrate, and the second direction intersects the first direction; in the first direction, the driving transistor and the first power supply connection line are respectively located on the two sides of the first transistor. The present application realizes the connection of the power supply signal line and the second electrode of the first transistor through the first power supply connection line, and the driving transistor and the first power supply connection line are respectively located on the two sides of the first transistor, that is, the position of the first power supply connection line does not limit the spacing between the first electrode of the first transistor and the driving transistor, that is, the spacing between the first electrode of the first transistor and the driving transistor is large enough, so that the actual size of the driving transistor and the actual area of the capacitor can meet the design requirements.

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0040] In addition, in order to better illustrate the present application, a large number of specific details are given in the specific embodiments below. Those skilled in the art should understand that the present application can also be implemented without certain specific details. In some examples, methods and means familiar to those skilled in the art are not described in detail in order to highlight the main idea of the present application.

[0041] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0042] In addition, if the terms "first", "second" and the like are used, they are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0043] Figure 3 The top view structural schematic diagram of the array substrate provided by an embodiment of the present application is shown. As shown in the figure, the array substrate comprises a substrate substrate 1, a semiconductor layer 2 and a plurality of conductive layers 3, the semiconductor layer 2 is located on one side of the substrate substrate 1, and the plurality of conductive layers 3 are stacked on the side of the semiconductor layer 2 away from the substrate substrate 1. Figure 3As shown, the embodiment of the present application provides an array substrate 100, the array substrate 100 comprises a substrate, a semiconductor layer and a plurality of conductive layers, the semiconductor layer is located on one side of the substrate, and the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate; wherein the semiconductor layer and the plurality of conductive layers comprise a pixel circuit 110 and a plurality of signal lines, the pixel circuit 110 comprises a driving transistor DTFT and a first transistor T1, and the plurality of signal lines comprise a power signal line elvdd and a first power connection line Line1 which are arranged in different layers; a first electrode of the first transistor T1 is connected to a first electrode of the driving transistor DTFT, and a second electrode of the first transistor T1 is electrically connected to the power signal line elvdd through the first power connection line Line1; the power signal line elvdd extends along a first direction F1 parallel to the substrate, the first power connection line Line1 extends along a second direction F2 parallel to the substrate, and the second direction F2 intersects the first direction F1; in the first direction F1, the driving transistor DTFT and the first power connection line Line1 are respectively located on two sides of the first transistor T1.

[0044] In Figure 3 the first direction F1 refers to the vertical direction, and the second direction F2 refers to the horizontal direction.

[0045] In actual application, the connection between the power signal line elvdd and the second electrode of the first transistor T1 is realized through the first power connection line Line1, thereby canceling Figure 1 the first connection line L1 in the related art, and the driving transistor DTFT and the first power connection line Line1 are respectively located on two sides of the first transistor T1, that is, the position of the first power connection line Line1 does not limit the spacing between the first electrode of the first transistor T1 and the driving transistor DTFT, that is, the spacing between the first electrode of the first transistor T1 and the driving transistor DTFT is large enough, so that the actual size of the driving transistor DTFT and the actual area of the capacitance can meet the design requirements.

[0046] In one embodiment, the first electrode of the first transistor T1 is connected to the first electrode of the driving transistor DTFT through a first conductive via K1, and the orthographic projection of the first conductive via K1 on the substrate and the orthographic projection of the semiconductor layer on the substrate overlap. For example, the overlapping area of the orthographic projection of the first conductive via K1 on the substrate and the orthographic projection of the semiconductor layer on the substrate is greater than half of the area of the orthographic projection of the first conductive via K1. Since the first connection line L1 is canceled Figure 1 , there is enough space around the driving transistor DTFT to accommodate the first conductive via K1, without compressing the occupied space of the driving transistor DTFT, avoiding the distortion of the active part a of the driving transistor DTFT in the semiconductor layer.

[0047] Figure 4 As shown Figure 3 A magnified structural diagram of a local area. Figure 4 It shows Figure 3 The driving transistor DTFT and the first conductive via K1 are shown in the figure. Figure 4 As shown, the active portion a of the driving transistor DTFT is located in the semiconductor layer. The active portion a has a symmetry axis in the first direction F1, that is, the active portion a has a symmetrical structure, and the symmetry axis is parallel to the first direction F1. It can be seen that since the first conductive via K1 will not squeeze the driving transistor DTFT, the active portion a can be designed as a symmetrical structure, which is beneficial for mass production.

[0048] In one embodiment, such as Figure 4 As shown, the distance D between the orthographic projection of the control electrode of the driving transistor DTFT on the substrate and the orthographic projection of the first conductive via K1 on the substrate is greater than or equal to 0.9 micrometers. For example, the distance D can be 0.9 micrometers, 1 micrometer, 1.1 micrometers, etc. By setting the distance D to be greater than or equal to 0.9 micrometers, signal interference between the control electrode of the driving transistor DTFT and the first conductive via K1 can be reduced, thereby improving reliability.

[0049] Figure 5 The diagram shown is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 5 As shown, in some embodiments, the pixel circuit 110 includes an 8T1C pixel circuit, that is, the pixel circuit 110 provided in this application embodiment includes eight transistors and a storage capacitor. The eight transistors include a driving transistor DTFT, a first transistor T1 and a second transistor T2. Other transistors are not described in detail in this application.

[0050] The pixel circuit 110, composed of eight transistors and a storage capacitor, has the following advantages: First, it allows for more precise control over the brightness and color of each pixel, thereby achieving high resolution and detailed display; second, it provides more accurate color control, helping the display panel to present more accurate colors and improve color reproduction; third, through the rational design and control of the eight transistors and the storage capacitor, energy-saving effects can be achieved, reducing energy consumption and improving the energy efficiency of the display panel; fourth, it has a fast response speed, which helps reduce image ghosting and blurring in dynamic scenes; fifth, the pixel circuit 110 has a relatively simple and stable structure, is easy to integrate and control, and improves the reliability and stability of the display panel; sixth, compared with other complex pixel circuits, the 8T1C pixel circuit provided in this application embodiment has lower manufacturing and maintenance costs.

[0051] Figure 6 The diagram shown is a top view of an array substrate provided in another embodiment of this application.Figure 6 As shown in the array substrate 100 provided by the embodiment of the present application, the second electrode of the first transistor T1 is connected with the first power connection line Line1 through the second conductive via K2, and the first power connection line Line1 is connected with the power signal line elvdd through the third conductive via K3. The second conductive via K2 and the third conductive via K3 are arranged along the second direction F2.

[0052] The embodiment of the present application realizes the connection between the power signal line elvdd and the second electrode of the first transistor T1 through the first power connection line Line1, the second conductive via K2 and the third conductive via K3. Figure 6 In the embodiment, the second conductive via K2 and the third conductive via K3 are arranged along the transverse direction, and the second conductive via K2 is located at the right side of the third conductive via K3.

[0053] Preferably, the second electrode comprises a source electrode, and the first electrode comprises a drain electrode.

[0054] Preferably, the second direction F2 is perpendicular to the first direction F1.

[0055] In one embodiment, as shown in Figure 6 As shown in the array substrate 100 provided by the embodiment of the present application, the plurality of signal lines further comprise a bridging connection line Line3, and the pixel circuit 110 further comprises a second transistor T2. The first electrode of the second transistor T2 is electrically connected with the first electrode of the first transistor T1 through the bridging connection line Line3.

[0056] The embodiment of the present application realizes the connection between the first transistor T1 and the second transistor T2 through the bridging connection line Line3. Specifically, one end of the bridging connection line Line3 is connected with the first electrode of the second transistor T2, and the other end of the bridging connection line Line3 is connected with the first electrode of the first transistor T1.

[0057] In some embodiments, the plurality of conductive layers comprise a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked along a direction gradually away from the substrate.

[0058] Preferably, the bridging connection line Line3 and the first power connection line Line1 are located in the same conductive layer. Specifically, the bridging connection line Line3 and the first power connection line Line1 are both located in the third metal layer. The power signal line elvdd is located in the fourth metal layer.

[0059] Referring to Figure 6 Preferably, the first electrode of the second transistor T2 is connected with the bridging connection line Line3 through a fourth conductive via K4.

[0060] Referring to Figure 5Preferably, the plurality of signal lines further comprises a reference voltage signal line Vref, and the reference voltage signal line Vref is connected to the second electrode of the second transistor T2.

[0061] In actual application, after the second transistor T2 is turned on, the reference voltage signal in the reference voltage signal line Vref is transmitted from the second electrode of the second transistor T2 to the first electrode of the second transistor T2, and further transmitted to the first electrode of the driving transistor DTFT and the first electrode of the first transistor T1, so that the first electrode of the driving transistor DTFT and the first electrode of the first transistor T1 are initialized by the reference voltage signal in the reference voltage signal line Vref.

[0062] Figure 7 Fig. 2 shows a top view of an array substrate according to another embodiment of the present application. As shown in Fig. 2, in the array substrate 100 according to the embodiment of the present application, the plurality of signal lines further comprises a second power connection line Line2, and the pixel circuit 110 further comprises a capacitor C, the first plate of the capacitor C shares the control electrode of the driving transistor DTFT, the second plate of the capacitor C is connected to the second power connection line Line2, and the second power connection line Line2 is connected to a power signal line elvdd. Figure 7

[0063] The first plate of the capacitor C and the control electrode of the driving transistor DTFT are both located in the first metal layer. The actual size of the driving transistor DTFT meets the design requirement size, so that the actual area of the capacitor C also meets the design requirement area.

[0064] In actual application, the actual width of the driving transistor DTFT obtained by the present application is 2.7 microns (equal to the width design requirement), the actual length of the driving transistor DTFT is 18 microns (equal to the length design requirement), and the actual area of the capacitor C is 67 square microns (equal to the area design requirement). Therefore, the actual size of the driving transistor DTFT and the actual area of the capacitor C provided by the present application both meet the design requirements.

[0065] In some embodiments, the spacing between the capacitor and the first electrode of the first transistor in the second direction is greater than 0.9 microns.

[0066] Preferably, the second plate and the second power connection line Line2 are arranged in different layers, and the second plate is connected to the second power connection line Line2 through a fifth conductive via K5 and a sixth conductive via K6.

[0067] The second plate is located in the second metal layer, and the second power connection line Line2 is located in the third metal layer. The second power connection line Line2 is connected to the power signal line elvdd through the fifth conductive via K5.

[0068] ​It should be emphasized that the fifth conductive via K5 serves as a point of connection between the power signal line elvdd and the pixel circuit 110, and the first conductive via K1 and the second conductive via K2 jointly serve as another point of connection between the power signal line elvdd and the pixel circuit 110. Through the two connection points, the electrical conduction performance of the array substrate 100 is improved.

[0069] Preferably, in the first direction F1, the second power connection line Line2 and the first power connection line Line1 are respectively located on two sides of the first transistor T1. Referring to Figure 7 In the vertical direction, the second power connection line Line2 is located above the first transistor T1, and the first power connection line Line1 is located below the first transistor T1.

[0070] Preferably, the second power connection line Line2 extends along the second direction F2. Referring to Figure 7 , the second power connection line Line2 extends horizontally.

[0071] In some embodiments, the second power connection line Line2 and the first power connection line Line1 are located in the same conductive layer. Specifically, the second power connection line Line2 and the first power connection line Line1 are both located in the third metal layer.

[0072] Referring to Figure 7 , preferably, the first power connection line Line1 and the second power connection line Line2 are arranged at intervals in the same conductive layer.

[0073] Referring to Figure 7 The plurality of signal lines further include a data signal line Data, and the orthogonal projection of the data signal line Data on the substrate and the orthogonal projection of each of the first power connection line Line1 and the second power connection line Line2 on the substrate at least partially overlap.

[0074] The data signal line Data extends vertically, and the first power connection line Line1 and the second power connection line Line2 both extend horizontally. That is, the orthogonal projection of the data signal line Data on the substrate and the orthogonal projection of the first power connection line Line1 on the substrate intersect, and the orthogonal projection of the data signal line Data on the substrate and the orthogonal projection of the second power connection line Line2 on the substrate also intersect.

[0075] Referring to Figure 7 In the array substrate 100 provided in the embodiments of the present application, the plurality of conductive layers include a plurality of pixel circuits 110, and the plurality of pixel circuits 110 are arranged along the second direction F2. At least one of the first power connection line Line1 and the second power connection line Line2 is located between adjacent pixel circuits 110 in the second direction F2.

[0076] The plurality of (which can be two) pixel circuits 110 are arranged in a lateral direction, and two adjacent pixel circuits 110 are connected by the same first power supply connection line Line1 to provide a power supply voltage for the two adjacent pixel circuits 110 through the same first power supply connection line Line1; and the same second power supply connection line Line2 also connects two adjacent pixel circuits 110 to provide a power supply voltage for the two adjacent pixel circuits 110 through the same second power supply connection line Line2.

[0077] In one embodiment, at least one of the first power supply connection line Line1 and the second power supply connection line Line2 has an axis of symmetry in the first direction F1.

[0078] In one embodiment, at least one of the first power supply connection line Line1 and the second power supply connection line Line2 connects adjacent pixel circuits 110 in the second direction F2.

[0079] Reference Figure 7 In the array substrate 100 provided by the embodiments of the present application, the same second power supply connection line Line2 connects the second plate of the capacitor C in the adjacent pixel circuits 110; and / or the same first power supply connection line Line1 connects the second electrode of the first transistor T1 in the adjacent pixel circuits 110.

[0080] In actual application, the first power supply connection line Line1 simultaneously provides a power supply voltage for the second electrode of the first transistor T1 in two adjacent pixel circuits 110, and the second power supply connection line Line2 simultaneously provides a power supply voltage for the second plate of the capacitor C in two adjacent pixel circuits 110.

[0081] Figure 8 The structure of the display panel provided by an embodiment of the present application is shown. As shown in the figure, Figure 8 As shown, the display panel 10 provided by the embodiments of the present application includes the array substrate 100 provided by any of the above embodiments, and the technical principles and effects are similar, which will not be repeated here.

[0082] It can be understood that the display panel 10 can be applied to a display device, which can be any product or component with display function, such as a mobile terminal, a tablet computer, a computer display, a television, a wearable device, or an information query machine.

[0083] The basic principles of the application are described above in conjunction with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present application are only examples and are not limiting, and it cannot be considered that these advantages, benefits, effects and the like are necessarily possessed by each embodiment of the present application. In addition, the above specific details disclosed are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present application to necessarily adopt the above specific details to realize.

[0084] It should also be noted that in the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present application. Although a number of example aspects and embodiments have been discussed above, one of skill in the art will recognize certain modifications, alternatives, changes, additions and subcombinations.

Claims

1. An array substrate, characterized by, The application relates to a display panel, comprising: a substrate; a semiconductor layer on one side of the substrate; a plurality of conductive layers stacked on the side of the semiconductor layer away from the substrate; wherein the semiconductor layer and the plurality of conductive layers comprise a pixel circuit and a plurality of signal lines, the pixel circuit comprises a driving transistor and a first transistor, and the plurality of signal lines comprises a power signal line and a first power connection line arranged in different layers; a first electrode of the first transistor is connected to a first electrode of the driving transistor, and a second electrode of the first transistor is electrically connected to the power signal line through the first power connection line; the power signal line extends along a first direction parallel to the substrate, the first power connection line extends along a second direction parallel to the substrate, and the second direction intersects the first direction; in the first direction, the driving transistor and the first power connection line are respectively located on the two sides of the first transistor; the first electrode of the first transistor is connected to the first electrode of the driving transistor through a first conductive via, and a projection of the first conductive via on the substrate and a projection of the semiconductor layer on the substrate overlap; a distance between a projection of a control electrode of the driving transistor on the substrate and a projection of the first conductive via on the substrate is greater than or equal to 0.9 microns. An active part of the driving transistor is located in the semiconductor layer, and the active part has an axis of symmetry in the first direction.

2. The array substrate of claim 1, wherein, the second electrode of the first transistor is connected to the first power connection line through a second conductive via, and the first power connection line is connected to the power signal line through a third conductive via, and the second conductive via and the third conductive via are arranged along the second direction.

3. The array substrate of claim 1, wherein, The second electrode comprises a source, and the first electrode comprises a drain.

4. The array substrate of claim 1, wherein, The second direction is perpendicular to the first direction.

5. The array substrate of claim 1, wherein, The plurality of signal lines further comprises a cross-connection line, and the pixel circuit further comprises a second transistor, and a first electrode of the second transistor is electrically connected to a first electrode of the first transistor through the cross-connection line.

6. The array substrate of claim 1, wherein, The cross-connection line and the first power connection line are located in the same conductive layer.

7. The array substrate of claim 6, wherein, The first electrode of the second transistor is connected to the cross-connection line through a fourth conductive via.

8. The array substrate of claim 6, wherein, The plurality of signal lines further comprises a reference voltage signal line connected to a second electrode of the second transistor.

9. The array substrate of claim 6, wherein, The plurality of signal lines further comprises a second power connection line, and the pixel circuit further comprises a capacitor, a first plate of the capacitor shares a control electrode of the driving transistor, a second plate of the capacitor is connected to the second power connection line, and the second power connection line is connected to the power signal line.

10. The array substrate of claim 1, wherein, The second plate and the second power connection line are arranged in different layers, and the second plate is connected to the second power connection line through a fifth conductive via and a sixth conductive via.

11. The array substrate of claim 10, wherein, In the first direction, the second power connection line and the first power connection line are respectively located on the two sides of the first transistor.

12. The array substrate of claim 10, wherein, The second power connection line extends along the second direction.

13. The array substrate of claim 10, wherein, ​ 14. The array substrate of claim 10, wherein, The second power supply connection line and the first power supply connection line are located in the same conductive layer.

15. The array substrate of claim 14, wherein, The first power supply connection line and the second power supply connection line are arranged at intervals in the same conductive layer.

16. The array substrate of claim 10, wherein, The plurality of signal lines further include a data signal line, a projection of the data signal line on the substrate and a projection of each of the first power supply connection line and the second power supply connection line on the substrate at least partially overlap.

17. The array substrate of claim 10, wherein, The semiconductor layer and the plurality of conductive layers include a plurality of pixel circuits, and the plurality of pixel circuits are arranged along the second direction; and at least one of the first power supply connection line and the second power supply connection line is located between adjacent pixel circuits in the second direction.

18. The array substrate of claim 17, wherein, At least one of the first power supply connection line and the second power supply connection line has an axis of symmetry in the first direction.

19. The array substrate of claim 17, wherein, At least one of the first power supply connection line and the second power supply connection line connects adjacent pixel circuits in the second direction.

20. The array substrate of claim 17, wherein, The same second power supply connection line connects the second plate of the capacitor in adjacent pixel circuits; and / or The same first power supply connection line connects the second electrode of the first transistor in adjacent pixel circuits.

21. The array substrate of claim 20, wherein, The pixel circuit includes an 8T1C pixel circuit.

22. A display panel comprising: An array substrate as claimed in any one of claims 1 to 21.

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