Display panel and electronic equipment

Abstract

The invention provides a display panel and electronic equipment. The power consumption can be reduced. The display panel comprises a plurality of picture updating periods and a plurality of pixels, and each picture updating period comprises a resetting stage, a data writing stage and a light emitting stage; the reset stage comprises a selection sub-stage and a reset sub-stage; each pixel comprises a pixel driving circuit and a light-emitting element; the pixel driving circuit comprises a pixel driving module, a gating module, a control module, a data signal end and a reset signal end, the gating module is electrically connected with the control module and the pixel driving module, and the control module is electrically connected with the data signal end; in the selection sub-stage, the control module controls the gating module to be switched on or switched off according to a data signal written by a data signal end; when the gating module is switched on, a reset signal resets the pixel driving module in a reset sub-stage; in the data writing stage, data signals are written into the pixel driving module, the pixel driving module generates driving current, and in the light emitting stage, the driving current is provided for the light emitting element.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] The main component of an electronic device to realize the display function is the display panel. The display panel includes a display area and a non-display area. The display area includes a plurality of pixels arranged in an array. Each pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit is used to drive the light-emitting element to emit light to display an image or video; the non-display area is provided with a scanning driving circuit for providing a scanning signal to the pixel driving circuit so that the light-emitting element is lit row by row under the drive of the pixel driving circuit.

[0003] When current electronic devices display images, generally all areas of the screen have the same refresh frequency, that is, all pixels in the display area are refreshed at the same frequency, which makes the power consumption of the display panel relatively high, is not conducive to improving the battery life of the electronic device, and reduces the user experience. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a display panel and an electronic device, which can reduce power consumption.

[0005] In a first aspect, an embodiment of the present application provides a display panel, which includes: multiple pixels, each pixel includes a pixel driving circuit and a light-emitting element; the pixel driving circuit includes a pixel driving module, a gating module, a control module, a data signal terminal and a reset signal terminal, the gating module is electrically connected to the control module and the pixel driving module respectively, and the control module is electrically connected to the data signal terminal; the data signal terminal is used to transmit a data signal; the reset signal terminal is used to transmit a reset signal; the display panel also includes multiple picture update cycles, the picture update cycle includes a reset stage, a data writing stage and a light-emitting stage; the reset stage includes a selection sub-stage and a reset sub-stage; in the selection sub-stage, the control module is used to control the gating module to be turned on or off according to the data signal written by the data signal terminal; when the gating module is turned on, in the reset sub-stage, the reset signal is written to the pixel driving module to reset the pixel driving module; in the data writing stage, the data signal is written to the pixel driving module to enable the pixel driving module to generate a driving current, and in the light-emitting stage, the driving current is provided to the light-emitting element to enable the light-emitting element to emit light corresponding to the driving current.

[0006] The settings of the gating module and the control module can control whether the pixel driving module generates a driving current. When the gating module and the control module control the pixel driving module to generate a driving current, the pixel can be refreshed; when the gating module and the control module control the pixel driving module to fail to generate a driving current, the pixel cannot be refreshed. In this way, the refresh frequency of the pixel is controlled. And because the control module controls the gating module to be turned on or off according to the data signal, it controls whether the pixel driving module generates a driving current. For example, when the data signal is the first data signal, the gating module is turned on, and the pixel driving module generates a driving current; when the data signal is the second data signal, the gating module is turned off, and the pixel driving module cannot generate a driving current. Therefore, the data signal can control whether each pixel is refreshed, so that the refresh of any area and any position of the display panel can be completed, that is, the refresh of any single pixel in the display panel is completed, and it is no longer limited to the local refresh of a certain area, and all pixels are no longer refreshed, which is conducive to reducing power consumption.

[0007] In addition, the gating module and the control module provided in the embodiment of the present application are located in the display area of ​​the display panel and will not occupy the non-display area of ​​the display panel, which is beneficial to the narrow frame design of the display panel.

[0008] Exemplarily, in the selection sub-stage, the data signal is a first level signal, and in the reset sub-stage, the data writing stage and the light emitting stage, the data signal is a second level signal. The first level signal and the second level signal are in opposite phases, for example, the first level signal can be a low level signal, and the second level signal can be a high level signal.

[0009] Exemplarily, when the selection module is turned on, in the reset sub-stage, a reset signal is written to the pixel driving module to reset the pixel driving module; in the data writing stage, a data signal is written to the pixel driving module to enable the pixel driving module to generate a driving current, and in the light emitting stage, a driving current is provided to the light emitting element so that the light emitting element emits light corresponding to the driving current, and the pixel can be refreshed.

[0010] When the strobe module is turned off, in the reset sub-phase, the reset signal cannot be written into the pixel driving module; in the data writing phase, the data signal cannot be written into the pixel driving module, and the pixel cannot be refreshed.

[0011] According to the second aspect, the gating module includes a first gating unit, a second gating unit and a third gating unit; the pixel driving module includes a driving module; the control module, the control end of the first gating unit, the control end of the second gating unit and the control end of the third gating unit are coupled to the first node; the control module is used to send a control signal to the control end of the first gating unit, the second gating unit and the third gating unit in a selection sub-stage according to the data signal written by the data signal end to control the first gating unit, the second gating unit and the third gating unit to be turned on or off; when the first gating unit is turned on, in the reset sub-stage, the reset signal is written to the control end of the driving module to reset the control end of the driving module; when the second gating unit and the third gating unit are turned on, in the data writing stage, the driving module generates a driving current according to the data signal.

[0012] The setting of the first selection unit can select whether the reset signal resets the control end of the driving module. The setting of the second selection unit and the third selection unit can select whether the data signal will cause the driving module to generate a new driving current to drive the light-emitting element to emit light. By setting the selection modules separately, it is possible to more flexibly control whether to reset the control end of the driving module and whether to cause the driving module to generate a new driving current to drive the light-emitting element to emit light.

[0013] Exemplarily, the driving module is the driving transistor M1 in the following content.

[0014] According to the first aspect, or any implementation of the first aspect above, the pixel driving module also includes a first reset module, a threshold compensation module and a data writing module, and the pixel driving circuit also includes a first scanning signal terminal, a second scanning signal terminal and a third scanning signal terminal; the first end of the first reset module is electrically connected to the reset signal terminal, the second end of the first reset module is electrically connected to the first end of the first gating unit, the control end of the first reset module is electrically connected to the first scanning signal terminal, the second end of the first gating unit, the control end of the driving module and the first end of the threshold compensation module are coupled to the second node; the first end of the data writing module is electrically connected to the data signal terminal, the second end of the data writing module is electrically connected to the first end of the second gating unit, the control end of the data writing module is electrically connected to the second scanning signal terminal, the second end of the second gating unit is electrically connected to the first end of the driving module, and the second end of the driving module is electrically connected to the second end of the threshold compensation module; the control end of the threshold compensation module is electrically connected to the first end of the third gating unit, and the second end of the third gating unit is electrically connected to the third scanning signal terminal.

[0015] That is, a first gating unit is arranged between the first reset module and the second node, a second gating unit is arranged between the data writing module and the first end of the driving module, and a third gating unit is arranged between the control end of the threshold compensation module and the third scanning signal end. This arrangement can better intercept the reset signal and the data signal and facilitate the control of the control module.

[0016] Exemplarily, the first reset module is the reset transistor M4 described below.

[0017] Exemplarily, the threshold compensation module is the threshold compensation transistor M3 in the following content.

[0018] Exemplarily, the data writing module is the data writing transistor M2 in the following content.

[0019] According to the first aspect, or any implementation of the first aspect above, the first selection unit includes a first transistor; the gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second end of the first reset module, and the second electrode of the first transistor is electrically connected to the second node.

[0020] The reset signal can be controlled by a transistor (i.e. whether to transmit the reset signal to the control end of the driving module). The structure of the first selection unit is simple, which makes the structure of the pixel driving circuit simple, and while realizing single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0021] According to the first aspect, or any implementation of the first aspect above, the second selection unit includes a second transistor; the gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second end of the data writing module, and the second electrode of the second transistor is electrically connected to the first end of the driving module.

[0022] The data signal can be controlled by a transistor (i.e., whether the data signal will generate a new driving current through the driving module). The structure of the second selection unit is simple, which makes the structure of the pixel driving circuit simple, and while realizing single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0023] According to the first aspect, or any implementation of the first aspect above, the third selection unit includes a third transistor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control end of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal end.

[0024] The data signal can be controlled by a transistor (i.e., whether the data signal will generate a new driving current through the driving module). The structure of the third selection unit is simple, which makes the structure of the pixel driving circuit simple, and while realizing single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0025] According to the first aspect, or any implementation of the first aspect above, the control module includes a data writing unit, a first control unit and a second control unit; the data writing unit, the first control unit and the second control unit are all electrically connected to the gating module; in the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; when the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; in the light-emitting stage, the second control unit is used to control the gating module to be turned off.

[0026] The configuration of the data writing unit, the first control unit and the second control unit can more flexibly control the switching on or off of the gating module, and avoid the influence of other signals on the state of the gating module, thereby improving the reliability of the circuit.

[0027] According to the first aspect, or any implementation of the first aspect above, the control module also includes a voltage stabilizing unit, the first end of the voltage stabilizing unit, the data writing unit, the first control unit and the second control unit are coupled to the third node, and the second end of the voltage stabilizing unit, the first control unit, the second control unit and the selection module are coupled to the first node.

[0028] The setting of the voltage stabilizing unit makes the signal output to the gating module more stable.

[0029] According to the first aspect, or any implementation of the first aspect above, the voltage stabilizing unit includes a first capacitor, a first pole of the first capacitor, a data writing unit, a first control unit and a second control unit are coupled to a third node, and a second pole of the first capacitor, a first control unit, a second control unit and a gating module are coupled to a first node.

[0030] The voltage stabilizing unit has a simple structure, which in turn makes the structure of the pixel driving circuit simple, and is beneficial to improving the aperture ratio of the pixel while realizing the refresh of a single pixel.

[0031] According to the first aspect, or any implementation of the first aspect above, the pixel driving circuit also includes a fourth scanning signal terminal; the data writing unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the fourth scanning signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor and the gate of the fifth transistor, and the second electrode of the fifth transistor is electrically connected to the third node.

[0032] The selection of the state of the selection module (on or off) in the selection sub-stage can be achieved through two transistors. The structure of the data writing unit is simple, which makes the structure of the pixel driving circuit simple, and while achieving single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0033] According to the first aspect, or any implementation of the first aspect above, the pixel driving circuit also includes a fourth scanning signal terminal; the first control unit includes a sixth transistor and a seventh transistor, the first electrode of the sixth transistor and the gate of the sixth transistor are both electrically connected to the fourth scanning signal terminal, the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor, the second electrode of the seventh transistor is electrically connected to the selection module, and the gate of the seventh transistor is electrically connected to the third node.

[0034] Two transistors can be used to maintain the state of the selection module (on or off) in the reset sub-stage and the data writing stage. The structure of the first control unit is simple, which makes the structure of the pixel driving circuit simple, and while achieving single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0035] According to the first aspect, or any implementation of the first aspect above, the pixel driving circuit also includes a fourth scanning signal terminal and a fifth scanning signal terminal; the second control unit includes an eighth transistor and a ninth transistor, the gate of the eighth transistor and the gate of the ninth transistor are both electrically connected to the fifth scanning signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth scanning signal terminal, the second electrode of the eighth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the selection module.

[0036] The state of the selection module can be restored in the light-emitting stage by two transistors, that is, no matter whether the state of the selection module is in the off state or the on state in the reset stage and the data writing stage, the eighth transistor and the ninth transistor will control the selection module to be restored to the off state, thereby avoiding the influence on whether the next frame is refreshed. The structure of the second control unit is simple, which makes the structure of the pixel driving circuit simple, and realizes the refresh of a single pixel, which is beneficial to improve the aperture ratio of the pixel.

[0037] According to the first aspect, or any implementation of the first aspect above, the effective level duration of the selection sub-phase is shorter than the effective level duration of the reset sub-phase.

[0038] This arrangement allows for a longer time to reset the previous frame signal, thereby avoiding the influence of the previous frame signal on the current frame signal and improving display uniformity.

[0039] According to the first aspect, or any implementation of the first aspect above, a plurality of pixels are arranged in an array; the display panel further includes a driving circuit and a plurality of scan line groups; the driving circuit includes at least a first scan driving circuit and a second scan driving circuit, and the scan line group includes at least a first scan signal line and a second scan signal line; the first scan driving circuit includes a plurality of first scan signal output terminals, the second scan driving circuit includes a plurality of second scan signal output terminals, the plurality of first scan signal output terminals are electrically connected to the plurality of first scan signal lines in a one-to-one correspondence, and the plurality of second scan signal output terminals are electrically connected to the plurality of second scan signal lines in a one-to-one correspondence; the pixel driving circuit further includes a first scan signal terminal, a second scan signal terminal, and a second scan signal terminal. second scanning signal terminal, a third scanning signal terminal, a fourth scanning signal terminal and a fifth scanning signal terminal; the second scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the same first scanning signal line, the third scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the same second scanning signal line, the first scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scanning signal line corresponding to other pixel rows, the fourth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to other pixel rows, and the fifth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to other pixel rows.

[0040] This arrangement reduces the number of scan drive circuits in the drive circuit, and eliminates the need to provide a corresponding scan drive circuit for each scan signal terminal, thereby simplifying the structure of the drive circuit and allowing the drive circuit to occupy less non-display area, which is beneficial to a narrow-frame design of the display panel and is low-cost.

[0041] According to the first aspect, or any implementation method of the first aspect above, the first scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scanning signal line corresponding to the previous pixel row, the fourth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to the previous pixel row, and the fifth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to the next pixel row.

[0042] This arrangement makes the signal line electrically connecting the first scanning signal end with the second scanning signal line corresponding to the previous pixel row shorter, avoiding the signal line occupying more of the light-emitting area, which is beneficial to improving the pixel aperture ratio.

[0043] Of course, this does not constitute a limitation of the present application. Optionally, the fourth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to the upper two pixel rows. Accordingly, when the fourth scanning signal terminal inputs a valid level (a level that can turn on the structure or transistor electrically connected to the fourth scanning signal terminal), at this moment, the data signal input to the data signal terminal is also a valid data signal (that is, a signal that turns on the selection module).

[0044] In a second aspect, an embodiment of the present application provides an electronic device, the electronic device comprising the display panel of the first aspect and any one of the implementations of the first aspect, and the second aspect corresponds to the first aspect and any one of the implementations of the first aspect. The technical effects corresponding to the second aspect can refer to the technical effects corresponding to the first aspect and any one of the implementations of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1a One of the application scenarios of an electronic device provided in an embodiment of the present application;

[0046] Figure 1b One of the application scenarios of an electronic device provided in an embodiment of the present application;

[0047] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application;

[0050] Figure 5 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0051] Figure 6 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0052] Figure 7 A timing diagram of various signals of the pixel driving circuit provided in an embodiment of the present application;

[0053] Figure 8 is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the reset stage;

[0054] Fig. 9 is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the reset stage;

[0055] Fig.10 is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the data writing stage;

[0056] Fig.11 is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the data writing stage;

[0057] Fig.12 is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the light emitting stage;

[0058] Fig.13 is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the light emitting stage;

[0059] Fig.14 Another timing diagram of various signals of the pixel driving circuit provided in the embodiment of the present application;

[0060] Fig.15 is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the reset stage;

[0061] Fig.16 is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the reset stage;

[0062] Fig.17 is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the data writing stage;

[0063] Fig.18 is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the data writing stage;

[0064] Fig.19 is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the light emitting stage;

[0065] Fig. 20 is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the light emitting stage;

[0066] Fig.21 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0067] Fig. 22 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0068] Fig.23 Another timing diagram of various signals of the pixel driving circuit provided in the embodiment of the present application;

[0069] Fig.24 Another timing diagram of various signals of the pixel driving circuit provided in the embodiment of the present application;

[0070] Fig.25 A refreshing process of a display screen provided in an embodiment of the present application;

[0071] Fig.26 This is one of the application scenarios of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0073] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0074] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0075] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0076] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0077] Figure 1a and Figure 1b FIG. 1 is a schematic diagram of an exemplary application scenario. Figure 1a As shown, the electronic device 100 (such as a mobile phone) displays various contents through a display panel; Figure 1b As shown, the electronic device 100 (such as a notebook computer) displays various contents through a display panel. Figure 1a and Figure 1bIn the embodiment, the display area of ​​the display panel display content is divided into three areas: a status bar 101, a video playback area 102, and a static content display area 103. The status bar 101 is used to display status information, such as the remaining battery power, time, etc.; the video playback area 102 is used to display dynamic content, such as playing videos, etc.; and the static content display area 103 is used to display static content, such as text, pictures, etc.

[0078] In similar Figure 1a and Figure 1b In the illustrated scenario, if the display content of all regions is refreshed at the same refresh rate, the power consumption of the display panel will be relatively high, but the display quality will not be significantly improved.

[0079] Based on this, the embodiments of the present application propose a display panel and an electronic device using the display panel, wherein the electronic device can be a mobile phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a car computer, a smart wearable device, a smart home device, and other smart terminals including a display panel. The embodiments of the present application do not limit the specific form of the above-mentioned electronic devices.

[0080] By refreshing the displayed content at a relatively low refresh rate for areas where the displayed content remains unchanged or where static content such as text and pictures is displayed, the displayed content is refreshed at a relatively high refresh rate for areas where the displayed content changes in real time or where dynamic content such as videos is displayed. In other words, different refresh rates are selected to refresh the displayed content according to the different displayed content in different areas. In this way, the refresh rate of areas such as areas where the displayed content remains unchanged or where static content such as text and pictures is displayed is relatively low. Since the displayed content in these areas remains unchanged or static content such as text and pictures is displayed, although the refresh rate is reduced, the display quality is not significantly affected, so that the display panel reduces power consumption while maintaining the display quality, thereby improving the battery life of the electronic device.

[0081] The following describes the various structures in the display panel provided by the embodiment of the present application and the principle of achieving different refresh frequencies in different areas and positions in conjunction with the electronic device, wherein see Figure 2 , taking the electronic device being a mobile phone as an example for explanation.

[0082] like Figure 2As shown, the mobile phone 100 includes a display panel 10, a rear shell 20 and a middle frame 30. The display panel 10, the rear shell 20 and the middle frame 30 can enclose a housing cavity. Structures such as a printed circuit board, a battery and functional devices (not shown in the figure) are arranged in the housing cavity. Functional devices include, for example, a display driver chip and a processor, etc. The display driver chip and the processor are arranged on a printed circuit board, and the electrical connection between the display driver chip and the processor is realized through the printed circuit board. The processor sends a corresponding signal to the display driver chip so that the display driver chip drives the display panel 10 to display.

[0083] The material of the rear cover 20 may include, for example, opaque materials such as plastic, plain leather, and glass fiber; or may include translucent materials such as glass. The material of the rear cover 20 is not limited in the embodiment of the present application.

[0084] The display panel 10 may include a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, an LED display panel, etc., wherein the LED display panel may include a Micro-LED display panel, a Mini-LED display panel, etc. The embodiment of the present application does not limit the type of the display panel 10. The following description takes the display panel 10 as an OLED display panel as an example.

[0085] See also Figure 3 , Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 3 As shown, the display panel 10 includes a display area AA and a non-display area NAA, and the non-display area NAA is located on at least one side of the display area AA, wherein: Figure 3 The description is made by taking the non-display area NAA surrounding the display area AA as an example. A plurality of pixels 11, a plurality of scan line groups 12 and a plurality of data lines 13 arranged in an array are provided in the display area AA of the display panel 10. Each pixel 11 includes a pixel driving circuit 111 and a light-emitting element 112. The plurality of data lines 13 correspond one-to-one to the pixel driving circuits 111 in the plurality of columns of pixels 11, that is, the pixel driving circuit 111 in one column of pixels 11 corresponds to one data line 13. The plurality of scan line groups 12 correspond one-to-one to the pixel driving circuits 111 in the plurality of rows of pixels 11, that is, the pixel driving circuit 111 in one row of pixels 11 corresponds to one scan line group 12.

[0086] Combination Figure 4 , Figure 4This is a structural diagram of a pixel driving circuit. The pixel driving circuit 111 may include a pixel driving module. The pixel driving module includes 8T1C (8 transistors and 1 storage capacitor), that is, the pixel driving module may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4, M5 and M8, light emitting control transistors M6 and M7, and a storage capacitor Cst.

[0087] It is understandable that the specific structure of the pixel driving module includes but is not limited to the above examples. In other optional embodiments, the pixel driving module can also be configured in other ways (i.e., including more transistors or fewer transistors, and including more storage capacitors or fewer storage capacitors), as long as it can drive the light emitting element 112 to emit light. For example, Figure 5 As shown, the pixel driving module may also include 7T1C (7 transistors and 1 storage capacitor), that is, the pixel driving module may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light emitting control transistors M6 and M7, and a storage capacitor Cst.

[0088] It should be noted that the embodiment of the present application is described by taking the example that the pixel driving module may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4, M5 and M8, light emitting control transistors M6 and M7, and a storage capacitor Cst.

[0089] In some embodiments, the reset transistor M4 and the threshold compensation transistor M3 may be transistors with oxide semiconductor materials as active layers. The oxide semiconductor material may include indium gallium zinc oxide (IGZO) material, and the transistor is, for example, an N-type transistor. The driving transistor M1, the data writing transistor M2, the reset transistors M5 and M8, and the light emitting control transistors M6 and M7 are transistors with silicon materials as active layers, and the transistors are, for example, P-type transistors. That is, the LTPS transistor and the IGZO transistor are integrated on a substrate to form a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display panel 10.

[0090] Low temperature polysilicon transistors have advantages such as high carrier mobility, fast response, and low power consumption, and oxide semiconductor transistors have the advantage of low leakage current, so when the pixel driving circuit 111 includes both transistors with LTPS materials as active layers and transistors with IGZO materials as active layers, it can be ensured that the pixel driving circuit 111 has better performance. For example, oxide semiconductor transistors have the advantage of low leakage current, so when refreshing at a low frequency, the gate potential of the driving transistor M1 can be kept stable and not leaked, thereby keeping the picture from flickering at a low frequency.

[0091] In addition, the combination of N-type transistors and P-type transistors will effectively reduce the number of thin film transistors required for the pixel driving circuit 111, making the structure of the pixel driving circuit 111 simpler.

[0092] Of course, this is not enough to limit the present application. In other optional embodiments of the present application, the above-mentioned driving transistor M1, data writing transistor M2, threshold compensation transistor M3, reset transistors M4, M5 and M8, and light-emitting control transistors M6 and M7 can all be transistors with silicon materials as active layers. The silicon material may include polycrystalline silicon material, etc., and the polycrystalline silicon material may include low-temperature polycrystalline silicon (LTPS) material. And the transistor is, for example, a P-type transistor.

[0093] When the pixel driving module includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light-emitting control transistors M6 and M7, and a storage capacitor Cst, the driving transistor M1, the data writing transistor M2, the threshold compensation transistor M3, the reset transistors M4 and M5, and the light-emitting control transistors M6 and M7 may all be transistors with silicon material as an active layer. Alternatively, the reset transistor M4 and the threshold compensation transistor M3 may be transistors with oxide semiconductor material as an active layer, and the driving transistor M1, the data writing transistor M2, the reset transistor M5, and the light-emitting control transistors M6 and M7 may all be transistors with silicon material as an active layer.

[0094] It should be noted that the embodiments of the present application are all described by taking the reset transistor M4 and the threshold compensation transistor M3 as transistors having an oxide semiconductor material as an active layer, and the transistors are, for example, N-type transistors, and the driving transistor M1, the data writing transistor M2, the reset transistors M5 and M8, and the light emitting control transistors M6 and M7 as transistors having a silicon material as an active layer, and the transistors are, for example, P-type transistors.

[0095] Continue to see Figure 4The pixel driving circuit 111 also includes initialization signal terminals Vref1, Vref2 and Vref3, a first power terminal PVDD, a second power terminal PVEE, a data signal terminal Data, a first scan signal terminal Scan1, a second scan signal terminal Scan2, a third scan signal terminal Scan3, a sixth scan signal terminal Scan6 and a light emitting control signal terminal Emit. The first electrode of the light-emitting control transistor M6 is electrically connected to the first power supply terminal PVDD, the first electrode of the data writing transistor M2 is electrically connected to the data signal terminal Data, the gate of the data writing transistor M2 is electrically connected to the second scanning signal terminal Scan2, the gate of the threshold compensation transistor M3 is electrically connected to the third scanning signal terminal Scan3, the first electrodes of the reset transistors M4, M5 and M8 are electrically connected to the initialization signal terminal Vref1, the initialization signal terminal Vref2, and the initialization signal terminal Vref3 respectively (the initialization signal terminals corresponding to the three may be the same or different), the gate of the reset transistor M4 may be electrically connected to the first scanning signal terminal Scan1, the gates of the reset transistors M5 and M8 may be electrically connected to the sixth scanning signal terminal Scan6, the gates of the light-emitting control transistors M6 and M7 may be electrically connected to the light-emitting control signal terminal Emit respectively, the light-emitting control transistor M7 is electrically connected to the anode of the light-emitting element 112, and the cathode of the light-emitting element 112 is electrically connected to the second power supply terminal PVEE.

[0096] Continue to see Figure 3 Each scanning line group 12 includes a first scanning signal line 121 , a second scanning signal line 122 , a third scanning signal line 123 and a light emitting control signal line 122 .

[0097] The pixel driving circuit 111 in a column of pixels 11 mentioned above corresponds to one data line 13 , that is, the data signal terminals Data in the pixel driving circuits 111 of the pixels 11 in the same column are electrically connected to the same data line 13 . The pixel driving circuit 111 in a row of pixels 11 corresponds to a scan line group 12, that is, the second scan signal terminal Scan2 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the first scan signal line 121 corresponding to the pixel in the row, the third scan signal terminal Scan3 in the pixel driving circuit 111 of the pixels 11 in the same row is electrically connected to the second scan signal line 122 corresponding to the pixel in the row, the sixth scan signal terminal Scan6 in the pixel driving circuit 111 of the pixels 11 in the same row is electrically connected to the third scan signal line 123 corresponding to the pixel in the row, the light emitting control signal terminal Emit in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the light emitting control signal line 124 corresponding to the row, and the first scan signal terminal Scan1 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the second scan signal line 122 corresponding to the pixels in other rows (such as the previous row).

[0098] It should be noted that in order to ensure the simplicity and clarity of the circuit, Figure 3 It is not shown that the first scan signal terminal Scan1 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the second scan signal line 122 corresponding to the pixels in other rows.

[0099] That is, the first scan signal transmitted by the first scan signal line 121 can control the data writing transistor M2 to turn on or off, the second scan signal transmitted by the second scan signal line 122 can control the threshold compensation transistor M3 to turn on or off, and the third scan signal transmitted by the third scan signal line 123 can control the reset transistors M5 and M8 to turn on or off. The second scan signal transmitted by the second scan signal line 122 corresponding to other rows (such as the previous row) controls the reset transistor M4 to turn on or off; the light control signal transmitted by the light control signal line 124 can control the light control transistors M6 and M7 on the light branch to turn on or off.

[0100] When the second scanning signal line 122 and the third scanning signal line 123 provide the second scanning signal and the third scanning signal to the pixel 11 of the corresponding row, the gate of the driving transistor M1, the first electrode of the driving transistor M1 and the anode of the light-emitting element 112 can be refreshed to avoid the influence of the previous frame signal on the current frame signal and improve the display uniformity. When the first scanning signal line 121 provides the first scanning signal to the pixel 11 of the corresponding row, the pixel 11 to be refreshed can be selected. The data line 13 provides the data signal to the pixel driving circuit 111 of the corresponding column to refresh the data signal for the pixel 11 selected by the scanning signal. The light-emitting control signal line provides the light-emitting control signal to the pixel 11 of the corresponding row to control the light-emitting time of the pixel 11. The pixel driving circuit 111 generates a driving current under the action of the scanning signal, the light-emitting control signal and the data signal to drive the light-emitting element 112 to emit light. The specific principle of the pixel driving circuit 111 generating a driving current to drive the light-emitting element 112 to emit light based on the data signal, the light-emitting control signal and the scanning signal is similar to the principle of the 8T1C pixel driving circuit in the prior art generating a driving current to drive the light-emitting element to emit light, which will not be repeated here.

[0101] Continue to see Figure 3, a driving circuit 14 is provided in the non-display area NAA of the display panel 10, wherein the driving circuit 14 may include a first scanning driving circuit, a second scanning driving circuit, a third scanning driving circuit and a light-emitting control driving circuit (all not shown in the figure). The first scanning driving circuit, the second scanning driving circuit and the third scanning driving circuit each include a plurality of scanning signal output terminals (i.e., the first scanning driving circuit includes a plurality of first scanning signal output terminals, the second scanning driving circuit includes a plurality of second scanning signal output terminals, and the third scanning driving circuit includes a plurality of third scanning signal output terminals), and the light-emitting control driving circuit includes a plurality of light-emitting control signal output terminals. The plurality of scanning signal output terminals of the first scanning driving circuit are electrically connected to the plurality of first scanning signal lines 121 of the display area AA in a one-to-one correspondence, the plurality of scanning signal output terminals of the second scanning driving circuit are electrically connected to the plurality of second scanning signal lines 122 of the display area AA in a one-to-one correspondence, the plurality of scanning signal output terminals of the third scanning driving circuit are electrically connected to the plurality of third scanning signal lines 123 of the display area AA in a one-to-one correspondence, and the plurality of light-emitting control signal output terminals of the light-emitting control driving circuit are electrically connected to the light-emitting control signal lines 124 of the display area AA in a one-to-one correspondence. The first scan drive circuit transmits the above-mentioned first scan signal to the first scan signal line 121 through its scan signal output end, the second scan drive circuit transmits the above-mentioned second scan signal to the second scan signal line 122 through its scan signal output end, the third scan drive circuit transmits the above-mentioned third scan signal to the third scan signal line 123 through its scan signal output end, and the light-emitting control drive circuit transmits the above-mentioned light-emitting control signal to the light-emitting control signal line 122 through the light-emitting control signal output end.

[0102] It should be noted that the driving circuit 14 can be arranged on one side of the display area AA, such as Figure 3As shown. The driving circuit 14 can also be arranged on two opposite sides of the display area AA, that is, the driving circuit 14 is arranged on both opposite sides of the display area AA. That is to say, the first scan driving circuit can be arranged on one side of the display area AA, or on both opposite sides of the display area AA; the second scan driving circuit can be arranged on one side of the display area AA, or on both opposite sides of the display area AA; the third scan driving circuit can be arranged on one side of the display area AA, or on both opposite sides of the display area AA; the light emitting control driving circuit can be arranged on one side of the display area AA, or on both opposite sides of the display area AA. Exemplarily, when the first scan driving circuit in the driving circuit 14 is arranged on both opposite sides of the display area AA (that is, the first scan driving circuit is arranged on both opposite sides of the display area AA), the scan signal output ends of the two first scan driving circuits are electrically connected to a first scan signal line 121 to provide the first scan signal to the first scan signal line 121. In this way, the voltage drop of the first scan signal can be reduced. When the second scan driving circuit in the driving circuit 14 is arranged on two opposite sides of the display area AA (i.e., the first scan driving circuit is arranged on both opposite sides of the display area AA), the scan signal output ends of the two second scan driving circuits are electrically connected to a second scan signal line 122, so as to provide the second scan signal to the second scan signal line 122. In this way, the voltage drop of the second scan signal can be reduced. When the third scan driving circuit in the driving circuit 14 is arranged on two opposite sides of the display area AA (i.e., the third scan driving circuit is arranged on both opposite sides of the display area AA), the scan signal output ends of the two third scan driving circuits are electrically connected to a third scan signal line 123, so as to provide the third scan signal to the third scan signal line 123. In this way, the voltage drop of the third scan signal can be reduced. When the light-emitting control driving circuit in the driving circuit 14 is arranged on two opposite sides of the display area AA (that is, the light-emitting control driving circuit is arranged on both opposite sides of the display area AA), the light-emitting control signal output ends of the two light-emitting control driving circuits are electrically connected to a light-emitting control signal line 122 to provide light-emitting control signals to the light-emitting control signal line 122. Such an arrangement can reduce the voltage drop of the light-emitting control signal.

[0103] It should be noted that, in the embodiment of the present application, the first scan signal terminal Scan1 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the second scan signal line 122 corresponding to the pixels in other rows (such as the previous row), that is, the scan signal of the first scan signal terminal Scan1 is provided by the second scan driving circuit electrically connected to the second scan signal line 122, so that there is no need to set a separate scan driving circuit for the first scan signal terminal Scan1 in the pixel driving circuit 111, that is, the number of scan driving circuits in the driving circuit 14 is reduced, which is conducive to the narrow frame design of the display panel. Of course, this does not constitute a limitation of the present application. In other optional embodiments of the present application, a fourth scan driving circuit can also be set separately. Accordingly, the scan line group 12 can also include a fourth scan signal line, and the fourth scan driving circuit provides a fourth scan signal to the first scan signal terminal Scan1 in the pixel driving circuit 111 of each pixel 11 in the same row through the fourth scan signal line.

[0104] The above-mentioned refreshing of different areas and different positions of the display panel is to refresh the single pixel 11 at different areas and different positions of the display panel, that is, to reset the pixel driving circuit 111 of the pixel 11 at the area and the position, and to provide a new data signal to the pixel driving circuit 111 of the pixel 11 at the area and the position, so that the data signal in the pixel driving circuit 111 is updated (that is, the potential of the gate of the driving transistor M1 is refreshed), so that the driving current of the driving transistor M1 is refreshed. When the pixel 11 is not refreshed, the pixel driving circuit 111 of the pixel 11 in the area is not reset, the data signal in the pixel driving circuit 111 of the pixel 11 remains the data signal of the previous frame, and the driving current remains the driving current of the previous frame when emitting light. When the pixel 11 is not refreshed, the corresponding transistor remains turned off, no current flows, and thus the power consumption is reduced.

[0105] However, based on the above pixel driving circuit 111 (such as Figure 4 or Figure 5 The pixel driving circuit 111 shown can only use the same refresh rate to refresh the display content of all areas.

[0106] In order to achieve different refresh rates for individual pixels 11 in different regions and positions, Figure 6 , Figure 6A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application. The pixel driving circuit 111 includes not only a pixel driving module, initialization signal terminals Vref1, Vref2 and Vref3, a first power terminal PVDD, a second power terminal PVEE, a data signal terminal Data, a first scan signal terminal Scan1, a second scan signal terminal Scan2, a third scan signal terminal Scan3, a sixth scan signal terminal Scan6 and a light emitting control signal terminal Emit, but also includes a fourth scan signal terminal Scan4, a fifth scan signal terminal Scan5, a control module 1111 and a gating module 1112.

[0107] The gating module 1111 includes a first gating unit 1111 a , a second gating unit 1111 b , and a third gating unit 1111 c .

[0108] The first gating unit 1111 a includes a first transistor T1 , the second gating unit 1111 b includes a second transistor T2 , and the third gating unit 1111 c includes a third transistor T3 .

[0109] The control module 1112 includes a data writing unit 1112a, a first control unit 1112b, a second control unit 1112c and a voltage stabilizing unit 1112d.

[0110] The data writing unit 1112a includes a fourth transistor T4 and a fifth transistor T5, the first control unit 1112b includes a sixth transistor T6 and a seventh transistor T7, the second control unit 1112c includes an eighth transistor T8 and a ninth transistor T9, and the voltage stabilizing unit 1112d includes a first capacitor C1.

[0111] The gate of the first transistor T1, the gate of the second transistor T2, and the gate of the third transistor T3 are coupled to the first node N1, the first electrode of the first transistor T1 is electrically connected to the second electrode of the reset transistor M4, and the second electrode of the first transistor T1 is electrically connected to the second node N2. The first electrode of the second transistor T2 is electrically connected to the second electrode of the data writing transistor T2, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the driving transistor M1. The first electrode of the third transistor T3 is electrically connected to the gate of the threshold compensation transistor M3, and the second electrode of the third transistor T3 is electrically connected to the third scan signal terminal Scan3.

[0112] The first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5 and the gate of the fifth transistor T5, the second electrode of the fifth transistor T5 is electrically connected to the third node N3, the gate of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Scan4, and the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to other pixel rows (such as the previous pixel row), so there is no need to set a separate scan driving circuit for the fourth scan signal terminal Scan4.

[0113] The first electrode of the sixth transistor T6 and the gate of the sixth transistor T6 are also electrically connected to the fourth scan signal terminal Scan4, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7, the second electrode of the seventh transistor T7 is electrically connected to the first node N1, and the gate of the seventh transistor T1 is electrically connected to the third node N3.

[0114] The first electrode of the eighth transistor T8 is also electrically connected to the fourth scan signal terminal Scan4, the second electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the ninth transistor T9 is electrically connected to the third node N3, the second electrode of the ninth transistor T9 is electrically connected to the first node N1, the gate of the eighth transistor T8 and the gate of the ninth transistor T9 are both electrically connected to the fifth scan signal terminal Scan5, and the fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to other pixel rows (such as the next pixel row), so there is no need to set a separate scan driving circuit for the fifth scan signal terminal Scan5.

[0115] A first electrode of the first capacitor C1 is electrically connected to the third node N3 , and a second electrode of the first capacitor C1 is electrically connected to the first node N1 .

[0116] Exemplarily, the first scan signal terminal Scan1 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the second scan signal line 122 corresponding to the previous pixel row, the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the previous pixel row, and the fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the next pixel row. In other words, the scan signal input by the first scan signal terminal Scan1 and the third scan signal terminal Scan3 are output by the same scan driving circuit, and the scan signal input by the fourth scan signal terminal Scan4, the scan signal input by the fifth scan signal terminal Scan5, and the second scan signal terminal Scan2 are output by the same scan driving circuit. In this way, the number of scan driving circuits can be reduced, and the signal line electrically connecting the first scan signal terminal to the second scan signal line corresponding to the previous pixel row can be made shorter, so as to avoid the signal line occupying more of the light-emitting area, which is beneficial to improving the aperture ratio of the pixel.

[0117] The structure of the pixel driving circuit 111 is specifically introduced above. It should be noted that the structures of the control module 1111 and the gating module 1112 are not limited to the above examples, and the structures of the first gating unit 1111a, the second gating unit 1111b, and the third gating unit 1111c in the gating module 1112, as well as the structures of the data writing unit 1112a, the first control unit 1112b, the second control unit 1112c, and the voltage stabilizing unit 1112d in the control module 1111 are not limited to the above examples. Those skilled in the art can set the specific structures of the control module 1111 and the gating module 1112, the specific structures of the first gating unit 1111a, the second gating unit 1111b, and the third gating unit 1111c, as well as the specific structures of the data writing unit 1112a, the first control unit 1112b, the second control unit 1112c, and the voltage stabilizing unit 1112d according to actual conditions. As long as the control module 1111 cooperates with the data signal to control the gating module 1112, and then realizes the control of the refresh frequency of a single pixel 11, they are all within the protection scope of the present application.

[0118] The following is an introduction to the working process of the pixel driving circuit 111 to realize the refresh of a single pixel. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors, and the first scanning signal terminal Scan1 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the second scanning signal line 122 corresponding to the previous pixel row (i.e., the scanning signal line electrically connected to the third scanning signal terminal Scan3 of the previous pixel row), the fourth scanning signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scanning signal line 121 corresponding to the previous pixel row (i.e., the scanning signal line electrically connected to the second scanning signal terminal Scan2 of the previous pixel row), and the fifth scanning signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scanning signal line 121 corresponding to the next pixel row (i.e., the scanning signal line electrically connected to the second scanning signal terminal Scan2 of the next pixel row).

[0119] First, the specific process of refreshing the pixel 11 in the Nth row and the Mth column is described.

[0120] Figure 7 A timing diagram of each signal of the pixel driving circuit is shown. It can be understood that the display panel can include multiple picture update cycles, each picture update cycle corresponds to a frame of the picture, and each frame of the picture corresponds to a refresh. When each pixel is refreshed, it can be divided into a reset stage T1, a data writing stage T2 and a light-emitting stage T3, wherein the setting of the reset stage can avoid the influence of the previous frame of the picture on the current frame of the picture, the setting of the data writing stage can write a new data signal into the pixel 11 to generate a driving current different from the previous frame of the picture, and the setting of the light-emitting stage can emit light corresponding to the driving current based on the driving current generated in the current frame, thereby completing the display and refresh of the current frame of the picture. In the embodiment of the present application, in order to achieve the refresh of a certain single pixel, the reset stage T1, the data writing stage T2 and the light emitting stage T3 are divided into two sub-stages, that is, the reset stage T1 is divided into a first sub-stage (also called a selection sub-stage) T1-1 and a second sub-stage (also called a reset sub-stage) T1-2, the data writing stage T2 is divided into a first sub-stage T2-1 and a second sub-stage T2-2, and the light emitting stage T3 is divided into a first sub-stage T3-1 and a second sub-stage T3-2. In addition, Figure 7In the figure, ScanN represents the scan signal received by the third scan signal terminal Scan3, ScanN-1 represents the scan signal received by the first scan signal terminal Scan1, ScanN+1 represents the scan signal received by the third scan signal terminal Scan3 of the next row of pixels 11, and ScanN-1, ScanN and ScanN+1 are respectively the scan signals output by the N-1th scan signal output terminal, the Nth scan signal output terminal and the N+1th scan signal output terminal of the above-mentioned second scan driving circuit. ScanP represents the scan signal received by the second scan signal terminal Scan2, ScanP-1 represents the scan signal received by the fourth scan signal terminal Scan4, ScanP+1 represents the scan signal received by the fifth scan signal terminal Scan5, and ScanP-1, ScanP and ScanP+1 are respectively the scan signals output by the P-1th scan signal output terminal, the Pth scan signal output terminal and the P+1th scan signal output terminal of the above-mentioned first scan driving circuit. Vdata represents the data signal received by the data signal terminal Data.

[0121] Combined with the timing diagram below, Figure 6 The working process of the pixel driving circuit 111 shown is described.

[0122] In the first sub-phase T1-1 of the reset phase T1: see Figure 8 , Figure 8 : is a working state diagram of each transistor in the first sub-stage of the pixel driving circuit in the reset stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row of pixels 11 is a low-level signal, and the fourth transistor T4 and the sixth transistor T6 are turned on. The data signal Vdata provided by the data signal terminal Data in the Mth column of pixels 11 (the data signal sent by the display driver chip side to the data line 13 corresponding to the Mth column of pixels 11) is a low-level signal, which is written to the gate of the fifth transistor T5 through the turned-on fourth transistor T4, and the fifth transistor T5 is turned on, and the low-level data signal is written to the third node N3, the seventh transistor T7 is turned on, and the signal at the second pole of the seventh transistor T7 is a low-level signal. In other words, the signals at both poles of the first capacitor C1 are low-level signals. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row of pixels 11 is a high-level signal, and the eighth transistor T8 and the ninth transistor T9 are turned off. At this time, the signal at the first node N1 is a low level signal, and the first transistor T1 , the second transistor T2 , and the third transistor T3 are turned on.

[0123] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is at a high level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is at a high level, the reset transistor M4 is turned on, and the data writing transistor M2 is turned off. The initialization signal of the initialization signal terminal Vref1 is written into the gate of the driving transistor M1 (i.e., the control terminal of the driving module) through the turned-on reset transistor M4 and the first transistor T1 to initialize the storage capacitor Cst and the gate of the driving transistor M1, wherein the initialization signal provided by the initialization signal terminal Vref1 is a low level signal to ensure that the driving transistor M1 can be turned on in the next stage.

[0124] In addition, the light-emitting control signal provided by the light-emitting control signal terminal Emit is a high-level signal (not shown in the figure), and the scanning signal provided by the sixth scanning signal terminal Scan6 is a high-level signal (not shown in the figure), the light-emitting control transistors M6 and M7 are turned off, and the gates of the reset transistors M5 and M8 are turned off.

[0125] In the second subphase T1-2 of the reset phase T1: see Fig. 9 , Fig. 9 : is a working state diagram of each transistor in the second sub-stage of the pixel driving circuit in the reset stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row of pixels 11 is still a low-level signal, and the fourth transistor T4 and the sixth transistor T6 continue to be turned on. The data signal Vdata provided by the data signal terminal Data in the Mth column of pixels 11 (the data signal sent by the display driver chip side to the data line 13 corresponding to the Mth column of pixels 11) is a high-level signal, and the high-level signal is written to the gate of the fifth transistor T5 through the turned-on fourth transistor T4, and the fifth transistor T5 is turned off. The high-level data signal cannot be written to the third node N3. Due to the existence of the first capacitor C1, the seventh transistor T7 continues to be turned on. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row of pixels 11 is still a high-level signal, and the eighth transistor T8 and the ninth transistor T9 are still turned off. At this time, the signal at the first node N1 is still a low level signal, and the first transistor T1, the second transistor T2 and the third transistor T3 continue to be turned on.

[0126] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is still at a high level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is still at a high level, the reset transistor M4 is still turned on, and the data writing transistor M2 is still turned off. The initialization signal of the initialization signal terminal Vref1 continues to be written into the gate of the driving transistor M1 (i.e., the control terminal of the driving module) through the turned-on reset transistor M4 and the first transistor T1, so as to continue to initialize the storage capacitor Cst and the gate of the driving transistor M1. That is, in the first sub-stage T1-1 and the second sub-stage T2-1 of the reset stage T1, the storage capacitor Cst and the gate of the driving transistor M1 are initialized.

[0127] In some embodiments, the duration of the first sub-stage T1 - 1 of the reset stage T1 is shorter than the duration of the second sub-stage T2 - 1 of the reset stage T1 , so that the storage capacitor Cst and the gate of the driving transistor M1 can be initialized better.

[0128] In addition, the light control signal provided by the light control signal terminal Emit is still a high level signal, and the scan signal provided by the sixth scan signal terminal Scan6 is still a high level signal, the light control transistors M6 and M7 are still turned off, and the reset transistors M5 and M8 are still turned off.

[0129] It can be understood that in the second sub-stage T1-2 of the reset stage T1, the data signal terminal Data in the Mth column pixel 11 provides a high-level data signal Vdata. Since the N-1th row of pixels is in the data writing stage at this time, the high-level data signal Vdata charges the pixel 11 in the N-1th row and the Mth column. Because the pixels in this row (i.e., the Nth row) are in the reset stage, the high-level data signal Vdata will not affect the pixels 11 in this row.

[0130] In the first sub-phase T2-1 of the data writing phase T2: see Fig.10 , Fig.10: is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the data writing stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row pixel 11 is a high-level signal, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. Due to the existence of the first capacitor C1, the signal at the third node N3 is still a low-level signal, and the seventh transistor T7 is turned on. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row pixel 11 is a high-level signal, and the eighth transistor T8 and the ninth transistor T9 are turned off. Due to the existence of the first capacitor C1, the signal at the first node N1 is a low-level signal at this time, and the first transistor T1, the second transistor T2 and the third transistor T3 are turned on.

[0131] The scan signal ScanN-1 received by the first scan signal terminal Scan1 is low level, the scan signal ScanP received by the second scan signal terminal Scan2 is low level, the reset transistor M4 is turned off, and the data writing transistor M2 is turned on. The scan signal ScanN received by the third scan signal terminal Scan3 is high level, and the threshold compensation transistor M3 is turned on.

[0132] The data signal Vdata provided by the data signal terminal Data in the Mth column pixel 11 (the data signal sent by the display driver chip side to the data line 13 corresponding to the Mth column pixel 11) is a high-level signal. The high-level signal is written to the gate of the driving transistor M1 and the storage capacitor Cst through the turned-on data writing transistor M2, the driving transistor M1, and the threshold compensation transistor M3, so that the gate voltage of the driving transistor M1 gradually increases.

[0133] It can be understood that the first sub-stage T2-1 of the data writing stage T2 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 of the N+1th row and the Mth column pixel 11, and the data signal Vdata provided by the data signal terminal Data at this time can be a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a high-level signal, the high-level signal can be a charging signal of the pixel 11, or it can not be a charging signal of the pixel 11, because the first sub-stage T2-1 of the data writing stage T2 is mainly set to determine whether the N+1th row and the Mth column pixel 11 needs to be refreshed; if the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, the low-level signal makes the state of each transistor of the N+1th row and the Mth column pixel 11 the same as the first sub-stage T1-1 of the reset stage T1 of the Nth row and the Mth column pixel 11 and the second sub-stage T1-2 of the reset stage T1, so as to determine that the N+1th row and the Mth column pixel 11 needs to be refreshed.

[0134] In addition, in this sub-stage, the light-emitting control signal provided by the light-emitting control signal terminal Emit is still a high-level signal (not shown in the figure), and the scanning signal provided by the sixth scanning signal terminal Scan6 is still a high-level signal (not shown in the figure), the light-emitting control transistors M6 and M7 are still turned off, and the reset transistors M5 and M8 are still turned off.

[0135] In the second sub-phase T2-2 of the data writing phase T2, this sub-phase is the actual charging phase: see Fig.11 , Fig.11 : is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the data writing stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row pixel 11 is still a high-level signal, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are still turned off. Due to the existence of the first capacitor C1, the signal at the third node N3 is still a low-level signal, and the seventh transistor T7 is turned on. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row pixel 11 is a high-level signal, and the eighth transistor T8 and the ninth transistor T9 are turned off. Due to the existence of the first capacitor C1, the signal at the first node N1 is still a low-level signal at this time, and the first transistor T1, the second transistor T2 and the third transistor T3 continue to be turned on.

[0136] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is low level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is low level, the reset transistor M4 continues to be turned off, and the data writing transistor M2 continues to be turned on. The scanning signal ScanN received by the third scanning signal terminal Scan3 is high level, and the threshold compensation transistor M3 continues to be turned on.

[0137] The data signal Vdata provided by the data signal terminal Data in the Mth column pixel 11 (the data signal sent by the display driver chip to the data line 13 corresponding to the Mth column pixel 11) is a high-level signal, which is the signal that the Nth row and Mth column pixel 11 actually needs to be charged. The high-level signal is written to the gate of the driving transistor M1 and the storage capacitor Cst through the turned-on data writing transistor M2, the driving transistor M1, and the threshold compensation transistor M3, so that the gate voltage of the driving transistor M1 gradually increases. Until the voltage difference between the gate voltage of the driving transistor M1 and the first electrode of the driving transistor M1 is equal to the threshold voltage V of the driving transistor M1. th , that is, the gate voltage V of the driving transistor M1 N2 =V d -|V th |, where V d The data signal Vdata provided by the data signal terminal Data; the gate voltage of the driving transistor M1 is stored in the storage capacitor Cst.

[0138] In addition, in this sub-stage, the light-emitting control signal provided by the light-emitting control signal terminal Emit is still a high-level signal (not shown in the figure), and the scanning signal provided by the sixth scanning signal terminal Scan6 is still a high-level signal (not shown in the figure), the light-emitting control transistors M6 and M7 are still turned off, and the reset transistors M5 and M8 are still turned off.

[0139] In the first sub-phase T3-1 of the light-emitting phase T3: see Fig.12 , Fig.12: is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the light-emitting stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row of pixels 11 is a high-level signal, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row of pixels 11 is a low-level signal, the eighth transistor T8 and the ninth transistor T9 are turned on, and the high-level scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 is written to the first node N1 through the turned-on eighth transistor T8 and the ninth transistor T9. The high-level signal of the signal at the first node N1 causes the first transistor T1, the second transistor T2 and the third transistor T3 to be turned off, and the first capacitor C1 has two high-level signals at both ends, preventing the first transistor T1, the second transistor T2 and the third transistor T3 from being turned on by mistake in the next frame.

[0140] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is at a low level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is at a high level, the reset transistor M4 is turned off, and the data writing transistor M2 is turned off. The light control signal provided by the light control signal terminal Emit is a low level signal (not shown in the figure), the light control transistors M6 and M7 are turned on, and the power signal voltage V pvdd The first electrode of the driving transistor M1 is written through the turned-on light emitting control transistor M6. At this time, the voltage difference V between the first electrode of the driving transistor M1 and the gate of the driving transistor M1 is sg =V pvdd -V d +|V th |, the driving transistor M1 generates a driving current, and the driving current flows into the light-emitting element 112 through the light-emitting control transistor M7, driving the light-emitting element 112 to emit light. The driving current I d for:

[0141]

[0142] Where μ is the carrier mobility, C ox is the channel capacitance per unit area of ​​the driving transistor M1, and W / L is the width-to-length ratio of the driving transistor M1. It can be seen that the driving current I generated by the driving transistor M1 d The threshold voltage V of the driving transistor M1 th The threshold voltage compensation of the driving transistor M1 is realized, and the display abnormality problem caused by the threshold voltage drift of the driving transistor M1 is solved.

[0143] It can be understood that the first sub-stage T3-1 of the light emitting stage T3 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 of the N+2th row and the Mth column pixel 11, and the data signal Vdata provided by the data signal terminal Data at this time can be a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, the low-level signal makes the state of each transistor of the N+2th row and the Mth column pixel 11 the same as the first sub-stage T1-1 of the reset stage T1 of the Nth row and the Mth column pixel 11 and the second sub-stage T1-2 of the reset stage T1, so as to determine that the N+2th row and the Mth column pixel 11 needs to be refreshed.

[0144] In addition, in this sub-phase, the scan signal provided by the sixth scan signal terminal Scan6 is still a high-level signal (not shown in the figure), and the reset transistors M5 and M8 are still turned off.

[0145] In the second sub-phase T3-2 of the light-emitting phase T3: see Fig.13 , Fig.13 : is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the light-emitting stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The working state of each transistor in this sub-stage and the flow direction of each signal are the same as those of each transistor in the first sub-stage T3-1 of the light-emitting stage T3, and the details can be referred to the description of the first sub-stage T3-1 of the light-emitting stage T3, which will not be repeated here.

[0146] That is, during the light emitting stage, the driving current I generated by the driving transistor M1 of the pixel 11 in the row (i.e., the Nth row) and the Mth column d When the light emitting element 112 is driven to emit light and the pixel 11 in the Nth row and the Mth column is refreshed, since the pixel 11 in the next row (the N+1th row) is in the data writing stage, the scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in this stage is a low-level signal. The low-level signal turns on the eighth transistor T8 and the ninth transistor T9, and the high-level scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 is written to the first node N1 through the turned-on eighth transistor T8 and the ninth transistor T9. The high-level signal of the signal at the first node N1 turns off the first transistor T1, the second transistor T2, and the third transistor T3, and the first capacitor C1 has two high-level signals, which prevents the first transistor T1, the second transistor T2, and the third transistor T3 from being turned on by mistake in the next frame.

[0147] It should be noted that the scanning signal provided by the sixth scanning signal terminal Scan6 turns on the reset transistors M5 and M8, so that the initialization signal of the initialization signal terminal Vref2 is written into the anode of the light-emitting element 112 through the turned-on reset transistor M5, and the anode potential of the light-emitting element 40 is initialized (so as to reduce the influence of the anode voltage of the light-emitting element 40 in the previous frame on the anode voltage of the light-emitting element 40 in the next frame), and the initialization signal of the initialization signal terminal Vref3 is written into the first electrode of the driving transistor M1 through the turned-on reset transistor M8. The time for initializing the first electrode of the driving transistor M1 is not limited in the embodiment of the present application, and those skilled in the art can set it according to actual conditions.

[0148] The above describes the process of refreshing the pixel 11 in the Nth row and the Mth column. It should be noted that N can be any number and M can be any number.

[0149] The following introduces the process of not refreshing the pixel 11 in the Nth row and the Mth column.

[0150] Fig.14 Another timing diagram of various signals of the pixel driving circuit is shown. Fig.14 The meaning of each signal in Figure 7 Same, for details, please refer to Figure 7 The description is not repeated here.

[0151] Combined with the timing diagram below, Figure 6 The working process of the pixel driving circuit 111 shown is described.

[0152] In the first subphase T1-1 of the reset phase T1: see Fig.15 , Fig.15 The working state diagram of each transistor in the first sub-stage of the pixel driving circuit in the reset stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row of pixels 11 is a low-level signal, and the fourth transistor T4 and the sixth transistor T6 are turned on. The data signal Vdata provided by the data signal terminal Data in the Mth column of pixels 11 (the data signal sent by the display driver chip side to the data line 13 corresponding to the Mth column of pixels 11) is the actual required data signal Vdata or high impedance, which is written to the gate of the fifth transistor T5 through the turned-on fourth transistor T4, and the fifth transistor T5 cannot be turned on, thereby causing the seventh transistor T7, the first transistor T1, the second transistor T2 and the third transistor T3 to be turned off.

[0153] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is at a high level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is at a high level, the reset transistor M4 is turned on, and the data writing transistor M2 is turned off. Since the first transistor T1 is turned off, the initialization signal of the initialization signal terminal Vref1 cannot be written into the gate of the driving transistor M1 (i.e., the control terminal of the driving module) through the turned-on reset transistor M4, and the voltage of the gate of the driving transistor M1 is consistent with the previous frame.

[0154] In addition, the light-emitting control signal provided by the light-emitting control signal terminal Emit is a high-level signal (not shown in the figure), and the scanning signal provided by the sixth scanning signal terminal Scan6 is a high-level signal (not shown in the figure), the light-emitting control transistors M6 and M7 are turned off, and the gates of the reset transistors M5 and M8 are turned off.

[0155] In the second subphase T1-2 of the reset phase T1: see Fig.16 , Fig.16 : is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the reset stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The working state of each transistor in this sub-stage and the flow direction of each signal are the same as those of each transistor in the first sub-stage T1-1 of the reset stage T1, and the details can be referred to the description of the first sub-stage T1-1 of the reset stage T1, which will not be repeated here.

[0156] In the first sub-phase T2-1 of the data writing phase T2: see Fig.17 , Fig.17 : is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the data writing stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row pixel 11 is a high-level signal, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. And because the signal at the third node N3 does not become a low-level signal, the seventh transistor T7 cannot be turned on. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row pixel 11 is a high-level signal, and the eighth transistor T8 and the ninth transistor T9 are turned off. And because the signal at the first node N1 does not become a low-level signal, the first transistor T1, the second transistor T2 and the third transistor T3 cannot be turned on. And because the signal at the gate of the threshold compensation transistor M3 does not become a low-level signal, the threshold compensation transistor M3 cannot be turned on.

[0157] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is at a low level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is at a low level, the reset transistor M4 is turned off, and the data writing transistor M2 is turned on.

[0158] The data signal Vdata provided by the data signal terminal Data in the Mth column pixel 11 (the data signal sent by the display driver chip to the data line 13 corresponding to the Mth column pixel 11) cannot be written into the gate of the driving transistor M1, and the gate voltage of the driving transistor M1 is consistent with the previous frame.

[0159] It can be understood that the first sub-stage T2-1 of the data writing stage T2 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 of the N+1th row and the Mth column pixel 11, and the data signal Vdata provided by the data signal terminal Data at this time can be a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a high-level signal, the high-level signal can be a charging signal of the pixel 11, or it can not be a charging signal of the pixel 11, because the first sub-stage T2-1 of the data writing stage T2 is mainly set to determine whether the N+1th row and the Mth column pixel 11 needs to be refreshed; if the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, the low-level signal makes the state of each transistor of the N+1th row and the Mth column pixel 11 the same as the first sub-stage T1-1 of the reset stage T1 of the Nth row and the Mth column pixel 11 and the second sub-stage T1-2 of the reset stage T1, so as to determine that the N+1th row and the Mth column pixel 11 needs to be refreshed.

[0160] In addition, in this sub-stage, the light-emitting control signal provided by the light-emitting control signal terminal Emit is still a high-level signal (not shown in the figure), and the scanning signal provided by the sixth scanning signal terminal Scan6 is still a high-level signal (not shown in the figure), the light-emitting control transistors M6 and M7 are still turned off, and the reset transistors M5 and M8 are still turned off.

[0161] In the second sub-phase T2-2 of the data writing phase T2, this sub-phase is the actual charging phase: see Fig.18 , Fig.18 : is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the data writing stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The working state of each transistor in this sub-stage and the flow direction of each signal are the same as the working state of each transistor and the flow direction of each signal in the first sub-stage T2-1 of the data writing stage T2. For details, please refer to the description of the first sub-stage T2-1 of the data writing stage T2, which will not be repeated here.

[0162] In the first sub-phase T3-1 of the light-emitting phase T3: see Fig.19 , Fig.19 : is a working state diagram of each transistor of the pixel driving circuit in the first sub-stage of the light-emitting stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 in the Nth row of pixels 11 is a high-level signal, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. The scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in the Nth row of pixels 11 is a low-level signal, the eighth transistor T8 and the ninth transistor T9 are turned on, and the high-level scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 is written to the first node N1 through the turned-on eighth transistor T8 and the ninth transistor T9. The high-level signal of the signal at the first node N1 causes the first transistor T1, the second transistor T2 and the third transistor T3 to continue to be turned off, and the first capacitor C1 has high-level signals at both ends, preventing the first transistor T1, the second transistor T2 and the third transistor T3 from being turned on by mistake in the next frame.

[0163] The scanning signal ScanN-1 received by the first scanning signal terminal Scan1 is at a low level, the scanning signal ScanP received by the second scanning signal terminal Scan2 is at a high level, the reset transistor M4 is turned off, and the data writing transistor M2 is turned off. The light control signal provided by the light control signal terminal Emit is a low level signal (not shown in the figure), the light control transistors M6 and M7 are turned on, and the power signal voltage V pvdd The first electrode of the driving transistor M1 is written through the turned-on light-emitting control transistor M6, but since the voltage of the gate of the driving transistor M1 is consistent with that of the previous frame, the voltage difference V between the first electrode of the driving transistor M1 and the gate of the driving transistor M1 is sg =V pvdd -V d +|V th | remains unchanged, the driving current generated by the driving transistor M1 remains unchanged, and the driving current flows into the light-emitting element 112 through the light-emitting control transistor M7, driving the light-emitting element 112 to emit light, that is, maintaining the display of the previous frame.

[0164] It can be understood that the first sub-stage T3-1 of the light emitting stage T3 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 of the N+2th row and the Mth column pixel 11, and the data signal Vdata provided by the data signal terminal Data at this time can be a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, the low-level signal makes the state of each transistor of the N+2th row and the Mth column pixel 11 the same as the first sub-stage T1-1 of the reset stage T1 of the Nth row and the Mth column pixel 11 and the second sub-stage T1-2 of the reset stage T1, so as to determine that the N+2th row and the Mth column pixel 11 needs to be refreshed.

[0165] In addition, in this sub-phase, the scan signal provided by the sixth scan signal terminal Scan6 is still a high-level signal (not shown in the figure), and the reset transistors M5 and M8 are still turned off.

[0166] In the second sub-phase T3-2 of the light-emitting phase T3: see Fig. 20 , Fig. 20 : is a working state diagram of each transistor of the pixel driving circuit in the second sub-stage of the light-emitting stage, wherein the transistor covered with "×" is a non-conducting transistor, and the transistor not covered with "×" is a conducting transistor. The working state of each transistor in this sub-stage and the flow direction of each signal are the same as those of each transistor in the first sub-stage T3-1 of the light-emitting stage T3, and the details can be referred to the description of the first sub-stage T3-1 of the light-emitting stage T3, which will not be repeated here.

[0167] That is to say, in the light-emitting stage, although the voltage of the gate of the driving transistor M1 of the Mth column pixel 11 in the current row (i.e., the Nth row) is consistent with that in the previous frame. However, since the pixels 11 in the next row (the N+1th row) are in the data writing stage, the scanning signal ScanP+1 received by the fifth scanning signal terminal Scan5 in this stage is a low-level signal. The low-level signal turns on the eighth transistor T8 and the ninth transistor T9, and the high-level scanning signal ScanP-1 received by the fourth scanning signal terminal Scan4 is written to the first node N1 through the turned-on eighth transistor T8 and the ninth transistor T9. The high-level signal of the signal at the first node N1 turns off the first transistor T1, the second transistor T2, and the third transistor T3, and the first capacitor C1 has two high-level signals at both ends, which prevents the first transistor T1, the second transistor T2, and the third transistor T3 from being turned on by mistake in the next frame.

[0168] It should be understood that Figure 7 and Fig.14 This is only an example of how to control whether each row of pixels 11 is refreshed by the pixel driving circuit 111. In practical applications, the waveform and timing of each signal are not limited to Figure 7 and14 shown.

[0169] It can be known from the above content that Vdata is the waveform received by the data signal terminal Data of the Mth column, and each row scanning stage (i.e., the time period when the scanning driving circuit outputs the scanning signal) is divided into two time periods, the first sub-stage and the second sub-stage. The first sub-stage of the current row controls whether the display of the next row of pixels 11 in the column is refreshed. If the Vdata of the first sub-stage is a preset low-level signal (the negative voltage of the first transistor T1, the second transistor T2, and the third transistor T3 is turned on), the display content of the next row of pixels 11 in the column is refreshed. If the Vdata of the first sub-stage maintains other signals (such as floating or other non-preset low-level signals), the display content of the next row of pixels 11 in the column is not refreshed; if the display content of the pixel 11 in the current row needs to be refreshed, the Vdata of the second sub-stage is the Vdata actually required by the pixel 11; if the display content of the pixel 11 in the current row does not need to be refreshed, the Vdata of the second sub-stage can be the Vdata of the position in the previous frame, or it can be floating, so as to save power consumption.

[0170] It should be noted that the above content is based on the example that the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the previous pixel row (that is, the scan signal line electrically connected to the second scan signal terminal Scan2 of the previous pixel row), and the fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the next pixel row (that is, the scan signal line electrically connected to the second scan signal terminal Scan2 of the next pixel row). Accordingly, when the scan signal transmitted by the first scan signal line 121 corresponding to the previous pixel row is a low-level signal, the data signal terminal Data of the pixel 11 also transmits a low-level signal, thereby completing the refresh of the pixel 11. In this arrangement, the signal line electrically connecting the fourth scanning signal terminal Scan4 with the first scanning signal line 121 corresponding to the previous pixel row is shorter, and the signal line electrically connecting the fifth scanning signal terminal Scan5 with the first scanning signal line 121 corresponding to the next pixel row is shorter, thereby avoiding the signal line occupying more of the light-emitting area, which is beneficial to improving the aperture ratio of the pixel.

[0171] Of course, this does not constitute a limitation of the present application. Optionally, the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 can also be electrically connected to the first scan signal line 121 corresponding to the upper two pixel rows (that is, the scan signal line electrically connected to the second scan signal terminal Scan2 of the upper two pixel rows). Accordingly, the scan signal transmitted by the first scan signal line 121 corresponding to the upper two pixel rows is a low-level signal. At this moment, the data signal terminal Data of the pixel 11 also transmits a low-level signal, thereby completing the refresh of the pixel 11.

[0172] It can be seen from the above content that when the reset transistor M4 and the threshold compensation transistor M3 are transistors with oxide semiconductor materials as active layers, and the transistors are, for example, N-type transistors, and the driving transistor M1, the data writing transistor M2, the reset transistors M5 and M8, and the light emitting control transistors M6 and M7 are transistors with silicon materials as active layers, and the transistors are, for example, P-type transistors, the working process of the above-mentioned pixel driving circuit is as described above.

[0173] Understandably, see Fig.21 , when the pixel driving module includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light emission control transistors M6 and M7, and a storage capacitor Cst, and the reset transistor M4 and the threshold compensation transistor M3 are transistors with oxide semiconductor materials as active layers, and the driving transistor M1, the data writing transistor M2, the reset transistor M5, the light emission control transistors M6 and M7 are transistors with silicon materials as active layers, the pixel achieves refresh timing and Figure 7 Same, the pixel is not refreshed at the same time Fig.14 same.

[0174] See also Fig. 22 , when the pixel driving module includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light emission control transistors M6 and M7, and a storage capacitor Cst, and the driving transistor M1, the data writing transistor M2, the threshold compensation transistor M3, the reset transistors M4 and M5, and the light emission control transistors M6 and M7 are all transistors with silicon material as an active layer, the timing of the pixel to achieve refresh is as follows Fig.23 As shown, the pixel is not refreshed at the same time Fig.24 As shown, the specific implementation process is similar to the above content, which can be referred to above and will not be repeated here.

[0175] Based on the above structure and working process, Figure 1bThe process of achieving different refresh rates in the three areas of the status bar 101, the video playback area 102, and the static content display area 103 is introduced. Take the video playback area 102 playing advertisements, the static content display area 103 as the video pause screen, the status bar 101 without screen display, the refresh rate of the status bar 101 is 1hz, the refresh rate of the video playback area 102 is 60hz, and the refresh rate of the static content display area 103 is 30hz as an example for explanation. Among them, the status bar 101 includes area A and area E, the video playback area 102 includes area C, and the static content display area 103 includes area B, area G, area D and area F.

[0176] See also Fig.25 , Fig.25 A refresh process of a display screen provided in an embodiment of the present application, wherein the refresh process is a process in which a display driver chip provides a data signal to a display panel. Fig.25 As shown, in the first frame, the scanning driving circuit completes the scanning of all pixel rows, and the data signal terminals corresponding to each pixel 11 are all low level in the first sub-phase T1-1 of the reset phase T1, and the refresh of all pixels is completed, that is, in the first frame, all refreshes of the three areas of the status bar 101, the video playback area 102, and the static content display area 103 are completed; in the second frame, when the scanning driving circuit scans the pixel row corresponding to the area C, the data signal terminals corresponding to the pixel columns in the area C are all low level in the first sub-phase T1-1 of the reset phase T1, and the refresh of the pixels in the area C is completed, that is, in the second frame, only the refresh of the image in the video playback area 102 is completed; in the third frame, when the scanning driving circuit scans the pixel rows corresponding to the large area of ​​area C, area B, area G, area D and area F (that is, all pixel rows), the data signal terminals corresponding to the pixel columns in the large area of ​​area C, area B, area G, area D and area F are all low level. The first sub-stage T1-1 of the reset stage T1 is all low level, completing the refresh of the pixels in area C, area B, area G, area D and area F, that is, completing the partial refresh of the video playback area 102 and the static content display area 103 in the third frame; in the fourth frame, when the scanning drive circuit scans the pixel row corresponding to area C, the data signal end corresponding to the pixel column in area C is all low level in the first sub-stage T1-1 of the reset stage T1, completing the refresh of the pixels in area C, that is, completing only the refresh of the video playback area 102 in the fourth frame; ...; that is, the refresh mode of the second frame and the third frame is cycled in sequence until the sixty-first frame, and then the refresh mode of the first frame to the sixtieth frame is cycled again, so as to realize different refresh rates in different areas in turn, that is, the refresh frequency of the status bar 101 is 1hz, the refresh frequency of the video playback area 102 is 60hz, and the refresh frequency of the static content display area 103 is 30hz.

[0177] It should be noted that the above refresh frequencies are only examples and do not constitute a limitation on the present application. Those skilled in the art can set different refresh frequencies corresponding to different areas according to actual conditions.

[0178] It should also be noted that the above example is based on the example of three areas corresponding to different refresh frequencies, but it does not constitute a limitation on the present application. Since the pixel driving circuit provided in the embodiment of the present application can realize the refresh of any single pixel, therefore, in other optional embodiments of the present application, four areas may correspond to different refresh frequencies, five areas may correspond to different refresh frequencies, etc., and the refresh frequencies of two non-adjacent areas may be the same, and the refresh of areas formed by arbitrary shapes may be performed, etc. For example, Fig.26 As shown, only the pixels in area E are refreshed. Specifically, when the pixel row corresponding to area E is scanned, the data signal terminals corresponding to the pixel columns in area E are all low level in the first sub-stage T1-1 of the reset stage T1, and the pixels in area E are refreshed.

[0179] In summary, without changing the scanning drive circuit and the light emitting control drive circuit, the pixel drive circuit provided in the embodiment of the present application can make any single pixel 11 in the display panel 10 refresh the data signal at different refresh rates, that is, different areas and different positions of the display panel 10 refresh the display content at different refresh rates. For areas where the display picture / text does not change, the display content can be refreshed at a lower refresh rate, for example, refreshing the display content at a refresh rate of 1Hz or 10Hz. For areas that change in real time such as displaying videos, the display content can be refreshed at a higher refresh rate, for example, refreshing the display content at a refresh rate of 60Hz. In this way, since the refresh rate of the display panel 10 is reduced, the power consumption of the display panel is reduced. And the pixel drive circuit provided in the embodiment of the present application can not only realize local refresh of local areas, but also realize local refresh of areas formed by arbitrary shapes.

[0180] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixels, each pixel comprising a pixel driving circuit and a light emitting element; The pixel driving circuit comprises a pixel driving module, a gating module, a control module, a data signal terminal and a reset signal terminal, the gating module is electrically connected to the control module and the pixel driving module respectively, and the control module is electrically connected to the data signal terminal; The data signal terminal is used to transmit data signals; The reset signal terminal is used to transmit a reset signal; The display panel further includes a plurality of picture update cycles, wherein the picture update cycle includes a reset phase, a data writing phase and a light emitting phase; the reset phase includes a selection sub-phase and a reset sub-phase; In the selection sub-stage, the control module is used to control the gating module to be turned on or off according to the data signal written by the data signal terminal; When the selection module is turned on, in the reset sub-stage, the reset signal is written into the pixel driving module to reset the pixel driving module; in the data writing stage, the data signal is written into the pixel driving module to enable the pixel driving module to generate a driving current, and in the light emitting stage, the driving current is provided to the light emitting element to enable the light emitting element to emit light corresponding to the driving current.

2. The display panel according to claim 1, characterized in that: The gating module comprises a first gating unit, a second gating unit and a third gating unit; The pixel driving module includes a driving module; The control module, the control end of the first gating unit, the control end of the second gating unit and the control end of the third gating unit are coupled to the first node; The control module is used to send a control signal to the control terminals of the first gating unit, the second gating unit and the third gating unit in the selection sub-phase according to the data signal written by the data signal terminal, so as to control the first gating unit, the second gating unit and the third gating unit to be turned on or off; When the first gating unit is turned on, in the reset sub-stage, the reset signal is written to the control end of the driving module to reset the control end of the driving module; when the second gating unit and the third gating unit are turned on, in the data writing stage, the driving module generates a driving current according to the data signal.

3. The display panel according to claim 2, characterized in that: The pixel driving module further includes a first reset module, a threshold compensation module and a data writing module, and the pixel driving circuit further includes a first scanning signal terminal, a second scanning signal terminal and a third scanning signal terminal; A first end of the first reset module is electrically connected to the reset signal end, a second end of the first reset module is electrically connected to a first end of the first gating unit, a control end of the first reset module is electrically connected to the first scanning signal end, and a second end of the first gating unit, a control end of the driving module and a first end of the threshold compensation module are coupled to a second node; The first end of the data writing module is electrically connected to the data signal end, the second end of the data writing module is electrically connected to the first end of the second gating unit, the control end of the data writing module is electrically connected to the second scanning signal end, the second end of the second gating unit is electrically connected to the first end of the driving module, and the second end of the driving module is electrically connected to the second end of the threshold compensation module; The control end of the threshold compensation module is electrically connected to the first end of the third gating unit, and the second end of the third gating unit is electrically connected to the third scan signal end.

4. The display panel according to claim 3, characterized in that: The first gating unit includes a first transistor; The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second end of the first reset module, and the second electrode of the first transistor is electrically connected to the second node.

5. The display panel according to claim 3 or 4, characterized in that: The second gating unit includes a second transistor; The gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second end of the data writing module, and the second electrode of the second transistor is electrically connected to the first end of the driving module.

6. The display panel according to any one of claims 3 to 5, characterized in that: The third gating unit includes a third transistor; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control end of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal end.

7. The display panel according to any one of claims 1 to 6, characterized in that: The control module includes a data writing unit, a first control unit and a second control unit; the data writing unit, the first control unit and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-phase, in the reset sub-phase and the data writing phase, the first control unit is used to control the gating module to continue to be turned on; In the light emitting stage, the second control unit is used to control the gating module to be turned off.

8. The display panel according to claim 7, characterized in that: The control module also includes a voltage stabilizing unit, a first end of the voltage stabilizing unit, the data writing unit, the first control unit and the second control unit are coupled to a third node, and a second end of the voltage stabilizing unit, the first control unit, the second control unit and the selection module are coupled to a first node.

9. The display panel according to claim 8, characterized in that: The voltage stabilizing unit includes a first capacitor, a first electrode of the first capacitor, the data writing unit, the first control unit and the second control unit are coupled to a third node, and a second electrode of the first capacitor, the first control unit, the second control unit and the gating module are coupled to a first node.

10. The display panel according to any one of claims 8 or 9, characterized in that: The pixel driving circuit further includes a fourth scanning signal terminal; The data writing unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the fourth scanning signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor and the gate of the fifth transistor, and the second electrode of the fifth transistor is electrically connected to the third node.

11. The display panel according to any one of claims 8 to 10, characterized in that: The pixel driving circuit further includes a fourth scanning signal terminal; The first control unit includes a sixth transistor and a seventh transistor, the first electrode of the sixth transistor and the gate of the sixth transistor are electrically connected to the fourth scanning signal terminal, the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor, the second electrode of the seventh transistor is electrically connected to the selection module, and the gate of the seventh transistor is electrically connected to the third node.

12. The display panel according to any one of claims 8 to 11, characterized in that: The pixel driving circuit further includes a fourth scanning signal terminal and a fifth scanning signal terminal; The second control unit includes an eighth transistor and a ninth transistor, the gate of the eighth transistor and the gate of the ninth transistor are both electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth scan signal terminal, the second electrode of the eighth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the selection module.

13. The display panel according to any one of claims 1 to 12, characterized in that: The effective level duration of the selection sub-phase is shorter than the effective level duration of the reset sub-phase.

14. The display panel according to any one of claims 1 to 13, characterized in that: Multiple pixel arrays are arranged; The display panel also includes a driving circuit and a plurality of scanning line groups; The driving circuit at least includes a first scanning driving circuit and a second scanning driving circuit, and the scanning line group at least includes a first scanning signal line and a second scanning signal line; The first scan driving circuit includes a plurality of first scan signal output terminals, and the second scan driving circuit includes a plurality of second scan signal output terminals, wherein the plurality of first scan signal output terminals are electrically connected to the plurality of first scan signal lines in a one-to-one correspondence, and the plurality of second scan signal output terminals are electrically connected to the plurality of second scan signal lines in a one-to-one correspondence; The pixel driving circuit further includes a first scanning signal terminal, a second scanning signal terminal, a third scanning signal terminal, a fourth scanning signal terminal and a fifth scanning signal terminal; The second scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the same first scanning signal line, the third scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the same second scanning signal line, the first scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scanning signal line corresponding to other pixel rows, the fourth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to other pixel rows, and the fifth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to other pixel rows.

15. The display panel according to claim 14, characterized in that: The first scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scanning signal line corresponding to the previous pixel row, the fourth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to the previous pixel row, and the fifth scanning signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scanning signal line corresponding to the next pixel row.

16. An electronic device, characterized in that: Comprising a display panel as described in any one of claims 1-15.

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