Display device

Abstract

Provided is a display device which is provided with a GDM circuit including an oxide semiconductor TFT, and which is suitable for use as an In-cell (in-cell) touch panel. The display device includes a scanning signal line driving circuit capable of alternately switching between a driving period and a non-driving period in one vertical scanning period. A unit circuit of the scanning signal line driving circuit includes a clock terminal, a set terminal, a reset terminal, an output terminal, and first, second, and third thin film transistors. A gate electrode of the second thin film transistor is electrically connected to the set terminal, and one of a source electrode and a drain electrode of the second thin film transistor is electrically connected to the internal node. The gate electrode of the second thin film transistor is an upper gate electrode disposed above the semiconductor layer, and the other of the source electrode and the drain electrode of the second thin film transistor is electrically connected to a high-potential-side power supply line. The second thin film transistor further has a lower gate electrode disposed below the semiconductor layer and electrically connected to a low-potential-side power supply line.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] The active matrix substrate used in a liquid crystal display device, an organic electroluminescent (EL) display device, etc. has a display area and a non-display area. The display area has a plurality of pixels, and the non-display area (sometimes also referred to as a "frame area") is located around the display area. In the display area, a thin film transistor (hereinafter referred to as "TFT") is provided in each pixel. As the TFT provided for each pixel, a TFT using an amorphous silicon film as an active layer (hereinafter referred to as an "amorphous silicon TFT") and a TFT using a polycrystalline silicon film as an active layer (hereinafter referred to as a "polycrystalline silicon TFT") are currently widely used.

[0003] As the material of the active layer of TFT, it is proposed to use oxide semiconductor instead of amorphous silicon or polycrystalline silicon. Such TFT is called "oxide semiconductor TFT". Oxide semiconductor has higher mobility than amorphous silicon. Therefore, oxide semiconductor TFT has the ability to operate at a higher speed than amorphous silicon TFT.

[0004] The structure of TFT is roughly divided into bottom gate structure and top gate structure. At present, the bottom gate structure is mostly used in oxide semiconductor TFT, but the use of top gate structure has also been proposed (for example, Patent Document 1). In the top gate structure, the gate insulating layer can be made thinner, so that higher current supply performance can be obtained.

[0005] In the non-display area of ​​the active matrix substrate, a peripheral circuit including a TFT is sometimes formed in a monolithic (integrated) manner. By forming the peripheral circuit in a monolithic manner, it is possible to achieve a narrowing of the non-display area (narrowing of the frame) and a reduction in cost due to the simplification of the installation process. For example, there is a case where a gate driver circuit is formed in a monolithic manner in the non-display area, and a source driver circuit is installed in a COG (Chip on Glass) manner. A gate driver circuit formed in a monolithic manner is called a GDM (Gate Driver Monolithic: gate driver monolithic) circuit. Patent document 2 discloses a liquid crystal display device in which a GDM circuit is formed on an active matrix substrate.

[0006] In this specification, the TFTs of each pixel arranged in the display area are referred to as "pixel TFTs". In addition, the TFTs constituting the peripheral circuits arranged in the non-display area are referred to as "peripheral circuit TFTs". When the pixel TFTs are oxide semiconductor TFTs, the peripheral circuit TFTs are also preferably oxide semiconductor TFTs from the viewpoint of the manufacturing process.

[0007] On the other hand, in recent years, display devices equipped with touch sensors (referred to as "touch panels") have been widely used in smartphones, tablet computers, etc. As the type of touch sensors, various types such as resistive film type, electrostatic capacitance type, and optical type are known.

[0008] Display devices with touch sensors (hereinafter referred to as "touch panels") are generally divided into a method in which the touch sensor is mounted externally on the display device ("external type") and a method in which the touch sensor is built into the display device ("built-in type"). Built-in touch panels are more advantageous in terms of thinness and weight than external touch panels, and have the advantage of increased light transmittance.

[0009] There are two types of built-in touch panels: On-cell (covered surface) type and In-cell (embedded) type. Here, "cell" refers to the display panel. In the In-cell type, the layer that performs the touch sensor function is provided inside the display panel. In the On-cell type, the layer that performs the touch sensor function is arranged between the display panel and the polarizing plate provided on the observer side of the display panel. Prior art literature Patent Literature

[0010] Patent Document 1: Japanese Patent Application Publication No. 2015-109315 Patent Document 2: International Patent Publication No. 2011 / 055584 Summary of the invention Technical Problems to be Solved by the Invention

[0011] The In-cell type can realize the thinnest and lightest touch panel in principle. However, when a GDM circuit including an oxide semiconductor TFT is formed in an In-cell type touch panel, various problems as described below may occur.

[0012] The embodiments of the present invention have been made in view of the above-mentioned problems, and an object of the present invention is to provide a display device including a GDM circuit including an oxide semiconductor TFT and suitable for use as an In-cell type touch panel. Solutions to the problem

[0013] This specification discloses a display device described in the following items.

[0014] [Project 1] A display device comprising: A display panel having a plurality of scanning signal lines; and a scanning signal line driving circuit, which drives the plurality of scanning signal lines, The scanning signal line driving circuit can alternately switch between a driving period and a non-driving period during one vertical scanning period, and makes the plurality of scanning signal lines sequentially selected during the driving period, and does not drive the plurality of scanning signal lines during the non-driving period. In the display device, The display panel further includes a high potential side power line and a low potential side power line, and the scanning signal line driving circuit includes a shift register circuit including a plurality of stages, and the unit circuits constituting each of the plurality of stages include: a clock terminal to which a clock signal is input; a set terminal to which a set signal is input; a reset terminal to which a reset signal is input; an output terminal electrically connected to a corresponding scan signal line among the plurality of scan signal lines and outputting a scan signal; A first thin film transistor having a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is electrically connected to an internal node, one of the first source electrode and the first drain electrode is electrically connected to the clock terminal, and the other of the first source electrode and the first drain electrode is electrically connected to the output terminal; a second thin film transistor having a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is electrically connected to the set terminal, and one of the second source electrode and the second drain electrode is electrically connected to the internal node; and a third thin film transistor having a third semiconductor layer, a third gate electrode, a third source electrode and a third drain electrode, wherein the third gate electrode is electrically connected to the reset terminal, and one of the third source electrode and the third drain electrode is electrically connected to the internal node; The second gate electrode of the second thin film transistor is an upper gate electrode disposed above the second semiconductor layer via a gate insulating layer. The other of the second source electrode and the second drain electrode of the second thin film transistor is electrically connected to the high potential side power supply line, The second thin film transistor further includes a lower gate electrode, which is arranged below the second semiconductor layer, faces the channel region of the second semiconductor layer via a lower insulating layer, and is electrically connected to the low potential side power supply line.

[0015] [Project 2] In the display device according to item 1, the unit circuit further includes a capacitor including a pair of electrodes, one of the pair of electrodes is electrically connected to the internal node, and the other of the pair of electrodes is electrically connected to the output terminal.

[0016] [Item 3] In the display device according to item 1 or 2, a control signal is applied to the other of the third source electrode and the third drain electrode of the third thin film transistor, and the control signal is at a first potential lower than the threshold voltage of the first thin film transistor during the driving period, and is at a second potential higher than the first potential during at least a part of the non-driving period.

[0017] [Item 4] In the display device according to any one of items 1 to 3, the display panel further comprises: a plurality of electrodes for a touch sensor to which mutually different signals can be applied; and A plurality of wirings for the touch sensor, each of which is electrically connected to a corresponding electrode among the plurality of electrodes, During the non-driving period, the touch sensor is driven.

[0018] [Item 5] In the display device according to any one of items 1 to 4, the display panel has an active matrix substrate including the plurality of scanning signal lines. The scanning signal line driving circuit is formed monolithically on the active matrix substrate.

[0019] [Item 6] In the display device according to any one of items 1 to 5, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are respectively oxide semiconductor layers.

[0020] [Item 7] In the display device according to item 6, the oxide semiconductor layer includes an In-Ga-Zn-O based semiconductor. Effects of the Invention

[0021] According to the embodiment of the present invention, it is possible to provide a display device including a GDM circuit including an oxide semiconductor TFT and suitable for use as an In-cell touch panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 2 is a schematic cross-sectional view schematically showing a liquid crystal display device 100 according to an embodiment of the present invention. Figure 2 1 is a schematic plan view schematically showing the liquid crystal display device 100 . Figure 3 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100 . Figure 41 is a plan view illustrating the arrangement relationship between the touch sensor electrodes TX and the touch wirings TL in the liquid crystal display device 100 . Figure 5 : is a timing chart showing an example of the gate clock signal GCK in one vertical scanning period. Figure 6 2 is a block diagram showing the configuration of the shift register circuit 41 included in the gate driver 40 . Figure 7 2 is a circuit diagram showing an example of the configuration of the unit circuit SR (the configuration of each stage of the shift register circuit 41 ). Figure 8 1 is a cross-sectional view schematically showing a region of the TFT substrate 10 where the second transistor MB is provided. Fig. 9 It is a timing diagram for explaining the operation of the unit circuit. Fig.10 : is a circuit diagram showing the configuration of a unit circuit SRA of a gate driver included in the touch panel of Comparative Example 1. Fig.11 1 is a diagram showing the potentials of the internal node netA and each signal during the non-driving period T2 of the n-th stage unit circuit SRAn of the touch panel of Comparative Example 1. FIG. Fig.12 : is a circuit diagram showing the configuration of a unit circuit SRB of a gate driver included in the touch panel of Comparative Example 2. Fig.13 1 is a diagram showing the potentials of the internal node netA and each signal during the non-driving period T2 of the n-th stage unit circuit SRBn of the touch panel of Comparative Example 2. Fig.14 1 is a diagram showing the relationship between the potentials of the internal node netA and the set signal S when the second transistor MB of the unit circuit SRA of Comparative Example 1 is not selected, charged (precharged), boosted, just before reset and in the non-driving period T2, and the presence or absence of bias. Fig.15 1 and 2. It is a diagram showing the relationship between the potentials of the internal node netA and the set signal S when the second transistor MB of the unit circuit SRB of Comparative Example 2 is not selected, is charged, is boosted, immediately before resetting, and during the non-driving period T2, and the presence or absence of bias. Fig.16 3 is a graph showing the relationship between the gate voltage Vg and the drain current Id of Reference Example 1 (gate voltage-drain current characteristics). Fig.17 3 is a graph showing the relationship between the gate voltage Vg and the drain current Id in Example 1 (gate voltage-drain current characteristics). Fig.183 is a graph showing the relationship between the gate voltage Vg and the drain current Id of Reference Example 2 (gate voltage-drain current characteristics). Fig.19 3 is a graph showing the relationship between the gate voltage Vg and the drain current Id (gate voltage-drain current characteristics) in Example 2. Fig. 20 is a cross-sectional view schematically showing a region of the TFT substrate where the first transistor MA is provided. Fig.21 1 is a cross-sectional view schematically showing a region of the TFT substrate 10 where the third transistor MC is provided. DETAILED DESCRIPTION

[0023] The following describes an embodiment of the present invention with reference to the accompanying drawings. In addition, as a display device according to an embodiment of the present invention, a liquid crystal display device is exemplified below, but the display device according to an embodiment of the present invention is not limited to a liquid crystal display device. In addition, the thin film transistor in the following description is an n-type TFT, and the electrical connection relationship when using an n-type TFT is described. It should be noted that the electrical connection of the source and drain of the p-type TFT is opposite to the electrical connection of the source and drain of the n-type TFT.

[0024] [Schematic Structure of Liquid Crystal Display Device] First, refer to Figure 1 , Figure 2 and Figure 3 A schematic configuration of a liquid crystal display device 100 according to an embodiment of the present invention will be described. The liquid crystal display device 100 is an in-cell type touch panel. Figure 1 as well as Figure 2 Each of the diagrams is a schematic cross-sectional view and a schematic top view schematically showing the liquid crystal display device 100 . Figure 3 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100 .

[0025] like Figure 1 As shown, the liquid crystal display device 100 includes a display panel 1. The display panel 1 includes an active matrix substrate (hereinafter referred to as a "TFT substrate") 10, an opposing substrate (sometimes also referred to as a "color filter substrate") 20 disposed opposite to the TFT substrate 10, and a liquid crystal layer 30 provided between the TFT substrate 10 and the opposing substrate 20.

[0026] like Figure 2 As shown, the liquid crystal display device 100 has a display area DR and a non-display area (also called a "frame area") FR. The display area DR is defined by a plurality of pixels P. The plurality of pixels P are arranged in a matrix including a plurality of rows and a plurality of columns. The non-display area FR is located around the display area DR and is an area that does not contribute to the display.

[0027] The display panel 1 (more specifically, the TFT substrate 10) of the liquid crystal display device 100 has a plurality of (i) gate bus lines (scanning signal lines) GL1 to GLi and a plurality of (j) source bus lines (image signal lines) SL1 to SLj. The gate bus lines GL1 to GLi (sometimes collectively referred to as "gate bus lines GL") extend in the row direction, and the source bus lines SL1 to SLj (sometimes collectively referred to as "source bus lines SL") extend in the column direction (a direction substantially orthogonal to the row direction).

[0028] like Figure 3 As shown, a thin film transistor (pixel TFT) 11 and a pixel electrode PE are provided in each pixel P. The pixel TFT 11 is supplied with a scanning signal (gate signal) from the corresponding gate bus GL, and is supplied with a display signal (source signal) from the corresponding source bus SL. The pixel TFT 11 is an oxide semiconductor TFT having an oxide semiconductor layer as an active layer. The pixel electrode PE is electrically connected to the pixel TFT 11. A common electrode CE is arranged in a manner opposite to the pixel electrode PE.

[0029] The liquid crystal display device 100 further includes a gate driver (scanning signal line driving circuit) 40 that drives the gate bus lines GL1 to GLi and a source driver (video signal line driving circuit) 50 that drives the source bus lines SL1 to SLj. The gate driver 40 and the source driver 50 are disposed in the non-display region FR.

[0030] The gate driver 40 sequentially puts the plurality of gate bus lines GL1 to GLi into a selected state (a state in which a scanning signal is applied with a high-level potential). The gate driver 40 has a shift register circuit 41 including a plurality of stages (here, i stages). The plurality of stages are arranged along the column direction. The plurality of stages are respectively composed of a unit circuit SR. That is, the shift register circuit 41 has a plurality of (here, i) unit circuits SR1 to SRi. Here, the gate driver 40 is formed as a single chip on the active matrix substrate 10. That is, the gate driver 40 is a GDM circuit.

[0031] As already described, the liquid crystal display device 100 is an In-cell type touch panel. Figure 4 , the configuration of electrodes and wiring used in the touch sensor is explained.

[0032] like Figure 4 As shown, in the display region DR, the common electrode CE is divided into a plurality of segments TX. Since different signals (voltages) can be applied, the plurality of segments TX can function as electrodes for touch sensors (hereinafter referred to as "touch sensor electrodes"). That is, the display panel 1 has a plurality of touch sensor electrodes TX. Each touch sensor electrode TX is provided corresponding to two or more pixels P.

[0033] In addition, the display panel 1 also has a plurality of wirings (hereinafter referred to as "touch wirings") TL for touch sensors. Each touch wiring TL is electrically connected to a corresponding touch sensor electrode TX among a plurality of touch sensor electrodes TX. The connection portion TC between the touch sensor electrode TX and the touch wiring TL is called a "touch wiring contact portion". In the example shown in the figure, the touch wiring TL extends in the column direction (the same direction as the source bus SL). A portion of the touch wiring TL extends across one or more other touch sensor electrodes TX to the corresponding touch sensor electrode TX.

[0034] If we focus on a certain touch sensor electrode TX, the first touch wiring TL1 that provides a signal to the touch sensor electrode TX extends to the touch wiring contact portion TC, and the second touch wiring TL2 that provides a signal to other touch sensor electrodes TX extends across the touch sensor electrode TX. In addition, depending on the position of the touch sensor electrode TX, there may be a case where two or more touch wirings TL are configured to extend across the touch sensor electrode TX, and there may also be a case where no touch wiring TL is configured to extend across the touch sensor electrode TX.

[0035] The touch wiring TL is connected to a touch drive unit TD provided in the non-display region FR. The touch drive unit TD is configured, for example, to switch between a display mode in which a plurality of touch sensor electrodes TX function as a common electrode CE and a touch detection mode in which a plurality of touch sensor electrodes TX function in a time-sharing manner. For example, in the display mode, the touch drive unit TD applies a common signal to the touch sensor electrode TX (common electrode CE) via the touch wiring TL. On the other hand, in the touch detection mode, the touch drive unit TD applies a touch drive signal to the touch sensor electrode TX via the touch wiring TL.

[0036] Figure 5 1 is a timing diagram showing an example of a gate clock signal GCK in one vertical scanning period. Figure 5 As shown, during one vertical scanning period, the gate driver 40 can alternately switch between a driving period T1 in which the gate buses GL1 to GLi are sequentially selected and a non-driving period T2 in which the gate buses GL1 to GLi are not driven (i.e., the gate clock signal GCK remains at a low level). During the non-driving period T2, the touch sensor is driven.

[0037] [Configuration of the shift register circuit of the gate driver] Reference Figure 6 The configuration of the shift register circuit 41 of the gate driver 40 will be described. Figure 6 2 is a block diagram showing the configuration of the shift register circuit 41 . Figure 6The shift register circuit 41 includes a plurality of unit circuits SR1 to SRi, and an n-th unit circuit SRn that supplies a scanning signal to the gate bus line GLn of the n-th row is exemplified. Figure 6 As shown in the example, each unit circuit SR is provided with a clock terminal to which a gate clock signal GCK is input, a set terminal to which a set signal S is input, and a reset terminal to which a reset signal R is input. In addition, each unit circuit SR is also provided with a high-level power supply terminal to which a high-level power supply potential VDD is input, a low-level power supply terminal to which a low-level power supply potential VSS is input, a control terminal to which a control signal VTP is input, and an output terminal to output a scanning signal Gout. The display panel 1 has: a wiring for supplying a high-level power supply potential VDD (hereinafter referred to as a "high-potential side power supply line VDD"); and a wiring for supplying a low-level power supply potential VSS (hereinafter referred to as a "low-potential side power supply line VSS").

[0038] A gate clock signal GCK is input to each unit circuit SR. As the gate clock signal GCK, a multi-phase clock signal such as a 4-phase, 6-phase or 8-phase is used. In addition, a gate start pulse signal or a scanning signal Gout output from another stage is provided to each unit circuit SR as a set signal S, and the scanning signal Gout output from another stage is used as a reset signal R. In addition, a control signal VTP is input to each unit circuit SR. The control signal VTP is a signal that becomes a low-level potential during the driving period T1 and becomes a high-level potential during at least a portion of the non-driving period T2 (typically, during the entire non-driving period T2). In addition, a scanning signal Gout is output from each unit circuit SR.

[0039] [Unit circuit configuration] Figure 7 4 is a circuit diagram showing an example of the configuration of the unit circuit SR (the configuration of each stage of the shift register circuit 41). Figure 7 As shown, the unit circuit SR includes: a first thin film transistor (hereinafter referred to as "first transistor") MA, a second thin film transistor (hereinafter referred to as "second transistor") MB, a third thin film transistor (hereinafter referred to as "third transistor") MC and a capacitor Cb.

[0040] The first transistor MA functions as an "output transistor" that outputs a scanning signal Gout to a corresponding gate bus GL. The gate electrode of the first transistor MA is electrically connected to the internal node netA. In addition, the drain electrode of the first transistor MA is electrically connected to the clock terminal, and the source electrode of the first transistor MA is electrically connected to the output terminal.

[0041] The second transistor MB functions as a "setting transistor" for precharging (boosting) the internal node netA. The gate electrode of the second transistor MB (referred to as the "upper gate electrode" as described later) is electrically connected to the set terminal. In addition, the drain electrode of the second transistor MB is electrically connected to the high-level power supply terminal (i.e., electrically connected to the high-potential side power supply line VDD), and the source electrode of the second transistor MB is electrically connected to the internal node netA.

[0042] The third transistor MC functions as a "reset transistor" for stepping down the internal node netA. The gate electrode of the third transistor MC is electrically connected to the reset terminal. In addition, the drain electrode of the third transistor MC is electrically connected to the internal node netA, and the source electrode of the third transistor MC is electrically connected to the control terminal.

[0043] The capacitor Cb holds the voltage of the internal node netA precharged by the second transistor MB. One of a pair of electrodes included in the capacitor Cb is electrically connected to the internal node netA, and the other is electrically connected to the output terminal.

[0044] The semiconductor layers of the first transistor MA, the second transistor MB, and the third transistor MC are oxide semiconductor layers, that is, the first transistor MA, the second transistor MB, and the third transistor MC are oxide semiconductor TFTs.

[0045] Here, the structure of the second transistor MB is described. Figure 8 FIG. 1 is a cross-sectional view schematically showing a region of the TFT substrate 10 where the second transistor MB is provided. Figure 8 The region shown includes a substrate 10 a , a light shielding layer 12 , and a second transistor MB.

[0046] The substrate 10a is transparent and has insulating properties. The substrate 10a is, for example, a glass substrate or a plastic substrate. The substrate 10a supports the second transistor MB and the like.

[0047] The light shielding layer 12 is provided on the substrate 10 a. The light shielding layer 12 is formed of a material having light shielding properties and electrical conductivity (for example, a metal material). A lower insulating layer 13 is provided so as to cover the light shielding layer 12 .

[0048] The second transistor MB includes an oxide semiconductor layer 14 disposed on the lower insulating layer 13, a gate insulating layer 15 disposed on the oxide semiconductor layer 14, and a gate electrode 16 disposed so as to face the oxide semiconductor layer 14 via the gate insulating layer 15. The second transistor MB further includes a source electrode 17 and a drain electrode 18 electrically connected to the oxide semiconductor layer 14.

[0049] The gate electrode 16 is electrically connected to the set terminal. The gate electrode 16 is arranged above the oxide semiconductor layer 14 via the gate insulating layer 15, so the gate electrode 16 is also referred to as the "upper gate electrode" below. The source electrode 17 is electrically connected to the internal node netA. The drain electrode 18 is electrically connected to the high potential side power line VDD (i.e., the high level power terminal).

[0050] The gate insulating layer 15 is formed on the oxide semiconductor layer 14 so as to overlap with a part of the oxide semiconductor layer 14 in a plan view.

[0051] The oxide semiconductor layer 14 includes a channel region 14a and a first low resistance region 14b and a second low resistance region 14c located on both sides of the channel region 14a. The channel region 14a overlaps with the gate insulating layer 15 (and the upper gate electrode 16) when viewed from above. The first low resistance region 14b and the second low resistance region 14c do not overlap with the gate insulating layer 15 (and the upper gate electrode 16) when viewed from above, and have a resistivity lower than that of the channel region 14a. The first low resistance region 14b is located on the source electrode 17 side of the channel region 14a. The second low resistance region 14c is located on the drain electrode 18 side of the channel region 14a. The first low resistance region 14b and the second low resistance region 14c can be formed, for example, by performing a low resistance treatment on the oxide semiconductor layer 14 using the upper gate electrode 16 and the gate insulating layer 15 as masks.

[0052] An upper insulating layer 19 is disposed on the oxide semiconductor layer 14, the gate insulating layer 15, and the upper gate electrode 16. The source electrode 17 is disposed in an opening (source-side opening) 19a formed on the upper insulating layer 19 and in the upper insulating layer 19, and is connected to a portion of the oxide semiconductor layer 14 (a portion of the first low-resistance region 14b) in the source-side opening 19a. Similarly, the drain electrode 18 is disposed in an opening (drain-side opening) 19b formed on the upper insulating layer 19 and in the upper insulating layer 19, and is connected to another portion of the oxide semiconductor layer 14 (a portion of the second low-resistance region 14c) in the drain-side opening 19b.

[0053] The light shielding layer 12 is disposed below the oxide semiconductor layer 14 and faces the channel region 14a of the oxide semiconductor layer 14 via the lower insulating layer 13. Therefore, the light shielding layer 12 functions as the "lower gate electrode" of the second transistor MB by applying a predetermined potential. Figure 7 As shown, the lower gate electrode (light shielding layer) 12 is electrically connected to the low potential side power supply line VSS, and a low level power supply potential VSS is applied thereto.

[0054] In addition, although not shown here, the second transistor MB is covered by the interlayer insulating layer. In the display region DR, a pixel electrode PE and the like are provided on the interlayer insulating layer. The pixel electrode PE is formed of a transparent conductive material (e.g., ITO or IZO). When the display mode of the liquid crystal display device 100 is an FFS mode (a type of lateral electric field mode), the TFT substrate 10 further includes a common electrode CE that is opposite to the pixel electrode PE via a dielectric layer. The common electrode CE is formed of a transparent conductive material (e.g., ITO or IZO).

[0055] [Unit Circuit Operation] Reference Fig. 9 The operation of the unit circuit SR will be described. Fig. 9 It is a timing diagram for explaining the operation of the unit circuit SR, and shows the potentials of the gate clock signal GCK, the scan signal Gout, the set signal S, the reset signal R, the internal node netA, the high potential side power line VDD, and the low potential side power line VSS.

[0056] like Fig. 9 As shown, in the period before time t1, the potential of the set signal S, the potential of the internal node netA, and the potential of the scanning signal Gout are maintained at a low level. When reaching time t1, the set signal S changes from a low level to a high level. As a result, since the second transistor MB becomes conductive, the capacitor Cb is charged during the period from time t1 to t2, and the potential of the internal node netA rises.

[0057] When the time t2 is reached, the gate clock signal GCK changes from a low level to a high level. Along with this, the drain potential of the first transistor MA rises. At this time, the first transistor MA becomes a conducting state, so the potential of the scanning signal Gout (the potential of the output terminal) also rises. When the potential of the output terminal rises, the potential of the internal node netA further rises via the capacitor Cb (the internal node netA becomes a boosted state). As a result, since a larger voltage is applied to the gate electrode of the first transistor MA, the high-level gate clock signal GCK is provided to the output terminal via the first transistor MA at the original level. Thus, the scanning signal Gout becomes a high level. Then, the state in which the scanning signal Gout becomes a high level is maintained until the time t3. In addition, when the time t2 is reached, since the set signal S changes from a high level to a low level, the second transistor MB becomes a cut-off state.

[0058] When reaching time t3, the gate clock signal GCK changes from a high level to a low level. At this time, since the first transistor MA is in an on state, as the drain potential (the potential of the clock terminal) decreases, the potential of the scanning signal Gout (the potential of the output terminal) decreases. As the potential of the output terminal decreases, the potential of the internal node netA also decreases via the capacitor Cb.

[0059] When reaching time t4, the reset signal R changes from the low level to the high level. As a result, the third transistor MC is turned on, and the potential of the internal node netA is pulled to the low level.

[0060] [Effect] The liquid crystal display device 100 of this embodiment has the above-described structure due to the unit circuit SR of the gate driver 40 and can be suitably used as an In-cell touch panel. The reason for this will be described below with reference to the structures of the touch panels of Comparative Examples 1 and 2.

[0061] Fig.10 1 is a circuit diagram showing the structure of a unit circuit SRA of a gate driver included in a touch panel of Comparative Example 1 (hereinafter, simply referred to as “unit circuit of Comparative Example 1”). Similar to the unit circuit SR of the present embodiment, the unit circuit SRA of Comparative Example 1 includes a first transistor MA functioning as an “output transistor”, a second transistor MB functioning as a “setting transistor”, a third transistor MC functioning as a “reset transistor”, and a capacitor Cb.

[0062] However, in the unit circuit SRA of Comparative Example 1, the drain electrode of the second transistor MB is electrically connected to the set terminal together with the gate electrode (upper gate electrode) (i.e., diode connection). In addition, in the unit circuit SRA of Comparative Example 1, the second transistor MB does not include a lower gate electrode to which the low-level power supply potential VSS is provided.

[0063] The unit circuit SRA of Comparative Example 1 can be said to be a structure that can simply apply the structure of a unit circuit of a gate driver for a general liquid crystal display device to an in-cell touch panel. The unit circuit SR of Comparative Example 1 has the following problems.

[0064] Here, consider the following situation: after the gate bus lines GL1 to GLn-1 of the first to (n-1)th rows are selected during a certain driving period T1, the touch sensor is driven during the non-driving period T2, and the gate bus line GLn of the nth row is selected during the next driving period T1. Fig.11 2 shows the potentials of the internal node netA and each signal during the non-driving period T2 of the n-th stage unit circuit SRAn in this case. Fig.11In the figure, a high-level potential is represented by "H" and a low-level potential is represented by "L".

[0065] In the n-th unit circuit SRAn, the potentials of the internal node netA and each signal have Fig.11 As shown in the relationship, charge escape occurs from the internal node netA (precharged in the previous driving period T1) during the non-driving period T2. Therefore, after the non-driving period T2 ends, the gate bus line GLn may not be properly selected during the next driving period T1.

[0066] Fig.12 1 is a circuit diagram showing the structure of a unit circuit SRB of a gate driver of a touch panel of Comparative Example 2 (hereinafter, referred to as “unit circuit of Comparative Example 2”). The difference from the unit circuit SRA of Comparative Example 1 is that in the unit circuit SRB of Comparative Example 2, the drain electrode of the second transistor MB is electrically connected to the high potential side power line VDD.

[0067] Here, similarly to the unit circuit SRA of Comparative Example 1, the following situation is considered: after the gate bus lines GL1 to GLn-1 of the first to (n-1)th rows are selected during a certain driving period T1, the touch sensor is driven during the non-driving period T2, and the gate bus line GLn of the nth row is selected during the next driving period T1. Fig.13 4 shows the potentials of the internal node netA and each signal during the non-driving period T2 of the n-th stage unit circuit SRBn in this case.

[0068] In the n-th unit circuit SRBn, the potentials of the internal node netA and each signal have Fig.13 The relationship shown in FIG. 1 prevents the charge from escaping from the internal node netA during the non-driving period T2 by electrically connecting the drain electrode of the second transistor MB to the high potential side power line VDD. Therefore, after the non-driving period T2 ends, the gate bus line GLn can be well selected during the next driving period T1.

[0069] Thus, by electrically connecting the drain electrode of the second transistor MB to the high potential side power line VDD as in the unit circuit SRB of the comparative example 2, the charge escape problem generated in the unit circuit SRA of the comparative example 1 can be eliminated. However, according to the research of the inventors of the present application, it is known that in the unit circuit SRB of the comparative example 2, a new problem that the threshold voltage of the second transistor MB shifts in the negative direction will occur. The reason is described below.

[0070] Fig.141 is a diagram showing the relationship between the potentials of the internal node netA and the set signal S when the second transistor MB of the unit circuit SRA of Comparative Example 1 is not selected, charged (precharged), boosted, just before reset and in the non-driving period T2, and the presence or absence of bias.

[0071] like Fig.14 As shown, in the unit circuit SRA of Comparative Example 1, no bias is applied to the second transistor MB during non-selection, boosting, immediately before resetting, and non-driving period T2, and a forward bias is applied to the second transistor MB during charging.

[0072] Fig.15 It is a diagram showing the relationship between the potentials of the internal node netA and the set signal S when the second transistor MB of the unit circuit SRB of Comparative Example 2 is not selected, charged (precharged), boosted, just before reset and in the non-driving period T2, and the presence or absence of bias.

[0073] like Fig.15 As shown, in the unit circuit SRB of Comparative Example 2, no bias is applied to the second transistor MB when not selected, and a forward bias is applied to the second transistor MB when charging. In contrast, a reverse bias is applied to the second transistor MB when boosting, just before resetting, and in the non-driving period T2.

[0074] Thus, in the unit circuit SRB of Comparative Example 2, since the moment of applying reverse bias to the second transistor MB occurs, the influence of light irradiating the second transistor MB from the back side is also combined to shift the threshold voltage of the second transistor MB in the negative direction. The shift of the threshold voltage in the negative direction leads to increased power consumption, and when the degree of the negative shift becomes serious, the gate driver may not work normally.

[0075] In contrast, in the unit circuit SR of the liquid crystal display device 100 of the present embodiment, the second transistor MB has a lower gate electrode 12 electrically connected to the low potential side power supply line VSS so as to be provided with a low level power supply potential VSS (also referred to as a gate cutoff potential Vgl). Thus, the threshold voltage of the second transistor MB can be increased, and the tolerance to the offset in the negative direction can be improved. Therefore, the increase in power consumption can be suppressed, and poor lighting caused by the failure of the gate driver 40 to operate normally can be prevented.

[0076] In addition, the specific configuration of each unit circuit SR is not limited to Figure 7 For example, each unit circuit SR may include four or more TFTs or two or more capacitors.

[0077] [Verification of the effect] A second transistor MB having an oxide semiconductor layer formed of an In-Ga-Zn-O semiconductor was fabricated, and the effect of electrically connecting the lower gate electrode 12 to the low-potential side power supply line VSS (i.e., providing a low-level power supply potential VSS) was verified. The verification results are described below.

[0078] Verification for specifications of channel width W of 10 μm and channel length of 5 μm ("Specification A") and a specification in which the channel width W is 50μm and the channel length is 5μm ("Specification B"). The case in which a low-level power supply potential VSS is applied to the lower gate electrode 12 in Specification A is referred to as "Example 1", and the case in which a low-level power supply potential VSS is applied to the lower gate electrode 12 in Specification B is referred to as "Example 2". Specifically, the low-level power supply potential VSS is -15V. In addition, the case in which the same potential as the upper gate electrode 16 is applied to the lower gate electrode 12 in Specification A is referred to as "Reference Example 1", and the case in which the same potential as the upper gate electrode 16 is applied to the lower gate electrode 12 in Specification B is referred to as "Reference Example 2".

[0079] The threshold voltage Vth was measured for Examples 1 and 2 and Reference Examples 1 and 2. The source-drain voltage Vds was 1V and 10V. Figures 16 to 19 The measurement results are shown in . Figures 16 to 19 It is a graph showing the relationship between the gate voltage Vg and the drain current Id (gate voltage-drain current characteristics).

[0080] [Table 1]

[0081] From Table 1 and Figures 16 to 19 It can be seen that in Example 1, the threshold voltage Vth is higher than that in Reference Example 1, and in Example 2, the threshold voltage Vth is higher than that in Reference Example 2. Thus, it was confirmed that the threshold voltage Vth of the second transistor MB can be increased by electrically connecting the lower gate electrode 12 to the low potential side power supply line VSS.

[0082] [Configuration of the First Transistor and the Third Transistor] Here, an example of the configuration of the first transistor MA and the third transistor MC will be described. Fig. 20 is a cross-sectional view schematically showing a region of the TFT substrate where the first transistor MA is provided, Fig.21 1 is a cross-sectional view schematically showing a region of the TFT substrate 10 where the third transistor MC is provided.

[0083] like Fig. 20 and Fig.21As shown, the first transistor MA and the third transistor MC each have an oxide semiconductor layer 14 , a gate insulating layer 15 , an upper gate electrode 16 , a source electrode 17 , and a drain electrode 18 similarly to the second transistor MB.

[0084] Below the oxide semiconductor layer 14 of the first transistor MA and the third transistor MC, a light shielding layer 12' is provided, which is opposite to the channel region 14a via the lower insulating layer 13. The light shielding layer 12' provided corresponding to the first transistor MA and the third transistor MC can be either in an electrically floating state (floating) or can be applied with a predetermined potential to function as a lower gate electrode. When the light shielding layer 12' functions as a lower gate electrode, the light shielding layer 12' can be applied with the same potential as the upper gate electrode 16, for example.

[0085] [Oxide semiconductor] The oxide semiconductor (also referred to as metal oxide or oxide material) contained in the oxide semiconductor layer of each TFT in this embodiment may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axis is oriented substantially perpendicular to the layer.

[0086] The oxide semiconductor layer may have a stacked structure of more than two layers. In the case where the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it may include multiple crystalline oxide semiconductor layers with different crystal structures. In addition, it may also include multiple amorphous oxide semiconductor layers. In the case where the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the layer located on the gate electrode side of the two layers (if it is a bottom gate structure, it is the lower layer, if it is a top gate structure, it is the upper layer) may also be smaller than the energy gap of the oxide semiconductor included in the layer located on the side opposite to the gate electrode (if it is a bottom gate structure, it is the upper layer, if it is a top gate structure, it is the lower layer). However, in the case where the difference in the energy gaps of these layers is small, the energy gap of the oxide semiconductor of the layer located on the gate electrode side may be greater than the energy gap of the oxide semiconductor of the layer located on the side opposite to the gate electrode.

[0087] The materials, structures, film formation methods, and configurations of amorphous oxide semiconductors and the above-mentioned crystalline oxide semiconductors, and oxide semiconductors having a stacked structure are described in, for example, Japanese Patent Application Laid-Open No. 2014-007399. The entire disclosure of Japanese Patent Application Laid-Open No. 2014-007399 is cited in this specification for reference.

[0088] The oxide semiconductor layer may contain, for example, at least one metal element selected from In, Ga, and Zn. In the present embodiment, the oxide semiconductor layer may contain, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and may include, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer may be formed by an oxide semiconductor film containing an In-Ga-Zn-O semiconductor.

[0089] In-Ga-Zn-O semiconductors may be amorphous or crystalline. As crystalline In-Ga-Zn-O semiconductors, preferably, those in which the c-axis is oriented substantially perpendicular to the layer plane.

[0090] In addition, the crystal structure of the semiconductor of the crystalline In-Ga-Zn-O system is disclosed in, for example, the above-mentioned Japanese Patent Laid-Open No. 2014-007399 Gazette, Japanese Patent Laid-Open No. 2012-134475 Gazette, and Japanese Patent Laid-Open No. 2014-209727 Gazette. For reference, the entire disclosure of Japanese Patent Laid-Open No. 2012-134475 Gazette and Japanese Patent Laid-Open No. 2014-209727 Gazette is cited in this specification. The TFT having an In-Ga-Zn-O system semiconductor layer has high mobility (more than 20 times compared to a-SiTFT) and low leakage current (less than one percent compared to a-SiTFT), and is therefore preferably used as a driving TFT (for example, a TFT present in a driving circuit, which is arranged in the periphery of a display area including a plurality of pixels and on the same substrate as the display area) and a pixel TFT (a TFT arranged in a pixel).

[0091] The oxide semiconductor layer may also include other oxide semiconductors instead of the In-Ga-Zn-O semiconductor. For example, it may include an In-Sn-Zn-O semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may also include In-Al-Zn-O series semiconductors, In-Al-Sn-Zn-O series semiconductors, Zn-O series semiconductors, In-Zn-O series semiconductors, Zn-Ti-O series semiconductors, Cd-Ge-O series semiconductors, Cd-Pb-O series semiconductors, CdO (cadmium oxide), Mg-Zn-O series semiconductors, In-Ga-Sn-O series semiconductors, In-Ga-O series semiconductors, Zr-In-Zn-O series semiconductors, Hf-In-Zn-O series semiconductors, Al-Ga-Zn-O series semiconductors, Ga-Zn-O series semiconductors, In-Ga-Zn-Sn-O series semiconductors, In-W-Zn-O series semiconductors, etc. Industrial Applicability

[0092] According to the embodiment of the present invention, it is possible to provide a display device including a GDM circuit including an oxide semiconductor TFT and suitable for use as an In-cell touch panel. Description of Reference Numerals

[0093] 1 Display Panel 10Active matrix substrate 10a substrate 11-pixel TFT 12 light shielding layer (lower gate electrode) 12' sunshade layer 13 Lower insulation layer 14Semiconductor layer 14a channel region 14b First low resistance region 14c The second low resistance area 15Gate insulation layer 16 Gate electrode (upper gate electrode) 17 Source electrode 18 Drain electrode 19 Upper insulation layer 19a Source side opening 19b Drain side opening 20 Opposing substrate 30 Liquid crystal layer 40 Gate driver (scanning signal line drive circuit) 41 Shift register circuit 50 Source driver (image signal line drive circuit) 100 Liquid crystal display device DR display area FR non-display area P Pixel PE pixel electrode CE common electrode GL gate bus (scanning signal line) SL source bus (image signal line) TL touch wiring TX touch sensor electrodes TD touch driver SR unit circuit MA First Transistor MB second transistor MC third transistor Cb capacitor netA internal node VDD high potential side power line VSS low potential side power line.

Claims

1. A display device comprising: A display panel having a plurality of scanning signal lines; and a scanning signal line driving circuit, which drives the plurality of scanning signal lines, The scanning signal line driving circuit can alternately switch between a driving period and a non-driving period during one vertical scanning period, and makes the plurality of scanning signal lines sequentially selected during the driving period, and does not drive the plurality of scanning signal lines during the non-driving period. The display device is characterized in that The display panel also has a high potential side power line and a low potential side power line. The scanning signal line driving circuit has a shift register circuit including a plurality of stages, The unit circuit constituting each of the plurality of stages includes: a clock terminal to which a clock signal is input; a set terminal to which a set signal is input; a reset terminal to which a reset signal is input; an output terminal electrically connected to a corresponding scan signal line among the plurality of scan signal lines and outputting a scan signal; A first thin film transistor having a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is electrically connected to an internal node, one of the first source electrode and the first drain electrode is electrically connected to the clock terminal, and the other of the first source electrode and the first drain electrode is electrically connected to the output terminal; a second thin film transistor having a second semiconductor layer, a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode is electrically connected to the set terminal, and one of the second source electrode and the second drain electrode is electrically connected to the internal node; as well as a third thin film transistor having a third semiconductor layer, a third gate electrode, a third source electrode and a third drain electrode, wherein the third gate electrode is electrically connected to the reset terminal, and one of the third source electrode and the third drain electrode is electrically connected to the internal node; The second gate electrode of the second thin film transistor is an upper gate electrode disposed above the second semiconductor layer via a gate insulating layer. The other of the second source electrode and the second drain electrode of the second thin film transistor is electrically connected to the high potential side power supply line, The second thin film transistor further includes a lower gate electrode, which is arranged below the second semiconductor layer, faces the channel region of the second semiconductor layer via a lower insulating layer, and is electrically connected to the low potential side power supply line.

2. The display device according to claim 1, characterized in that The unit circuit further includes a capacitor including a pair of electrodes. One of the pair of electrodes is electrically connected to the internal node, and the other of the pair of electrodes is electrically connected to the output terminal.

3. The display device according to claim 1 or 2, characterized in that: A control signal is applied to the other of the third source electrode and the third drain electrode of the third thin film transistor, wherein the control signal is at a first potential lower than the threshold voltage of the first thin film transistor during the driving period and is at a second potential higher than the first potential during at least a portion of the non-driving period.

4. The display device according to claim 1 or 2, characterized in that: The display panel also has: a plurality of electrodes for a touch sensor to which mutually different signals can be applied; and A plurality of wirings for the touch sensor, each of which is electrically connected to a corresponding electrode among the plurality of electrodes, During the non-driving period, the touch sensor is driven.

5. The display device according to claim 1 or 2, characterized in that: The display panel has an active matrix substrate including the plurality of scanning signal lines. The scanning signal line driving circuit is formed monolithically on the active matrix substrate.

6. The display device according to claim 1 or 2, characterized in that: The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are oxide semiconductor layers, respectively.

7. The display device according to claim 6, characterized in that: The oxide semiconductor layer includes an In-Ga-Zn-O-based semiconductor.

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