Power control circuit, read / write circuit, and memory

Abstract

The present application provides a power control circuit, a read / write circuit and a memory, relating to the technical field of memories. The power control circuit includes: a first control circuit, a second control circuit, a sampling feedback circuit and an output selection circuit; a first input end of the first control circuit receives a clock signal, and a second input end receives a power control signal; a control end of the sampling feedback circuit is connected to an output end of the first control circuit, an input end is connected to an output end of a bit line precharge circuit or a word line power supply circuit in the read / write circuit, and an output end is connected to an input end of the second control circuit; the output end of the first control circuit and the output end of the second control circuit are respectively connected to a first input end and a second input end of the output selection circuit, and a third input end of the output selection circuit receives the clock signal; an output end of the output selection circuit is connected to a control end of the bit line precharge circuit or the word line power supply circuit. The present application can achieve adaptive adjustment of the precharge state of the bit line or the power supply state of the word line.

Description

Technical Field

[0001] The present application relates to the technical field of memories, and more particularly, to a power control circuit, a read / write circuit, and a memory. Background Art

[0002] With the continuous progress of contemporary technology, the chip area of memories becomes smaller. As an important part of a memory, the read / write unit is directly connected to many modules, and the optimization of most modules in the memory will affect it. Therefore, the read / write unit often becomes the most complex module in terms of structure.

[0003] Before the read / write unit reads from or writes to the memory array in the memory, the bit lines of the memory array will be precharged first, and then the word lines of some memory cells in the memory array are controlled to be raised to a high level.

[0004] However, in the prior art, whether it is the precharge circuit for precharging the bit lines or the power supply circuit for supplying power to the word lines, it can only maintain a precharge state or a power supply state, and cannot flexibly adjust the precharge state or the power supply state. Summary of the Invention

[0005] An object of the present application is to provide a power control circuit, a read / write circuit, and a memory for adaptively adjusting the precharge state of the bit lines or the power supply state of the word lines in view of the deficiencies in the above-mentioned prior art.

[0006] To achieve the above object, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, an embodiment of the present application provides a power control circuit, which includes: a first control circuit, a second control circuit, a sampling feedback circuit, and an output selection circuit;

[0008] A first input terminal of the first control circuit is configured to receive a preset clock signal, and a second input terminal of the first control circuit is configured to receive a preset power control signal, so that the first control circuit generates a first control signal based on the preset power control signal and the preset clock signal;

[0009] A control terminal of the sampling feedback circuit is connected to an output terminal of the first control circuit. An input terminal of the sampling feedback circuit is configured to be connected to an output terminal of a bit line precharge circuit or a word line power supply circuit in the read / write circuit. An output terminal of the sampling feedback circuit is connected to an input terminal of the second control circuit, so that the second control circuit outputs a second control signal based on a sampling feedback signal;

[0010] The output terminal of the first control circuit and the output terminal of the second control circuit are respectively connected to the first input terminal and the second input terminal of the output selection circuit. The third input terminal of the output selection circuit is used to receive the preset clock signal, so that the output selection circuit outputs a target power control signal based on the preset clock signal, the first control signal, and the second control signal;

[0011] The output terminal of the output selection circuit is used to connect to the control terminal of the bit line precharge circuit or the word line power supply circuit, so as to control the bit line precharge circuit or the word line power supply circuit to provide power for the corresponding bit line or word line according to the output target power control signal.

[0012] Optionally, the first control circuit includes: a first NAND gate, a first NOT gate, and a second NOT gate;

[0013] The first input terminal of the first NAND gate serves as the first input terminal of the first control circuit. The input terminal of the first NOT gate serves as the second input terminal of the first control circuit. The output terminal of the first NOT gate is connected to the second input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate serves as the output terminal of the first control circuit;

[0014] When the preset clock signal is at a high level, the first control signal is the inverted signal of the preset power control signal.

[0015] Optionally, the second control circuit includes: a voltage division sampling protection circuit and a Schmitt trigger;

[0016] The input terminal of the voltage division sampling protection circuit serves as the feedback input terminal of the second control circuit. The output terminal of the voltage division sampling protection circuit is connected to the input terminal of the Schmitt trigger. The output terminal of the Schmitt trigger serves as the output terminal of the second control circuit.

[0017] Optionally, the voltage division sampling protection circuit includes: a voltage division sampling circuit, a first switching transistor, and a protection resistor;

[0018] The input terminal of the voltage division sampling circuit serves as the input terminal of the voltage division sampling protection circuit. The output terminal of the voltage division sampling circuit is connected to the gate of the first switching transistor. One of the source or drain of the first switching transistor is used to connect to a preset supply voltage. The other of the source or drain of the first switching transistor is connected to the protection resistor, and the connection point serves as the output terminal of the voltage division sampling protection circuit.

[0019] Optionally, the output selection circuit includes: a first NOR gate and a second NOR gate;

[0020] The first input terminal of the first NOR gate and the first input terminal of the second NOR gate serve as the first input terminal and the second input terminal of the output selection circuit respectively. The second input terminal of the first NOR gate serves as the third input terminal of the output selection circuit. The output terminal of the first NOR gate is connected to the second input terminal of the second NOR gate. The output terminal of the second NOR gate serves as the output terminal of the output selection circuit.

[0021] Optionally, the sampling feedback circuit includes: a second switching transistor;

[0022] One of the source or drain of the second switching transistor is connected to the bit line terminal of the bit line precharging circuit or the word line voltage terminal of the word line power supply circuit. The gate of the second switching transistor serves as the control terminal of the sampling feedback circuit. The other of the source or drain of the second switching transistor serves as the output terminal of the sampling feedback circuit.

[0023] Optionally, the sampling feedback circuit includes: a third switching transistor and a fourth switching transistor;

[0024] One of the source or drain of the third switching transistor is used to connect to the bit line terminal of the bit line precharging circuit. One of the source or drain of the fourth switching transistor is used to connect to the complementary bit line terminal of the bit line precharging circuit;

[0025] The gates of the third switching transistor and the fourth switching transistor are connected to serve as the control terminal of the sampling feedback circuit. The other of the source or drain of the third switching transistor and the other of the source or drain of the fourth switching transistor are connected to the output terminal of the sampling feedback circuit.

[0026] In a second aspect, an embodiment of the present application further provides a read / write circuit, which includes: a plurality of read / write units, a plurality of bit line precharging circuits, a plurality of word line power supply circuits, and a power control circuit;

[0027] Each read / write unit is used to connect to at least one bit line in the storage array. The plurality of bit line precharging circuits are also connected to multiple bit lines in the storage array. The control terminals of the plurality of bit line precharging circuits are all connected to the power control circuit, and the power control circuit is the circuit according to any item in the first aspect; the plurality of word line power supply circuits are respectively connected to multiple word lines of the storage array.

[0028] In a third aspect, an embodiment of the present application further provides a read / write circuit, which includes: a plurality of read / write units, a plurality of bit line precharging circuits, a plurality of word line power supply circuits, and a plurality of power control circuits;

[0029] Each read / write unit is connected to at least one bit line in the storage array. The plurality of bit line precharging circuits are respectively connected to multiple bit lines in the storage array;

[0030] The multiple word line power circuits are respectively connected to multiple word lines of the memory array, and control ends of the multiple word line power circuits are respectively connected to the multiple power control circuits, and the multiple power control circuits are the circuits described in any item of the first aspect.

[0031] In a fourth aspect, an embodiment of the present application further provides a memory, and the memory includes a read-write circuit and a memory array as described in the second aspect or the third aspect.

[0032] The beneficial effects of the present application are as follows:

[0033] When it is determined based on a preset clock signal that the memory is in a working state, the bit line precharge circuit is controlled to precharge the bit line, or the word line power circuit is controlled to charge the word line according to a target power control signal generated according to a preset power control signal. When it is determined based on a preset clock signal that the memory is in a sleep state, the bit line precharge circuit is controlled to precharge the bit line, or the word line power circuit is controlled to charge the word line according to a target power control signal generated according to a sampled feedback signal, so as to realize the adaptive adjustment of the bit line voltage or the word line voltage. The power control circuit has higher flexibility and can effectively improve the speed at which the memory resumes from the sleep state to the working state. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0035] Figure 1 It is a circuit schematic diagram of an existing precharge circuit;

[0036] Figure 2 It is a principle block diagram of the power control circuit provided by the embodiment of the present application;

[0037] Figure 3 It is a circuit of the power control circuit provided by the embodiment of the present application Figure 1 ;

[0038] Figure 4 It is a circuit of the power control circuit provided by the embodiment of the present application Figure 2 ;

[0039] Figure 5 It is a waveform diagram provided by the embodiment of the present application;

[0040] Figure 6The principle block diagram of the read-write circuit provided by the embodiment of the present application Figure 1 ;

[0041] Figure 7 The principle block diagram of the read-write circuit provided by the embodiment of the present application Figure 2 。 Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application.

[0043] Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0044] In addition, the terms "first", "third", etc. in the description and claims of the present application and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0045] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0046] Hereinafter, taking the precharge circuit of the prior art as an example, the defects existing in the prior art will be described.

[0047] Exemplarily, Figure 1 is the circuit schematic diagram of the existing precharge circuit, as Figure 1As shown in the figure, before the read / write unit reads or writes to the storage unit, the bit line precharge control signal BLPR is at a low level, and the three PMOS transistors IP1, IP2, and IP3 are in the conducting state. The bit line (Bit Line, BL) is connected to the complementary bit line (Bit Line Bar, BLB), and the power supply VDD precharges equally through the balancing transistors IP1 and IP, so that BL and BLB are at an equal-pressure high level when the storage unit performs read / write operations. When the storage unit starts to read or write, the precharge is turned off.

[0048] It can be seen that there is only one gear for the bit line precharge control signal BLPR in the existing precharge circuit. It can only control the precharge circuit to turn on or off the precharge when the memory is in the working state, and it cannot meet how to ensure the voltages of the bit line and the complementary bit line when the memory is in the sleep state. Therefore, it is impossible to quickly restore the voltages of the bit line and the complementary bit line when the memory resumes from the sleep state to the working state.

[0049] Similarly, the existing power supply circuit for powering the word line also has the same problem.

[0050] Based on the defects of the above existing technologies, the present application intends to provide a power control circuit, which can be applied to the bit line precharge circuit or the word line power supply circuit in the read / write circuit.

[0051] Figure 2 For the principle block diagram of the power control circuit provided by the embodiment of the present application, as Figure 2 shown, the power control circuit includes: a first control circuit 101, a second control circuit 102, a sampling feedback circuit 103, and an output selection circuit 104.

[0052] The first input terminal of the first control circuit 101 is used to receive a preset clock signal CK, and the second input terminal of the first control circuit 101 is used to receive a preset power control signal Power Control_0, so that the first control circuit 101 generates a first control signal Control based on the preset power control signal Power Control_0 and the preset clock signal CK.

[0053] The control terminal of the sampling feedback circuit 103 is connected to the output terminal of the first control circuit 101. The input terminal of the sampling feedback circuit 103 is used to connect to the output terminal of the bit line precharge circuit or the word line power supply circuit in the read / write circuit. The output terminal of the sampling feedback circuit 103 is connected to the input terminal of the second control circuit 102, so that the second control circuit 102 outputs a second control signal Control_Feedback based on the sampling feedback signal Feedback.

[0054] The output terminal of the first control circuit 101 and the output terminal of the second control circuit 102 are respectively connected to the first input terminal and the second input terminal of the output selection circuit 104. The third input terminal of the output selection circuit 104 is used to receive a preset clock signal CK, so that the output selection circuit 104 outputs a target power control signal Power Control_1 based on the preset clock signal CK, the first control signal Control, and the second control signal Control_Feedback.

[0055] The output terminal of the output selection circuit 104 is used to connect to the control terminal of the bit line precharge circuit or the word line power supply circuit, so as to control the bit line precharge circuit or the word line power supply circuit to provide electric energy for the corresponding bit line or word line according to the output target power control signal Power Control_1.

[0056] In this embodiment, the first control circuit 101 generates a first control signal Control based on a preset power control signal Power Control_0 and a preset clock signal CK. The control logic for generating the first control signal Control is that when the preset clock signal CK is a high-level signal, the first control signal Control is generated according to the preset power control signal Power, and when the preset clock signal CK is a low level, the first control signal Control is a fixed low-level signal.

[0057] The second control circuit 102 generates a second control signal Control_Feedback based on the sampling feedback signal Feedback provided by the sampling feedback circuit 103. Among them, when the sampling feedback signal Feedback indicates that the bit line voltage of the bit line precharge circuit or the word line voltage of the word line power supply circuit is less than a preset voltage value, the second control signal Control_Feedback is a low-level signal, and when the sampling feedback signal Feedback indicates that the bit line voltage of the bit line precharge circuit or the word line voltage of the word line power supply circuit is a full voltage, the second control signal Control_Feedback is a high-level signal.

[0058] The preset clock signal CK is also the selection indication signal of the output selection circuit 104, which is used to indicate whether to generate the target power control signal Power Control_1 according to the first control signal Control of the first control circuit 101 or according to the second control signal Control_Feedback of the second control circuit 102. Among them, when the preset clock signal CK is a high-level signal, the first control circuit 101 takes effect, and the output selection circuit 104 generates the target power control signal Power Control_1 according to the first control signal Control. Since when the preset clock signal CK is a high-level signal, the first control circuit 101 generates the first control signal Control according to the preset power control signal Power, when the preset clock signal CK is a high-level signal, the output selection circuit 104 generates the target power control signal Power Control_1 according to the preset power control signal PowerControl_0.

[0059] When the preset clock signal CK is a low-level signal, the second control circuit 102 takes effect, and the output selection circuit 104 generates the target power control signal Power Control_1 according to the second control signal Control_Feedback. Since the second control signal Control_Feedback is generated based on the sampled feedback signal Feedback, when the preset clock signal CK is a low-level signal, the output selection circuit 104 generates the target power control signal Power Control_1 according to the pre-sampled feedback signal Feedback.

[0060] The preset clock signal CK is the clock signal obtained by performing a logic operation on the logic clock signal of the memory where the read / write circuit is located and the sleep signal. When the logic clock signal indicates that the memory is in the working state for read / write operations, the preset clock signal CK is a high-level signal. The target power control signal Power Control_1 is generated according to the preset power control signal Power to control whether the bit line precharge circuit precharges the bit lines or whether the word line power supply circuit charges the word lines, so that the word lines reach a high level. When the sleep signal indicates that the memory is in the sleep state and no read / write operations are performed, the preset clock signal CK is a low-level signal. The target power control signal Power Control_1 is generated according to the feedback control signal Feedback to recharge the bit lines by controlling the bit line precharge circuit again when the voltage of the bit lines or the word lines decreases and is less than the preset voltage value, or to charge the word lines by controlling the word line power supply circuit. When the voltage of the bit lines or the word lines is the full voltage, the bit line precharge circuit is controlled to stop precharging the bit lines, or the word line power supply circuit is controlled to stop charging the word lines, ensuring that the line voltage of the bit lines or the word lines is maintained at the level value required for read / write operations, so that the bit lines or the word lines can be quickly awakened when the memory re-enters the working state.

[0061] For the power control circuit provided in the above embodiment, when it is determined based on the preset clock signal that the memory is in the working state, the target power control signal generated according to the preset power control signal controls the bit line precharge circuit to precharge the bit lines, or controls the word line power supply circuit to charge the word lines. When it is determined based on the preset clock signal that the memory is in the sleep state, the target power control signal generated according to the sampled feedback signal controls the bit line precharge circuit to precharge the bit lines, or controls the word line power supply circuit to charge the word lines, so as to realize the adaptive adjustment of the bit line voltage or the word line voltage. The flexibility of the power control circuit is higher, and the speed at which the memory resumes from the sleep state to the working state can be effectively improved.

[0062] Figure 3 For the circuit of the power control circuit provided in the embodiment of the present application Figure 1 , such as Figure 3 shown, taking the sampling feedback circuit and the second output circuit connected to the bit line precharge circuit in the read / write circuit as an example, the first control circuit 101 may include: a first NAND gate NAND1, a first NOT gate NOT1, and a second NOT gate NOT2.

[0063] The first input terminal of the first NAND gate NAND1 serves as the first input terminal of the first control circuit 101. The input terminal of the first NOT gate NOT1 serves as the second input terminal of the first control circuit 101. The output terminal of the first NOT gate NOT1 is connected to the second input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the second NOT gate NOT2. The output terminal of the second NOT gate NOT2 serves as the output terminal of the first control circuit 101. When the preset clock signal CK is at a high level, the first control signal Control is the inverted signal of the preset power control signal Power Control_0.

[0064] In this embodiment, the preset power control signal Power Control_0 is the bit line precharge signal BLPRB, and the target power control signal Power_Control_1 is PRB_Control. The working principle of the first control circuit 101 is as follows: When the preset clock signal CK is at a high level of 1, if the preset power control signal Power Control_0 is at a high level of 1, a low level of 0 is output after passing through the first NOT gate NOT1. The low level of 0 and the high level of 1 pass through the first NAND gate NAND1 to output a high level of 1, and the high level of 1 passes through the second NOT gate NOT2 to output a low level of 0. If the preset power control signal Power Control_0 is at a low level of 0, a high level of 1 is output after passing through the first NOT gate NOT1. The high level of 1 and the high level of 1 pass through the first NAND gate NAND1 to output a low level of 0, and the low level of 0 passes through the second NOT gate NOT2 to output a high level of 1. Therefore, when the preset clock signal CK is at a high level of 1, if the preset power control signal Power Control_0 is at a high level, the output of the first control circuit 101 is at a low level, and if the preset power control signal PowerControl_0 is at a low level of 0, the output of the first control circuit 101 is at a high level of 1.

[0065] At this time, since the output selection circuit 104 selects the preset power control signal Power Control_0 as the target power control signal Power Control_1, therefore, if the target power control signal Power Control_1 is at a high level of 1, it controls the bit line precharge circuit to precharge the bit lines. Similarly, if it is connected to the word line power supply circuit, it controls the word line power supply circuit to supply power to the word lines. If the target power control signal Power Control_1 is at a low level of 0, it controls the bit line precharge circuit to stop precharging the bit lines. Similarly, if it is connected to the word line power supply circuit, it controls the word line power supply circuit to stop supplying power to the word lines.

[0066] When the preset clock signal CK is at a low level of 0, if the preset power control signal Power Control_0 is at a high level of 1, regardless of whether the preset power control signal Power Control_0 is at a high level of 1 or a low level of 0, the output of the first NAND gate NAND1 is at a high level of 1, and after passing through the second NOT gate NOT2, a low level of 0 is output. Therefore, when the preset clock signal CK is at a low level of 0, the output of the first control circuit 101 is at a low level.

[0067] In a possible implementation, as Figure 3 shown, the second control circuit 102 may include: a voltage-dividing sampling protection circuit 121 and a Schmitt trigger 122.

[0068] The input terminal of the voltage-dividing sampling protection circuit 121 serves as the feedback input terminal of the second control circuit 102. The output terminal of the voltage-dividing sampling protection circuit 121 is connected to the input terminal of the Schmitt trigger 122, and the output terminal of the Schmitt trigger 122 serves as the output terminal of the second control circuit 102.

[0069] In this embodiment, the input terminal of the voltage-dividing sampling protection circuit 121 is connected to the output terminal of the sampling feedback circuit 103 to receive the sampling feedback signal Feedback, and outputs a trigger control signal according to the voltage-dividing signal of the sampling feedback signal Feedback for triggering the Schmitt trigger 122.

[0070] Among them, the structure of the Schmitt trigger 122 is as Figure 3 shown, which is composed of PMOS transistors IP1, IP2, IP3 and NMOS transistors IN1, IN2 and IN3. When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is lower than a preset voltage value, such as 60% of the power supply voltage, the voltage-dividing sampling protection circuit 121 outputs a high-level trigger control signal, and the high-level trigger control signal controls the conduction of IN1 and IN2 of the Schmitt trigger 122, and the output terminal of the Schmitt trigger 122 outputs a low-level second control signal Control_Feedback.

[0071] When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage reaches the full voltage, that is, the power supply voltage, the voltage-dividing sampling protection circuit 121 outputs a low-level trigger control signal, and the low-level trigger control signal controls the conduction of IP1 and IP2 of the Schmitt trigger 122, and the output terminal of the Schmitt trigger 122 outputs a high-level second control signal Control_Feedback.

[0072] In some embodiments, as Figure 3 shown, the voltage-dividing sampling protection circuit 121 may include: a voltage-dividing sampling circuit, a first switching transistor IP0 and a protection resistor R3.

[0073] The input end of the voltage-dividing sampling circuit serves as the input end of the voltage-dividing sampling protection circuit 121. The output end of the voltage-dividing sampling circuit is connected to the gate of the first switching transistor IP0. One of the source or drain of the first switching transistor IP0 is used to connect to the preset supply voltage VDD, and the other of the source or drain of the first switching transistor IP0 is connected to the protection resistor R3, and the connection point serves as the output end of the voltage-dividing sampling protection circuit 121.

[0074] In this embodiment, the voltage-dividing sampling circuit is composed of resistors R1 and R2. One end of the resistor R1 serves as the input end of the voltage-dividing sampling protection circuit 121. The other end of the resistor R1 is connected to one end of the resistor R2, and the connection point is connected to the gate of the first switching transistor IP0. The other end of the resistor R2 is grounded.

[0075] When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is lower than the preset voltage value, after the voltage division by the resistors R1 and R2 in the voltage-dividing sampling circuit, P0P is at a low level, controlling the first switching transistor IP0 to conduct. The connection point of the first switching transistor IP0 and the protection resistor R3 is at a high level, controlling the IN1 and IN2 of the Schmitt trigger 122 to conduct, and the output end of the Schmitt trigger 122 outputs a low-level second control signal Control_Feedback.

[0076] When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage reaches the full voltage, after the voltage division by the resistors R1 and R2 in the voltage-dividing sampling circuit, P0P is at a high level, controlling the first switching transistor IP0 to turn off. The connection point of the first switching transistor IP0 and the protection resistor R3 is at a low level, controlling the IP1 and IP2 of the Schmitt trigger 122 to conduct, and the output end of the Schmitt trigger 122 outputs a high-level second control signal Control_Feedback.

[0077] For example, the resistance ratio of the resistors R1 and R2 is 3:7. If the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is lower than 60% of the power supply voltage, P0P is lower than 42% of the power supply voltage, and the first switching transistor IP0 conducts. If the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is 100% voltage, P0P is 70% of the high-level voltage, and the first switching transistor IP0 turns off.

[0078] In a possible implementation, as Figure 3 shown, the output selection circuit 104 may include: a first NOR gate NOR1 and a second NOR gate NOR2.

[0079] The first input terminal of the first NOR gate NOR1 and the first input terminal of the second NOR gate NOR2 are respectively used as the first input terminal and the second input terminal of the output selection circuit 104. The second input terminal of the second NOR gate NOR2 is used as the third input terminal of the output selection circuit 104. The output terminal of the first NOR gate NOR1 is connected to the second input terminal of the second NOR gate NOR2. The output terminal of the second NOR gate NOR2 is used as the output terminal of the output selection circuit 104.

[0080] In this embodiment, as Figure 3 shown, the first NOR gate NOR1 respectively receives a preset clock signal CK and a second control signal Control_Feedback, and the second NOR gate NOR2 respectively receives a first control signal Control and the output signal of the first NOR gate NOR1.

[0081] The working principle of the output selection circuit 104 is as follows:

[0082] When the preset clock signal CK is at a high level of 1, regardless of whether the second control signal Control_Feedback is at a high level of 1 or a low level of 0, the output of the first NOR gate NOR1 is always at a low level of 0. At this time, if the preset power control signal PowerControl_0 is at a low level of 0, the output of the first control circuit 101 is at a high level of 1. After performing NOR operation on the high level of 1 and the low level of 0, the output of the second NOR gate NOR2 is at a low level of 0, that is, when the preset power control signal Power Control_0 is at a low level of 0, the target power control signal Power Control_1 is also at a low level of 0; if the preset power control signal Power Control_0 is at a high level of 1, the output of the first control circuit 101 is at a low level of 0. After performing NOR operation on the low level of 0 and the low level of 0, the output of the second NOR gate NOR2 is at a high level of 1, that is, when the preset power control signal Power Control_0 is at a high level of 1, the target power control signal PowerControl_1 is also at a high level of 1. Therefore, when the preset clock signal CK is at a high level, the target power control signal Power Control_1 is determined by the preset power control signal PowerControl_0, and the target power control signal Power Control_1 is in phase with the preset power control signal Power Control_0.

[0083] When the preset clock signal CK is at a low level of 0, regardless of whether the preset power control signal Power Control_0 is at a high level of 1 or a low level of 0, the first control signal Control is at a low level of 0. At this time, if the second control signal Control_Feedback is at a low level of 0, the output of the first NOR gate NOR1 is at a high level of 1, then the output of the second NOR gate NOR2 is at a low level of 0, that is, the second control signal Control_Feedback is at a low level of 0, and the target power control signal Power Control_1 is also at a low level of 0; if the second control signal Control_Feedback is at a high level of 1, the output of the first NOR gate is at a low level of 0, then the output of the second NOR gate NOR2 is at a high level of 1, that is, the second control signal Control_Feedback is at a high level of 1, and the target power control signal Power Control_1 is also at a high level of 1. Therefore, when the preset clock signal CK is at a low level, the target power control signal Power Control_1 is determined by the sampling feedback signal Feedback, and the target power control signal Power Control_1 is in phase with the second control signal Control_Feedback.

[0084] It can be seen that when the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is less than the preset voltage value, the target power control signal Power Control_1 controls the bit line precharge circuit to start precharging, or controls the word line power supply circuit to supply power. When the bit line voltage or the word line voltage reaches the full voltage, the target power control signal Power Control_1 controls the bit line precharge circuit to stop precharging, or controls the word line power supply circuit to stop supplying power. In this way, the bit line precharge circuit will not precharge the bit line all the time, and the word line power supply circuit will not supply power to the word line all the time. The bit line voltage or the word line voltage will be maintained within a certain range and can be used in the sleep state.

[0085] Figure 4 For the circuit of the power control circuit provided in the embodiment of the present application Figure 2 , such as Figure 4 shown, taking the sampling feedback circuit and the second output circuit connected to the word line power supply circuit in the read / write circuit as an example, the sampling feedback circuit 103 may include: a second switching transistor IP9.

[0086] One of the source or drain of the second switching transistor IP9 is connected to the bit line terminal of the bit line precharge circuit or the word line voltage terminal of the word line power supply circuit. The gate of the second switching transistor IP9 is used as the control terminal of the sampling feedback circuit 103, and the other of the source or drain of the second switching transistor IP9 is used as the output terminal of the sampling feedback circuit 103.

[0087] In this embodiment, the preset power control signal Power Control_0 is the word line power supply signal WLPRB, and the target power control signal Power_Control_1 is VWL_Control. If the memory array includes bit lines BL, the bit line terminal of the bit line precharge circuit is connected to the bit line BL of the memory array. Then, the sampling feedback circuit 103 includes a second switching transistor IP9. One of the source or drain of the second switching transistor IP9 is connected to the bit line terminal of the bit line precharge circuit to sample the bit line voltage of the bit line BL. The other of the source or drain of the second switching transistor IP9 is connected to the second control circuit 102 to provide a sampling feedback signal Feedback to the second control circuit 102. The gate of the second switching transistor IP9 is connected to the output terminal of the first control circuit 101 to control whether the sampling feedback circuit 103 performs sampling according to the first control signal Control.

[0088] Among them, when the preset clock signal CK is at a high level of 1, when the preset power control signal Power Control_0 is at a low level of 0, the first control signal Control is at a high level of 1, and the target power control signal Power Control_1 is at a low level of 0. The target power control signal Power Control_1 controls the bit line precharge circuit to precharge the bit line BL, and the second switching transistor IP9 is turned off, and the second switching transistor IP9 does not perform sampling during the precharging of the bit line BL. When the preset power control signal PowerControl_0 is at a high level of 1, the first control signal Control is at a low level of 0, and the target power control signal PowerControl_1 is at a high level of 1. The target power control signal Power Control_1 controls the bit line precharge circuit to stop precharging the bit line BL, and the second switching transistor IP9 is turned on, and the second switching transistor IP9 samples the bit line voltage.

[0089] When the preset clock signal CK is at a low level of 0, the first control signal Control is at a low level of 0, and the second switching transistor IP9 is always at a low level of 0, continuously sampling the bit line voltage. When the bit line voltage is too low, the bit line precharge circuit is controlled by the second control circuit 102 to precharge the bit line. When the bit line voltage reaches the full voltage, the bit line precharge circuit is controlled by the second control circuit 102 to stop precharging the bit line.

[0090] Similarly, the memory array further includes word lines WL. The word line terminal of the word line power supply circuit is connected to the word line WL of the memory array. The way the power control circuit controls the word line power supply circuit to supply power to the word line WL is the same as the working principle of the bit line precharge circuit for charging the bit line BL, and will not be elaborated again.

[0091] In another possible implementation, if the memory storage array includes bit lines BL and complementary bit lines BLB, the bit line terminal of the bit line pre-charge circuit is connected to the bit line BL of the storage array, and the complementary bit line terminal is connected to the complementary bit line BLB of the storage array, as Figure 3 shown, the sampling feedback circuit 103 may include: a third switching transistor IP7 and a fourth switching transistor IP8.

[0092] One of the source or drain of the third switching transistor IP7 is used to connect to the bit line terminal of the bit line pre-charge circuit, and one of the source or drain of the fourth switching transistor IP8 is used to connect to the complementary bit line terminal of the bit line pre-charge circuit.

[0093] The gates of the third switching transistor IP7 and the fourth switching transistor IP8 are connected as the control terminal of the sampling feedback circuit 103, and the other of the source or drain of the third switching transistor IP7 and the other of the source or drain of the fourth switching transistor IP8 are connected to the output terminal of the sampling feedback circuit 103.

[0094] In this embodiment, when the storage array includes bit lines BL and complementary bit lines BLB, during pre-charge, the voltages of the bit line BL and the complementary bit line BLB need to be charged to an equal voltage. Therefore, the bit line pre-charge circuit includes a bit line terminal and a complementary bit line terminal. For this reason, the sampling feedback circuit 103 needs to be provided with the third switching transistor IP7 and the fourth switching transistor IP8 to sample the bit line voltage and the complementary bit line voltage respectively.

[0095] Its working principle is the same as that of the sampling feedback circuit 103 that only includes the second switching transistor IP9, and will not be elaborated here.

[0096] Exemplarily, Figure 5 is the waveform diagram provided by the embodiment of the present application, and the working principle of the power control circuit will not be elaborated here.

[0097] Based on the power control circuit provided by the above embodiment, the embodiment of the present application further provides a read / write circuit based on the power control circuit.

[0098] In a possible implementation, Figure 6 is the principle block diagram of the read / write circuit provided by the embodiment of the present application Figure 1 , as Figure 6 shown, the read / write circuit may include: a plurality of read / write units 200, a plurality of bit line pre-charge circuits 300 (only one bit line pre-charge circuit is shown in the figure), a plurality of word line power supply circuits 400 (only one word line power supply circuit is shown in the figure), and a power control circuit 100.

[0099] Each read / write unit 200 is used to connect at least one bit line BL in the storage array. Multiple bit line precharge circuits 300 are also connected to multiple bit lines BL in the storage array. The control ends of the multiple bit line precharge circuits 300 are all connected to the power control circuit 100. Multiple word line power circuits 400 are respectively connected to multiple word lines WL in the storage array.

[0100] In this embodiment, the output end of the power control circuit 100 is connected to the control ends of the multiple bit line precharge circuits 300 to control the multiple bit line precharge circuits 300 to precharge the connected bit lines. The input end of the sampling feedback circuit of the power control circuit 100 is connected to the bit line end and the complementary bit line end of any one of the bit line precharge circuits 300 to sample the bit line voltage and the complementary bit line voltage.

[0101] In another possible implementation, Figure 7 is the principle block diagram of the read / write circuit provided by the embodiment of the present application Figure 2 , as Figure 7 shown, the read / write circuit may include: multiple read / write units 200, multiple bit line precharge circuits 300, multiple word line power circuits 400, and multiple power control circuits 100.

[0102] Each read / write unit 200 is used to connect at least one bit line BL in the storage array. Multiple bit line precharge circuits 300 are also connected to multiple bit lines BL in the storage array. Multiple word line power circuits 400 are respectively connected to multiple word lines WL in the storage array. The control ends of the multiple word line power circuits 400 are respectively connected to the multiple power control circuits 100.

[0103] In this embodiment, the output ends of the multiple power control circuits 100 are respectively connected to the control ends of the multiple word line power circuits 400 to control the multiple word line power circuits 400 to supply power to the connected word lines. The input end of the sampling feedback circuit of each power control circuit 100 is connected to the word line end of the corresponding word line power circuit 400 to sample the word line voltage.

[0104] It should be noted that when the read / write circuit reads and writes the storage array, all bit lines can be precharged uniformly. Therefore, only one power control circuit needs to be set. However, when reading and writing, only the storage units with the word lines set to high level will be executed for read / write operations. Therefore, each word line corresponds to a power control circuit.

[0105] Based on the read / write circuit provided in the above embodiment, the embodiment of the present application further provides a memory, including the read / write circuit as Figure 6 or as Figure 7 shown and a storage array.

[0106] The storage array is composed of M*N storage cells. The word lines of the storage cells in the same row are connected, the bit lines of the storage cells in the same column are connected, the complementary bit lines are connected, and each read / write unit in the read / write circuit can be connected to at least one bit line in the storage array.

[0107] The above are only the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A power control circuit, characterized in that: The electric energy control circuit comprises: a first control circuit, a second control circuit, a sampling feedback circuit and an output selection circuit; The first input end of the first control circuit is used to receive a preset clock signal, and the second input end of the first control circuit is used to receive a preset power control signal, so that the first control circuit generates a first control signal based on the preset power control signal and the preset clock signal, and the preset clock signal is a clock signal obtained by performing a logic operation on a logic clock signal of the memory where the read / write circuit is located and a sleep signal; The control end of the sampling feedback circuit is connected to the output end of the first control circuit, the input end of the sampling feedback circuit is used to connect to the output end of the bit line precharge circuit or the word line power supply circuit in the read / write circuit, and the output end of the sampling feedback circuit is connected to the input end of the second control circuit, so that the second control circuit outputs a second control signal based on the sampling feedback signal; The output end of the first control circuit and the output end of the second control circuit are connected to the first input end and the second input end of the output selection circuit respectively, and the third input end of the output selection circuit is used to receive the preset clock signal, so that the output selection circuit outputs the target power control signal based on the preset clock signal, the first control signal and the second control signal; The output end of the output selection circuit is used to connect to the control end of the bit line precharge circuit or the word line power supply circuit to control the bit line precharge circuit or the word line power supply circuit to provide power to the corresponding bit line or word line according to the output target power control signal.

2. The power control circuit according to claim 1, characterized in that: The first control circuit includes: a first NAND gate, a first NOT gate, and a second NOT gate; The first input end of the first NAND gate serves as the first input end of the first control circuit, the input end of the first NOT gate serves as the second input end of the first control circuit, the output end of the first NOT gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate serves as the output end of the first control circuit; When the preset clock signal is at a high level, the first control signal is a negated signal of the preset power control signal.

3. The power control circuit according to claim 1, characterized in that: The second control circuit includes: a voltage-dividing sampling protection circuit and a Schmitt trigger; The input end of the voltage-dividing sampling protection circuit serves as the feedback input end of the second control circuit, the output end of the voltage-dividing sampling protection circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger serves as the output end of the second control circuit.

4. The power control circuit according to claim 3, characterized in that: The voltage-dividing sampling protection circuit comprises: a voltage-dividing sampling circuit, a first switching tube and a protection resistor; The input end of the voltage-dividing sampling circuit serves as the input end of the voltage-dividing sampling protection circuit, the output end of the voltage-dividing sampling circuit is connected to the gate of the first switching tube, one of the source or drain of the first switching tube is used to connect to a preset power supply voltage, the other of the source or drain of the first switching tube is connected to the protection resistor, and the connection point serves as the output end of the voltage-dividing sampling protection circuit.

5. The power control circuit according to claim 1, characterized in that: The output selection circuit comprises: a first NOR gate and a second NOR gate; The first input end of the first NOR gate and the first input end of the second NOR gate serve as the first input end and the second input end of the output selection circuit respectively, the second input end of the first NOR gate serves as the third input end of the output selection circuit, the output end of the first NOR gate is connected to the second input end of the second NOR gate, and the output end of the second NOR gate serves as the output end of the output selection circuit.

6. The power control circuit according to claim 1, characterized in that: The sampling feedback circuit comprises: a second switch tube; One of the source or the drain of the second switch tube is connected to the bit line end of the bit line precharging circuit or the word line voltage end of the word line power supply circuit, the gate of the second switch tube serves as the control end of the sampling feedback circuit, and the other of the source or the drain of the second switch tube serves as the output end of the sampling feedback circuit.

7. The power control circuit according to claim 1, characterized in that: The sampling feedback circuit comprises: a third switch tube and a fourth switch tube; One of the source or drain of the third switch tube is used to connect to the bit line end of the bit line precharging circuit, and one of the source or drain of the fourth switch tube is used to connect to the complementary bit line end of the bit line precharging circuit; The gate of the third switch tube and the gate of the fourth switch tube are connected as the control end of the sampling feedback circuit, and the other of the source or drain of the third switch tube and the other of the source or drain of the fourth switch tube are connected to the output end of the sampling feedback circuit.

8. A read-write circuit, characterized in that: The read / write circuit comprises: a plurality of read / write units, a plurality of bit line pre-charging circuits, a plurality of word line power supply circuits and a power control circuit; Each read / write unit is used to connect at least one bit line in the storage array, the plurality of bit line precharging circuits are also connected to the plurality of bit lines in the storage array, the control ends of the plurality of bit line precharging circuits are all connected to the power control circuit, and the power control circuit is a circuit as claimed in any one of claims 1 to 7; The plurality of word line power supply circuits are respectively connected to a plurality of word lines of the memory array.

9. A read-write circuit, characterized in that: The read / write circuit comprises: a plurality of read / write units, a plurality of bit line pre-charging circuits, a plurality of word line power supply circuits and a plurality of power control circuits; Each read / write unit is connected to at least one bit line in the storage array, and the plurality of bit line precharging circuits are respectively connected to the plurality of bit lines in the storage array; The multiple word line power supply circuits are respectively connected to the multiple word lines of the storage array, and the control ends of the multiple word line power supply circuits are respectively connected to the multiple power control circuits, and the multiple power control circuits are the circuits as described in any one of claims 1 to 6.

10. A memory, characterized in that: The memory comprises the read / write circuit and the storage array as claimed in claim 8 or 9.

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