Semiconductor device and memory module

Abstract

Provided are a semiconductor device and a memory module capable of correctly maintaining a phase relationship between a data signal and a data strobe signal that determines a latch timing of the data signal. A variable delay circuit VDLYsA generates corresponding data strobe signals DQSin, DQSinM by delaying an input data strobe signal MDQS by a delay amount ST1, ST2. The timing adjustment circuit TMCT adjusts the delay amount ST1 based on a determination of a match / mismatch between the data signal DQo from the main limiter SLr and the data signal DQoM from the monitor limiter SLrM while changing the delay amount ST2.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese patent application No. 2023-188107 filed on November 2, 2023 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device and a memory module, for example, a semiconductor device such as a data buffer mounted on a memory module.

[0004] The disclosed techniques are listed below.

[0005] [Non-Patent Document 1] “DDR5 Data Buffer Definition (DDR5DB01)-Rev1.1”, JESD82-521, JEDEC Solid State Technology Association, December 2021, page 17

[0006] Non-patent document 1 defines standard specifications for a DDR5 data buffer for driving DQ and DQS signals in DDR5 LRDIMM applications, particularly specifications related to parameters and testing of DC and AC interfaces. Summary of the invention

[0007] For example, in systems such as clouds and enterprises, high-speed memory modules such as DDR5 (Double Data Rate 5) LRDIMM (Load Reduced Dual In-line Memory Module) are used. As shown in Non-Patent Document 1, such a memory module is equipped with a data buffer for driving a data signal (DQ signal) and a data selection signal (DQS signal). The data buffer includes a data holding circuit called a limiter, which latches the input DQ signal at the edge of the DQS signal. The data buffer uses a variable delay circuit to adjust the phase of the DQS signal, such as in an initial sequence, to ensure this latching operation.

[0008] On the other hand, in the data buffer, for example, a decision feedback equalizer (DFE) or the like capable of improving signal quality may be inserted in the transmission path of the input DQ signal. For example, the delay time of the DFE varies according to changes in the environment such as temperature and voltage. As a result, even if the phase of the DQS signal is adjusted by the initial sequence, the phase of the DQ signal may vary according to changes in the environment, so that the phase relationship between the DQ signal and the DQS signal may not be correctly maintained.

[0009] The embodiments described later are made in view of such problems, and other problems and novel features will become clear from the description of this specification and the accompanying drawings.

[0010] A semiconductor device according to one embodiment includes a first data holding circuit and a second data holding circuit, a variable delay circuit, and a timing adjustment circuit. The first data holding circuit latches an input data signal synchronously with a first data strobe signal. The second data holding circuit latches an input data signal synchronously with a second data strobe signal. The variable delay circuit generates a first data strobe signal and a second data strobe signal by delaying the input data strobe signal by a first delay amount and a second delay amount, respectively. The timing adjustment circuit adjusts the first delay amount based on the determination result by determining a match / mismatch between a first data signal from the first data holding circuit and a second data signal from the second data holding circuit while changing the second delay amount.

[0011] According to one embodiment, the phase relationship between a data signal and a data strobe signal defining latch timing of the data signal can be correctly maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram showing a configuration example of a memory module according to the first embodiment;

[0013] Figure 2 It is shown Figure 1 A circuit block diagram showing an example of a schematic configuration of a main portion of a data buffer in FIG.

[0014] Figure 3 is a diagram showing a method according to the first embodiment Figure 2 A circuit block diagram showing an example of a schematic configuration of a read latch circuit associated with a data buffer shown;

[0015] Figure 4 It is shown Figure 3 A circuit block diagram of a configuration example of a variable delay circuit in;

[0016] Figure 5 is shown with Figure 3 A circuit block diagram of an example configuration of a related adder / subtractor;

[0017] Figure 6 is shown with Figure 3 a timing diagram of a schematic operation example of a related read latch circuit;

[0018] Fig. 7A It is shown Figure 3 A flowchart showing an example of the processing contents of the buffer control circuit shown;

[0019] Figure 7B It is used to explain Fig. 7A Figure supplementing the flowchart shown;

[0020] Figure 7C It is used to explain Fig. 7A Figure supplementing the flowchart shown;

[0021] Figure 8 FIG. 1 is a diagram showing a semiconductor device according to a second embodiment. Figure 2 A circuit block diagram showing an example of a schematic configuration of a read latch circuit associated with a data buffer shown;

[0022] Fig. 9 It is shown Figure 8 A circuit block diagram of a configuration example of a variable delay circuit in;

[0023] Fig. 10A As a first comparative example, Figure 2 A circuit block diagram showing an example of a schematic configuration of a read latch circuit associated with a data buffer shown;

[0024] Fig. 10B is shown with Fig. 10A A timing diagram of an operation example of a related read latch circuit;

[0025] Fig.11A As a second comparative example, Figure 2 A circuit block diagram showing an example of a schematic configuration of a read latch circuit associated with a data buffer shown; and

[0026] Fig. 11B is shown with Fig.11A A timing diagram of an operation example of a related read latch circuit. DETAILED DESCRIPTION

[0027] In the following embodiments, for convenience, when necessary, the embodiments are described by being divided into a plurality of parts or embodiments. Unless otherwise specified, these parts or embodiments are not independent of each other; one part or embodiment may be part or all of a modified example, detail, supplementary description, etc. of another part or embodiment. In addition, in the following embodiments, when the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is mentioned, unless otherwise specified and clearly limited to a specific number in principle, it is not limited to the specific number, but may be more or less than the specific number.

[0028] In addition, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily necessary unless they are specifically indicated or are considered to be obviously necessary in principle. Similarly, in the following embodiments, when the shapes, positional relationships, etc. of components, etc. are mentioned, it is assumed that those that are substantially similar or similar to the shapes, etc. are included unless they are specifically indicated and are considered not to be so in principle. This also applies to the above-mentioned numerical values ​​and ranges.

[0029] Furthermore, the circuit elements constituting each functional block of the embodiment are not particularly limited but are formed on a semiconductor substrate such as single crystal silicon by an integrated circuit technology called CMOS (Complementary MOS Transistor) or the like.

[0030] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated descriptions are omitted. In addition, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary.

[0031] (First Embodiment) <Schematic Operation of Memory Module>

[0032] Figure 1 is a schematic diagram showing a configuration example of a memory module according to the first embodiment. For example, Figure 1 The memory module MDL shown is an LRDIMM. The memory module MDL includes a module wiring substrate MB, a plurality of memory chips MEM mounted on the module wiring substrate MB, a plurality of data buffers DB, and a register clock driver RCD.

[0033] In addition, the module wiring substrate MB is equipped with a plurality of external terminals. The plurality of external terminals include a control external terminal PNc and data external terminals PNdA, PNdB. The control external terminal PNc is an input terminal for memory control signals such as a clock signal CLK, a command signal CMD, and an address signal ADD. The data external terminals PNdA, PNdB are input / output terminals for a data signal DQ and a data selection signal DQS.

[0034] The register clock driver RCD is composed of, for example, a single semiconductor chip. The register clock driver RCD re-drives the memory control signal input via the control external terminal PNc, and outputs it to the plurality of memory chips MDL via the CA bus BS_CA. In addition, the register clock driver RCD generates a buffer control signal for the data buffer DB based on the input memory control signal, and outputs it to the plurality of data buffers DB via the BCOM bus BS_BCOM.

[0035] For example, each of the plurality of data buffers DB is composed of a single semiconductor chip. The plurality of data buffers DB identifies the write period and the read period of the memory chip MEM based on the buffer control signal from the register clock driver RCD. During the write period, the plurality of data buffers DB re-drive the data signal DQ and the data strobe signal DQS input through the external terminals PNdA, PNdB for data, and output them to the plurality of memory chips MEM. During the read period, the plurality of data buffers DB re-drive the data signal DQ and the data strobe signal DQS from the plurality of memory chips MEM, and output them to the external terminals PNdA, PNdB for data.

[0036] Each memory chip in the plurality of memory chips MEM is, for example, a DDR-SDRAM chip, specifically, a DDR5-SDRAM chip. Each memory chip MEM performs a write operation or a read operation in response to a memory control signal from a CA bus BS_CA. During a write operation, each memory chip MEMS uses a data strobe signal DQS to obtain a data signal DQ from a data buffer DB and writes it to a selected memory cell. During a read operation, each memory chip MEM outputs the data signal DQ read from the selected memory cell to the data buffer DB together with the data strobe signal DQS.

[0037] The host disposed outside the memory module MDL inputs and outputs the "2×m" bit data signal DQ input and output by the data buffer DB through the m-bit data terminal included in the external terminals PNdA and PNdB for data. At this time, the host inputs and outputs the m-bit data signal DQ within a half clock cycle "(1 / 2)Tck" based on the twice clock frequency "2×fck", and inputs and outputs the m-bit data signal DQ within the next half clock cycle. The register clock driver RCD and the plurality of data buffers DB absorb the speed difference between the memory interface MEM_IF and the host interface HST_IF by buffering.

[0038] Figure 2 It is shown Figure 1 1 is a circuit block diagram of a schematic configuration example of a main part of a data buffer DB in FIG. 10 . In order to simplify the explanation, a configuration example focusing on a 1-bit data signal DQ is shown. Figure 2The data buffer DB shown includes drivers TXh_St, TXh_Sc, TXh_D, receivers RXh_S, RXh_D, and a limiter SLw arranged on the host interface HST_IF side. In addition, the data buffer DB includes drivers TXm_St, TXm_Sc, TXm_D, and a read latch circuit RLT arranged on the memory interface MEM_IF side. In addition, the data buffer DB includes a buffer control circuit CTRL, a read buffer BUFR, and a write buffer BUFW.

[0039] Drivers TXh_St and TXh_Sc output complementary data strobe signals DQSt and DQSc to the host interface HST_IF side. Receiver RXh_S differentially inputs complementary data strobe signals DQSt and DQSc from the host interface HST_IF side, and outputs a clock signal for latching to the limiter SLw. Driver TXh_D outputs data from the read buffer BUFR as data signal DQ[n] to the host interface HST_IF side.

[0040] The receiver RXh_D differentially inputs the data signal DQ[n] from the host interface HST_IF side and the pre-generated reference voltage Vref, and outputs the data signal DQ[n] to the limiter SLw. The limiter SLw is composed of components such as a trigger. The limiter SLw latches the data signal DQ[n] from the receiver RXh_D in synchronization with the clock signal from the receiver RXh_S.

[0041] At the same time, drivers TXm_St and TXm_Sc output complementary data strobe signals MDQSt and MDQSc to the memory interface MEM_IF side. The read latch circuit RLT includes receivers RXm_S and RXm_D, a variable delay circuit VDLYs and a limiter SLr. The receiver RXm_S differentially inputs complementary data strobe signals MDQSt and MDQSc from the memory interface MEM_IF side, and outputs a clock signal for latching to the variable delay circuit VDLYs. The variable delay circuit VDLYs delays the input clock signal and outputs it to the limiter SLr.

[0042] The receiver RXm_D differentially inputs the data signal MDQ[n] from the memory interface MEM_IF side and the pre-generated reference voltage Vref, and outputs the data signal MDQ[n] to the limiter SLr. The limiter SLr is a data holding circuit composed of components such as a flip-flop. The limiter SLr latches the data signal MDQ[n] from the receiver RXm_D in synchronization with the clock signal from the variable delay circuit VDLYs.

[0043] Each of the read buffer BUFR and the write buffer BUFW is composed of, for example, a FIFO (First In First Out) buffer. The read buffer BUFR stores the data signal MDQ[n] from the slicer SLr on the memory interface MEM_IF side. Then, the read buffer BUFR outputs the stored data signal MDQ[n] as a data signal DQ[n] to the host interface HST_IF side through the driver TXh_D.

[0044] At the same time, the write buffer BUFW stores the data signal DQ[n] from the slicer SLw on the host interface HST_IF side. Then, the write buffer BUFW outputs the stored data signal DQ[n] as the data signal MDQ[n] to the memory interface MEM_IF side through the driver TXm_D.

[0045] The buffer control circuit CTRL inputs a buffer control signal from the BCOM bus BS_BCOM, and outputs an internal control signal CT for controlling each part in the data buffer DB based on the buffer control signal. The buffer control signal includes, for example, a clock signal BCK, a command signal BCOM, a chip select signal BCS, and a reset signal BRST. The internal control signal CT includes, for example, an enable signal for a driver and a receiver, an input clock and an output clock for a read buffer BUFR and a write buffer BUFW, and a setting value for a delay amount of a variable delay circuit VDLYs.

[0046] In addition, the buffer control circuit CTRL includes a phase-locked loop (PLL). The phase-locked loop (PLL) generates a new clock signal CK synchronized with the input clock signal BCK. Using the generated clock signal CK, the buffer control circuit CTRL generates complementary data strobe signals MDQSt, MDQSc for the memory interface MEM_IF side, and complementary data strobe signals DQSt, DQSc for the host interface HST_IF side.

[0047] <Configuration and Operation Related to Read Latch Circuit (Comparative Example)>

[0048] Fig. 10A is shown as Figure 2 A circuit block diagram showing a schematic configuration example of the read latch circuit RLTc of the first comparative example in the data buffer DB shown. Fig. 10B is shown with Fig. 10A A timing diagram showing an operation example related to the read latch circuit RLTc is shown. Fig. 10A The read latch circuit RLTc shown includes receivers RXm_D, RXm_S, a variable delay circuit VDLYs_C and a limiter SLr, similar to Figure 2 situation.

[0049] also, Fig. 10A The buffer control circuit CTRLc shown includes, for example, a delay locked loop (DLL). The delay locked loop (DLL) includes a variable delay circuit VDLYc, a phase comparator PHD, and a decoder QDEC. The phase comparator PHD searches for the delay amount of the variable delay circuit VDLYc so that the phase of the clock signal CK from the phase locked loop (PLL) matches the phase of the clock signal delayed by the variable delay circuit VDLYc. Therefore, the delay amount is determined by the period "Tck" of the clock signal CK.

[0050] The decoder QDEC sets a value "(1 / 4)Tck" which is one quarter of the delay amount "Tck" in the variable delay circuit VDLYs_C within the read latch circuit RLTc. As a result, the data strobe signal MDQS from the receiver RXm_S is input to the limiter SLr as the data strobe signal DQSin after a delay time of "(1 / 4)Tck". The limiter SLr latches the data signal DQin from the receiver RXm_D in synchronization with the data strobe signal DQSin.

[0051] Specifically, Fig. 10B As shown, first, the phase of the data signal MDQ[n] output from the memory chip MEM is matched with the phase of the data strobe signal MDQS. In addition, the delay time td_dq in the transmission path of the data signal MDQ[n] and the delay time td_dqs in the transmission path of the data strobe signal MDQS are pre-adjusted to be equal.

[0052] The delay time td_dq is the delay time from the output terminal of the memory chip MEM to the data input node of the limiter SLr, including the delay time of the receiver RXm_D and the delay time of the wiring of the transmission path. Similarly, the delay time td_dqs is the delay time from the output terminal of the memory chip MEM to the clock input node of the limiter SLr, including the delay time of the receiver RXm_S and the delay time of the wiring of the transmission path.

[0053] Therefore, by adding the delay time "(1 / 4)Tck" from the decoder QDEC to the delay time td_dqs of the variable delay circuit VDLYs_C, the edge timing of the data selection signal DQSin can be set in the middle of the eye width W of the data signal DQin at the input node of the limiter SLr. Fig. 10B States of the data strobe signal DQSin and the data signal DQin under a typical case (typ) and a worst case (WC) are shown.

[0054] The worst case (WC) refers to a case where the delay time varies the most in response to changes in the environment such as temperature and voltage, for example. Since the receivers RXm_D, RXm_S are generally composed of similar circuits, the delay time of each receiver RXm_D, RXm_S is equal even if the environment changes. Therefore, even in the worst case (WC), the edge timing of the data strobe signal DQSin can be set in the middle of the eye width W of the data signal DQin.

[0055] Fig.11A is shown with as Figure 2 A circuit block diagram showing a schematic configuration example of the read latch circuit RLTd of the second comparative example in the data buffer DB shown. Fig. 11B is shown with Fig.11A A timing diagram showing an operation example related to the read latch circuit RLTd is shown. Fig.11A The read latch circuit RLTd shown includes Fig. 10A Compared to the configuration example shown, an adder-subtractor DFE_SUM is added, which is a component of the decision feedback equalizer (DFE). The adder-subtractor DFE_SUM is inserted into the wiring between the receiver RXm_D and the limiter SLr. As for the buffer control circuit CTRLc, it is connected to Fig. 10A The same situation.

[0056] For example, Figure 1 As shown, when a 2-column configuration is used to widen the bandwidth of the memory, power consumption increases compared to the case of a 1-column configuration. In order to suppress the increase in power consumption, the transmission path between the memory chip MEM and the data buffer DB can be made to have a high impedance. Specifically, for example, the resistance value of the terminal resistor in the transmission path is increased and the signal amplitude in the transmission path can be reduced.

[0057] However, in this case, the signal quality in the transmission path may deteriorate. Fig.11A In the example shown, a decision feedback equalizer (DFE) is provided to compensate for the degradation of signal quality. The decision feedback equalizer (DFE) is provided not only to compensate for the side effects associated with low power consumption, but also to simply compensate for the degradation of signal quality associated with higher data transmission speeds.

[0058] However, when a decision feedback equalizer (DFE) is provided, such as Fig. 11B As shown, Fig. 10BThe phase relationship between the data signal DQin and the data strobe signal DQSin may not be correctly maintained, depending on the situation. To explain in detail, first, for example, by appropriately setting the initial value of the variable delay circuit VDLYs_C during the training period of the initial sequence, the delay time td_dq in the transmission path of the data signal MDQ[n] and the delay time td_dqs in the transmission path of the data strobe signal MDQS are set to equal values. This state corresponds to a typical situation (typ).

[0059] On the other hand, the adder-subtractor DFE_SUM is composed of an analog circuit. Therefore, the delay time caused by the adder-subtractor DFE_SUM may vary by the time "dt" according to changes in environments such as temperature and voltage. Therefore, the time "dt" is simply added to or subtracted from the delay time td_dq. As a result, as shown in the worst case (WC), the phase relationship between the data signal DQin and the data strobe signal DQSin changes, and the limiter SLr may not be able to correctly latch the data signal DQin with the data strobe signal DQSin.

[0060] In this case, for example, by resetting the initial value of the variable delay circuit VDLYs_C through retraining, it is possible to return to a state similar to the typical case (typ). Specifically, for example, considering changes in the environment, it is recommended to perform training regularly. However, performing training regularly will reduce the operating time of the system during training. Therefore, it is beneficial to use the method of the following embodiment.

[0061] <Configuration Related to Readout Latch Circuit (Embodiment)>

[0062] Figure 3 It is shown Figure 2 1 is a circuit block diagram of a schematic configuration example of a sense latch circuit RLTa related to the first embodiment in a data buffer DB shown. Figure 4 It is shown Figure 3 A circuit block diagram of a configuration example of the variable delay circuit VDLYs_A in FIG. Figure 5 is shown with Figure 3 A circuit block diagram of a configuration example related to the adder-subtractor DFE_SUM in FIG.

[0063] Similar to Fig.11A situation, Figure 3 The sensing latch circuit RLTa shown includes receivers RXm_D, RXm_S, a main limiter (first data holding circuit) SLr, and an adder-subtractor DFE_SUM. In addition, the sensing latch circuit RLTa includes a monitoring limiter (second data holding circuit) SLr_M and a variable delay circuit VDLYs_A, which is similar to Fig.11A The situation is different.

[0064] Similar to Fig.11A In the case of, the receivers RXm_D, RXm_S respectively input the data signal MDQ[n] and the data strobe signal MDQS from the memory chip MEM. Each of the receivers RXm_D, RXm_S is composed of a differential amplifier, and more specifically, a differential variable gain amplifier (VGA), such as Figure 2 Shown in detail.

[0065] The master limiter (first data holding circuit) SLr latches the input data signal DQin transmitted from the memory chip MEM through the receiver RXm_D and the adder / subtractor DFE_SUM in synchronization with the master data strobe signal (first data strobe signal) DQSin. At the same time, the monitoring limiter (second data holding circuit) SLr_M latches the input data signal DQin in synchronization with the monitoring data strobe signal (second data strobe signal) DQSin_M.

[0066] The variable delay circuit VDLYs_A delays the input data strobe signal MDQS transmitted from the memory chip MEM through the receiver RXm_S by the main delay amount (first delay amount) ST1 and the monitoring delay amount (second delay amount) ST2, respectively. Therefore, the variable delay circuit VDLYs_A generates a main data strobe signal DQSin reflecting the main delay amount ST1 and a monitoring data strobe signal DQSin_M reflecting the monitoring delay amount ST2.

[0067] like Figure 4 As shown in detail, the variable delay circuit VDLYs_A includes a series of connected delay elements DE[0]-DE[k] and selection circuits SEL1 and SEL2. Each of the plurality of delay elements DE[0]-DE[k] is composed of, for example, a two-stage CMOS inverter circuit that implements a delay of a unit delay time "dTof".

[0068] The selection circuit SEL1 selects one from the multiple outputs of the multiple delay elements DE[0]-DE[k] based on the main delay amount ST1, and outputs it as the main data strobe signal DQSin. Similarly, the selection circuit SEL2 selects one from the multiple outputs of the multiple delay elements DE[0]-DE[k] based on the monitoring delay amount ST2, and outputs it as the monitoring data strobe signal DQSin_M.

[0069] Back to Figure 3 , except for something like Fig.11AThe buffer control circuit CTRLa includes a timing adjustment circuit TMCT in addition to a delay locked loop (DLL) for the case of the buffer control circuit CTRLa. The timing adjustment circuit TMCT has an exclusive OR circuit EOR and a search circuit SC. The exclusive OR circuit EOR is a data determination circuit for determining a match / mismatch between a data signal (first data signal) DQo from a main limiter SLr and a data signal (second data signal) DQo_M from a monitoring limiter SLr_M. The exclusive OR circuit EOR outputs a monitoring determination result MPF indicating a match / mismatch (in other words, pass / fail).

[0070] The search circuit SC usually monitors the monitoring determination result MPF while changing the monitoring delay amount ST2, and adjusts the main delay amount ST1 based on the monitoring determination result MPF. As a prerequisite for starting such adjustment, the initial value of the main delay amount ST1 before adjustment needs to be reasonable and appropriate. That is, the initial value of the main delay amount ST1 must at least enable the main limiter SLr to correctly latch the input data signal DQin. Therefore, the search circuit SC determines the initial value of the main delay amount ST1 by reflecting the "(1 / 4) Tck" from the delay locked loop (DLL).

[0071] The adder / subtractor DFE_SUM is a component of a decision feedback equalizer (DFE) and is inserted into the transmission path of the input data signal DQin. The decision feedback equalizer (DFE) performs waveform equivalence of the input data signal DQin. Specifically, Figure 5 As shown, the decision feedback equalizer (DFE) includes an adder / subtractor DFE_SUM and a main limiter SLr, in addition to a plurality of delay circuits DLY2, DLY3, ... and a plurality of weighting circuits W1, W2, W3, ...

[0072] Each of the plurality of delay circuits DLY2, DLY3, ... is composed of, for example, a flip-flop similar to the limiter SLr, and implements a delay of one clock cycle. The weighting circuit W1 applies weighting, i.e., multiplication, to the output of the limiter SLr. Similarly, the weighting circuits W2, W3, ... apply weighting to the outputs of the delay circuits DLY2, DLY3, ..., respectively. The adder / subtractor DFE_SUM adds or subtracts the outputs from the plurality of weighting circuits W1, W2, W3, ... to the input data signal MDQ[n].

[0073] <Schematic Operation Related to Read Latch Circuit (Embodiment)>

[0074] Figure 6 is shown with Figure 31 is a timing diagram of an exemplary schematic operation related to the read latch circuit RLTa shown in FIG. The timing adjustment circuit TMCT sequentially changes the monitoring delay amount ST2 while keeping the main delay amount ST1 fixed. Therefore, based on the edge timing of the main data strobe signal DQSin, the edge timing of the monitoring data strobe signal DQSin_M is scanned on the setting side and the holding side, as shown in FIG. Figure 6 shown.

[0075] Then, by sequentially changing the monitoring delay amount ST2 in this manner and monitoring the monitoring determination result MPF from the exclusive OR circuit EOR, the timing adjustment circuit TMCT can detect the eye width W of the input data signal DQin based on the edge timing at the change point from pass (match) to fail (mismatch). The timing adjustment circuit TMCT adjusts the main delay amount ST1 so that the edge timing of the main data strobe signal DQSin is located at the center of the eye width W.

[0076] By using this method, the phase relationship between the data signal (input data signal DQin) and the data strobe signal (main data strobe signal DQSin) that determines the latch timing of the data signal can be correctly maintained. That is, the edge timing of the data strobe signal can be fixed at the center of the eye width W of the data signal.

[0077] In addition, by providing the monitoring limiter SLr_M and scanning the monitoring data strobe signal DQSin_M, the eye width W of the input data signal DQin can be detected without affecting the normal read operation in the memory chip MEM. That is, in the subsequent stage, while the data signal DQo from the main limiter SLr is transmitted to the data external terminals PNdA, PNdB as the read data signal from the memory chip MEM, as shown in FIG. Figure 1 As shown, the eye width W of the input data signal DQin can be detected in the background.

[0078] Therefore, for example, during a normal read operation, even if the environment such as temperature and voltage changes, and thus the delay time of the transmission path changes due to a decision feedback equalizer (DFE) or the like, the strobe timing can be optimized while tracking the change in real time. Therefore, a system that is robust to environmental changes can be realized. In addition, for example, it is not necessary to interrupt the normal read operation to retrain the strobe timing or the like. Therefore, the operating time of the system can be ensured.

[0079] In addition, since the change in the delay time of the transmission path can be compensated according to the change in the environment, a circuit with temperature dependence, such as a decision feedback equalizer (DFE), can be easily installed in the transmission path. By installing a decision feedback equalizer (DFE), higher data transmission speed and lower power consumption can be achieved, such as Fig.11AIt should be noted that although the examples described herein involve inserting a decision feedback equalizer (DFE) into a data signal transmission path, the circuit to be inserted is not limited thereto, and may also be another circuit having temperature dependency.

[0080] <Details of Buffer Control Circuit (Timing Adjustment Circuit)>

[0081] Fig. 7A It is shown Figure 3 A flowchart showing an example of the processing contents of the buffer control circuit CTRLa shown. Figure 7B and Figure 7C It is used to explain Fig. 7A Supplementary figure to the flowchart shown. Fig. 7A The processing contents during the initial sequence period (step S10) and the processing contents during the subsequent normal operation period (step S20) are shown. These processes are mainly performed by the timing adjustment circuit TMCT. The timing adjustment circuit TMCT is executed by executing Fig. 7A It consists of a sequencer for the processing shown.

[0082] In the initial sequence period (step S10), first, the delay locked loop (DLL) is locked (step S101). Fig. 10A and Fig. 10B As shown, the phase comparison result of the phase comparator PHD converges, and therefore, the decoder QDEC outputs the delay amount “(1 / 4)Tck”. Subsequently, the buffer control circuit CTRLa performs read training using a well-known training circuit during the training period of the memory chip MEM (step S102 ).

[0083] For example, by reading training, such as Fig.11A and Fig. 11B As shown, the delay amount of the variable delay circuit in which "td_dq=td_dqs" is searched. Figure 3 The timing adjustment circuit TMCT in the embodiment determines the initial value of the main delay amount ST1 by adding the delay amount "(1 / 4)Tck" from the decoder QDEC to the delay amount acquired during the read training. Thus, for example, Fig. 11B The state shown in the typical case (typ).

[0084] In the subsequent normal operation period (step S20), the timing adjustment circuit TMCT starts its operation by setting the main delay amount ST1 from the state determined by the initial value acquired during the initial sequence period (step S10). In summary, in step S20, the following processing is performed.

[0085] First, if Figure 7BAs shown, the timing adjustment circuit TMCT generates a corresponding monitoring delay amount ST2 based on the edge timing tm of the main data strobe signal DQSin to obtain the edge timing th, ts of the monitoring data strobe signal DQSin_M. The edge timing th, ts is a timing that is offset from the edge timing tm by "N times dTof" ("N×dTof") on both the hold and set sides. Initially, "N" is determined as an initial value "N_init" (step S201).

[0086] The timing adjustment circuit TMCT determines pass / fail based on the monitoring judgment result MPF when the edge timing of the monitoring data strobe signal DQSin_M is set to one of the edge timings th and ts, and then determines pass / fail based on the monitoring judgment result MPF when the edge timing is set to the other of the edge timings th and ts. Then, as long as the monitoring judgment result MPF is pass, the timing adjustment circuit TMCT sequentially increases the integer "N" to gradually expand the offset width of the edge timings th and ts based on the edge timing tm (steps S202-S206).

[0087] Here, the monitoring judgment result MPF in steps S203 and S205 is obtained by using the normal reading operation of the memory chip MEM. Figure 7C As shown, during the normal operation of the memory module MDL and the memory chip MEM, a write cycle and a read cycle Trd1, Trd2 are appropriately included. The buffer control circuit CTRLa and the timing adjustment circuit TMCT can identify the data reading period in the read cycle Trd1, Trd2 based on the buffer control signal from the BCOM bus BS_BCOM, as shown in FIG. Figure 2 shown.

[0088] Therefore, for example, in step S203, the timing adjustment circuit TMCT acquires the monitoring judgment result MPF at the holding side edge timing th during the data reading period in the reading cycle Trd1. Subsequently, in step S205, the timing adjustment circuit TMCT acquires the monitoring judgment result MPF at the setting side edge timing ts during the data reading period in the reading cycle Trd2.

[0089] On the other hand, if the offset widths of the edge timings th, ts are sequentially expanded, at a certain point, a failure occurs in at least one of the edge timings th, ts. First, assume a case where a failure occurs at the edge timing th on the holding side and a failure also occurs at the edge timing ts on the setting side (steps S202, S203, S207, S208, S211). This state indicates that the main edge timing tm is located at the center of the eye width W of the input data signal DQin. Therefore, the timing adjustment circuit TMCT maintains the main edge timing tm (i.e., the main delay amount ST1) unchanged (step S211), and returns to the state corresponding to step S201. Figure 7B Status shown.

[0090] Next, it is assumed that a failure occurs at the holding side edge timing th and a pass occurs at the setting side edge timing ts (steps S202, S203, S207, S208, S210). This state indicates that the main edge timing tm is located on the holding side instead of the center of the eye width W. Therefore, the timing adjustment circuit TMCT shifts the main edge timing tm by the unit delay time "dTof" in the setting direction (i.e., in the direction of delay reduction) (step S210), and returns to step S201.

[0091] Finally, assume a situation where a pass occurs at the holding side edge timing th and a fail occurs at the setting side edge timing ts (steps S202, S203, S204, S205, S209). This state indicates that the main edge timing tm is located on the setting side instead of the center of the eye width W. Therefore, the timing adjustment circuit TMCT shifts the main edge timing tm by the unit delay time "dTof" in the holding direction (i.e., in the direction of increasing delay) (step S209), and returns to step S201.

[0092] For example, by using such a flowchart, during the normal operation period (step S20), the edge timing tm of the main data strobe signal DQSin can be fixed to the center of the eye width W of the input data signal DQin. Therefore, by optimizing the main delay amount ST1 during the normal operation period (step S20), for example, during the initial sequence period (S10), it is not necessary to accurately determine the initial value of the main delay amount ST1, and specifically, it is not necessary to determine the main delay amount ST1. As a result, for example, the delay locked loop (DLL) can be simplified, and the time required to lock the delay locked loop (DLL), that is, the time required for the process in step S101, can also be shortened.

[0093] <About various additional matters>

[0094] More specifically, in a DDR-SDRAM chip, a plurality of data signals MDQ are assigned to a single data strobe signal MDQS. In this case, the timing adjustment circuit TMCT may, for example, perform the following steps: Fig. 7A The process shown targets a representative data signal among the plurality of data signals MDQ selected therefrom.

[0095] Alternatively, the timing adjustment circuit TMCT may perform as follows Fig. 7A In the processing shown in FIG. 1 , the target is a plurality of data signals MDQ. In this case, a plurality of monitoring determination results MPF targeting a plurality of data signals MDQ can be obtained simultaneously on both the holding side and the setting side. For example, the timing adjustment circuit TMCT can perform the following steps: Fig. 7A In the process shown, if one or more of the multiple monitoring determination results MPF fail, the entire set is considered to have failed.

[0096] In addition, for example, in Figure 7C In the embodiment, each of the read cycles Trd1, Trd2 may include multiple data signals MDQ in time series due to burst reading, etc. In this case, the timing adjustment circuit TMCT may, for example, obtain multiple monitoring determination results MPF of the multiple data signals MDQ, and if one or more of them fail, the entire set is regarded as failed and the following is performed. Fig. 7A Processing shown.

[0097] Notice, Figure 3 The application of the configuration of the read latch circuit RLTa and the buffer control circuit CTRLa shown is not necessarily limited to the memory module MDL. That is, the configuration can also be applied to a semiconductor chip such as a SoC constituting a host, and a memory interface circuit mounted on the semiconductor chip.

[0098] <Main Effects of the First Embodiment>

[0099] As described above, in the method of the first embodiment, a monitoring limiter SLr_M is provided, and the phase of the data strobe signal DQSin of the main limiter SLr is adjusted to an optimal value using the monitoring limiter SLr_M. This generally allows the phase relationship between the data signal and the data strobe signal to be correctly maintained. In particular, even if the environment such as temperature and voltage changes during the normal operation period, the phase of the data strobe signal can be adjusted in real time in the background without retraining.

[0100] (Second Embodiment) <Configuration and Operation Related to Read Latch Circuit (Embodiment)>

[0101] Figure 8 FIG. 1 is a diagram showing a semiconductor device according to a second embodiment. Figure 2A circuit block diagram of a schematic configuration example related to a read latch circuit RLTb in a data buffer DB shown in FIG. Figure 3 The read latch circuit RLTa shown is different. Figure 8 The read latch circuit RLTb shown includes a monitoring slicer (second data holding circuit) SLr_M and also includes another monitoring slicer (third data holding circuit) SLr_M2. Like the monitoring slicer SLr_M, the monitoring slicer SLr_M2 latches the input data signal DQin synchronously with the monitoring data strobe signal (third data strobe signal).

[0102] Due to this configuration difference, the read latch circuit RLTb includes a variable delay circuit VDLYs_B, which is Figure 3 and Figure 4 The variable delay circuit VDLYs_A shown in FIG. 1 is an extended version of the variable delay circuit VDLYs_A. That is, the variable delay circuit VDLYs_B generates the monitoring data strobe signal DQSin_M by delaying the input data strobe signal MDQS by the monitoring delay amount ST2 which is less than the main delay amount ST1. In addition, the variable delay circuit VDLYs_B generates the monitoring data strobe signal DQSin_M2 by delaying the input data strobe signal MDQS by the monitoring delay amount ST3 which is greater than the main delay amount ST1.

[0103] Fig. 9 It is shown Figure 8 This is a circuit block diagram of a configuration example of a variable delay circuit VDLYs_B in FIG. Figure 4 In addition to the configuration examples shown, Fig. 9 The variable delay circuit VDLYs_B shown also includes a selection circuit SEL3. Like the selection circuits SEL1 and SEL2, the selection circuit SEL3 selects one output from the multiple outputs of the multiple delay elements DE[0]-DE[k] based on the monitoring delay amount ST3 and outputs it as the monitoring data strobe signal DQSin_M2.

[0104] Back to Figure 8 The buffer control circuit CTRLb includes a timing adjustment circuit TMCTB, which is Figure 3 The timing adjustment circuit TMCT shown is an extended version of the Figure 3 In addition to the XOR circuit EOR shown, the timing adjustment circuit TMCTB includes another XOR circuit EOR2. The XOR circuit EOR2 determines the match / mismatch between the data signal (first data signal) DQo from the main limiter SLr and the data signal (third data signal) DQo_M2 from the monitoring limiter SLr_M2. Then, the XOR circuit EOR2 outputs a monitoring determination result MPF2, which indicates match / mismatch, in other words, pass / fail.

[0105] On the other hand, similar to Figure 3 In the case shown, the search circuit SC determines the match / mismatch between the data signal DQo from the main limiter SLr and the data signal DQo_M from the monitoring limiter SLr_M using the exclusive OR circuit EOR while changing the monitoring delay amount ST2. In addition, the search circuit SC determines the match / mismatch between the data signal DQo from the main limiter SLr and the data signal DQo_M2 from the monitoring limiter SLr_M2 using the exclusive OR circuit EOR2 while changing the monitoring delay amount ST3. Then, the search circuit SC adjusts the main delay amount ST1 based on these monitoring determination results MPF, MPF2.

[0106] By using such a configuration, the real-time performance can be further improved when optimizing the main delay amount ST1 according to changes in the environment such as temperature and voltage. Fig. 7A , Figure 7B and Figure 7C In the example shown, the monitoring determination result MPF at the holding side edge timing th is acquired in a certain reading cycle, and then the monitoring determination result MPF at the setting side edge timing ts is acquired in the next reading cycle. Figure 8 With the configuration example shown, the monitoring determination result MPF2 at the holding side edge timing th and the monitoring determination result MPF at the setting side edge timing ts can be simultaneously acquired within a single read cycle.

[0107] <Main Effects of the Second Embodiment>

[0108] As described above, by using the method of the second embodiment, an effect similar to that described in the first embodiment can be achieved. In addition, compared with the method of the first embodiment, although the circuit area overhead is slightly increased, the real-time performance can be further improved when the phase of the data strobe signal is optimized according to environmental changes. Therefore, a more robust system can be implemented to cope with environmental changes.

[0109] Although the invention of the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device comprising: A first data holding circuit, for latching an input data signal synchronously with a first data strobe signal; A second data holding circuit, used for latching the input data signal synchronously with a second data strobe signal; a variable delay circuit for generating the first data strobe signal and the second data strobe signal by delaying an input data strobe signal by a first delay amount and a second delay amount, respectively; as well as a timing adjustment circuit, configured to set the first delay amount and the second delay amount in the variable delay circuit, wherein the timing adjustment circuit adjusts the first delay amount based on a determination of a match / mismatch between a first data signal from the first data holding circuit and a second data signal from the second data holding circuit while changing the second delay amount.

2. The semiconductor device according to claim 1, The input data signal and the input data strobe signal are signals output from a memory chip.

3. The semiconductor device according to claim 2, The memory chip is a DDR-SDRAM chip.

4. The semiconductor device according to claim 2, wherein the timing adjustment circuit operates during a normal operation period in which the memory chip performs a normal read operation, and The first data signal is transmitted to a subsequent stage as a read data signal from the memory chip.

5. The semiconductor device according to claim 4, wherein an initial sequence period including a training period of the memory chip is provided before the normal operation period, wherein the initial value of the first delay amount is determined during the initial sequence period, and wherein the timing adjustment circuit operates from the initial value of the first delay amount during the normal operation period.

6. The semiconductor device according to claim 1, The timing adjustment circuit detects the eye width of the input data signal by determining the match / mismatch while changing the second delay amount, and adjusts the first delay amount so that the edge of the first data selection signal is located at the center of the eye width. 7 . The semiconductor device according to claim 1 , further comprising a decision feedback equalizer (DFE) inserted in a transmission path of the input data signal for performing waveform equivalence of the input data signal of the semiconductor device.

8. The semiconductor device according to claim 1, further comprising: a third data holding circuit, configured to latch the input data signal synchronously with a third data strobe signal; wherein the variable delay circuit generates the second data strobe signal by delaying the input data strobe signal by a second delay amount that is smaller than the first delay amount, wherein the variable delay circuit generates the third data strobe signal by delaying the input data strobe signal by a third delay amount greater than the first delay amount, and The timing adjustment circuit adjusts the first delay amount based on the determination of the match / mismatch between the first data signal and the second data signal and the match / mismatch between the first data signal and the third data signal from the third data holding circuit while changing the second delay amount and the third delay amount.

9. The semiconductor device according to claim 1, The semiconductor device is a semiconductor chip that provides a function of a data buffer in a memory module.

10. A memory module, comprising: A module wiring board having a control external terminal and a data external terminal; A plurality of DDR-SDRAM chips are mounted on the module wiring board; a registered clock driver mounted on the module wiring board for re-driving a memory control signal input through a control external terminal and outputting the memory control signal to the plurality of DDR-SDRAM chips; as well as a data buffer mounted on the module wiring board for re-driving the data signal and the data strobe signal input through the data external terminal and outputting the data signal and the data strobe signal to the plurality of DDR-SDRAM chips, and for re-driving the input data signal and the input data strobe signal from the plurality of DDR-SDRAM chips and outputting the input data signal and the input data strobe signal to the data external terminal, wherein the data buffer has a first data holding circuit for latching the input data signal in synchronization with a first data strobe signal, a second data holding circuit for latching the input data signal in synchronization with a second data strobe signal, a variable delay circuit for generating the first data strobe signal and the second data strobe signal by delaying the input data strobe signal by the first delay amount and the second delay amount, respectively, and a timing adjustment circuit for setting the first delay amount and the second delay amount in the variable delay circuit, and The timing adjustment circuit adjusts the first delay amount based on a determination of whether the first data signal from the first data holding circuit matches or does not match the second data signal from the second data holding circuit while changing the second delay amount.

11. The memory module according to claim 10, wherein the timing adjustment circuit operates during a normal operation period in which the plurality of DDR-SDRAM chips perform normal read operations, and The first data signal is transmitted to the external data terminal as a read data signal from the plurality of DDR-SDRAM chips.

12. The memory module according to claim 11, wherein an initial sequence period including a training period of the plurality of DDR-SDRAM chips is provided before the normal operation period, wherein the initial value of the first delay amount is determined during the initial sequence period, and wherein the timing adjustment circuit starts operating from a state in which the first delay amount is set to the initial value during the normal operation period.

13. The memory module according to claim 10, The timing adjustment circuit detects the eye width of the input data signal by determining the match / mismatch while changing the second delay amount, and adjusts the first delay amount so that the edge of the first data selection signal is located at the center of the eye width.

14. The memory module according to claim 10, The data buffer further includes a decision feedback equalizer (DFE), the DEF being inserted in a transmission path of the input data signal and performing waveform equalization of the input data signal.

15. The memory module according to claim 10, wherein the data buffer further comprises a third data holding circuit for latching the input data signal synchronously with a third data strobe signal, wherein the variable delay circuit generates the second data strobe signal by delaying the input data strobe signal by a second delay amount less than the first delay amount, and generates the third data strobe signal by delaying the input data strobe signal by a third delay amount greater than the first delay amount, and The timing adjustment circuit adjusts the first delay amount based on the determination of the match / mismatch between the first data signal and the second data signal and the match / mismatch between the first data signal and the third data signal from the third data holding circuit while changing the second delay amount and the third delay amount.

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