A memory operation method, a memory and a storage system

Abstract

The present disclosure provides an operating method of a memory, a memory and a storage system, and relates to the technical field of semiconductor chips. The operating method comprises: in response to a first read instruction, applying a read voltage to a word line, reading data of a plurality of memory cells to obtain a first read result; in response to a second read instruction, applying the read voltage to the word line, reading data of the plurality of memory cells to obtain a second read result; determining a target memory cell according to the first read result and the second read result; applying the read voltage to a word line coupled to the target memory cell; performing a read operation on the target memory cell to obtain a true random binary sequence. The generated true random binary sequence can be used for encryption when data is encrypted in a 3D NAND product, so that the problem of low data security caused by encryption of data with pseudo-random numbers can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular, to a memory operation method, a memory, and a storage system. BACKGROUND

[0002] At present, the security of data is widely concerned, and in this context, the data encryption of 3D NAND products becomes particularly important. Data encryption aims to protect sensitive information from unauthorized access and theft, so the security of data stored in 3D NAND chips is of great significance. The data encryption of 3D NAND products often relies on the generation of random numbers, and the pseudo-random numbers generated by a pseudo-random number generator (PRNG) are used for data encryption in existing 3D NAND products. SUMMARY

[0003] Embodiments of the present disclosure provide a memory operation method, a memory, and a storage system, aiming to improve the problem that the use of pseudo-random numbers in 3D NAND products for data encryption can lead to reduced data security.

[0004] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, a memory operation method is provided, the method comprising: in response to a first read instruction, applying a read voltage to a word line, reading data of a plurality of storage units to obtain a first read result, wherein the plurality of storage units are coupled to the word line; in response to a second read instruction, applying a read voltage to the word line, reading data of the plurality of storage units to obtain a second read result; if the difference between the number of first logic values in the first read result and the number of first logic values in the second read result is less than a threshold value, determining the storage units in the plurality of storage units that are different between the first read result and the second read result as target storage units, applying a read voltage to the word line coupled to the target storage units, and performing a read operation on the target storage units to obtain a true random binary sequence.

[0006] The memory operation method provided by the present disclosure screens out target storage units that are easily affected by random noise by comparing multiple read results. And the logic value corresponding to the storage state of the target storage unit is obtained as a true random number by reading the storage state of the target storage unit again. True random numbers are generated by using the physical characteristics of storage units, and data encryption is performed based on the true random numbers that are difficult to predict, meeting the security requirements of data encryption. And since no additional circuit is added, the production cost is not increased and the product size is not increased.

[0007] In some embodiments, the memory includes a page buffer, the memory includes a page buffer circuit, the page buffer circuit includes a first latch, a first data latch, and a second data latch, and in response to the first read instruction, applying a read voltage to the word line, reading data of the plurality of memory cells to obtain a first read result includes: reading data of the plurality of memory cells, storing the read data in the first latch, performing an AND operation between the data stored in the first latch and mask data of a preset storage state pre-stored in the first data latch to obtain the first read result, and storing the first read result to the second data latch.

[0008] In some embodiments, the page buffer circuit further includes a second latch and a VFC (voltage to frequency converter) circuit, and in response to the first read instruction, applying a read voltage to the word line, reading data of the plurality of memory cells to obtain a first read result further includes: transferring the data stored in the second data latch to the second latch, and counting a number of first logic values stored in the second latch by the VFC circuit.

[0009] In some embodiments, in response to the second read instruction, applying a read voltage to the word line, reading data of the plurality of memory cells to obtain a second read result includes: reading data of the plurality of memory cells, storing the read data in the first latch, performing an AND operation between the data stored in the first latch and mask data of a preset storage state pre-stored in the first data latch to obtain the second read result, and storing the second read result to the first latch.

[0010] In some embodiments, in response to the second read instruction, applying a read voltage to the word line, reading data of the plurality of memory cells to obtain a second read result includes: reading data of the plurality of memory cells, storing the read data in the first latch, performing an AND operation between the data stored in the first latch and mask data of a preset storage state pre-stored in the first data latch to obtain the second read result, and storing the second read result to the first latch.

[0011] In some embodiments, the page buffer circuit further includes a second latch and a VFC circuit, and in response to the second read instruction, applying a read voltage to the word line, reading data of the plurality of memory cells to obtain a second read result further includes:

[0012] transferring the data stored in the first latch to the second latch, and counting a number of first logic values stored in the second latch by the VFC circuit.

[0013] In some embodiments, before reading data of the plurality of memory cells, the method further includes: storing mask data of a preset storage state to the first data latch.

[0014] In some embodiments, determining the target storage unit as the storage unit where the first read result differs from the second read result among a plurality of storage units includes: XORing the data stored in the second data latch with the data stored in the first latch, and storing the XOR result in the first latch.

[0015] The memory cell corresponding to the first latch with a stored logic value of 1 is determined as the target memory cell.

[0016] In some embodiments, the method further includes: if the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is greater than or equal to a threshold, then repeatedly execute the second read operation in response to the first read instruction and the second read instruction to read data from multiple storage units and obtain the first read result and the second read result respectively, until the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than the threshold.

[0017] In a second aspect, a memory is provided, comprising: a memory cell array and peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured to: in response to a first read instruction, apply a read voltage to a word line, read data from a plurality of memory cells to obtain a first read result, wherein the plurality of memory cells are coupled to the word line; in response to a second read instruction, apply a read voltage to the word line, read data from the plurality of memory cells to obtain a second read result; if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold, determine the memory cell from the plurality of memory cells whose first read result differs from the second read result as a target memory cell, apply a read voltage to the word line coupled to the target memory cell, perform a read operation on the target memory cell, and obtain a truly random binary sequence.

[0018] In some embodiments, the peripheral circuitry further includes a page buffer circuit. The page buffer circuit includes a first latch, a first data latch, and a second data latch. The page buffer circuit is specifically configured to: read data from multiple storage units, store the read data in the first latch, AND the data stored in the first latch with a mask data of a preset storage state pre-stored in the first data latch to obtain a first read result, and store the first read result in the second data latch.

[0019] In some embodiments, the page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured to: transfer data stored in the second data latch to the second latch, and count the number of first logic values ​​stored in the second latch through the VFC circuit.

[0020] In some embodiments, the peripheral circuitry further includes a page buffer circuit, which includes a first latch and a first data latch. Specifically, the page buffer circuit is configured to read data from multiple memory units and store the read data in the first latch.

[0021] The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first read result, and the first read result is stored in the first latch.

[0022] In some embodiments, the page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured to: transfer data stored in the first latch to the second latch, and count the number of first logic values ​​stored in the second latch through the VFC circuit.

[0023] In some embodiments, the page buffer circuit is further configured to store the mask data in a preset storage state into a first data latch.

[0024] In some embodiments, the page buffer circuit is specifically configured to: XOR the data stored in the second data latch with the data stored in the first latch, store the result of the XOR in the first latch, and determine the storage cell corresponding to the first latch with a stored logic value of 1 as the target storage cell.

[0025] In some embodiments, the page buffer circuit is further configured to: if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to a threshold, then repeatedly execute the second read operation in response to the first read instruction, read data from multiple memory cells, and obtain the first read result and the second read result respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

[0026] Thirdly, a storage system is provided, comprising: a memory and a storage controller, the storage controller being connected to the memory via a flash memory interface circuit; the storage controller being the memory provided in any embodiment of the second aspect.

[0027] Fourthly, a computer-readable storage medium is provided, which stores computer-executable instructions; when executed, the computer-executable instructions are able to implement any of the methods in the first aspect above.

[0028] Fifthly, an electronic device is provided, including a host such as the storage system provided in the third aspect, the host being connected to the storage system to write data to the storage system or read data stored in the storage system.

[0029] Understandably, the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0030] Figure 1 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0031] Figure 2 A block diagram of a storage system provided in an embodiment of this disclosure;

[0032] Figure 3 A block diagram of another storage system provided in an embodiment of this disclosure;

[0033] Figure 4 A schematic diagram illustrating the distribution of threshold voltage in a memory cell according to an embodiment of this disclosure;

[0034] Figure 5 This is a schematic diagram of the structure of the memory and peripheral circuits provided in the embodiments of this disclosure;

[0035] Figure 6 A flowchart illustrating the operation method of the memory provided in this embodiment of the disclosure;

[0036] Figure 7 A schematic diagram showing the distribution of another memory cell threshold voltage provided in an embodiment of this disclosure;

[0037] Figure 8 A schematic diagram showing the distribution of another memory cell threshold voltage provided in an embodiment of this disclosure;

[0038] Figure 9 A schematic diagram showing the distribution of another memory cell threshold voltage provided in an embodiment of this disclosure;

[0039] Figure 10 A schematic diagram showing the distribution of another memory cell threshold voltage provided in an embodiment of this disclosure;

[0040] Figure 11 A schematic diagram showing the distribution of another memory cell threshold voltage provided in an embodiment of this disclosure;

[0041] Figure 12 A schematic diagram showing the distribution of another memory cell threshold voltage provided in an embodiment of this disclosure;

[0042] Figure 13 A schematic diagram of the page buffer circuit provided in the embodiments of this disclosure;

[0043] Figure 14 A flowchart illustrating the operation method of the memory provided in this embodiment of the disclosure;

[0044] Figure 15This is a flowchart illustrating the operation method of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes three combinations: A only, B only, and a combination of A and B. The use of "applies to" or "configured to" in this document implies open and inclusive language, which does not preclude applicability to or configuration to perform additional tasks or steps on devices. Additionally, the use of "based on" implies openness and inclusivity, as processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0051] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0052] Embodiments of this disclosure provide an electronic device, such as any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc. See also Figure 1 , Figure 1 The diagram illustrates an electronic device 10 provided in an embodiment of the present disclosure, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking a mobile phone as an example, the central processing unit (CPU) and digital signal processor (DSP) of the mobile phone can all act as masters to access the storage system.

[0053] For example, see Figure 2 , Figure 2 A schematic diagram of a storage system 110 provided in an embodiment of the present disclosure is shown. The storage system 110 includes a storage controller 111 and a memory 112. The storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2D) memory or a three-dimensional (3D) memory.

[0054] Storage system 110 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, storage system 110 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device that incorporates storage.

[0055] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 may be integrated into a memory card. The memory card includes any one of the following: a personal computer memory card (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD card), and UFS.

[0056] In other embodiments, see Figure 3 The storage system 110 includes a storage controller 111 and multiple storage devices 112, and the storage system 110 is integrated into a solid state drive (SSD).

[0057] In some embodiments of the storage system 110, the storage controller 111 is configured to operate in a low duty cycle environment, such as an SD card, CF card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0058] In other embodiments, the storage controller 111 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0059] In some embodiments, the storage controller 111 may be configured to manage data stored in the memory 112 and to communicate with an external device (e.g., host 100). In some embodiments, the storage controller 111 may also be configured to control operations of the memory 112, such as read, erase, and program operations. In some embodiments, the storage controller 111 may also be configured to manage various functions relating to data stored or to be stored in the memory 112, including at least one of bad block management, garbage collection (GC), logical-to-physical address translation, and wear leveling. In some embodiments, the storage controller 111 is also configured to process error correction codes relating to data read from or written to the memory 112.

[0060] Furthermore, the storage controller 111 can communicate with external devices (e.g., host 100) via at least one of various interface protocols. It should be noted that the interface protocols include at least one of the following: Universal Serial Bus (USB) protocol, Microsoft Management Console (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and FireWire protocol.

[0061] For 3D NAND products, using pseudo-random numbers generated by a pseudo-random number generator for data encryption can introduce some security and predictability issues:

[0062] Predictability: Pseudo-random number generators use an algorithm to generate seemingly random sequences of numbers, but in reality, they generate random sequences based on an initial seed value. If an attacker can obtain or deduce the seed value, they can reproduce the pseudo-random number sequence, thereby breaking the encryption.

[0063] Reduced security: The algorithm of the pseudo-random number generator is known, so attackers can analyze the algorithm to find patterns or weaknesses, leading to password cracking or attacks.

[0064] Risk of reuse: If a pseudo-random number generator uses the same initial seed value to generate a sequence, then the sequences generated using the same seed value will also be the same.

[0065] In summary, using pseudo-random numbers generated by a pseudo-random number generator for data encryption in 3D NAND products may reduce encryption security and weaken its ability to resist attacks. To avoid these risks, a true random number generator (TRNG) can be used to generate truly random numbers that meet the randomness requirements. A TRNG uses the unpredictability of physical processes or devices to generate truly random numbers. Unlike pseudo-random number generators, TRNGs do not rely on deterministic algorithms or seed values; instead, they utilize the randomness of physical processes to generate random numbers. Therefore, TRNGs rely on unpredictable physical processes, making it difficult for attackers to predict the generated random numbers and crack the encryption.

[0066] For 3D NAND products, adding a true random number generator to the existing product would lead to increased costs and larger product size.

[0067] On the one hand, adding a true random number generator would significantly increase costs. Designing, manufacturing, and integrating such circuits typically requires additional R&D resources and technological investment. This could increase the production cost of the product.

[0068] On the other hand, adding a true random number generator would increase the product size. 3D NAND products typically employ a compact design to achieve greater storage capacity within a relatively small physical size. In this case, introducing additional circuitry may limit the flexibility of product design, making it difficult to accommodate more components within the existing size framework.

[0069] Against this backdrop, how to achieve the application of true random number generators while maintaining reasonable cost and product size is a key concern in the 3D NAND product field.

[0070] Based on this, the embodiments of this disclosure provide a solution: to use the electronic devices in the 3D NAND product to build a true random number generator, that is, to make full use of the physical characteristics of the electronic devices in the 3D NAND to generate true random numbers without introducing additional circuits or components.

[0071] For a storage cell, there is inherent random read noise. Under the influence of random read noise, the threshold voltage of the storage cell will be subject to unpredictable and irregular interference or changes. Random read noise is naturally present and is not affected by external factors, thus possessing truly random characteristics. Due to the influence of random read noise, the threshold voltage of the storage cell will change.

[0072] For example, see Figure 4 The inherent threshold voltage of a memory cell is near the read voltage Vrd. If, at time T1, the threshold voltage of the memory cell is less affected by random read noise (shifts to the left), then at time T1, if the read voltage Vrd is used, the state stored in the memory cell will be read as the first logic value "1". If, at time T2, the threshold voltage of the memory cell is more affected by random read noise (shifts to the right), then at time T2, if the read voltage Vrdd is used, the state stored in the memory cell will be read as the second logic value "0". Therefore, if the inherent threshold voltage of a memory cell is near the read voltage, due to the influence of random read noise, its threshold voltage will also change randomly, causing the state of the read memory cell to fluctuate between the second logic value "0" and the first logic value "1".

[0073] Figure 5 A schematic diagram of the memory cell array and its peripheral circuitry is shown. Figure 5 In this circuit, peripheral circuitry 400 includes an I / O interface 410, control logic circuitry 420, row decoder 430, voltage generator 440, column decoder 450, page buffer circuitry 460, data bus 470, and registers 480. It should be understood that in some examples, it may also include... Figure 5 Additional circuitry not shown.

[0074] I / O interface 410 can be coupled to control logic circuitry 420 and act as a control buffer to buffer data from the memory controller (e.g., Figure 2 The I / O interface 410 receives control commands from the storage controller 111 and relays them to the control logic circuit 420, and buffers status information received from the control logic circuit 420 and relays it to the host. The I / O interface 410 can also be coupled to the page buffer circuit 460 via the data bus 470 to buffer data and relay it to or from the memory cell array 300.

[0075] The control logic circuit 420 can be coupled to the voltage generator 440, page buffer circuit 460, column decoder 450, row decoder 430, and I / O interface 410, and is configured to control the operation of each peripheral circuit. The control logic circuit 420 can generate operation signals in response to commands (CMDs) or control signals from the memory controller 111 to control the operation of the row decoder 430, column decoder 450, page buffer circuit 460, and voltage generator 440; wherein the commands can be programming commands, read commands, etc.

[0076] The row decoder 430, in response to control by the control logic circuit 420, supplies word line voltages generated from the voltage generator 440 to the selected and unselected word lines of the memory cell array 300. As described in detail below, the row decoder 430 is configured to perform programming operations on memory cells coupled to one or more selected word lines in the memory cell array 300.

[0077] Voltage generator 440 can use external or internal power supply voltages to generate various voltages for performing operations such as erasing, programming, reading, and verification on the memory cell array 300.

[0078] The column decoder 450 can respond to control logic circuitry 420 and select one or more strings of memory cells in the memory cell array 300 by applying bit line voltages generated from voltage generator 440.

[0079] Page buffer circuit 460 can read data from memory cell array 300 and program (write) data to memory cell array 300 according to control signals from control logic circuit 420. In one example, page buffer circuit 460 can store programming data to be programmed into memory cell array 300 (write data). In another example, page buffer circuit 460 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer circuit 460 can also detect a low-power signal from the bit line representing the data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0080] Register 480 can be coupled to control logic circuit 420 and includes a status register, a command register and an address register for storing status information, command opcode (OP code) and command address for controlling the operation of each peripheral circuit.

[0081] Specifically, when the aforementioned peripheral circuit 400 is working, it performs the following... Figure 6The operation method shown includes steps S10-S40, and the peripheral circuit 400 can execute steps S10 to S40.

[0082] In some implementations, during the construction of a true random number generator, it is necessary to select target storage units with random characteristics as entropy sources. The number of target storage units needs to be determined based on the actual application requirements. However, it should be noted that the number of target storage units as entropy sources needs to be much greater than the number of maximum binary random numbers required for data encryption.

[0083] For example, if data encryption in a 3D NAND product requires a maximum binary sequence of 8 bits, then the number of target storage units can be 12. This number not only meets the data encryption requirements but also provides additional backup target storage units. The advantage of this redundancy design is that even if some target storage units are damaged during use, truly random numbers can still be generated from the backup target storage units.

[0084] Secondly, after determining the number of target storage cells, the number of target storage cells is compared with a maximum threshold number of target storage cells that can be filtered out on a single word line. This maximum threshold number is a pre-defined value. If the number of target storage cells is less than or equal to the maximum threshold number of target storage cells that can be filtered out on a single word line, a single word line is randomly selected, and steps S10-S20 are performed on its coupled storage cells to filter out the target storage cells. If the number of target storage cells is greater than the threshold number of target storage cells that can be filtered out on a single word line, multiple word lines that meet the required number of cells are randomly selected, and steps S10-S20 are performed on their coupled storage cells to filter out the target storage cells.

[0085] Before executing step S10, an erase voltage is applied to the selected word line to erase the data of the memory cell coupled to the selected word line.

[0086] For example, during the erase phase, the control logic circuit 420 controls the row decoder 430 to apply the erase voltage Vss generated by the voltage generator 440 to the word line, and the control logic circuit 420 controls the row decoder 430 to apply the erase voltage Vers generated by the voltage generator 440 to the bit line. It should be noted that the erase voltage Vers is a high potential, and the erase voltage Vss is a low potential (0V), thereby creating a large potential difference between the channel potential and the gate potential of the memory block to be erased, thus achieving the erasure of the memory cells in the memory block.

[0087] After the erase operation of the memory cell coupled to the selected word line is completed, the memory cell needs to be programmed to a different memory state.

[0088] For example, during the programming phase, the control logic circuit 420 controls the row decoder 430 to apply the programming voltage generated by the voltage generator 440 to the select word line, thereby creating a large potential difference with the channel potential, allowing electrons to tunnel and inject into the charge trapping layer. Simultaneously, it also controls the row decoder 430 to apply the through voltage generated by the voltage generator 440 to the non-select word line, thereby turning on memory cells not selected for programming. This allows the memory cells coupled to the select word line to be programmed into N different programming states.

[0089] After the above operations are completed on the selected storage unit, the target storage unit is selected by executing operations S10-S30.

[0090] S10: In response to the first read instruction, a read voltage is applied to the word line to read data from multiple memory cells and obtain the first read result.

[0091] In order to select the largest number and most stable target memory cells, the read voltage needs to be adjusted adaptively when applying the read voltage.

[0092] For example, using SLC mode as an example, when the threshold voltage of the memory cell is within the threshold voltage range corresponding to the erase state, its logic value is the first logic value "1"; when the threshold voltage is within the threshold voltage range corresponding to the programming state, its logic value is the second logic value "0". See also... Figure 7 Based on the threshold voltage distribution in SLC mode, the number of memory cells near the initial read voltage Vrd is almost zero. Therefore, to select the largest possible number of target memory cells, the read voltage Vrd needs to be adjusted to the position with the highest number of memory cells in the P0 erase state or P1 memory state, thus obtaining a corrected Vrd. In other words, the read voltage Vrd is set to the position corresponding to the peak of the P0 erase state or P1 memory state. Then, a read operation is performed on the memory cell based on the corrected read voltage Vrd to obtain the first read result.

[0093] Furthermore, in order to screen for stable storage units, refer to... Figure 8 The corrected read voltage Vrd can be set at the position corresponding to the peak of the P1 storage state, thus obtaining VrdP1. (See also...) Figure 9 The threshold voltage at the location corresponding to the peak of the P1 storage state is about 0V, and the storage cell with a threshold voltage of 0V has the highest stability.

[0094] For example, if each storage cell stores multiple bits of data, only one or more bits can be read during retrieval. Taking the UP logical page read process in TLC mode as an example, which involves reading the highest-order bit of each storage cell, the storage cell threshold voltage is within the threshold voltage range corresponding to the erase state, and its logical value is "1". When the threshold voltage is within the threshold voltage range corresponding to the programming state, its logical value is "0". See [reference needed]. Figure 10 According to the threshold voltage distribution in TLC mode, the number of memory cells with the inherent threshold voltage near the initial read voltage Vrd1 is almost zero. Therefore, to select the largest number of target memory cells, the position of the read voltage Vrd1 needs to be moved to the position with the highest number of memory cells. That is, the read voltage Vrd1 is set to the position corresponding to the peak of any one of the memory states: P0 erase state, P1 memory state, P2 memory state, P3 memory state, P4 memory state, P5 memory state, P6 memory state, or P7 memory state, and Vrd2 is moved to the right of the P7 memory state. Then, a read operation is performed on the memory cell based on the adjusted read voltages Vrd1 and Vrd2 to obtain the first read result.

[0095] Furthermore, in order to screen for stable storage units, refer to... Figure 11 The read voltage Vrd1 can be set to the position corresponding to the peak of the P3 storage state to obtain VrdP3, and the read voltage Vrd2 can be set to the right position of the P7 storage state to obtain VrdP7. See [reference needed]. Figure 12 The threshold voltage at the location corresponding to the peak of the P3 storage state is about 0V, and the storage cell with a threshold voltage of 0V has the highest stability.

[0096] For example, in the first read cycle, the control logic circuit 420 controls the row decoder 430 to apply the read voltage generated by the voltage generator 440 to the word lines coupled to the selected memory cells as screening targets, and to the word lines coupled to the unselected memory cells. Then, based on the detection of current on the bit lines, the logic state of each memory cell is determined. If current is detected on the bit lines, it indicates that the selected memory cell is conducting, and the state of the selected memory cell is a first logic value "1"; if no current is detected on the bit lines, it indicates that the selected memory cell is not conducting, and the state of the selected memory cell is a second logic value "0". The logic states of each memory cell are then integrated to obtain the first read result.

[0097] S20: In response to the second read instruction, a read voltage is applied to the word line to read data from multiple memory cells and obtain the second read result.

[0098] After obtaining the first read result, a second read instruction is triggered after a preset time. In response to the second read instruction, a second read operation is performed to obtain the second read result of the memory cell. It should be noted that the read voltage applied to the word line coupled to the memory cell selected as the filtering target is the same in both the first and second read cycles.

[0099] For example, in the second read cycle, the control logic circuit 420 controls the row decoder 430 to apply the read voltage generated by the voltage generator 440 to the word lines coupled to the selected memory cells as screening targets, and to the word lines coupled to the unselected memory cells. Then, based on the detection of current on the bit lines, the logic state of each memory cell is determined. If current is detected on the bit lines, it indicates that the selected memory cell is turned on, and the selected memory cell is in the state of the first logic value "1"; if no current is detected on the bit lines, it indicates that the selected memory cell is not turned on, and the selected memory cell is in the state of the second logic value "0". Then, the logic states of each memory cell are integrated to obtain the second read result.

[0100] The first read cycle refers to the process of obtaining the first read result, and the second read cycle refers to the process of obtaining the second read result. After obtaining the first and second read results, the first read result includes the logical value corresponding to each storage unit in the first read cycle, and the second read result includes the logical value corresponding to each storage unit in the second read cycle. Then, based on the changes in the logical values ​​corresponding to the read results of each storage unit in the first and second read cycles, the target storage units are selected.

[0101] S30: If the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than the threshold, the storage unit in which the first read result and the second read result are different is determined as the target storage unit.

[0102] After obtaining the read results of the storage unit in the first read cycle and the read results in the second read cycle, the target storage unit can be selected by comparing whether the logical value of the storage unit changes in the two read operations and the nature of the change.

[0103] For example, the number of storage units used to filter target storage units is 50, and the preset threshold is 4. In the first read cycle, the number of storage units with a read result of the first logical value "1" is 26, and the number of storage units with a read result of the second logical value "0" is 24. In the second read cycle, the number of storage units with a read result of the first logical value "1" is 25, and the number of storage units with a read result of the second logical value "0" is 25. The difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is 1, which is less than the preset threshold of 4, thus satisfying the filtering condition. Then, storage units with a read result of the first logical value "1" in the first read cycle and a read result of the second logical value "0" in the second read cycle, or vice versa, are all determined as target storage units. This is because these storage units exhibit sufficient randomness during multiple reads, meeting the requirements for constructing a true random number generator.

[0104] S40: In response to the random number generation instruction, a read voltage is applied to the word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a truly random binary sequence.

[0105] After selecting the target storage units, they can be used as entropy sources to construct a true random number generator. This generator generates truly random numbers. When data encryption is required, a random number generation instruction is triggered, followed by a read operation to obtain the read result from the target storage unit. It's important to note that during the true random number generation phase, the read voltage applied to the word line coupled to the target storage unit is the same as the read voltage applied in the first read cycle and the second read cycle.

[0106] For example, if the random number generation instruction indicates that a true random binary sequence of a preset number of bits is required, and the preset number of bits is less than the number of target memory cells, then the control logic circuit 420 controls the row decoder 430 to apply the read voltage generated by the voltage generator 440 to the word line coupled to the target memory cell, and to apply the pass voltage to the word line coupled to the non-target memory cell. Then, based on the detection of the current on the bit line, the logic state of each target memory cell is determined, and the logic value representing the logic target memory cell state is used as the true random binary sequence.

[0107] The memory operation method disclosed herein filters out target memory cells susceptible to random noise by comparing multiple read results. It then reads the storage state of the target memory cell again and uses the corresponding logical value as a true random number. By utilizing the physical characteristics of the memory cell to generate true random numbers, it achieves genuine randomness, thereby meeting the requirements of data encryption.

[0108] See Figure 13 The page buffer circuit 460 includes a first latch 501, a second latch 504, a first data latch 502, and a second data latch 503. The latches are connected to the data lines and can be used to store input data received during programming operations or output data from the read operation device. The page buffer circuit 460 is coupled to a corresponding bit line in the bit lines. That is, the page buffer circuit 460 can be coupled to the memory cell of the corresponding column through the corresponding bit line.

[0109] Data latches store input data during programming operations. The number of data latches can be adjusted according to the type of flash memory. For example, each cell of TLC flash memory can store 3 bits of data, so 3 data latches are needed. Each cell of QLC flash memory can store 4 bits of data, so 4 data latches are needed. The memory cells can be configured to operate in SLC mode, or they can be configured to operate in MLC mode, TLC mode, QLC mode, or PLC mode.

[0110] When performing a read operation on a storage unit, not only are the read results obtained from the storage unit in the target storage state, but also from the storage unit in the non-target storage state. The read results from the storage units in the non-target storage state are considered unnecessary data. In order to retain only the read results from the storage units in the target storage state, it is necessary to eliminate the interference of unnecessary data.

[0111] In some embodiments, before reading data from multiple storage units, the method further includes storing a mask data in a preset storage state into a first data latch.

[0112] Mask data refers to data used to block or restrict other data. Therefore, the mask data of the target storage state can be used to eliminate data that is not in the target storage state, so that only the reading results of the storage unit in the target storage state are left.

[0113] As an example, before performing a read operation on a memory cell, a mask data of a preset memory state can be assigned to the first data latch. When the memory uses SLC mode, the preset memory state can be P1; when the memory uses TLC mode, the preset memory state can be P3. It should be noted that in TLC mode, the preset memory state can be any one of P1 to P7.

[0114] See Figure 14 In one possible implementation, upon obtaining the first read result, S10 includes the following sub-steps:

[0115] S101: Read data from multiple storage units and store the read data in the first latch.

[0116] During the first read operation, data from data pages of multiple storage units needs to be read and then temporarily stored in the first latch for subsequent processing operations.

[0117] S102: AND the data stored in the first latch with the mask data of the preset storage state pre-stored in the first data latch to obtain the first read result, and store the first read result in the second data latch.

[0118] The mask data in the preset storage state is a set of specific bit values ​​used to perform a bitwise AND operation with the data stored in the first latch to obtain the read result. Then, the data after the AND operation is performed is stored in the second data latch.

[0119] When the memory uses the SLC mode, the target memory state is P1, and the read voltage is set to the peak of the P1 memory state, the read result of the memory cell with a threshold voltage less than the read voltage VrdP1 is the first logic value "1". However, this part of the memory cell includes not only the memory cell located in the P1 memory state, but also the memory cell located in the P0 erase state. The target of the screening is the memory cell with a threshold voltage near the read voltage VrdP1. Therefore, it is necessary to screen the memory cell with the first logic value "1" and remove the read data of the memory cell located in the P0 erase state.

[0120] For example, there are eight memory cells numbered A1 to A8. A1 to A2 are memory cells with the threshold voltage in the P0 erase state, and A3 to A8 are memory cells with the threshold voltage in the P1 storage state. The mask in the first data latch (D1 latch) can be 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1 / 1, and the data stored in the first latch (C latch) is 1 / 1 / 0 / 1 / 0 / 1 / 0 / 1. This means that each memory cell corresponds to one bit. The result of the bitwise AND operation is 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1. Then, the read result 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1 is stored in the second data latch (D2 latch). It should be noted that during data storage, since one latch can only store one bit of data, the number of latches needs to be determined based on the size of the data to be read. For example, when there are 8 memory cells, the required number of latches is 8. It can be seen that even if the read logic value of the storage cells A1 and A2 is the first logic value "1", after the masking removal process, its read logic value is also set to the second logic value "0".

[0121] When the memory uses TLC mode, the target memory state is P3, and the read voltage is set to the peak of the P3 memory state, the read result of memory cells with a threshold voltage less than the read voltage VrdP3 is the first logic value "1". However, this part of memory cells includes not only memory cells located in the P3 memory state, but also memory cells with threshold voltages located in the P0, P1, and P2 memory states. The target of the screening is memory cells with threshold voltages near the read voltage Vread3. Therefore, it is necessary to screen memory cells with read results of the first logic value "1" and remove the read data of memory cells located in the P0, P1, and P2 memory states.

[0122] For example, consider eight memory cells numbered A1 to A8, where A1 to A8 are memory cells with threshold voltages in storage states P0, P1, P2, P3, P4, P5, P6, and P7. The mask in the first data latch (D1 latch) can be 0 / 0 / 0 / 1 / 0 / 0 / 0 / 0, and the data stored in the first latch (C latch) is 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1. The result of the bitwise AND operation is 0 / 0 / 0 / 1 / 0 / 0 / 0 / 0. Then, the read result 0 / 0 / 0 / 0 / 0 / 0 / 1 / 0 / 1 is stored in the second data latch (D2 latch). It can be seen that even if the read logic value of all memory cells is "1", after masking, except for memory cell A3, the read logic value of the remaining memory cells is set to the second logic value "0".

[0123] After the read results, which have been masked, are stored in the second data latch, it is necessary to count the number of first logic values ​​"1" contained in the read results stored in the second data latch.

[0124] The page buffer circuit 460 also includes a VFC circuit, which can be used to count the number of the first logic value "1".

[0125] See Figure 14 In one possible implementation, the following is included after S102:

[0126] S103: Transfer the data stored in the second data latch to the second latch. The VFC circuit counts the number of first logic values ​​stored in the second latch.

[0127] The VFC circuit can convert the input level signal into a corresponding frequency signal, and then count the number of the first logic value "1" based on the high and low frequency signals.

[0128] For example, the first read result stored in the second data latch (D2 latch) is first transferred to the second latch (L latch), and the VFC circuit uses the logic value stored in the second latch as input. These input level values ​​are then converted into corresponding frequency signals. The frequency of the signal output by the VFC circuit is proportional to the number of logic 1s in the input levels. For the first read result 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1, the number of its first logic values ​​is 3.

[0129] In one possible implementation, when obtaining the second read result, S20 includes the following sub-steps:

[0130] S201: Read data from multiple storage units and store the read data in the first latch.

[0131] During the second read operation, data from the data pages of multiple storage units needs to be read and then temporarily stored in the first latch for subsequent processing operations.

[0132] S202: AND the data stored in the first latch with the mask data of the preset storage state pre-stored in the first data latch to obtain the second read result, and store the second read result in the first latch.

[0133] Continuing with the implementation process in step S102, for example, there are eight memory cells numbered A1 to A8. A1 to A2 are memory cells with the threshold voltage in the P0 erase state, and A3 to A8 are memory cells with the threshold voltage in the P1 storage state. The mask in the first data latch (D1 latch) can be 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1, and the data stored in the first latch (C latch) is 1 / 1 / 1 / 0 / 1 / 0 / 1 / 0. This means that each memory cell corresponds to one bit. The result of the bitwise AND operation is 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0. Then, the read result 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0 is stored in the first latch (C latch).

[0134] S203: Transfer the data stored in the first latch to the second latch. The VFC circuit counts the number of first logic values ​​stored in the second latch.

[0135] For example, the second read result stored in the first latch (C latch) is first transferred to the second latch (L latch), and the VFC circuit uses the logic value stored in the second latch as input. These input level values ​​are then converted into corresponding frequency signals. For the second read result 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0, the number of its first logic values ​​is 3.

[0136] After obtaining the first and second read results, it is necessary to determine whether the result of this operation meets the preset threshold requirements based on the comparison between the first and second read results, and then select the target storage unit if the preset threshold requirements are met.

[0137] See Figure 15 In one possible implementation, when selecting target storage units, S30 includes the following sub-steps:

[0138] S301: XOR the data stored in the second data latch with the data stored in the first latch, and store the result of the XOR in the first latch.

[0139] S302: Determine the memory cell corresponding to the first latch with a stored logic value of 1 as the target memory cell.

[0140] The second data latch is used to store the first read result, and the first latch is used to store the second read result. By comparing the first read result and the second read result, the target storage unit is selected.

[0141] For example, the first read result is 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1, while the second read result is 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0. After performing a bitwise XOR operation, the result is 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1. It can be seen that the logical values ​​of memory cells A3-A8 changed in both read operations. Therefore, memory cells A3-A8 can all be used as target memory cells. Then, the address information of memory cells A3-A8 is stored in the first latch. The address information of the memory cells represents the index position of the true random bit generator. That is, the target memory cell can be found based on the address information, and a true random number sequence can be generated by reading the state of the target memory cell.

[0142] If the difference between the number of first logic values ​​"1" in the first read result and the number of first logic values ​​"1" in the second read result exceeds a preset threshold, it indicates that the read result does not meet the randomness requirement. This is because, under normal conditions, the probability of a memory cell's state flipping between two read operations is equal due to random read noise. This means that the probability of the first logic value changing to the second logic value and the second logic value changing to the first logic value is the same in two read operations. Therefore, if the difference between the two read results exceeds the preset threshold, it may indicate that the state change of the memory cell is not caused by randomness, but may be influenced by some non-random factors. Therefore, if the read result does not meet the randomness requirement, steps S10-S30 need to be repeated until the target memory cell is selected.

[0143] In some embodiments, if the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is greater than or equal to a threshold, then the second read operation, which responds to the first read instruction, reads data from multiple storage units and obtains the first read result and the second read result respectively, is repeatedly executed until the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than the threshold.

[0144] For example, the number of storage units used to filter target storage units is 50, and the threshold is 4. In the first read cycle, the number of storage units with a read result of the first logical value "1" is 26, and the number of storage units with a read result of the second logical value "0" is 24. In the second read cycle, the number of storage units with a read result of the first logical value "1" is 15, and the number of storage units with a read result of the second logical value "0" is 35. The difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is 9, which is greater than the preset threshold of 4, and the filtering condition is not met. Therefore, steps S10 to S30 need to be executed again until the target storage units are filtered out.

[0145] The memory operation method disclosed herein filters out target memory cells that are prone to change due to random noise by comparing the read results of multiple read operations. Then, by rereading the storage state of the target memory cell, the logical value corresponding to its storage state is used as a true random number. By using the physical characteristics of the memory cell to generate random numbers, the generated binary sequence possesses true randomness, thus meeting the requirements of data encryption.

[0146] Embodiments of this disclosure also provide a memory, for example, the memory can be the aforementioned Figure 5 The memory shown includes a memory cell array 300 and peripheral circuitry 400 coupled to the memory cell array. The peripheral circuitry 400 is configured as follows:

[0147] In response to a first read instruction, a read voltage is applied to the word line to read data from multiple memory cells and obtain a first read result. In response to a second read instruction, a read voltage is applied to the word line to read data from multiple memory cells and obtain a second read result. If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold, the memory cell whose first read result differs from the second read result is identified as the target memory cell. A read voltage is applied to the word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a true random binary sequence.

[0148] In one possible implementation of this disclosure, the peripheral circuit 400 further includes a page buffer circuit 460, which includes a first latch, a first data latch, and a second data latch. The page buffer circuit 460 is specifically configured to: read data from multiple memory cells, store the read data in the first latch, perform an AND operation between the data stored in the first latch and a mask data of a preset storage state pre-stored in the first data latch to obtain a first read result, and store the first read result in the second data latch.

[0149] In one possible implementation of this disclosure, the page buffer further includes a second latch, and the page buffer circuit 460 is specifically configured to: transfer data stored in the second data latch to the second latch, and the VFC circuit counts the number of first logic values ​​stored in the second latch.

[0150] In one possible embodiment of this disclosure, the peripheral circuitry further includes a page buffer circuit, which includes a first latch and a first data latch. The page buffer circuit 460 is specifically configured to: read data from multiple memory cells and store the read data in the first latch.

[0151] The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first read result, and the first read result is stored in the first latch.

[0152] In one possible implementation of this disclosure, the page buffer further includes a second latch, and the page buffer circuit 460 is specifically configured to: transfer data stored in the first latch to the second latch, and the VFC circuit counts the number of first logic values ​​stored in the second latch.

[0153] In one possible implementation of this disclosure, the page buffer circuit 460 is further configured to store the mask data in a preset storage state into a first data latch.

[0154] In one possible implementation of this disclosure, the page buffer circuit 460 is specifically configured to: XOR the data stored in the second data latch with the data stored in the first latch, and store the result of the XOR in the first latch; and determine the storage cell corresponding to the first latch with a stored logic value of 1 as the target storage cell.

[0155] In one possible implementation of this disclosure, the page buffer circuit 460 is further configured to: if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to a threshold, then repeatedly execute the second read operation in response to the first read instruction, read data from multiple memory cells, and obtain the first read result and the second read result respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

[0156] This disclosure also provides a storage system, for example, the storage system including a memory and a storage controller as described in the foregoing embodiments, wherein the memory and the storage controller are coupled. Exemplarily, the storage system can be as described above. Figure 2 or Figure 3 The storage system shown.

[0157] This disclosure also provides an electronic device, which includes a host computer and the aforementioned storage system. The host computer is connected to the storage system and is used to store data in the storage system or read data from the storage system. For example, the electronic device can be one of the aforementioned examples. Figure 1 The electronic device shown.

[0158] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0159] In the embodiments provided in this disclosure, it should be understood that the provided programming methods and memory can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0160] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0161] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The method includes: In response to a first read instruction, a read voltage is applied to the word line to read data from multiple memory cells and obtain a first read result, wherein the multiple memory cells are coupled to the word line; In response to the second read instruction, the read voltage is applied to the word line to read the data of the plurality of memory cells and obtain the second read result; If the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than a threshold, the storage unit in the plurality of storage units where the first read result and the second read result are different is determined as the target storage unit; The read voltage is applied to the word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a true random binary sequence.

2. The method according to claim 1, characterized in that, The memory includes a page buffer circuit, which includes a first latch, a first data latch, and a second data latch. The step of applying a read voltage to the word line in response to a first read instruction, reading data from multiple memory cells, and obtaining a first read result includes: Read data from the plurality of storage units and store the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first read result, and the first read result is stored in the second data latch.

3. The method according to claim 2, characterized in that, The page buffer circuit further includes a second latch and a voltage-to-frequency (VFC) conversion circuit. The step of applying a read voltage to the word line in response to a first read instruction, reading data from multiple memory cells, and obtaining a first read result further includes: The data stored in the second data latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

4. The method according to claim 2, characterized in that, In response to the second read instruction, a read voltage is applied to the word line to read the data of the plurality of memory cells and obtain a second read result, including: Read data from the plurality of storage units and store the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the second read result, and the second read result is stored in the first latch.

5. The method according to claim 4, characterized in that, The page buffer circuit further includes a second latch and a VFC circuit. The step of applying a read voltage to the word line in response to a second read instruction, reading data from the plurality of memory cells, and obtaining a second read result further includes: The data stored in the first latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

6. The method according to claim 2 or 4, characterized in that, Before reading the data from the plurality of storage units, the method further includes: The mask data of the preset storage state is stored in the first data latch.

7. The method according to claim 5, characterized in that, The step of determining the target storage unit as the storage unit where the first read result differs from the second read result among the plurality of storage units includes: The data stored in the second data latch is XORed with the data stored in the first latch, and the result of the XOR is stored in the first latch; The storage cell corresponding to the first latch with a stored logic value of 1 is determined as the target storage cell.

8. The method according to claim 1, characterized in that, The method further includes: If the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is greater than or equal to the threshold, then the response to the first read instruction and the response to the second read instruction are repeatedly executed to read the data of the plurality of storage units and the second read operation, respectively obtaining the first read result and the second read result, until the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than the threshold.

9. A memory, characterized in that, include: A memory cell array and peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured as follows: In response to a first read instruction, a read voltage is applied to the word line to read data from multiple memory cells and obtain a first read result, wherein the multiple memory cells are coupled to the word line; In response to the second read instruction, the read voltage is applied to the word line to read the data of the plurality of memory cells and obtain the second read result; If the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than a threshold, the storage unit in the plurality of storage units where the first read result and the second read result are different is determined as the target storage unit; The read voltage is applied to the word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a true random binary sequence.

10. The memory according to claim 9, characterized in that, The peripheral circuit includes a page buffer circuit, which includes a first latch, a first data latch, and a second data latch. The page buffer circuit is specifically configured as follows: Read data from the plurality of storage units and store the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first read result, and the first read result is stored in the second data latch.

11. The memory according to claim 10, characterized in that, The page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured as follows: The data stored in the second data latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

12. The memory according to claim 10, characterized in that, The peripheral circuit also includes a page buffer circuit, which includes a first latch and a first data latch. The page buffer circuit is specifically configured as follows: Read data from the plurality of storage units and store the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first read result, and the first read result is stored in the first latch.

13. The memory according to claim 12, characterized in that, The page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured as follows: The data stored in the first latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

14. The memory according to claim 10 or 12, characterized in that, The page buffer circuit is also configured to: The mask data of the preset storage state is stored in the first data latch.

15. The memory according to claim 13, characterized in that, The page buffer circuit is specifically configured as follows: The data stored in the second data latch is XORed with the data stored in the first latch, and the result of the XOR is stored in the first latch; The storage cell corresponding to the first latch with a stored logic value of 1 is determined as the target storage cell.

16. The memory according to claim 10, characterized in that, The page buffer circuit is also configured to: If the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is greater than or equal to the threshold, then the response to the first read instruction and the response to the second read instruction are repeatedly executed to read the data of the plurality of storage units and the second read operation, respectively obtaining the first read result and the second read result, until the difference between the number of first logical values ​​in the first read result and the number of first logical values ​​in the second read result is less than the threshold.

17. A storage system, characterized in that, It includes a storage controller and a memory as described in any one of claims 9-16, wherein the storage controller is configured to control the memory to write data or read data stored in the memory.

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