Backup techniques in stacked memory architectures

Abstract

The invention relates to backup techniques in a stacked memory architecture. A memory system may implement a stacked memory architecture that includes a set of array dies stacked in a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support backup, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die is operable to perform the remapping according to one or more granularity levels, such as at a die level, a channel level, a dummy channel level, a group level, or a combination thereof.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 595,650, filed by Mylavarapu et al. on November 2, 2023, entitled “SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES,” and U.S. Patent Application No. 18 / 775,981, filed by Mylavarapu et al. on July 17, 2024, entitled “SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES,” each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to spare techniques in stacked memory architectures. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selected memory, chalcogenide memory technology, "NOR" and "NAND" memory devices, etc. Memory cells can be described according to volatile configurations or non-volatile configurations. Memory cells in non-volatile configurations can maintain stored logic states for long periods of time even in the absence of external power. Memory cells in volatile configurations may lose stored states when disconnected from external power. Summary of the invention

[0006] A semiconductor system is described. The semiconductor system may include a plurality of array dies stacked in a certain direction, each array die including: one or more memory arrays; and one or more first interfaces, each first interface including a first circuit, the first circuit being operable to access at least one corresponding memory array in the one or more memory arrays. The semiconductor system may also include a logic die coupled to the plurality of array dies, the logic die including: a plurality of second interfaces, each second interface including a second circuit, the second circuit being operable to communicate access signaling with the corresponding first interfaces of the plurality of array dies to access at least one memory array corresponding to the corresponding first interface; and a logic circuit, which is operable to remap access to the plurality of array dies from one or more first memory arrays of the plurality of array dies using the first of the plurality of second interfaces to one or more second memory arrays of the plurality of array dies using the second of the plurality of second interfaces based on errors associated with access to the one or more first memory arrays.

[0007] A method for memory operation is described. The method may include: evaluating functionality of each of a plurality of array dies; based on the evaluating, setting one or more non-volatile storage elements of the plurality of array dies to indicate an error associated with one or more of the plurality of array dies; and based on setting the one or more non-volatile storage elements, remapping access to the plurality of array dies from one or more first memory arrays of the plurality of array dies to one or more second memory arrays of the plurality of array dies using logic circuitry of a logic die coupled to the plurality of array dies.

[0008] A semiconductor system is described. The semiconductor system may include: a plurality of array dies stacked in a certain direction, each array die including one or more memory arrays and non-volatile storage devices; and a logic die coupled to the plurality of array dies, the logic die including: a plurality of interfaces including circuits operable to convey access signaling to access the memory arrays of the plurality of array dies; and a logic circuit coupled to the plurality of interfaces. The logic circuit may be operable to: identify errors associated with one or more first memory arrays of the plurality of array dies based on accessing the non-volatile storage devices of one or more of the plurality of array dies; and remap access from one or more first memory arrays using a first interface of the plurality of interfaces to one or more second memory arrays of the plurality of array dies using a second interface of the plurality of interfaces based on identifying the errors.

[0009] A method for memory operation is described. The method may include: detecting, by logic circuitry of a logic die stacked with a plurality of array dies, an error associated with one or more first memory arrays of the plurality of array dies; remapping, by the logic circuitry, access to the plurality of array dies from the one or more first memory arrays using a first interface of the logic die to one or more second memory arrays of the plurality of array dies using a second interface of the logic die based on detecting the error; and accessing the one or more second memory arrays using the second interface based on the remapping.

[0010] A semiconductor system is described. The semiconductor system may include: a plurality of array dies stacked in a certain direction, each array die including one or more memory arrays; and a logic die coupled to the plurality of array dies, the logic die including: a plurality of interfaces including circuits operable to convey access signaling to access the memory arrays of the plurality of array dies; and a logic circuit coupled to the plurality of interfaces. The logic circuit may be operable to: detect an error based on an attempt to access one or more first memory arrays of the plurality of array dies using a first interface of the plurality of interfaces; and based on the detection of the error, remap access to the plurality of array dies from the one or more first memory arrays using the first interface to one or more second memory arrays of the plurality of array dies using a second interface of the plurality of interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting spare techniques in a stacked memory architecture according to examples disclosed herein is presented.

[0012] Figure 2 An example of a system supporting spare techniques in a stacked memory architecture according to examples disclosed herein is presented.

[0013] Figure 3 An example of an interface architecture supporting spare techniques in a stacked memory architecture according to examples disclosed herein is shown.

[0014] Figure 4 An example of a manufacturing process supporting spare technology in a stacked memory architecture according to examples disclosed herein is presented.

[0015] Figure 5A , 5B , 5C and 5D show examples of spare diagrams supporting spare techniques in a stacked memory architecture according to the examples disclosed herein.

[0016] Figure 6 A block diagram is shown of a system supporting spare techniques in a stacked memory architecture according to examples disclosed herein.

[0017] Figure 7 A block diagram showing a logic die supporting spare techniques in a stacked memory architecture according to examples disclosed herein.

[0018] Figure 8 and 9 A flow chart illustrating a method of supporting spare techniques in a stacked memory architecture according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0019] Some memory systems may include a stack of semiconductor dies, including one or more memory dies (which may be referred to as array dies) located above a logic die, which is operable to access a set of memory arrays distributed throughout one or more memories. Such a stacked architecture may be implemented as part of a tightly coupled dynamic random access memory (TCDRAM) system, and may support solutions with memory-centric logic, such as a graphics processing unit (GPU), as well as other implementations. In some examples, a TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled) to a processor (e.g., a GPU or other host) as part of a physical memory map accessible to the processor. This coupling may include one or more processors implemented in the same semiconductor die as at least a portion of the TCDRAM system (e.g., as part of a logic die), or a processor implemented in a die that is directly coupled (e.g., fused) to another die that includes at least a portion of the TCDRAM system. Unlike cache-based memory, TCDRAM may not be supported by external memory levels with the same physical address. For example, the TCDRAM may be associated with and located within a dedicated base address, wherein each portion of the TCDRAM may not overlap within the address.

[0020] In order to manufacture a memory system (e.g., a TCDRAM system) implementing a stacked architecture, the granularity of semiconductor die stacking (e.g., and coupling) may be at the wafer level. For example, due to the tight coupling of the stacked semiconductor dies, a semiconductor wafer including multiple semiconductor dies may be stacked and coupled (e.g., bonded) together, and the corresponding stack of coupled dies may be individually separated (e.g., cut, divided) from the stack of semiconductor wafers (e.g., instead of selecting individual semiconductor dies for stacking and coupling). Wafers with relatively high die yields (e.g., wafers including relatively few dies with defects (e.g., failures)) may be selected to be included in the wafer stack. However, the imperfect yield of the wafer may be exacerbated in the wafer stack, so that the yield of the resulting die stack separated from the wafer stack may be reduced. For example, an eight-high array die stack separated from a stack of wafers each having a yield of approximately 90% may have a yield of approximately 40%. As such, this stack may adversely affect the performance (e.g., latency, bandwidth, storage capacity) or yield of the memory system.

[0021] According to the techniques described herein, a memory system implementing a stacked architecture may support spare techniques to improve the yield of an array die stack (e.g., to compensate for a relatively low yield of an array die stack). For example, one or more spare arrays or dies may be included in the array die stack, and a logic die may include logic circuitry to support sparing (e.g., replacing) one or more failed components (e.g., groups, pseudo-channels, channels, arrays, array dies) of an array die with one or more components (e.g., spare groups, spare pseudo-channels, spare channels, spare arrays, spare array dies) of the one or more spare arrays or dies. For example, the logic die may include an interface block (e.g., a memory interface block (MIB)) for accessing one or more memory arrays of the array die. The logic circuitry may remap access to a failed component to a component of the one or more spare dies, such that access to an address space corresponding to the failed component (e.g., using one or more first interface blocks) may be changed to access one or more components of the one or more spare dies (e.g., using one or more second interface blocks) according to the remapping. Additionally or alternatively, one or more array dies of the array die stack may include a spare portion to which logic circuitry may remap access to a failed component.

[0022] Supporting backup according to the described techniques can improve the yield of a memory system (e.g., a TCDRAM system) implementing a stacked architecture, for example, by supporting the replacement of a faulty component with a backup component. Thus, the performance of the memory system can be improved. In addition, the time to market of a product implementing the TCDRAM system can be shortened. For example, a product released to the market can be associated with a yield constraint, and improving the yield through the backup techniques described herein can enable such constraints to be met without improving manufacturing technology to increase the yield of individual semiconductor wafers, which can involve delays before such improvements are achieved. Additionally or alternatively, the backup techniques described herein can reduce costs because the final yield of the array die stack may be unknown until the array die stack is coupled (e.g., wire-to-wire bonding) with a host system (e.g., included on a logic die). Therefore, if the yield does not meet the yield constraint, the entire system including the logic die and the array die can be discarded. Therefore, using the backup techniques described herein to improve the array die stack yield can increase the possibility of meeting the yield constraint, thereby reducing the cost of manufacturing the TCDRAM system.

[0023] Features of the present disclosure are illustrated and described in the context of systems and dies. Features of the present disclosure are further illustrated and described in the context of interface architectures, manufacturing processes, alternate diagrams, block diagrams, and flow charts.

[0024] Figure 1 An example of a system 100 that supports spare techniques in a stacked memory architecture according to examples disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 that couple the host system 105 with the memory system 110 (e.g., to provide a communicative coupling). The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system 110.

[0025] The host system 105 may be an example of a processor (e.g., circuit, processing circuit, one or more processing components) that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an Internet connection device, a vehicle controller, a system-on-chip (SoC), or a processing system of other stationary or portable electronic devices, among other examples. The host system 105 may include one or more of the following: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers, not shown). The components of the host system 105 may be coupled to each other using a bus 135.

[0026] The external memory controller 120 may be configured to enable communication of information (e.g., data, commands, control information, configuration information) between components of the system 100, e.g., between components of the host system 105 (e.g., the processor 125) and the memory system 110. The external memory controller 120 may process (e.g., convert, translate) communications exchanged between the host system 105 and the memory system 110. In some examples, the external memory controller 120 or other components of the system 100 or associated functionality described herein may be implemented by or be part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is illustrated as being external to the memory system 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165) or vice versa. In various examples, the host system 105 or the external memory controller 120 may be referred to as a host.

[0027] Processor 125 is operable to provide functionality (e.g., control functionality) for system 100 or host system 105. Processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. In some examples, processor 125 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples.

[0028] In some examples, system 100 or host system 105 may include input components, output components, or a combination thereof. Input components may include sensors, microphones, keyboards, another processor (e.g., on a printed circuit board), interfaces (e.g., user interfaces, interfaces between other devices), or peripherals that interface with system 100 via one or more peripheral components, among other examples. Output components may include displays, audio speakers, printing devices, another processor on a printed circuit board, or peripherals that interface with system 100 via one or more peripheral components, among other examples.

[0029] The memory system 110 may be a component of the system 100 that is operable to provide physical memory locations (e.g., addresses) that may be used or referenced by the system 100. The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity for data storage. The memory system 110 may be configured to work with one or more different types of host systems 105, and may respond to and execute commands provided by the host system 105 (e.g., via the external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive a write command indicating that the memory system 110 is to store data received from the host system 105, or receive a read command indicating that the memory system 110 is to provide data stored in the memory die 160 to the host system 105, or receive a refresh command indicating that the memory system 110 is to refresh data stored in the memory die 160, as well as other types of commands and operations.

[0030] The memory system controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory system controller 155 may control the operation of the memory system 110 in cooperation with the local memory controller 165 of the memory die 160.

[0031] Each memory die 160 may include a local memory controller 165 and a memory array 170. The memory array 170 may be a collection of memory cells, each of which may be operable to store one or more bits of data. The memory die 160 may include a two-dimensional (2D) array of memory cells, or a three-dimensional (3D) array of memory cells. In some examples, a 2D memory die 160 may include a single memory array 170. In some examples, a 3D memory die 160 may include two or more memory arrays 170, which may be stacked or positioned next to each other (e.g., relative to a substrate).

[0032] The local memory controller 165 may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 155. In some examples, the memory system 110 may not include a memory system controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165, or both, may include: a receiver for receiving signals (e.g., from the external memory controller 120); a transmitter for transmitting signals (e.g., to the external memory controller 120); a decoder for decoding or demodulating received signals; an encoder for encoding or modulating signals to be transmitted; a sensing component for sensing the state of memory cells of the memory array 170; a writing component for writing the state to the memory cells of the memory array 170; or various other components operable to support the described operations of the memory system 110.

[0033] The host system 105 (e.g., external memory controller 120) and the memory system 110 (e.g., memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission medium, electrical conductors, conductive paths) between terminals associated with components of the system 100. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. The terminal may be an example of a conductive input or output point of a device of the system 100, and the terminal may be operable to serve as part of the channel 115. In some implementations, at least the channel 115 between the host system 105 and the memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) at the host system 105 (e.g., at the external memory controller 120) or at the memory system 110 (e.g., at the memory system controller 155), or both.

[0034] In some examples, channel 115 (e.g., associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, signaling may be conveyed via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be registered for each clock cycle (e.g., on both a rising and falling edge of a clock signal).

[0035] In some examples, at least a portion of the system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some implementations, one or more semiconductor dies may include multiple instances of interface circuits (e.g., of a memory system 110, a memory interface block), each associated with accessing a respective set of one or more memory arrays 170 of one or more other semiconductor dies. In some cases, circuits for accessing one or more memory arrays 170 may be distributed among multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a logic block (e.g., a common logic block, a central logic block, a logic circuit) operable to configure a set of multiple first interface blocks (e.g., a MIB, an instance of a first interface circuit) of the first die. In some examples, the system may include a respective controller for each first interface block (e.g., a memory controller, a host interface controller, at least a portion of the memory system controller 155, at least a portion of the external memory controller 120, or a combination thereof) to support access operations (e.g., accessing one or more memory arrays 170) via the first interface blocks. The system 100 may also include a non-volatile storage device, one or more sensors, or a combination thereof to support various operations of the system 100.

[0036] In some examples, a plurality of semiconductor dies of a memory system 110 (e.g., a TCDRAM system) may include one or more array dies (e.g., memory die 160) stacked with a logic die (e.g., which includes a host system 105, the logic die being coupled to another die including the host system 105), the logic die including an interface block operable to access a set of memory arrays 170 distributed across one or more second dies. In some cases, one or more components of the array die may fail (e.g., be defective, fail), such that successful access to one or more of the memory arrays 170 of the array die using the interface block of the logic die may be unreliable or impossible. Thus, the yield of the array die may be reduced. Yield reduction may be exacerbated in a memory system 110 including a stack of array dies. For example, to manufacture such a memory system 110, semiconductor wafers may be stacked and coupled (e.g., bonded) together, and the corresponding stack of array dies may be individually separated (e.g., cut) from the stack of semiconductor wafers (e.g., rather than selecting individual semiconductor dies for stacking and coupling). Although wafers with relatively high yields may be selected to be included in such a wafer stack, the imperfect yield of the wafers may be exacerbated in the wafer stack, so that the yield of the resulting die stack separated from the wafer stack may be reduced. Therefore, such a stack may adversely affect the performance (e.g., latency, bandwidth, storage capacity) or yield of the memory system 110.

[0037] According to the techniques described herein, the system 100 implementing the stacked architecture may support spare techniques to improve the yield of an array die stack (e.g., memory system 110). For example, one or more spare array dies may be included in the array die stack, and the logic die may include logic circuitry to support sparing (e.g., replacing) one or more failed components (e.g., groups, pseudo-channels, channels, arrays, array dies) of the array die with one or more components (e.g., spare groups, spare pseudo-channels, spare channels, spare arrays, spare array dies) of the one or more spare dies. For example, the logic circuitry may remap access to failed components to components of the one or more spare dies, such that access to an address space corresponding to the failed components (e.g., available for use by the host system 105) may instead access the one or more components of the one or more spare dies according to the remapping. Additionally or alternatively, one or more array dies of the array die stack may include spare portions to which the logic circuitry may remap access to failed components.

[0038] In addition to applicability in systems as described herein, techniques for standby in stacked memory architectures may generally be implemented to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, electronic devices that support artificial intelligence applications and processes may be needed. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes, and may benefit from memory devices that can effectively and efficiently store relatively large amounts of data or access stored data relatively quickly. Implementation of the techniques described herein may support artificial intelligence and / or machine learning techniques by increasing memory access bandwidth and increasing memory capacity, for example, by supporting replacement of failed components with spare components to maintain bandwidth and capacity or mitigate bandwidth and capacity losses even in the event of component failures, as well as other benefits.

[0039] Figure 2 An example of a system 200 (e.g., a semiconductor system, a system of coupled semiconductor dies) supporting spare techniques in a stacked memory architecture according to examples disclosed herein is illustrated. The system 200 illustrates an example of a die 205 (e.g., a semiconductor die, a host die, a processor die, a logic die) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, a semiconductor die, a memory die, an array die). The die 205 or die 240 can be formed using: a respective semiconductor substrate (e.g., a substrate of a crystalline semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or gallium nitride), or a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG), silicon-on-sapphire (SOS)), or an epitaxial semiconductor material formed on another substrate, among other examples. Although the illustrated example of system 200 includes two dies 240, a system 200 according to the described techniques may include any number of one or more dies 240 coupled to die 205. Furthermore, although the non-limiting examples of system 200 herein are generally described in terms of applicability to memory systems, memory subsystems, memory devices, or combinations thereof, examples of system 200 are not limited thereto. For example, aspects of the present disclosure may also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem for applications such as data collection, data processing, data storage device, networking, communication, power supply, artificial intelligence, system-on-chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0040] System 200 illustrates an example of an interface circuit between a host and a memory (e.g., via a host interface, via a physical host interface) that is implemented in (e.g., divided between) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205 may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 and one or more memory arrays 250 (e.g., die 240-a-1 includes an interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, and die 240-a-2 includes an interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0041] Although the example of system 200 is illustrated as including one interface block 245 in each die 240, a die 240 according to the described techniques may include any number of one or more interface blocks 245, each coupled to a respective set of one or more memory arrays 250, and each coupled to a respective interface block 220 of die 205. Thus, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled to (e.g., in communication with) a corresponding interface block 245 of die 240 (e.g., external to die 205). In some examples, the coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels (e.g., one or more data channels, one or more control channels, one or more clock channels, or a combination thereof) may include or be referred to as a data path associated with a respective set of one or more memory arrays 250.

[0042] In some implementations, the die 205 may include a host processor 210. The host processor 210 may be an example of the host system 105 or a portion thereof (e.g., aspects of the processor 125, external memory controller 120, or both). The host processor 210 may be configured to perform operations to implement storage of the memory array 250. For example, the host processor 210 may receive data to be read from the memory array 250, or may transmit data to be written to the memory array 250, or both (e.g., depending on an application or other operation of the host processor 210). Additionally or alternatively, the host processor 210 may be external to the die 205, such as in another semiconductor die or other component coupled (e.g., communicatively coupled, directly coupled, bonded) to the die 205 via one or more contacts 212.

[0043] The host processor 210 may be configured to communicate (eg, transmit, receive) signaling with the interface block 220 via one or more host interfaces 216 (eg, physical host interfaces), which may implement reference Figure 1 The host processor 210 may be configured to transmit access signaling (e.g., control signaling, access command signaling, configuration signaling) via the host interface 216, which may be received by the interface block 220 to support access operations (e.g., read operations, write operations) to the memory array 250. In some examples, the host interface 216 may include a respective set of one or more signal paths for each interface block 220, so that the host processor 210 may communicate with each interface block 220 via the respective set of signal paths (e.g., perform access operations via the interface block 220 selected by the host processor 210 according to a selection of the respective set). Additionally or alternatively, the host interface 216 may include one or more signal paths shared among multiple interface blocks 220 (not shown), and the interface blocks 220 or the host processor 210 or both may interpret, ignore, respond to, or suppress a response to signaling via the shared signal paths of the host interface 216 based on logical indications (e.g., addressing indications or interface enable signals associated with the interface blocks 220, which may be provided by the host processor 210 or the corresponding interface blocks 220 depending on the signaling direction).

[0044] In some examples, a respective host interface 216 may be coupled between a set of one or more interface blocks 220 and a controller 215 (e.g., host interface 216-a-1 is coupled between interface block 220-a-1 and controller 215-a-1, and host interface 216-a-2 is coupled between interface block 220-a-2 and controller 215-a-2). The one or more interface blocks 220 and the controller 215 may communicate (e.g., collaborate) to perform one or more operations associated with the memory array 250 (e.g., scheduling operations, access operations, operations initiated by the host processor 210). The controller 215 may be an example of a control circuit (e.g., a memory controller circuit, a host interface control circuit), and may be associated with a respective example that implements one or more aspects of the external memory controller 120 or one or more aspects of the memory system controller 155, or a combination thereof, for each interface block 220. In some examples, controller 215 may be implemented in die 205, whether host processor 210 is included in die 205 or external to die 205, and interface block 220 may communicate with host processor 210 via one or more controllers 215. In some other examples, controller 215 may be implemented external to die 205 (e.g., in another die, not shown, coupled to a respective interface block 220 via respective terminals of each of respective host interfaces 216), which may be in the same die as the die including host processor 210 or in a different die. In some other examples, aspects of one or more controllers 215 may be included in host processor 210. Although the example of system 200 is illustrated as including a controller 215 for each interface block 220, in various examples, a controller 215 may be coupled to any number of one or more interface blocks 220, and a given interface block 220 may operate based on a single controller 215 or through one or more of a group of multiple controllers 215 (e.g., according to a controller multiplexing scheme).

[0045] In some examples, the host processor 210 may determine an access address (e.g., a logical address of the memory array 250, a physical address of the memory array 250, an address of the interface block 220), and determine which controller 215 transmits access signaling for accessing the address (e.g., the controller 215 or the interface block 220 corresponding to the address). In some examples, the address may be associated with a row of memory cells of the memory array 250. The host processor 210 may transmit the access signaling to the determined controller 215, and in turn, the determined controller 215 may transmit the access signaling to the corresponding interface block 220. The corresponding interface block 220 may then transmit the access signaling to the coupled interface block 245 to access the determined address (e.g., in the corresponding memory array 250).

[0046] The die 205 may also include logic blocks 230 (e.g., shared logic blocks, central logic blocks, common logic circuits) that may be configured to communicate (e.g., transmit, receive) signaling with interface blocks 220 of the die 205. In some cases, the logic blocks 230 may be configured to communicate information (e.g., commands, instructions, indications, data) with one or more interface blocks 220 to facilitate operation of the system 200. For example, the logic blocks 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling) that may be received by the interface blocks 220 to support configuration of the interface blocks 220 or to operate other aspects of the die 240 (e.g., via respective interface blocks 245). The logic block 230 may be coupled to each interface block 220 via a respective bus 231 (e.g., bus 231-a-1 associated with interface block 220-a-1, bus 231-a-2 associated with interface block 220-a-2). In some examples, the respective buses 231 may each include a respective set of one or more signal paths so that the logic block 230 may communicate with each interface block 220 via the respective set of signal paths. Additionally or alternatively, the respective bus 231 may include one or more signal paths shared among multiple interface blocks 220 (not shown).

[0047] In some implementations, logic block 230 may be configured to communicate (e.g., transmit, receive) signaling with host processor 210 (e.g., via bus 232, via contacts 212 of host processor 210 external to die 205) so that logic block 230 may support an interface between interface block 220 and host processor 210. For example, host processor 210 may be configured to transmit initialization signaling (e.g., a boot command), or other configuration or operational signaling that may be received by logic block 230 to support initialization, configuration, or other operations of interface block 220. Additionally or alternatively, in some implementations, logic block 230 may be configured to communicate (e.g., transmit, receive) signaling with components external to system 200 via bus 233 (e.g., and via contacts 234) so ​​that logic block 230 may support an interface that bypasses host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210, and may communicate with one or more memory arrays 250 of one or more dies 240 (e.g., to perform self-test operations of memory array 250). In some examples, such implementations may support evaluation, configuration, or other operations of system 200 via contacts 234 accessible at a physical interface of the system during manufacturing, assembly, verification, or other operations associated with system 200 (e.g., prior to coupling with host processor 210, without implementing host processor 210, for operations independent of the host processor). Additionally or alternatively, logic block 230 may implement one or more aspects of controller 215. For example, logic block 230 may include or operate as one or more controllers 215, and may perform operations attributed to controller 215.

[0048] Each interface block 220 may be coupled with at least a respective bus 221 of die 205 and a respective bus 246 of die 240, which are configured to communicate signaling (e.g., via one or more associated signal paths) with the corresponding interface block 245. For example, interface block 220-a-1 may be coupled with interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled with interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some examples, die 240 may include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which may bypass interface block 245 of die 240-a-1. Such techniques may be extended for interconnection between more than two dies 240 (e.g., for interconnection via respective buses 255 of multiple dies 240).

[0049] The respective signal paths of buses 221, 246, and 255 may be coupled to one another from one die to another via various arrangements of contacts at the surface of the interface die. For example, bus 221-a-1 may be coupled to bus 246-a-1 via contact 222-a-1 of die 205 (e.g., at the surface of die 205) and contact 247-a-1 of die 240-a-1, bus 221-a-2 may be coupled to bus 255-a-1 via contact 222-a-2 of die 205 and contact 256-a-1 of die 240-a-1, bus 255-a-1 may be coupled to bus 246-a-2 via contact 257-a-1 of die 240-a-1 and contact 247-a-2 of die 240-a-2, and so on. Although each respective bus is illustrated as having a single line coupled via a single contact, it is understood that each signal path of a given bus may be associated with a respective contact to support separate communication coupling of each signal path via the given bus. In some examples, bus 255 may traverse a portion of die 240 (e.g., in an in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement), which may support an arrangement of contacts 222 along a surface of die 205 coupled to interface blocks 245 of different dies 240 along a stacking direction (e.g., via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0050] The interconnection of interface contacts may be supported by various techniques. For example, in a hybrid bonding implementation, the interface contacts may be coupled by fusion of conductive materials (e.g., conductive materials) of the interface contacts (e.g., without solder or other intermediate materials between the contacts). For example, in an assembled state, the coupling of die 205 to die 240-a-1 may include fusion of the conductive material of contact 222-a-2 with the conductive material of contact 256-a-1, and the coupling of die 240-a-1 to die 240-a-2 may include fusion of the conductive material of contact 257-a-1 with the conductive material of contact 247-a-2, and so on. In some examples, such coupling may include non-operational fusion of contacts (e.g., non-communication coupling, physical coupling), such as fusion of contact 260-a-1 with contact 256-a-2, neither of which is coupled to the operating circuitry of die 240-a-1 or 240-a-2. In some examples, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contacts 260 that may not be operably coupled to either interface block 245 or interface block 220), or such coupling may be a byproduct of duplication of components that may be operable or inoperable in various configurations (e.g., where, for a die 240 having co-arranged contacts 256 and 257, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0051] In some examples, the fusion of conductive material between dies (e.g., between contacts) may be accompanied by fusion of other materials at one or more surfaces of the interface die. For example, in an assembled condition, the coupling of die 205 with die 240-a-1 may include fusion of dielectric material 207 (e.g., non-conductive material) of die 205 with dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 with die 240-a-2 may include fusion of dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some examples, such dielectric materials may include oxides, nitrides, carbides, oxide-nitrides, oxide-carbides, or other transformations or doping of semiconductor materials of die 205 or die 240, as well as other materials that may support such fusion. However, the coupling between die 205 and die 240 may be implemented according to other techniques that may implement solder, adhesives, thermal interface materials, and other intermediate materials.

[0052] In some examples, the dies 240 may be coupled in a stacked manner (e.g., forming a "cube" or other arrangement of dies 240), and the stack may be subsequently coupled to the die 205. In some examples, a respective set of one or more dies 240 may be coupled to each die 205 of the plurality of dies 205 as formed in a wafer (e.g., in a chip-to-wafer bonding arrangement, before dicing the wafer of dies 205), and the dies 205 of the wafer may be separated from each other (e.g., by dicing at least the wafer of dies 205), each die coupled to its respective set of dies 240. In some other examples, a respective set of one or more dies 240 may be coupled to the respective die 205 (e.g., in a wafer-to-wafer bonding arrangement) after the dies 205 are separated from the wafer of dies 205. In some other examples, a respective set of one or more dies 240, each including a plurality of dies 240, may be coupled in a stacked manner (e.g., in a wafer-to-wafer bonding arrangement). In various examples, such techniques may be followed by separating the stack of dies 240 from the coupled wafer, or the stack of wafers having dies 240 may be coupled to another wafer including a plurality of dies 205 (e.g., in a second wafer-to-wafer bonding arrangement), followed by separating the system 200 from the coupled wafer. In some other examples, the wafer-to-wafer coupling techniques may be implemented by stacking one or more wafers of dies 240 (e.g., sequentially) above a wafer of dies 205 prior to separation into the system 200, as well as other examples for forming the system 200.

[0053] The buses 221, 246, and 255 may be configured to provide configured signaling (e.g., coordination signaling, logic signaling, modulation signaling, digital signaling) between the interface block 220 and the corresponding interface block 245, which may involve various modulation or coding techniques performed by the transmit interface block (e.g., via a driver component of the transmit interface block). In some examples, such signaling may be supported (e.g., accompanied) by clock signaling communicated (e.g., coordinated with signal transmission) via the corresponding bus. For example, the bus may be configured to transmit one or more clock signals transmitted by the interface block 220 for reception by the interface block 245 (e.g., to trigger signal reception by a latch or other receiving component of the interface block 245 to support clock operation of the interface block 245). Additionally or alternatively, the bus may be configured to transmit one or more clock signals transmitted by the interface block 245 for reception by the interface block 220 (e.g., to trigger signal reception by a latch or other receiving component of the interface block 220 to support clock operation of the interface block 220). Such clock signals may be associated with the communication of various signaling (e.g., unidirectional communication, bidirectional communication), such as control signaling, command signaling, data signaling, or any combination thereof. For example, a bus may include one or more signal paths for communication of a data bus (e.g., one or more data channels, a DQ bus, a data interface via an interface block) according to one or more corresponding clock signals (e.g., a data clock signal), or one or more signal paths for communication of a control bus (e.g., a command / address (C / A) bus, a command interface via an interface block) according to one or more clock signals (e.g., a control clock signal), or any combination thereof.

[0054] Interface block 220, interface block 245, and logic block 230 may each include circuits (signaling circuits, multiplexing circuits, processing circuits, controller circuits) in various configurations (e.g., hardware configurations, logic configurations, software or instruction configurations) that support the functionality assigned to the respective blocks for accessing or otherwise operating a corresponding set of memory arrays 250. For example, interface block 220 may include circuits configured to perform a first subset of operations supporting access to memory array 250, and interface block 245 may include circuits configured to support a second subset of operations supporting access to memory array 250. In some examples, interface blocks 220 and 245 may support functional splitting or distribution of functions associated with memory system controller 155, local memory controller 165, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, or both, and may support one or more aspects of implementing memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from host processor 210, or operations performed without commands from host processor 210 (e.g., operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0055] In some implementations, system 200 may include one or more instances of non-volatile storage devices (e.g., non-volatile storage device 235 of die 205, non-volatile storage device 270 of one or more dies 240, or a combination thereof). In some examples, logic block 230, interface block 220, interface block 245, or a combination thereof may be configured to communicate signaling with one or more instances of non-volatile storage devices. For example, where applicable, logic block 230, interface block 220, or interface block 245 may be coupled to one or more instances of non-volatile storage devices via one or more buses (not shown) or corresponding contacts (not shown), which may each include one or more signal paths operable to communicate signaling (e.g., command signaling, data signaling). In some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on information stored in one or more instances of non-volatile storage devices. Additionally or alternatively, in some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (e.g., configuration information) to be stored in one or more instances of non-volatile storage devices. In some examples, such non-volatile storage devices may include fuses, antifuses, or other types of single-time programmable storage elements, or any combination thereof.

[0056] In some embodiments, the system 200 may include one or more sensors (e.g., one or more sensors 237 of the die 205, one or more sensors 275 of the die 240, or a combination thereof). In some embodiments, the logic block 230, the interface block 220, the interface block 245, or a combination thereof may be configured to receive one or more indications based on the measurement results of the one or more sensors of the system 200. For example, the logic block 230, the interface block 220, or the interface block 245 may be coupled to the one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some examples, the logic block 230, the one or more interface blocks 220, the one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of the one or more sensors. For example, the logic block 230 may configure one or more operations of the interface block 220 based on the signaling (e.g., indication, data) received from the one or more sensors. Additionally or alternatively, the interface block 220 may generate access signaling for transmission to a corresponding interface block 245 based on one or more sensors.

[0057] In some examples, the circuits of interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from doped portions of a substrate of a respective die. In some examples, the substrate of die 205 may have characteristics that differ from characteristics of a substrate of die 240. Additionally or alternatively, in some examples, transistors formed from the substrate of die 205 may have characteristics (e.g., manufacturing characteristics, performance characteristics) that differ from transistors formed from the substrate of die 240 (e.g., according to a different transistor architecture).

[0058] In some examples, interface block 220 may support a layout for one or more components within 220. For example, the layout may include pairing components to share access ports (e.g., command ports, data ports). Also in some examples, the layout may support an interface to controller 215 (e.g., host interface 216) that is different from an interface to interface block 245 (e.g., via bus 221). For example, host interface 216 may be synchronous and have separate channels for read and write operations, while the interface via buses 221 and 246 may be asynchronous and support both read and write operations utilizing the same channel.

[0059] The die 240 may include one or more cells 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of cells 265. Although each die 240 of the system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described technology may include any number of cells 265 that may be arranged in various patterns (e.g., a set of one or more cells 265 along a row direction, a set of one or more cells 265 along a column direction, and other patterns). Each cell 265 may include at least the circuitry of a corresponding interface block 245, and one or more memory arrays 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some instances, where applicable, each unit 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., associated with corresponding interface blocks 245 of units 265 of different dies 240), which may support various degrees of stackability or modularity among or through units 265 of other dies 240.

[0060] In some examples, the interface block 220 may include circuitry configured to receive first access command signaling from the host processor 210 or controller 215 (e.g., via the host interface 216, via one or more contacts 212 from the host processor 210 or controller 215 external to the die 205) and transmit second access command signaling to a respective (e.g., coupled) interface block 245 based on (e.g., in response to) the received first access command signaling. The interface block 245 may thus include circuitry configured to receive second access command signaling from the respective interface block 220 and, in some examples, access a respective set of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various examples, the first access command signaling may include an access command associated with an operation type (e.g., a read operation, a write operation, a refresh operation, a memory management operation), which may be associated with an indication of an address (e.g., a logical address, a physical address) of the one or more memory arrays 250. In some examples, the first access command signaling may include an indication of a logical address associated with the memory array 250, and the circuitry of the interface block 220 may be configured to generate the second access command signaling to indicate a physical address associated with the memory array 250 (e.g., a row address, a column address, using a logical-to-physical (L2P) table or other mapping or calculation functionality of the interface block 220).

[0061] In some examples, to support write operations of the system 200, the circuitry of the interface block 220 may be configured to receive first data signaling associated with the first access command signaling (e.g., from the host processor 210, from the controller 215, via the host interface 216, from the host processor 210 or the controller 215 external to the die 205 via the one or more contacts 212), and transmit second data signaling (e.g., associated with the second access command signaling) based on the received first access command signaling and the first data signaling. The interface block 245 may thus be configured to receive the second data signaling, and write data to the one or more memory arrays 250 based on the received second access command signaling and the second data signaling (e.g., according to the indicated address associated with the first access command signaling). In some instances, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, an ECC engine) that supports interface block 220 in generating second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits to be transmitted in the second data signaling and written with the data).

[0062] In some examples, to support read operations of the system 200, the circuitry of the interface block 245 may be configured to read data from the memory array 250 based on the received second access command signaling, and transmit the first data signaling based on the read data. The interface block 220 may thus be configured to receive the first data signaling, and transmit the second data signaling based on the received first data signaling (e.g., to the host processor 210, to the controller 215, via the host interface 216, to the host processor 210 or the controller 215 external to the die 205 via one or more contacts 212). In some examples, the interface block 220 may include an error control function that enables the interface block 220 to generate the second data signaling based on performing an error control operation using the received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0063] In some examples, access command signaling and other signaling transmitted by the interface block 220 to the interface block 245 may be generated (e.g., based on a configuration modified at the interface block 220 for accessing the memory array 250) according to various determination or generation techniques configured at the interface block 220 (e.g., based on access command signaling received from the host processor 210, based on initialization signaling received from the host processor 210, without receiving signaling from the host processor 210, or otherwise independent of signaling from the host processor 210). In some examples, such techniques may involve signaling or other coordination with the logic block 230, the host processor 210, one or more controllers 215, one or more instances of non-volatile storage devices, one or more sensors, or any combination thereof. Such techniques may support the interface block 220 in configuring aspects of access operations and other operations performed by the corresponding interface block 245 on the memory array 250. For example, interface block 220 may include evaluation circuits, access configuration circuits, signaling circuits, scheduling circuits, repair circuits, refresh circuits, error control circuits, adverse access circuits, and other circuits operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0064] In some cases, to manufacture system 200, semiconductor wafers including die 240 may be stacked and coupled together, and respective stacks of die 240 may be individually separated (e.g., cut) from the stack of semiconductor wafers (e.g., rather than selecting individual semiconductor dies for stacking and coupling). In some instances, semiconductor wafers including die 205 may also be stacked and coupled with the stack of semiconductor wafers, and respective stacks of die 240 and die 205 forming system 200 may be individually separated from the stack of semiconductor wafers. In some other instances, die 205 may be stacked and coupled with the stack of die 240, such as after separating the stack of die 240. Although wafers having relatively high yields (e.g., yields of die 240, yields of die 205) may be selected for inclusion in a wafer stack, imperfect yields of the die in such wafers may be exacerbated in the wafer stack, such that the yield of the resulting die stack 240 separated from the wafer stack may be reduced. As such, such stacking may adversely impact the performance (eg, latency, bandwidth, storage capacity) and yield of system 200 .

[0065] According to the techniques described herein, the system 200 may be configured to support spare techniques to improve the yield of the stack of dies 240, and thus improve the yield of the system 200. For example, one or more dies 240 may be spare dies included in the stack of dies 240. The logic block 230 of the die 205 may support sparing one or more failed components (e.g., groups, pseudo-channels, channels, entire die 240) of the die 240 with one or more components (e.g., spare groups, spare pseudo-channels, spare channels, entire spare die 240) of the one or more spare dies 240. For example, the logic block 230 may remap access to failed components using one or more interface blocks 220 to components of one or more spare dies 240 using one or more other interface blocks 220, so that access to an address space (e.g., an address space available for use by the host processor 210, a logical address space) corresponding to the failed component may be changed to access one or more components of the one or more spare dies 240. Additionally or alternatively, one or more dies 240 may include spare portions (e.g., one or more spare memory arrays 250) to which logic block 230 may remap access to the failed component (e.g., using a different interface block 220). In some examples, such techniques may remap signaling of one or more host interfaces 216 from a respective first interface block 220, or a portion thereof associated with the failed component (e.g., an accessed component or a subset of its addresses) to a second interface block 220, or a portion thereof associated with the spare component (e.g., an accessed component or a subset of its addresses) (e.g., using a multiplexing or mapping component between the host interface 216 and the interface block 220, not shown), which may support such spare techniques transparent to the host system 105.

[0066] Figure 3 An example of an interface architecture 300 supporting spare techniques in a stacked memory architecture according to examples disclosed herein is shown. Interface architecture 300 illustrates an example of an interface block 245-b (e.g., of die 240) coupled to an interface block 220-b (e.g., of die 205). Interface block 245-b may be communicatively coupled to interface block 220-b via one or more of bus 301, bus 302, bus 303, and bus 304, each of which may be an example of one or more signal paths of bus 221 and bus 246 and bus 255, where applicable.

[0067] The interface block 245-b includes a control interface 310 (e.g., a command interface) that can be configured to communicate signaling with the interface block 220-b. For example, the control interface 310 can include circuits (e.g., receivers, one or more latches) configured to receive control signaling (e.g., modulated control signaling, access command signaling, configuration signaling, address signaling, such as row address signaling or column address signaling) via the bus 301-a. The control interface 310 can also include circuits configured to receive clock signaling (e.g., clock signaling associated with the control interface 310, clock signaling with one or more phases (e.g., true and complementary phases), dk_t / c signaling from the interface block 220-b) via the bus 302-a, which the control interface 310 can use to receive control signaling (e.g., for triggering one or more latches) of the bus 301-a. The control interface 310 may transmit (eg, forward) control signaling, clock signaling (eg, for timing of other operations of the interface block 245 - b ) to the interface controller 320 .

[0068] Interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured to communicate signaling with interface block 220-b. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, operated based on) control signaling via control interface 310. Although the example of interface block 245-b includes two such data interfaces 330 associated with control interface 310 (e.g., in a "channel pair" arrangement), for a given control interface 310 of interface block 245, the described techniques for interface block 245 may include any number of one or more data interfaces 330 and associated buses and circuitry. Each data interface 330 may be associated with a corresponding data path circuit, which may include corresponding first-in-first-out (FIFO) and serialization / deserialization (SERDES) circuits (e.g., FIFO / SERDES 340), corresponding write / sense circuits 350, corresponding synchronization and sequencing circuits (e.g., sync / seq logic 360), and corresponding timing circuits 370, as well as interconnect signal paths (e.g., one or more buses). However, in some other examples, the data path circuits may be arranged in a different manner, or may include different circuit components, which may include circuits dedicated to the corresponding data path or shared among the data paths, or various combinations thereof. Each data interface 330 may also be associated with a corresponding set of one or more memory arrays 250. In some examples, each memory array 250 may be understood to include corresponding addressing circuits, such as group logic or decoders (e.g., row decoders, column decoders), and other array circuits. However, in some other examples, at least a portion of such circuits may be included in the interface block 245.

[0069] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via the corresponding bus 303. Each data interface 330 may also include circuitry to communicate clock signaling via the corresponding bus 304, which may support clock signal reception by the data interface 330 (e.g., first clock signaling associated with the data interface 330, clock signaling with one or more phases (e.g., true and complementary phases), DQS_t / c signaling from the interface block 220-b, clock signaling associated with data reception or write operations), or clock signal transmission by the data interface 330 (e.g., second clock signaling associated with the data interface 330, RDQS_t / c signaling to the interface block 220-b, clock signaling associated with data transmission or read operations), or both. In some examples, data interface 330, bus 303, or a combination of bus 303 and bus 304 may be associated with a "pseudo-channel," and multiple pseudo-channels may be associated with the same control interface 310 or the same control bus (e.g., bus 301, a combination of bus 301 and bus 302). Each data interface 330 may transmit clock signaling (e.g., received clock signaling, DQS_t / c signaling) to sync / seq logic 360 (e.g., for timing of other operations of interface block 245-b) via a respective bus.

[0070] The interface controller 320 may support various control or configuration functionalities of the interface block 245-b for accessing or otherwise managing the operation of the coupled memory array 250. For example, the interface controller 320 may support access command coordination or configuration, latency or timing compensation, access command buffering (e.g., according to a FIFO or other organizational scheme), mode registers or logic for configuration settings, or test functionality, among other functions or combinations thereof. For each data path of the interface block 245 (e.g., associated with a respective data interface 330), the interface controller 320 may be configured to transmit signaling (e.g., address signaling, such as row address or row activation signaling) to the respective memory array 250 via the bus 321. For each data path of the interface block 245, the interface controller 320 may communicate signaling (e.g., timing signaling, which may be based on clock signaling received from the control interface 310, configuration signaling) with the respective timing circuit 370 and sync / seq logic 360 via the respective bus.

[0071] For each data path, a respective timing circuit 370 may support timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) relative to timing signaling received from the interface controller 320. For example, the timing circuit 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other initialization signals for controlling the operation of the respective data path, and such signaling may include transitions (e.g., rising edge transitions, falling edge transitions, on / off transitions) that are offset, offset at a different rate, or otherwise different from the transitions of the signaling from the interface controller 320 to support a given operation or combination of operations. For example, the timing circuit 370 may be configured to transmit signaling (e.g., column select signaling, column address signaling) to the respective memory array 250, transmit signaling to the respective write / sense circuit 350 (e.g., latch or driver timing signaling), and transmit signaling to the respective sync / seq logic (e.g., timing signaling).

[0072] For each data path, a corresponding FIFO / SERDES 340 may be configured to convert between data signaling of a first bus width (e.g., a relatively wide bus width, a data read / write (DRW) bus, a bus with a relatively large number of signal paths for communicating with the write / sense circuit 350) and a second bus width (e.g., a relatively narrow bus width, a bus with a relatively small number of signal paths for communicating with the data interface 330). In some examples, such conversion may be accompanied by changing the signaling rate between the signaling from the data interface 330 and the write / sense circuit 350 (e.g., to maintain a given throughput). In various examples, the FIFO / SERDES 340 may receive data signaling from the data interface 330 and transmit the data signaling to the write / sense circuit 350 (e.g., to support a write operation), or may receive data signaling from the sense circuit 350 and transmit the data signaling to the data interface 330 (e.g., to support a read operation). In some examples (eg, to support read operations), the FIFO / SERDES 340 may be configured to transmit clock signaling (eg, RDQS_t / c signaling) to the data interface 330, which may be forwarded to the interface block 220-b.

[0073] The timing or other synchronization of operations performed by the FIFO / SERDES 340 may be supported by one or more clock signals and other signaling received from the corresponding sync / seq logic 360. For example, the sync / seq logic 360 may generate or otherwise coordinate clock signaling to support different signaling rates for different buses (e.g., based on the received clock signaling). Additionally or alternatively, the FIFO / SERDES 340 may operate in a certain direction (e.g., for data transmission to the data interface 330, for data reception from the data interface 330) or in other modes based on configuration signaling received from the sync / seq logic 360.

[0074] For each data path, a respective write / sense circuit 350 may be configured to support access (e.g., data signaling, write signaling, read signaling) to a respective set of one or more memory arrays 250. For example, the write / sense circuit 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which may include respective signal paths associated with each memory array 250, or may include signal paths shared by all memory arrays 250 of the set, in which case the memory array circuit may include multiplexing circuitry operable to couple the bus to a selected one of the memory arrays 250. In some examples, the bus between the write / sense circuit and the set of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuit 350 and the FIFO / SERDES 340 (e.g., for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other examples, the memory array 250 may include a number of columns that is an integer multiple of the number of signal paths of the bus, in which case the memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the columns of memory cells or associated circuitry to the bus.

[0075] To support write operations, write / sense circuitry 350 may be configured to drive signaling operable to write one or more logic states to memory cells of memory array 250 (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some examples, such signaling may be transmitted to or otherwise associated with support circuitry of memory array 250 (e.g., as an output of a signal corresponding to the logic state to be written), such as sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable to apply a bias across a storage element of a memory cell (e.g., across a capacitor, across a ferroelectric capacitor) or to apply a charge, current, or other signaling to a storage element of a memory cell (e.g., applying a current to a chalcogenide or other configurable memory material, applying a charge to a gate of a NAND memory cell), among other examples.

[0076] To support read operations, the write / sense circuit 350 may be configured to receive signaling that the write / sense circuit 350 may further amplify for communication through the interface block 245-b. For example, the write / sense circuit 350 may be configured to receive signaling corresponding to a logic state read from the memory array 250, but at a relatively low driver strength (e.g., relative to "analog" signaling, which may be associated with a relatively low drive strength of the sense amplifiers of the memory array 250). The write / sense circuit 350 may therefore include additional sense amplifiers (e.g., data sense amplifiers (DSAs) between signal paths between the write / sense circuit and a set of one or more memory arrays and corresponding signal paths between the write / sense circuit and the FIFO / SERDES), which may each have a relatively high drive strength (e.g., for driving relatively "digital" signaling).

[0077] Features of interface architecture 300 may be replicated in various numbers and arrangements to support semiconductor systems having multiple dies, such as various instances of system 200. In an example embodiment, each die 240 may be configured with 64 instances of interface block 245-b, which may support a data signaling width of 9,216 signal paths per die 240 (e.g., where each bus 303 of a channel pair is associated with 72 signal paths). For system 200 having a stack of eight dies 240 coupled to die 205, die 205 may thus be configured with 512 instances of interface block 220-b, thereby supporting a total data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 may be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 may be configured with different numbers of dies 240 per die 205.

[0078] According to the techniques described herein, a system (e.g., system 200) implementing interface architecture 300 may support spare techniques to improve the yield of a stack of dies 240, and thus improve the yield of an associated stacked semiconductor system. For example, one or more dies 240 may be spare dies included in the stack of dies 240. Logic block 230 of die 205 may support sparing one or more failed components (e.g., groups, pseudo-channels, channels, dies 240) of die 240 with one or more components (e.g., groups, pseudo-channels, channels, dies 240) of one or more spare dies 240. For example, logic block 230 may remap access to failed components using one or more interface blocks 220 to components of one or more spare dies 240 using one or more other interface blocks 220, so that access to an address space corresponding to the failed component (e.g., available for use by host processor 210) may instead access one or more components of one or more spare dies 240. Additionally or alternatively, one or more dies 240 may include spare portions (eg, one or more spare memory arrays 250) to which logic block 230 may remap access to failed components (eg, using a different interface block 220).

[0079] In some examples, the spare technique may include remapping of at least a portion of the interface block 220-b or the interface block 245-b, or both, for a given host interface 216 (e.g., isolating the interface block 220-b associated with the component failure from the host interface 216 and coupling the interface block 220-b associated with the spare component with the corresponding host interface 216). For example, to support die-level spare, the logic block 230 may remap each instance of the interface block 245-b (e.g., and the corresponding interface block 220-b) in the first die 240 (e.g., for the corresponding host interface 216) to a corresponding instance of the interface block 245-b (e.g., and the corresponding interface block 220-b) in the second die 240. To support channel-level sparing, logic block 230 may remap a first instance of interface block 245-b (e.g., in first die 240) and corresponding interface block 220-b to a second instance of interface block 245-b (e.g., in first die 240, in second die 240) and corresponding interface block 220-b. To support pseudo-channel-level sparing, logic block 230 may remap a first pseudo-channel (e.g., bus 303-a and bus 304-a, data channel) associated with a first instance of interface block 245-b (e.g., in first die 240) and, in some instances, the first instance of interface block 220-b to a second pseudo-channel associated with a second instance of interface block 245-b (e.g., in first die 240, in second die 240) and, in some instances, the second instance of interface block 220-b. To support group-level spare, logic block 230 may remap a first group (e.g., memory array 250-b, a group of memory array 250-b) associated with a first instance of interface block 245-b (e.g., in first die 240) and, in some instances, a first instance of interface block 220-b to a second group associated with a second instance of interface block 245-b (e.g., in first die 240, in second die 240) and, in some instances, a second instance of interface block 220-b.

[0080] Figure 4 An example of a manufacturing process 400 for supporting spare technology in a stacked memory architecture according to examples disclosed herein is shown. For example, Figure 4 Aspects of a sequence of manufacturing operations for manufacturing a stack 425 (eg, a stack of dies) may be described, which may be an example of at least a portion of the system 200. Figure 4The illustrated and described operations may be performed by a manufacturing system, such as a semiconductor manufacturing system configured to perform additive operations such as deposition or bonding, subtractive operations such as etching, trenching, planarization, or polishing, and supporting operations such as masking, patterning, photolithography, coupling, stacking, cutting, or alignment, and other operations supporting the described techniques. In some examples, the operations performed by such a manufacturing system may be supported by a process controller or components thereof as described herein.

[0081] The first set of one or more manufacturing operations may include forming die 240-b on wafer 405. For example, wafer 405 may be a semiconductor wafer on which a set of die 240-b are formed, such as via various additive operations, subtractive operations, supporting operations, doping operations, or combinations thereof, as well as other types of operations.

[0082] To manufacture the system 200, such as a TCDRAM system, coupling (e.g., bonding) the die 240-b in a stacked manner may occur at the wafer level. For example, the second set of one or more manufacturing operations may include coupling a set of wafers 405 into a stack 410 (e.g., a wafer stack). In some examples, the coupling wafer 405 may include respective conductive materials that fuse (e.g., bond) respective contacts (e.g., contacts 247, contacts 256, contacts 257, contacts 260) of the die 240-b. Thus, the stack 410 may include multiple stacks of die 240-b stacked in a certain direction (e.g., the direction in which the wafers 405 are stacked).

[0083] In some examples, the third set of one or more manufacturing operations may include coupling wafer 415 with stack 410 to form stack 420 (e.g., a wafer stack). Wafer 415 may be a semiconductor wafer on which a group of dies 205-b are formed, such as via various additive operations, subtractive operations, supporting operations, doping operations, or combinations thereof, as well as other types of operations. The third set of manufacturing operations may include fusing (e.g., bonding) respective conductive materials of respective contacts (e.g., contacts 222) of the group of dies 205-b with respective conductive materials of respective contacts (e.g., contacts 247, contacts 256) of die 240-b. For example, the corresponding contacts 222 of the group of dies 205-b may be coupled (e.g., fused, bonded) with the contacts of the corresponding bottom die 240-b of each stack of dies 240-b, while the group of dies 205-b is included in the chip 415 (e.g., a portion of), and the stack of dies 240-b is included in the chip 405 (e.g., a portion of).

[0084] In some examples, the fourth set of one or more manufacturing operations can include separating stacks 425 from stacks 420. For example, the fourth set of one or more manufacturing operations can include slicing respective stacks 425 from stacks 420, wherein each stack 425 includes a respective die 205-b of wafer 415 and a respective stack of die 240-b coupled to the respective die 205-b. Each stack 425 can be an instance of a respective system 200.

[0085] In some examples, coupling the stack of die 205-b with die 240-b to form stack 425 may occur after the stack of die 240-b is separated from stack 410. For example, a third set of one or more manufacturing operations may include dicing the respective stack of die 240-b from stack 410. A fourth set of one or more manufacturing operations may include separating (e.g., dicing) the respective die 205-b from wafer 415 and coupling the respective die 205-b with the respective stack of die 240-b to form the respective stack 425. Although some techniques are described in the context of wafer stacking, the alternate techniques described herein may be implemented in stack 425 formed by other techniques, such as those involving directly stacking dies 240 and 205 (e.g., after one or more dies 240 or 205 are individually separated from one or more wafers).

[0086] The fabrication of the stack 425 may be configured to support spare techniques as described herein. For example, a set of wafers 405 coupled together to form a stack 410 may include one or more additional (e.g., spare) wafers 405 such that each stack of die 240-b separated from the stack 410 and included in the respective stack 425 may include one or more additional (e.g., spare) die 240-b. For example, a stack 425 may include a die 240-b-1, which may be an example of a spare array die including a component (e.g., a group, a channel, a pseudo-channel, an entire die 240-b-1) to which access may be remapped. In some examples, one or more die 240-b may additionally or alternatively include an additional (e.g., spare) portion including a spare component (e.g., a group, a channel, a pseudo-channel, a memory array) to which access may be remapped.

[0087] In some embodiments, one or more functions of each die 240-b may be evaluated at various stages of the manufacturing process 400 to determine whether to perform a backup associated with the die 240-b. In some examples, the function of each die 240-b may be evaluated before the stack 410 is formed (e.g., by a manufacturing system, by a tester). For example, coupling the set of wafers 405 to form the stack 410 may occur after the function of each die 240-b of each wafer 405 has been evaluated. Additionally or alternatively, the function of each die 240-b may be evaluated after the stack 410 is formed (e.g., before forming the stack 420, before the die 205-b is coupled to the corresponding stack 425). For example, a set of wafers 405 may be coupled together to form the stack 410, after which the function of each die 240-b may be evaluated. In some examples, the functionality of each die 240-b may be evaluated after the respective stack of die 240-b is separated from stack 410 and before the respective die 205-b is coupled to the respective stack of die 240-b. Additionally or alternatively, the functionality of each die 240-b may be evaluated after forming stack 425. For example, a stack of die 240-b may be coupled with die 205-b, including as part of stack 420 or as part of stack 425, and the functionality of each die 240-b in the stack of die 240-b may be evaluated, for example, using circuitry of die 205-b (e.g., interface block 220 of die 205-b).

[0088] Evaluating the functionality of each die 240-b may support detecting one or more errors associated with a given die 240-b to determine whether to perform a spare on the die 240-b. For example, evaluating the functionality of the die 240-b may include performing one or more operations (e.g., access operations) to determine whether components of the die 240-b (e.g., components of the interface block 245, components of the memory array 250, components of the bus 251, components of the bus 255, components of the bus 246, components of contacts or couplings thereof) function properly and whether there are errors (e.g., failures) associated with the given components. In some examples, evaluating the functionality of the die 240-b may be relatively more granular after forming the stack 425. For example, the circuitry of the interface block 220 of the die 205-b of the stack 425 may be used to evaluate the respective functionality of the die 240-b of the stack 425 at a finer granularity than the circuitry of the tester used to evaluate the respective functionality before forming the stack 425. Thus, in some cases, relatively more types of errors may be detected as part of the evaluation after forming stack 425 than as part of the evaluation before forming stack 425.

[0089] In some instances, errors associated with die 240-b may be detected during operation of stack 425 (e.g., during evaluation operations, during operation in an assembly or integration condition, in deployment of stack 425). For example, errors may occur over time due to wear or adverse operations (e.g., overvoltage operation, overtemperature operation), as well as other factors. In some instances, the error may occur as part of an attempt to access memory array 250 of die 240-b using interface block 220 of die 205-b. In some instances, the error may be detected by interface block 220 based on a failure of the attempted access. In some instances, interface block 220 may indicate the error to logic block 230 of die 205-b (e.g., transmit an indication of the error).

[0090] In some examples, the non-volatile storage devices of one or more dies 240-b or 205-b may be set to indicate an error, and the logic block 230 may detect (e.g., identify) the error for backup based on access to the non-volatile storage device. For example, the non-volatile storage device 270 of the first die 240-b where the error occurred may be set to indicate the error. Additionally or alternatively, the non-volatile storage device 270 of the second die 240-b to which the access is remapped may be set to indicate an error associated with the first die 240-b. Additionally or alternatively, the non-volatile storage device 235 of the die 205-b may be set to indicate an error associated with the first die 240-b (e.g., and indicate the second die 240-b to which the access is remapped). In some examples, in order to set the non-volatile storage device 270 or the non-volatile storage device 235, a one-time programmable storage element of the non-volatile storage device may be set. For example, one or more fuses or antifuses of the nonvolatile storage device may be set (e.g., blown) to indicate an error. In some cases, a tester performing an evaluation of die 240-b may set nonvolatile storage device 270 of die 240-b. In some cases, circuitry (e.g., interface block 220, logic block 230) of logic die 205-b may set nonvolatile storage device 270 of die 240-b or nonvolatile storage device 235 of logic die 205-b (e.g., cause it to be set).

[0091] Sparing may be performed based on detection (e.g., identification) of an error associated with die 240-b. For example, logic block 230 of die 205-b may remap access to the stack of die 240-b (e.g., via one or more host interfaces 216) based on (e.g., in response to) detecting an error (e.g., by accessing non-volatile storage device 270 or 235 or based on failed attempts to access one or more memory arrays 250 of the stack of die 240-b). Logic block 230 may support remapping of access to the stack of die 240-b according to various levels of granularity (e.g., based on the type of error detected). For example, logic block 230 may support remapping at a die-level granularity, a channel-level granularity, a pseudo-channel-level granularity, a group-level granularity, or a combination thereof.

[0092] By supporting spares based on error detection, the yield of stack 425 (e.g., system 200, TCDRAM system) can be improved, for example, by supporting replacement of faulty components with spare components. In this way, the performance of stack 425 can be improved, including bandwidth, storage capacity, and latency. In addition, the time to market of products implementing stack 425 is shortened. For example, products released to the market may be associated with yield constraints, and improving yields through spare techniques described herein may enable such constraints to be met without improving manufacturing technology to increase the yield of individual semiconductor wafers, which may involve delays before such improvements are achieved. In addition, the spare techniques described herein may reduce costs because the final yield of the stack of die 240-b may be unknown until it is coupled with die 205-b (e.g., because the finer granularity of the function of die 240-b can be tested after coupling with die 205-b). Therefore, if the yield fails to meet the yield constraint, the entire stack 425 may be discarded. Thus, improving the yield of the stack of dies 240 - b using the spare techniques described herein may increase the likelihood of meeting yield constraints, thereby reducing the cost of manufacturing the stack 425 .

[0093] Figure 5A , 5B 5C and 5D show examples of spare maps 500 supporting spare techniques in a stacked memory architecture according to examples disclosed herein. Spare map 500 illustrates examples of remapping operations that may be performed to support spares within a stack 425 (e.g., system 200, TCDRAM system) according to various levels of granularity.

[0094] Figure 5AA spare diagram 500-a is shown that supports die-level spares. For example, spare diagram 500-a depicts die 205-c-1 coupled to a group of die 240-c stacked in a direction (e.g., a z-direction, a direction perpendicular to die 205-c-1), which may collectively be instances of stack 425. Errors associated with die 240-c-1 in the group of die 240-c may be detected, as described herein. Based on the detection of the error, logic block 230 of die 205-c-1 may remap access to die 240-c-1 to die 240-c-2 in the group of die 240-c. For example, an address space available to (e.g., accessible to) a host system (e.g., host system 105, host processor 210, such as host processor 210 of die 205-c-1 or host processor 210 included in another die coupled to die 205-c-1) via a set of host interfaces 216 of die 205-c-1 may include a portion of addresses that the host system may use to access die 240-c-1 (e.g., memory array 250 of die 240-c-1). Logic block 230 may remap the portion of addresses so that use of addresses within the portion by the host system (e.g., via a subset of host interfaces 216 of die 205-c-1) may instead access die 240-c-2 (e.g., memory array 250 of die 240-c-2). In some examples, die 240-c-2 may be a spare die of the set of dies 240-c.

[0095] Die 240-c-1 may include an interface block 245 via which a memory array 250 of die 240-c-1 may be accessed. To support die-level granularity remapping (e.g., an entire portion of an address space corresponding to die 240-c-1), logic block 230 may remap access (e.g., via a subset of host interfaces 216 corresponding to die 240-c-1) from all interface blocks 245 of die 240-c-1 to corresponding interface blocks 245 of die 240-c-2. For example, a portion of the address space corresponding to die 240-c-1 may be remapped to an interface block 245 of die 240-c-2. In some examples, a first set of interface blocks 220 of die 205-c-1 may be coupled to an interface block 245 of die 240-c-1. To support the remapping, logic block 230 may remap accesses from the first set of interface blocks 220 (e.g., remap couplings to a subset of host interfaces 216) to a second set of interface blocks 220 of die 205-c-1 coupled to interface blocks 245 of die 240-c-2. For example, a portion of the address space corresponding to die 240-c-1 may be remapped to the second set of interface blocks 220 such that accesses to addresses within the remapped portion of the address space may be supported by respective interface blocks 220 in the second set of interface blocks 220. In some examples, the second set of interface blocks 220 may be referred to as spare interface blocks 220 for die 205-c-1 (e.g., based on coupling to interface blocks 245 of spare die 240-c).

[0096] In some examples, one or more spare dies 240 (e.g., for die-level sparing, for channel-level sparing, for pseudo-channel-level sparing, for group-level sparing) according to the described techniques may be located at various positions (e.g., stack positions, positions along the z-direction) in the stack 425 to support various operational characteristics of the system. For example, one or more spare dies 240 may be located at the bottom of the stack 425 (e.g., a spare die 240 of the stack 425 located closest to the die 205 along the z-direction, such as the die 240-c-2 adjacent to the die 205-c-1, one or more spare dies 240 between the die 205 and one or more dies 240 assigned to nominal or initial operation). In some examples, positioning one or more spare dies 240 at the bottom of the stack 425 may provide thermal benefits to the system. For example, a die 240-c positioned relatively closer to die 205-c-1 in the z-direction may be relatively hotter than a die 240-c positioned further away from die 205-c-1, which may be due to a relatively high power density associated with die 205-c-1, or having a thermal path that is otherwise not conducive to heat dissipation, among other considerations. In some cases, relatively high temperatures may be associated with a relatively high likelihood of error or otherwise degraded performance of die 240. Thus, by positioning spare die 240 relatively closer to die 205, adverse thermal characteristics of spare die 205 may be avoided in a nominal (e.g., initial, as-built) configuration, and may be implied or addressed if spare die 240 or some portion thereof is implemented (e.g., by logic block 230). In addition, the die 240 of the stack 425 configured for nominal operation can be relatively cooler than one or more spare dies by positioning it relatively away from the die 205, thereby improving the nominal performance of the system (e.g., improving the performance of the die 240 for nominal operation), reducing the likelihood of errors that may involve resolution with the aid of spares, or both.

[0097] In some other examples, the spare die 240 may be located at another location within the stack 425. For example, the spare die 240 may be located at the top of the stack 425 (e.g., above the other die 240-c in the z-direction). In some examples, such an implementation may be associated with relatively shorter or otherwise less complex electrical routing (e.g., shorter distances in the z-direction, fewer interconnections between dies), which may be associated with relatively favorable signaling characteristics or relatively higher nominal yields in the nominal configuration (e.g., due to the relatively fewer die-to-die connections involved in the nominal configuration, and the reduced likelihood of needing a spare). In some other examples, the location of the spare die 240 may not be predetermined, and the spare die 240 may be assigned at various locations based on an evaluation of the die 240 itself, or an evaluation of the die 240 after stacking, or various combinations thereof.

[0098] Figure 5B An example of a spare diagram 500-b that supports channel-level spares is shown. For example, spare diagram 500-b depicts die 205-c-2 coupled to a group of die 240-c stacked in a direction (e.g., z-direction), which may be an example of stack 425. Errors associated with die 240-c-3 in the group of die 240-c may be detected, as described herein. For example, each die 240-c may include a group of channels 505-a (e.g., 64 channels, associated with 64 cells 265), via which information may be communicated between interface block 220 of die 205-c-2 and interface block 245 of die 240-c. For example, each channel 505-a may include a command channel (e.g., bus 301 and bus 302) and a set of data channels (e.g., each data channel includes bus 303 and bus 304), and the interface block 220 and the interface block 245 may communicate signaling via the command channel and the set of data channels. In some examples, each channel 505-a may include one command channel and two data channels (e.g., channel pair, two pseudo channels). In some examples, the group of channels 505-a within the stacked die 240-c may be arranged (e.g., organized) according to a channel set 510-a. For example, the channel set 510-a may include a respective channel 505-a across each cell 265 of the group of dies 240-c, for which the signaling may pass through the bus 255 of the cell 265 stacked in the z-direction. In some examples, the interface block 220 of the die 205-c-2 may be associated with the respective channel 505-a or channel set 510-a. For example, die 205 - c - 2 may include a respective interface block 220 for each channel 505 - a of the set of die 240 - c .

[0099] exist Figure 5BIn an example of the embodiment of the present invention, an error associated with the channel 505-a-1 of the die 240-c-3 may be detected. Based on the detection of the error, the logic block 230 of the die 205-c-2 may remap access to the channel 505-a-1 (e.g., corresponding to the cell 265 of the channel 505-a-1) to another channel 505-a of the set of dies 240-c (e.g., mapped to another cell 265). For example, the logic block 230 may remap access to the channel 505-a-1 to the channel 505-a-2 of the die 240-c-4 in the set of dies 240-c, which may be included in the channel set 510-a-1 including the channels 505-a-1 and 505-a-2. In some other examples, the logic block 230 may remap access to the channel 505-a-1 to another channel 505-a of the die 240-c-4 that is not included in the channel set 510-a-1 (e.g., included in another channel set 510-a). In some other examples, the die 240-c-3 may include one or more spare channels 505-a, and the logic block 230 may remap access to the channel 505-a-1 to the spare channel 505-a of the die 240-c-3. In some examples, the die 240-c-4 may be a spare die in the set of dies 240-c, and the channel 505-a of the die 240-c-4 may be the spare channel 505-a.

[0100] To support remapping, logic block 230 may remap a portion of the address space available to the host system that corresponds to channel 505-a-1. For example, logic block 230 may remap a portion of the address space so that use of addresses within the portion by the host system may instead access channel 505-a-2 (e.g., memory array 250 of unit 265 accessible via channel 505-a-2) or some other channel 505-a to which logic block 230 remaps access to channel 505-a-1. In order to remap the portion of the address space, logic block 230 may remap interface block 245 of die 240-c-3 associated with channel 505-a-1 to interface block 245 of die 240-c-4 associated with channel 505-a-2, or to interface block 245 associated with some other channel 505-a to which access to channel 505-a-1 is remapped (e.g., another interface block 245 of die 240-c-3 associated with a spare channel 505-a of die 240-c-3).

[0101] Additionally or alternatively, logic block 230 may remap access from a first interface block 220 of die 205-c-2 associated with channel 505-a-1 to a second interface block 220 of die 205-c-2 associated with channel 505-a-2 or some other channel 505-a to which access to channel 505-a-1 is remapped. For example, the portion of the address space corresponding to channel 505-a-1 may be remapped to second interface block 220 such that access to addresses within the remapped portion of the address space may be supported by second interface block 220. In some examples, second interface block 220 may be referred to as a spare interface block 220 (e.g., based on coupling with interface block 245 associated with spare channel 505-a).

[0102] In some examples, the die 240 that includes the channel 505 to which a portion of the address space is remapped (e.g., the channel 505 of the spare die 240) can be located at various locations within the stack 425. In some cases, the spare die 240 can be located at the bottom of the stack 425, which can provide thermal benefits to the other die 240 of the stack 425. For example, due to the high power density associated with the die 205-c-2, the die 240-c located closer to the die 205-c-2 in the z-direction can be relatively hotter than the die 240-c located farther away from the die 205-c-2. By positioning the spare die 240-c closer to the die 205-c-2, the other die 240-c of the stack 425 can be relatively cooler, thereby improving the performance of the nominal configuration, or reducing the possibility of errors that can cause the logic block 230 to perform remapping, or both.

[0103] Figure 5CAn example of a spare diagram 500-c supporting pseudo channel level spare is shown. For example, spare diagram 500-c depicts die 205-c-3 coupled to a group of die 240-c stacked in a certain direction (e.g., z-direction), which die may be an example of stack 425. Errors associated with one or more die 240-c in the group of die 240-c may be detected as described herein. For example, each die 240-c may include a set of channels 505-a, each of which includes a command channel (e.g., bus 301-a and bus 302-a) and a set of data channels (e.g., each data channel includes bus 303-a and bus 304-a), and respective interface blocks 220 and interface blocks 245 may communicate signaling via the command channels and the set of data channels. Each channel 505-a may include a set of pseudo channels 515, each of which may be associated with a respective data interface 330. For example, a command channel of channel 505-a (e.g., associated with control interface 310) may be shared (e.g., common) by a data channel of channel 505-a. That is, command signaling associated with communicating data via each of the data channels of channel 505a may be communicated via the shared command channel. Pseudo-channel 515 may include the respective data channels of channel 505-a and the shared command channel. Figure 5C 205-c-3 may include a respective interface block 220 for each channel 505-a of the set of dies 240-c. Thus, each interface block 220 may be used for (e.g., through which signaling is communicated) a set of pseudo channels 515 included in the corresponding channel 505-a.

[0104] exist Figure 5CIn an example of the present invention, one or more errors associated with one or more pseudo channels 515 may be detected. For example, an error associated with pseudo channel 515-a-1 of die 240-c-5 in the set of dies 240-c may be detected, or an error associated with pseudo channel 515-a-2 of die 240-c-6 in the set of dies 240-c may be detected, or both. Based on the detection of the one or more errors, the logic block 230 of the die 205-c-3 may remap access to the pseudo channel 515-a-1 or 515-a-2 to other pseudo channels 515-a of the set of dies 240-c. For example, logic block 230 may remap access to pseudo-channel 515-a-1 to pseudo-channel 515-a-3 of die 240-c-7 in the set of dies 240-c, or remap access to pseudo-channel 515-a-2 to pseudo-channel 515-a-4 of die 240-c-7, or both. In some examples, the pseudo-channel 515-a to which access is remapped may be included in the same channel set 510-a (e.g., channel set 510-a-2) that includes pseudo-channels 515-a-1 and 515-a-2. In some other examples, logic block 230 may remap access to pseudo-channel 515-a-1 and pseudo-channel 515-a-2 to other pseudo-channels 515-a of die 240-c-7 that are not included in channel set 510-a-2 (e.g., included in another channel set 510-a). In some other examples, in some cases, the die 240-c-5 and / or 240-c-6 may include one or more spare channels 505-a, and the logic block 230 may remap access to the pseudo-channel 515-a-1 and the pseudo-channel 515-a-2 to other pseudo-channels 515-a of the die 240-c-5 and 240-c-6, respectively (e.g., spare pseudo-channels 515-a included in spare channels 505-a). In some examples, the die 240-c-7 may be a spare die in the set of dies 240-c, and the pseudo-channel 515-a of the die 240-c-7 may be the spare channel 515-a.

[0105] In some instances, remapping access from pseudo channels 515-a-1 and 515-a-2 may include remapping access from corresponding data channels of pseudo channels 515-a-1 and 515-a-2 to data channels of pseudo channel 515-a to which pseudo channels 515-a-1 and 515-a-2 are remapped (e.g., pseudo channels 515-a-3 and 515-a-4).

[0106] To support remapping, logic block 230 may remap a portion of the address space available to the host system that corresponds to pseudo channels 515-a-1 and 515-a-2. For example, logic block 230 may remap the portion of the address so that the host system's use of addresses within the portion may instead access pseudo channels 515-a-3 and 515-a-4, respectively (e.g., memory array 250 accessible via pseudo channels 515-a-3 and 515-a-4) or some other pseudo channel 515-a to which logic block 230 remaps access to pseudo channels 515-a-1 and 515-a-2. Due to pseudo channel 515-a sharing a command channel with at least one other pseudo channel 515-a, in some examples, communication of shared command signaling via the remapped pseudo channel 515-a may be coordinated. For example, the logic block 230 may configure the first interface block 220 associated with the pseudo channel 515-a-1 and / or the second interface block 220 associated with the pseudo channel 515-a-3 to communicate shared command signaling via the command channel of the first channel 505-a including the pseudo channel 515-a-1 and the command channel of the second channel 505-a including the pseudo channel 515-a-3. For example, command signaling may continue to be communicated via the command channel of the first channel 505-a using the first interface block 220 associated with communicating data via another pseudo channel 515-a of the first channel 505-a, and command signaling associated with communicating data via the pseudo channel 515-a-1 may instead be communicated via the command channel of the second channel 505-a using the second interface block 220. The logic block 230 may similarly configure a third interface block 220 associated with the pseudo channel 515-a-2 and / or a second interface block 220 associated with the pseudo channel 515-a-4 to communicate shared command signaling via a command channel of the channel 505-a including the pseudo channel 515-a-2 and a command channel of the channel 505-a including the pseudo channel 515-a-4.

[0107] In some examples, the die 240 that includes the pseudo channel 515 to which a portion of the address space is remapped (e.g., the pseudo channel of the spare die 240) can be located at various locations within the stack 425. In some cases, the spare die 240 can be located at the bottom of the stack 425, which can provide thermal benefits to the other die 240 of the stack 425. For example, due to the high power density associated with the die 205-c-3, the die 240-c located closer to the die 205-c-3 in the z-direction can be relatively hotter than the die 240-c located farther away from the die 205-c-3. By positioning the spare die 240-c closer to the die 205-c-3, the other die 240-c of the stack 425 can be relatively cooler, thereby improving the performance of the nominal configuration, or reducing the possibility of errors that can cause the logic block 230 to perform remapping, or both.

[0108] Figure 5D An example of a spare diagram 500-d that supports group-level spares is shown. For example, the spare diagram 500-d depicts a die 205-c-4 coupled to a group of die 240-c stacked along a certain direction (e.g., the z-direction), which die may be an instance of a stack 425. Errors associated with a die 240-c-8 in the group of die 240-c may be detected as described herein. For example, each die 240-c may include one or more channels 505-a, and one or more memory arrays 250 of the die 240-c may be accessed via the one or more channels 505-a. In some examples, the memory array 250 may include one or more groups 520-a, which may be groups of memory cells. In some examples, the memory array 250, or a portion thereof, may be an instance of a group 520-a. In Figure 5D In the example of , die 240-c-8 may include channel 505-a-3 through which one or more groups 520-a may be accessed. For example, channel 505-a-3 may be used to access groups 520-a-1, 520-a-2, 520-a-3, and 520-a-4. Figure 5D In the example, errors associated with group 520-a-2 can be detected.

[0109] Based on the detection of the error, the logic block 230 of the die 205-c-4 may remap access to the group 520-a-2 to another group 520-a of the group of die 240-c. For example, the address space available to the host system may include a portion of the address that can be used by the host system to access the group 520-a-2. The logic block 230 may remap the portion of the address so that the host system's use of the address within the portion can instead access another group 520-a, which can be referred to as a spare group 520-a. For example, the die 240-c-9 in the group of die 240-c may include a channel 505-a-4 (e.g., included in the same channel set 510-a that includes channel 505-a-3) that supports access to groups 520-a-5, 520-a-6, 520-a-7, and 520-a-8. Logic block 230 may remap access from group 520-a-2 to group 520-a-6 or channel 505-a-4 or some other group 520-a of die 240-c-9. Additionally or alternatively, die 240-c-8 may include one or more spare groups 520 (e.g., associated with one or more spare channels 505-a), and logic block 230 may remap access to group 520-a-2 to spare group 520-a of die 240-c-8. In some examples, die 240-c-9 may be a spare die in the group of die 240-c, and the group 520-a of die 240-c-9 may be the spare group 520-a.

[0110] To support remapping of portions of the address space, logic block 230 may remap access to group 520-a-2 from a first interface block 220 of die 205-c-4 associated with channel 505-a-3 to a second interface block 220 of die 205-c-4 associated with channel 505-a-4 or some other channel 505-a, the channel 505-a-4 including group 520-a-6, the some other channel 505-a including group 520-a to which access to group 520-a-2 is remapped. For example, the portion of the address space corresponding to group 520-a-2 may be remapped to the second interface block 220 such that access to addresses within the remapped portion of the address space may be supported by the second interface block 220. In some examples, the second interface block 220 may be referred to as a spare interface block 220 (e.g., based on coupling with an interface block 245 associated with the spare channel 505-a).

[0111] In some examples, the die 240 that includes the group 520 to which a portion of the address space is remapped (e.g., the group 520 of spare die 240) may be located at various locations within the stack 425. In some cases, the spare die 240 may be located at the bottom of the stack 425, which may provide thermal benefits to the other die 240 of the stack 425. For example, due to the high power density associated with die 205-c-4, the die 240-c located closer to the die 205-c-4 in the z-direction may be relatively hotter than the die 240-c located farther away from the die 205-c-4. By positioning the spare die 240-c closer to the die 205-c-4, the other die 240-c of the stack 425 may be relatively cooler, thereby improving the performance of the nominal configuration, or reducing the likelihood of errors that may cause the logic block 230 to perform remapping, or both.

[0112] Figure 6 A block diagram 600 is shown of a system 620 that supports spare techniques in a stacked memory architecture according to examples disclosed herein. The system 620 may be as described in reference Figure 15. System 620 or its various components (e.g., interface block 220, circuitry of interface block 220, interface block 245, circuitry of interface block 245) may be examples of devices for performing various aspects of spare techniques in stacked memory architectures as described herein. For example, system 620 may include evaluation component 625, non-volatile storage component 630, remapping component 635, coupling component 640, or any combination thereof. In some examples, at least a portion of system 620 (e.g., at least a portion of evaluation component 625, at least a portion of non-volatile storage component 630, at least a portion of remapping component 635, or a combination thereof) may be included in a semiconductor system such as system 200. Additionally or alternatively, at least a portion of system 620 (e.g., at least a portion of evaluation component 625, at least a portion of non-volatile storage component 630, at least a portion of remapping component 635, at least a portion of coupling component 640, or a combination thereof) may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. For example, in some cases, one or more operations performed by evaluation component 625, non-volatile storage component 630, coupling component 640, or a combination thereof may be performed by a manufacturing system or one or more controllers associated with a manufacturing system. Each of these components or their subcomponents (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0113] The evaluation component 625 (e.g., of the interface block 220, of the interface block 245, of the logic block 230, of the manufacturing system) may be configured as or otherwise support means for evaluating the functionality of each of the plurality of array dies (e.g., die 240). The non-volatile storage component 630 (e.g., of the interface block 220, of the interface block 245, of the logic block 230, of the manufacturing system) may be configured as or otherwise support means for setting one or more non-volatile storage elements (e.g., of the non-volatile storage device 270) of the plurality of array dies based on the evaluation to indicate an error associated with one or more of the plurality of array dies. The remapping component 635 (e.g., of the interface block 220, of the logic block 230, of the manufacturing system) may be configured as or otherwise support a device for remapping access to the multiple array dies from one or more first memory arrays (e.g., memory array 250, channel 505, pseudo-channel 515, group 520) of the multiple array dies to one or more second memory arrays (e.g., memory array 250, channel 505, pseudo-channel 515, group 520) of the multiple array dies using logic circuits (e.g., of the logic block 230) of a logic die (e.g., die 205) coupled to the multiple array dies based on setting one or more non-volatile storage elements.

[0114] In some examples, coupling component 640 can be configured as or otherwise support means for coupling the plurality of array dies in a stacked form along a certain orientation (eg, in stack 410 ) after evaluating the functionality of each of the plurality of array dies.

[0115] In some examples, coupling component 640 may be configured as or otherwise support means for coupling multiple array dies in a stacked manner along a certain orientation (eg, in stack 410), and the function of evaluating each of the multiple array dies may be performed after the coupling.

[0116] In some examples, coupling component 640 may be configured as or otherwise support a device for coupling multiple array dies and logic dies (e.g., in stack 420, in stack 425), and the function of evaluating each of the multiple array dies may be performed after the coupling.

[0117] In some examples, to support setting one or more nonvolatile storage elements, the nonvolatile storage component 630 may be configured as or otherwise support a device for setting one or more one-time programmable storage elements (e.g., fuses, antifuses, or a combination thereof) of multiple array dies to indicate an error.

[0118] In some instances, to support remapping of access to multiple array dies, the remapping component 635 may be configured as or otherwise support means for remapping access from a first array die of the multiple array dies that includes one or more first memory arrays to a second array die of the multiple array dies that includes one or more second memory arrays.

[0119] In some instances, to support remapping of access to multiple array dies, the remapping component 635 may be configured as or otherwise support a device for remapping access from a first interface (e.g., first interface block 245) of an array die among the multiple array dies to a second interface (e.g., second interface block 245) of the array die, the first interface being associated with accessing one or more first memory arrays, the second interface being associated with accessing one or more second memory arrays.

[0120] In some examples, the logic die includes a plurality of second interfaces (e.g., interface block 220), each of the plurality of second interfaces being associated with a respective plurality of channels (e.g., channel 505, bus 221, bus 246, bus 255, bus 301, bus 302, bus 303, bus 304) for communicating with a respective first interface (e.g., interface block 245) of one of the plurality of array dies, the respective plurality of channels including a command channel (e.g., bus 301) and a plurality of data channels (e.g., bus 303), the plurality of data channels operable to communicate data with at least one memory array corresponding to the respective first interface. In some examples, to support remapping of accesses to the plurality of array dies, the remapping component 635 may be configured as or otherwise support means for remapping accesses from a first data channel associated with one second interface in the respective plurality of channels to a second data channel associated with another second interface in the respective plurality of channels.

[0121] In some examples, each array die in the plurality of array dies includes one or more memory arrays that each include one or more groups of memory cells, such as group 520. In some examples, to support remapping accesses to the plurality of array dies, remapping component 635 can be configured as or otherwise support means for remapping accesses from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

[0122] In some examples, the described functionality of system 620 or its various components may be supported by or may involve at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of system 620 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0123] Figure 7 A block diagram 700 is shown of a logic die 720 supporting spare techniques in a stacked memory architecture according to examples disclosed herein. The logic die 720 may be a Figure 15. Logic die 720 or its various components (e.g., interface block 220, logic block 230) may be examples of devices for performing various aspects of spare techniques in a stacked memory architecture as described herein. For example, logic die 720 (e.g., interface block 220, logic block 230, or a combination thereof) may include error component 725, remapping component 730, access component 735, or any combination thereof. Each of these components or their subcomponents (e.g., one or more processors, one or more memories) may communicate with each other directly or indirectly (e.g., via one or more buses).

[0124] The error component 725 may be configured as or otherwise support means for detecting an error associated with one or more first memory arrays (e.g., memory array 250, channel 505, pseudo channel 515, group 520) of the plurality of array dies (e.g., die 240) by a logic circuit (e.g., logic block 230) of a logic die (e.g., die 205) stacked with the plurality of array dies (e.g., die 240). The remapping component 730 may be configured as or otherwise support means for remapping access to the plurality of array dies from one or more first memory arrays using a first interface (e.g., first interface block 220) of the logic die to one or more second memory arrays (e.g., memory array 250, channel 505, pseudo channel 515, group 520) of the plurality of array dies using a second interface (e.g., second interface block 220) of the logic die based on detecting the error. The access component 735 may be configured as or otherwise support means for accessing the one or more second memory arrays based on the remapping using the second interface

[0125] In some examples, to support detecting errors, error component 725 may be configured as or otherwise support means for accessing non-volatile storage devices associated with one or more first memory arrays (e.g., non-volatile storage device 235, non-volatile storage device 270), wherein one or more non-volatile storage elements of the non-volatile storage devices indicate an error.

[0126] In some examples, to support detecting errors, error component 725 can be configured as or otherwise support means for determining errors associated with one or more first memory arrays based on an attempt to access the one or more first memory arrays using a first interface of the logic die.

[0127] In some instances, to support remapping of access to multiple array dies, the remapping component 730 may be configured as or otherwise support means for remapping access from a first array die of the multiple array dies that includes one or more first memory arrays to a second array die of the multiple array dies that includes one or more second memory arrays.

[0128] In some instances, to support remapping of access to multiple array dies, the remapping component 730 may be configured as or otherwise support a device for remapping access from a third interface (e.g., first interface block 245) of an array die among the multiple array dies to a fourth interface (e.g., second interface block 245) of the array die, the third interface being associated with accessing one or more first memory arrays, and the fourth interface being associated with accessing one or more second memory arrays.

[0129] In some examples, the first interface and the second interface are each associated with a respective plurality of channels (e.g., channels 505) including a command channel (e.g., bus 301) and a plurality of data channels (e.g., bus 303) operable to communicate data with at least one memory array corresponding to the interface. In some examples, remapping access to the plurality of array dies includes remapping access from a first data channel of the respective plurality of channels associated with the first interface to a second data channel of the respective plurality of channels associated with the second interface.

[0130] In some examples, each array die in the plurality of array dies includes one or more memory arrays that each include one or more groups of memory cells, such as group 520. In some examples, remapping access to the plurality of array dies includes remapping access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

[0131] In some examples, the described functionality of logic die 720 or its various components may be supported by or may involve at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of logic die 720 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0132] Figure 8A flowchart illustrating a method 800 for supporting spare techniques in a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 800 may be implemented by a system or components thereof (e.g., die 205, die 240, logic block 230) as described herein. For example, the operations of the method 800 may be implemented by a system or components thereof (e.g., die 205, die 240, logic block 230) as described herein. Figures 1 to 6 The system described in the present invention may perform the functions described. In some examples, the system may execute a set of instructions to control the functional elements of the device to perform the functions described. Additionally or alternatively, the system may use dedicated hardware to perform various aspects of the functions described. In some examples, one or more operations of method 800 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of a manufacturing system to perform the functions described. Additionally or alternatively, one or more controllers may use dedicated hardware to perform various aspects of the functions described.

[0133] At 805, the method may include evaluating the functionality of each of the plurality of array dies. In some examples, aspects of the operations of 805 may be as described with reference to Figure 6 The described evaluation component 625 performs. For example, the respective functions of the dies 240 in the die stack (e.g., in stack 410, in stack 420, in stack 425) can be evaluated. In some examples, aspects of the operations of 805 can be performed by a manufacturing system or one or more controllers associated with a manufacturing system.

[0134] At 810, the method may include, based on the evaluation, setting one or more non-volatile storage elements of the plurality of array dies to indicate an error associated with one or more of the plurality of array dies. In some examples, aspects of the operation of 810 may be as described with reference to Figure 6 The non-volatile storage components 630 described herein are performed. For example, non-volatile storage elements of one or more non-volatile storage devices 270 or non-volatile storage devices 235 may be set (e.g., by interface block 220, by interface block 245, by logic block 230) to indicate an error associated with one or more of the stacked dies 240. In some examples, aspects of the operations of 810 may be performed by a manufacturing system or one or more controllers associated with a manufacturing system.

[0135] At 815, the method may include remapping access to the plurality of array dies from one or more first memory arrays of the plurality of array dies to one or more second memory arrays of the plurality of array dies using logic circuitry of a logic die coupled to the plurality of array dies based on setting the one or more non-volatile storage elements. For example, logic block 230 of die 205 coupled to die 240 may remap access to die 240 from one or more first memory arrays (e.g., memory array 250, channel 505, pseudo-channel 515, group 520) of die 240 to one or more second memory arrays (e.g., memory array 250, channel 505, pseudo-channel 515, group 520) of die 240 based on setting the non-volatile storage elements of one or more non-volatile storage devices 270. In some examples, aspects of the operation of 815 may be described by reference to Figure 6 The described remapping component 635 performs.

[0136] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof. In some examples, one or more of the following aspects may be performed by a manufacturing system, which may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of a manufacturing system), or any combination thereof.

[0137] Aspect 1: A method, apparatus (e.g., a manufacturing system), or non-transitory computer-readable medium comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: evaluating functionality of each of a plurality of array dies; based on the evaluation, setting one or more non-volatile storage elements of the plurality of array dies to indicate an error associated with one or more of the plurality of array dies; and based on setting the one or more non-volatile storage elements, remapping access to the plurality of array dies from one or more first memory arrays of the plurality of array dies to one or more second memory arrays of the plurality of array dies using logic circuitry of a logic die coupled to the plurality of array dies.

[0138] Aspect 2: The method, apparatus (e.g., manufacturing system), or non-transitory computer-readable medium according to Aspect 1, further comprising operations, features, circuits, logic, methods, or instructions, or any combination thereof, for coupling multiple array dies in a stacked manner along a certain direction after evaluating the functionality of each of the multiple array dies.

[0139] Aspect 3: A method, apparatus (e.g., a manufacturing system), or non-transitory computer-readable medium according to any one of Aspects 1 to 2, further comprising operations, features, circuits, logic, devices, or instructions, or any combination thereof, for coupling a plurality of array dies in a stacked manner along a certain direction, wherein a function of evaluating each of the plurality of array dies is performed after the coupling.

[0140] Aspect 4: A method, apparatus (e.g., a manufacturing system), or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuits, logic, devices, or instructions, or any combination thereof, for coupling a plurality of array dies to a logic die, wherein evaluating the function of each of the plurality of array dies is performed after the coupling.

[0141] Aspect 5: A method, apparatus (e.g., a manufacturing system), or non-transitory computer-readable medium according to any one of Aspects 1 to 4, wherein setting one or more non-volatile storage elements includes an operation, feature, circuit, logic, device, or instruction, or any combination thereof, for setting one or more one-time programmable storage elements of a plurality of array dies to indicate an error.

[0142] Aspect 6: A method, apparatus (e.g., a manufacturing system), or non-transitory computer-readable medium according to any one of Aspects 1 to 5, wherein remapping access to multiple array dies includes operations, features, circuits, logic, devices, or instructions, or any combination thereof, for remapping access from a first array die of the multiple array dies that includes one or more first memory arrays to a second array die of the multiple array dies that includes one or more second memory arrays.

[0143] Aspect 7: A method, apparatus (e.g., a manufacturing system), or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein remapping access to multiple array dies includes operations, features, circuits, logic, methods, or instructions, or any combination thereof, for remapping access from a first interface of an array die among the multiple array dies to a second interface of the array die, wherein the first interface is associated with accessing one or more first memory arrays, and the second interface is associated with accessing one or more second memory arrays.

[0144] Aspect 8: A method, an apparatus (e.g., a manufacturing system), or a non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the logic die includes a plurality of second interfaces, each of the plurality of second interfaces being associated with a respective plurality of channels for communicating with a respective first interface of one of a plurality of array dies, the respective plurality of channels including a command channel and a plurality of data channels, the plurality of data channels being operable to communicate data with at least one memory array corresponding to the respective first interface, and remapping access to the plurality of array dies includes remapping access from a first data channel associated with one second interface in the respective plurality of channels to a second data channel associated with another second interface in the respective plurality of channels.

[0145] Aspect 9: A method, an apparatus (e.g., a manufacturing system), or a non-transitory computer-readable medium according to any one of Aspects 1 to 8, wherein each array die of a plurality of array dies includes one or more memory arrays, each of the one or more memory arrays including one or more groups of memory cells, and remapping access to the plurality of array dies includes remapping access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

[0146] Fig. 9 A flowchart illustrating a method 900 for supporting spare techniques in a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 900 may be implemented by a logic die (e.g., die 205) or a component thereof (e.g., interface block 220, logic block 230) as described herein. For example, the operations of the method 900 may be implemented by a logic die (e.g., die 205) or a component thereof (e.g., interface block 220, logic block 230) as described herein. Figure 1 5 and 7 are performed by the logic die described. In some examples, the logic die can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the logic die can use dedicated hardware to perform aspects of the described functions.

[0147] At 905, the method may include detecting, by logic circuitry of a logic die stacked with the plurality of array dies, errors associated with one or more first memory arrays of the plurality of array dies. For example, logic block 230 of die 205 stacked with a group of dies 240 (e.g., in stack 425) may detect errors associated with one or more first memory arrays (e.g., memory array 250, channel 505, dummy channel 515, group 520) of die 240. In some examples, aspects of the operation of 905 may be described with reference to Figure 7 The described error component 725 executes.

[0148] At 910, the method may include remapping, by logic circuitry, access to the plurality of array dies from one or more first memory arrays using a first interface of the logic die to one or more second memory arrays of the plurality of array dies using a second interface of the logic die based on detecting the error. For example, based on detecting the error, logic block 230 may remap access to die 240 from one or more first memory arrays (e.g., memory array 250, channel 505, pseudo channel 515, group 520) using a first interface block 220 of die 205 to one or more second memory arrays (e.g., memory array 250, channel 505, pseudo channel 515, group 520) using a second interface block 220 of die 205. In some examples, aspects of the operation of 910 may be described with reference to Figure 7 The described remapping component 730 performs.

[0149] At 915, the method may include accessing one or more second memory arrays using a second interface based on the remapping. For example, the second interface block 220 may access one or more second memory arrays (e.g., memory array 250, channel 505, pseudo channel 515, group 520) based on the remapping. In some examples, aspects of the operation of 915 may be described as in reference to Figure 7 The described access component 735 performs.

[0150] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0151] Aspect 10: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for performing: detecting, by logic circuitry of a logic die stacked with a plurality of array dies, an error associated with one or more first memory arrays of the plurality of array dies; remapping, by the logic circuitry, access to the plurality of array dies using one or more first memory arrays of a first interface of the logic die to one or more second memory arrays of the plurality of array dies using a second interface of the logic die based on detecting the error; and accessing the one or more second memory arrays using the second interface based on the remapping.

[0152] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to Aspect 10, wherein detecting an error comprises operations, features, circuits, logic, methods, or instructions, or any combination thereof, for accessing a non-volatile storage device associated with one or more first memory arrays, wherein one or more non-volatile storage elements of the non-volatile storage device indicate an error.

[0153] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 10-11, wherein detecting an error comprises operations, features, circuits, logic, means, or instructions, or any combination thereof, for determining an error associated with the one or more first memory arrays based on an attempt to access the one or more first memory arrays using a first interface of the logic die.

[0154] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 10 to 12, wherein remapping access to multiple array dies includes operations, features, circuits, logic, devices, or instructions, or any combination thereof, for remapping access from a first array die of the multiple array dies that includes one or more first memory arrays to a second array die of the multiple array dies that includes one or more second memory arrays.

[0155] Aspect 14: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 10 to 13, wherein remapping access to multiple array dies includes operations, features, circuits, logic, methods, or instructions, or any combination thereof, for remapping access from a third interface of an array die among the multiple array dies to a fourth interface of the array die, wherein the third interface is associated with accessing one or more first memory arrays and the fourth interface is associated with accessing one or more second memory arrays.

[0156] Aspect 15: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 10 to 14, wherein the first interface and the second interface are each associated with a corresponding plurality of channels, the corresponding plurality of channels including a command channel and a plurality of data channels, the plurality of data channels being operable to communicate data with at least one memory array corresponding to the interface, and remapping access to the plurality of array dies includes remapping access from a first data channel associated with the first interface in the corresponding plurality of channels to a second data channel associated with the second interface in the corresponding plurality of channels.

[0157] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 10 to 15, wherein each array die of the plurality of array dies includes one or more memory arrays, the one or more memory arrays each including one or more groups of memory cells, and remapping access to the plurality of array dies includes remapping access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

[0158] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the described methods may be combined.

[0159] A system is described. The following provides an overview of aspects of the apparatus as described herein:

[0160] Aspect 17: A system comprising: a plurality of array dies stacked in a direction, each array die comprising: one or more memory arrays; and one or more first interfaces, each first interface comprising a first circuit, the first circuit being operable to access at least one corresponding memory array of the one or more memory arrays; and a logic die coupled to the plurality of array dies, the logic die comprising: a plurality of second interfaces, each second interface comprising a second circuit, the second circuit being operable to communicate access signaling with corresponding first interfaces of the plurality of array dies to access at least one memory array corresponding to the corresponding first interface; and a logic circuit being operable to remap access to the plurality of array dies from one or more first memory arrays of the plurality of array dies using a first of the plurality of second interfaces to one or more second memory arrays of the plurality of array dies using a second of the plurality of second interfaces based on errors associated with access to the one or more first memory arrays.

[0161] Aspect 18: A system according to Aspect 17, wherein, in order to remap access to multiple array dies, the logic circuit is operable to: remap access from one of the first interfaces of an array die among the multiple array dies to another of the first interfaces of the array die, wherein the one of the first interfaces includes a first circuit operable to access one or more first memory arrays, and the other of the first interfaces includes a first circuit operable to access one or more second memory arrays.

[0162] Aspect 19: A system according to any one of Aspects 17 to 18, wherein, in order to remap access to multiple array dies, the logic circuit is operable to: remap access from a first array die among the multiple array dies that includes one or more first memory arrays to a second array die among the multiple array dies that includes one or more second memory arrays.

[0163] Aspect 20: A system according to any one of Aspects 17 to 19, wherein, in order to remap access to the multiple array dies, the logic circuit is operable to: remap access from all first interfaces of a first array die among the multiple array dies to corresponding first interfaces of a second array die among the multiple array dies.

[0164] Aspect 21: A system according to any one of Aspects 17 to 20, wherein: each second interface is associated with a corresponding plurality of channels for communicating with the corresponding first interface, the corresponding plurality of channels including a command channel and a plurality of data channels, the plurality of data channels being operable to communicate data with at least one memory array corresponding to the corresponding first interface; and in order to remap access to a plurality of array dies, the logic circuit is operable to remap access from a first data channel associated with one second interface in the corresponding plurality of channels to a second data channel associated with another second interface in the corresponding plurality of channels.

[0165] Aspect 22: The system of aspect 21, wherein the logic circuit is further operable to: configure one second interface, another second interface, or both to communicate shared command signaling via a command channel associated with the one second interface and via a command channel associated with the another second interface.

[0166] Aspect 23: A system according to any one of Aspects 17 to 22, wherein: each of the one or more memory arrays includes one or more groups of memory cells; and in order to remap access to multiple array dies, the logic circuit is operable to remap access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

[0167] Aspect 24: A system according to any one of Aspects 17 to 23, wherein the logic circuit is further operable to: identify errors associated with access to one or more first memory arrays based on accessing a non-volatile storage device of an array die that includes the one or more first memory arrays; and remap access to multiple array dies from the one or more first memory arrays to one or more second memory arrays based on the identification.

[0168] Aspect 25: A system according to any one of Aspects 17 to 24, wherein the logic circuit is further operable to: identify errors associated with access to one or more first memory arrays based on accessing a non-volatile storage device of an array die that includes one or more second memory arrays; and remap access to multiple array dies from the one or more first memory arrays to the one or more second memory arrays based on the identification.

[0169] Aspect 26: A system according to any one of Aspects 17 to 25, wherein the logic circuit is further operable to: determine an error associated with access to the one or more first memory arrays based on an attempt to access the one or more first memory arrays by one of the plurality of second interfaces; and remap access to the plurality of array dies from the one or more first memory arrays to the one or more second memory arrays based on the determination.

[0170] Aspect 27: The system of aspect 26, wherein the logic circuit is further operable to: store the indication of the determined error in a non-volatile storage device in one or more of the logic die, the array die, or a combination thereof.

[0171] Aspect 28: The system of any one of Aspects 17 to 27, wherein, to remap access to the plurality of array dies, the logic circuit is operable to: remap a portion of an address space accessible to the host system from the one or more first memory arrays to the one or more second memory arrays.

[0172] Aspect 29: The system of any of Aspects 17 to 28, wherein one or more second memory arrays are included in an array die of a plurality of array dies that is located closest to the logic die.

[0173] Aspect 30: The system of any one of aspects 17 to 29, wherein the one or more second memory arrays are included in an array die of a plurality of array dies, other array dies of the plurality of array dies being stacked on the array die.

[0174] A system is described. The following provides an overview of aspects of the apparatus as described herein:

[0175] Aspect 31: A system comprising: a plurality of array dies stacked in a direction, each array die comprising one or more memory arrays and non-volatile storage devices; and a logic die coupled to the plurality of array dies, the logic die comprising: a plurality of interfaces comprising circuits operable to convey access signaling to access the memory arrays of the plurality of array dies; and a logic circuit coupled to the plurality of interfaces and operable to: identify errors associated with one or more first memory arrays of the plurality of array dies based on accessing the non-volatile storage devices of one or more of the plurality of array dies; and based on identifying the errors, remap access from one or more first memory arrays using a first interface of the plurality of interfaces to one or more second memory arrays of the plurality of array dies using a second interface of the plurality of interfaces.

[0176] A system is described. The following provides an overview of aspects of the apparatus as described herein:

[0177] Aspect 32: A system comprising: a plurality of array dies stacked in a direction, each array die comprising one or more memory arrays; and a logic die coupled to the plurality of array dies, the logic die comprising: a plurality of interfaces comprising circuits operable to communicate access signaling to access the memory arrays of the plurality of array dies; and a logic circuit coupled to the plurality of interfaces and operable to: detect an error based on an attempt to access one or more first memory arrays of the plurality of array dies using a first interface of the plurality of interfaces; and based on detecting the error, remap access to the plurality of array dies from the one or more first memory arrays using the first interface to one or more second memory arrays of the plurality of array dies using a second interface of the plurality of interfaces.

[0178] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols of the signaling that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0179] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (e.g., in conductive contact with each other, connected to each other, coupled to each other) if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication with each other (e.g., in conductive contact with each other, connected to each other, coupled to each other) may be an open circuit or a closed circuit based on the operation of the device including the connected components. The conductive path between the connected components may be a direct conductive path between the components, or may be an indirect conductive path including an intermediate component (e.g., a switch, transistor, or other component). In some examples, one or more intermediate components such as a switch or transistor may be used, for example, to interrupt the flow of signals between the connected components for a period of time.

[0180] The term "isolation" may refer to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, the components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a component isolates two components, the component may initiate a change that blocks a signal from flowing between other components using a conductive path that previously permitted the signal to flow.

[0181] The term "coupled" (e.g., "electrically coupled") may refer to a condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components (e.g., via conductive paths), to a closed circuit relationship between components in which signals are able to communicate between components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component may initiate a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0182] The descriptions set forth herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0183] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label to distinguish among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the additional reference label.

[0184] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuit processing circuits, logic circuits), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed so that portions of the functions are implemented at different physical locations.

[0185] The illustrative blocks and modules described herein may be implemented or executed with one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0186] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0187] As used herein, the articles "a" and "an" preceding nouns, including in the claims, are open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "a", "at least one", "one or more", "at least one of one or more..." may be interchangeable. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions may be performed by a single component or by any combination of multiple components. Therefore, the term "component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. Subsequent references to components introduced with the article "a" using the term "the" or "said" may relate to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and subsequent references to "the component" in the claims may be understood to be equivalent to references to "at least one of the one or more components". Similarly, subsequent reference to a component introduced as "one or more components" using the term "the" or "said" may refer to any or all of the one or more components. For example, a subsequent reference to "the one or more components" in a claim may be understood to be equivalent to a reference to "at least one of the one or more components."

[0188] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a computer, or a combination of multiple media. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage, or any other non-transitory media or combination of media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer or processor.

[0189] The description and drawings are provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor system, comprising: A plurality of array dies are stacked in a certain direction, each array die comprising: one or more memory arrays; and one or more first interfaces, each first interface comprising a first circuit operable to access at least one corresponding memory array of the one or more memory arrays; and a logic die coupled to the plurality of array dies, the logic die comprising: a plurality of second interfaces, each second interface comprising a second circuit operable to communicate access signaling with a corresponding first interface of the plurality of array dies to access the at least one memory array corresponding to the corresponding first interface; and Logic circuitry operable to remap access to the one or more first memory arrays of the plurality of array dies using a first one of the plurality of second interfaces to access to the one or more second memory arrays of the plurality of array dies using a second one of the plurality of second interfaces based on an error associated with access to the one or more first memory arrays of the plurality of array dies.

2. The semiconductor system according to claim 1, wherein: To remap access to the plurality of array dies, the logic circuitry is operable to: Remapping access from one of the first interfaces of an array die among the plurality of array dies, the one of the first interfaces including the first circuitry operable to access the one or more first memory arrays, to another of the first interfaces of the array die, the another of the first interfaces including the first circuitry operable to access the one or more second memory arrays.

3. The semiconductor system according to claim 1, wherein: To remap access to the plurality of array dies, the logic circuitry is operable to: Accesses are remapped from a first array die of the plurality of array dies including the one or more first memory arrays to a second array die of the plurality of array dies including the one or more second memory arrays.

4. The semiconductor system according to claim 1, wherein: To remap access to the plurality of array dies, the logic circuitry is operable to: Accesses are remapped from all of the first interfaces of a first array die of the plurality of array dies to corresponding first interfaces of a second array die of the plurality of array dies.

5. The semiconductor system according to claim 1, wherein: each second interface being associated with a respective plurality of channels for communicating with the respective first interface, the respective plurality of channels comprising a command channel and a plurality of data channels operable to communicate data with the at least one memory array corresponding to the respective first interface; and To remap access to the plurality of array dies, the logic circuitry is operable to remap access from a first data channel of the respective plurality of channels associated with one second interface to a second data channel of the respective plurality of channels associated with another second interface.

6. The semiconductor system of claim 5, wherein the logic circuit is further operable to: The one second interface, the other second interface, or both are configured to communicate shared command signaling via the command channel associated with the one second interface and via the command channel associated with the other second interface.

7. The semiconductor system of claim 1, wherein: Each of the one or more memory arrays includes one or more groups of memory cells; and To remap access to the plurality of array dies, the logic circuitry is operable to remap access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

8. The semiconductor system of claim 1 , wherein the logic circuit is further operable to: identifying the error associated with access to the one or more first memory arrays based on accessing a non-volatile storage device of an array die that includes the one or more first memory arrays; and The access to the plurality of array dies is remapped from the one or more first memory arrays to the one or more second memory arrays based on the identifying.

9. The semiconductor system of claim 1 , wherein the logic circuit is further operable to: identifying the error associated with access to the one or more first memory arrays based on accessing a non-volatile storage device of an array die including the one or more second memory arrays; and The access to the plurality of array dies is remapped from the one or more first memory arrays to the one or more second memory arrays based on the identifying.

10. The semiconductor system of claim 1, wherein the logic circuit is further operable to: determining the error associated with access to the one or more first memory arrays based on an attempt to access the one or more first memory arrays by one of the plurality of second interfaces; and The access to the plurality of array dies is remapped from the one or more first memory arrays to the one or more second memory arrays based on the determination.

11. The semiconductor system of claim 10, wherein the logic circuit is further operable to: An indication of the determined error is stored in a non-volatile storage device in one or more of the logic die, the array die, or a combination thereof.

12. The semiconductor system according to claim 1, wherein: To remap the access to the plurality of array dies, the logic circuitry is operable to: A portion of an address space accessible to a host system is remapped from the one or more first memory arrays to the one or more second memory arrays.

13. The semiconductor system of claim 1, wherein the one or more second memory arrays are included in an array die among the plurality of array dies that is located closest to the logic die.

14. The semiconductor system of claim 1, wherein the one or more second memory arrays are included in an array die of the plurality of array dies, other array dies of the plurality of array dies being stacked on the array die.

15. A method for memory operation, comprising: evaluating functionality of each of the plurality of array dies; based on the evaluating, setting one or more non-volatile storage elements of the plurality of array dies to indicate an error associated with one or more of the plurality of array dies; and Based on setting the one or more non-volatile storage elements, access to the plurality of array dies is remapped from one or more first memory arrays of the plurality of array dies to one or more second memory arrays of the plurality of array dies using logic circuitry of a logic die coupled to the plurality of array dies.

16. The method according to claim 15, further comprising: After evaluating the function of each of the plurality of array dies, the plurality of array dies are coupled in a stacking manner along a certain direction.

17. The method according to claim 15, further comprising: The plurality of array dies are coupled in a stacked manner along a direction, wherein the function of evaluating each of the plurality of array dies is performed after the coupling.

18. The method of claim 15, further comprising: The plurality of array dies and the logic die are coupled, wherein evaluating the functionality of each of the plurality of array dies is performed after the coupling.

19. The method of claim 15, wherein providing the one or more non-volatile storage elements comprises: One or more one-time programmable storage elements of the plurality of array dies are set to indicate the error.

20. The method of claim 15, wherein remapping access to the plurality of array dies comprises: Accesses are remapped from a first array die of the plurality of array dies including the one or more first memory arrays to a second array die of the plurality of array dies including the one or more second memory arrays.

21. The method of claim 15, wherein remapping access to the plurality of array dies comprises: Access is remapped from a first interface of an array die of the plurality of array dies, the first interface being associated with accessing the one or more first memory arrays, to a second interface of the array die, the second interface being associated with accessing the one or more second memory arrays.

22. The method of claim 15, wherein: the logic die comprising a plurality of second interfaces, the plurality of second interfaces each being associated with a respective plurality of channels for communicating with a respective first interface of one of the plurality of array dies, the respective plurality of channels comprising a command channel and a plurality of data channels operable to communicate data with at least one memory array corresponding to the respective first interface; and Remapping access to the plurality of array dies includes remapping access from a first data channel of the corresponding plurality of channels associated with one second interface to a second data channel of the corresponding plurality of channels associated with another second interface.

23. The method of claim 15, wherein: Each array die of the plurality of array dies includes one or more memory arrays each including one or more groups of memory cells; and Remapping access to the plurality of array dies includes remapping access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

24. A semiconductor system comprising: A plurality of array dies stacked in a certain direction, each array die comprising one or more memory arrays and non-volatile storage devices; and a logic die coupled to the plurality of array dies, the logic die comprising: a plurality of interfaces comprising circuitry operable to communicate access signaling to access memory arrays of the plurality of array dies; and a logic circuit coupled to the plurality of interfaces and operable to: identifying errors associated with one or more first memory arrays of the plurality of array dies based on accessing the non-volatile storage device of one or more of the plurality of array dies; and Based on identifying the error, access is remapped from the one or more first memory arrays using a first interface of the plurality of interfaces to one or more second memory arrays of the plurality of array dies using a second interface of the plurality of interfaces.

25. A method for memory operation, comprising: detecting, by logic circuitry of a logic die stacked with a plurality of array dies, errors associated with one or more first memory arrays of the plurality of array dies; remapping, by the logic circuit, access to the plurality of array dies from the one or more first memory arrays using a first interface of the logic die to one or more second memory arrays of the plurality of array dies using a second interface of the logic die based on detecting the error; and Based on the remapping, the one or more second memory arrays are accessed using the second interface.

26. The method of claim 25, wherein detecting the error comprises: A nonvolatile storage device associated with the one or more first memory arrays is accessed, wherein one or more nonvolatile storage elements of the nonvolatile storage device indicate the error.

27. The method of claim 25, wherein detecting the error comprises: The error associated with the one or more first memory arrays is determined based on an attempt to access the one or more first memory arrays using the first interface of the logic die.

28. The method of claim 25, wherein remapping access to the plurality of array dies comprises: Accesses are remapped from a first array die of the plurality of array dies including the one or more first memory arrays to a second array die of the plurality of array dies including the one or more second memory arrays.

29. The method of claim 25, wherein remapping access to the plurality of array dies comprises: Access is remapped from a third interface of an array die of the plurality of array dies, the third interface being associated with accessing the one or more first memory arrays, to a fourth interface of the array die, the third interface being associated with accessing the one or more second memory arrays.

30. The method of claim 25, wherein: the first interface and the second interface are each associated with a respective plurality of channels, the respective plurality of channels comprising a command channel and a plurality of data channels operable to communicate data with at least one memory array corresponding to the interface; and Remapping access to the plurality of array dies includes remapping access from a first data channel of the corresponding plurality of channels associated with the first interface to a second data channel of the corresponding plurality of channels associated with the second interface.

31. The method of claim 25, wherein: Each array die of the plurality of array dies includes one or more memory arrays each including one or more groups of memory cells; and Remapping access to the plurality of array dies includes remapping access from one or more first groups included in the one or more first memory arrays to one or more second groups included in the one or more second memory arrays.

32. A semiconductor system comprising: A plurality of array dies stacked in a certain direction, each array die comprising one or more memory arrays; and a logic die coupled to the plurality of array dies, the logic die comprising: a plurality of interfaces comprising circuitry operable to communicate access signaling to access memory arrays of the plurality of array dies; and a logic circuit coupled to the plurality of interfaces and operable to: detecting an error based on an attempt to access one or more first memory arrays of the plurality of array dies using a first interface of the plurality of interfaces; and Based on detecting the error, access to the plurality of array dies is remapped from the one or more first memory arrays using the first interface to one or more second memory arrays of the plurality of array dies using a second interface of the plurality of interfaces.

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