Chip manufacturing quality detection and control method

Abstract

The invention discloses a chip manufacturing quality detection and control method, and belongs to the field of chip manufacturing. According to the scheme, by combining multiple detection methods, effective monitoring of the chip manufacturing quality is achieved, firstly, a data collecting and processing system is established, chip production data are automatically collected, and the reject ratio and the number of times are counted; and then setting a threshold value, and automatically generating a quality report when the threshold value reaches the standard. And meanwhile, a feedback warning mechanism and a processing tracking system are arranged. In a chip packaging process, low and good batches are screened through a final test, and process problems are analyzed by combining a substrate and test information. For LED chip production, after process data are obtained, the process yield is calculated through a chip process detection model, so that the product grade is determined, and electrical detection is carried out. Through combination of multiple detection methods, real-time feedback regulation and control can be performed on the substandard chip manufacturing process, the production efficiency and the qualified rate of chip manufacturing are remarkably improved, and the chip manufacturing quality is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing data processing, and in particular to a chip manufacturing quality detection and control method, electronic equipment and a readable storage medium. Background Art

[0002] Quality management is a crucial link in the semiconductor manufacturing process. With the rapid development of advanced packaging technology, the introduction of various new materials and new processes has increased the complexity of chip manufacturing, which has also led to more diverse sources of quality problems. The diversification of process integration and product specifications has further aggravated the difficulty of monitoring quality problems. Traditional quality management methods mainly rely on manual and empirical rules. However, this method can no longer meet the needs of modern semiconductor manufacturing.

[0003] Especially in the LCD manufacturing process, there are many factors that affect the quality of the finished product. Different sites, equipment, and process technology may have a significant impact on the final quality results. The main difficulties faced by quality inspection and control in this field include: the amount of data is huge and cumbersome, which is not easy to analyze and model efficiently; quality problems usually have a lag, and are often discovered only after the problem occurs and causes certain consequences. At this time, improving the relevant process parameters may have caused a lot of waste; in addition, although the categories of product quality problems are relatively small, once a problem occurs, the consequences are often very serious, so it is urgent to strictly control it. In summary, the quality management issues in conductor manufacturing and LCD processes need to be solved urgently. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a chip manufacturing quality detection and control method, an electronic device and a readable storage medium, which can detect quality problems more quickly, improve the efficiency of quality problem correction, reduce resource and cost waste, and improve yield.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A chip manufacturing quality detection and control method, characterized in that it includes the following steps:

[0007] S1: Establish a data collection and processing system to automatically collect chip production data from each site in real time, and perform statistics on defect rate and number of defect occurrences;

[0008] S2: Set multi-level defect rate thresholds and defect occurrence thresholds. When the thresholds are reached, use the neural network model to predict and classify quality problems and automatically generate quality problem reports;

[0009] S3: Equipped with quality problem feedback and warning mechanism, the development trend of quality problems is analyzed in real time through the neural network model, and corresponding alarms and warnings are triggered;

[0010] S4: Provide a quality problem processing tracking system, record processing information, calculate response time and processing time, and use neural network models to predict and optimize processing efficiency;

[0011] S5: Carry out final testing on the chip packaging process, screen out low-quality batches, combine substrate coordinates and test information, and use a neural network model to analyze packaging process problems;

[0012] S6: In LED chip production, obtain the process data of each device node, calculate the process yield through the chip process detection model combined with the neural network model, determine the product grade, and perform electrical testing.

[0013] Furthermore, in step S1,

[0014] Build a data collection and processing system to sense various physical parameters and status information in the chip production process in real time through sensors. The intelligent controller is responsible for coordinating the data collection rhythm and preliminary processing, and stably transmits the collected data to the data storage module;

[0015] The defect rate statistics are collected for each site data, and the time weighting factor is introduced to give different weights to the data at different time points.

[0016] where t i is the data collection time point, ω(t i ) is the weight function at the corresponding time point;

[0017] The data is analyzed again in combination with the anomaly detection model of deep learning. The anomaly detection model adopts the convolutional neural network (CNN) architecture. Its convolution layer extracts local features of the data through convolution kernels of different sizes, the pooling layer performs downsampling to reduce the amount of calculation, and the fully connected layer integrates and classifies the features. The loss function adopts the cross entropy function:

[0018]

[0019] where y i is the true label, To predict the label, N is the number of samples, and the network parameters are continuously adjusted through the back-propagation algorithm so that the model can accurately identify abnormal data points.

[0020] Furthermore, in step S2:

[0021] Set up a multi-level defect rate threshold and defect occurrence threshold system, analyze historical production data through deep neural network, use a combination of autoencoder and clustering algorithm to mine the inherent laws of the data, and determine the threshold ranges of different levels;

[0022] When the defect rate is greater than or equal to the set threshold, a quality problem report is automatically generated. The report content includes the severity of the problem, possible causes and related data statistics;

[0023] In the report generation process, a text generation model based on a recurrent neural network (RNN) is used. Its hidden layer saves historical information through memory units and generates a quality problem report described in natural language based on the input problem feature vector and the current hidden state. The formula is:

[0024] h t =tanh(W hh h t-1 +W xh x t +b h )

[0025] y t =W hy h t +b y

[0026] where h t is the current hidden state, h t-1 is the hidden state at the previous moment, x t is the current input feature vector, W hh , W xh , W hy is the weight matrix, b h 、b y is the bias vector, y t The generated text output.

[0027] Furthermore, in step S3, the quality problem feedback and warning mechanism includes:

[0028] Intelligent alarms are equipped for lines with quality problems. The alarm lights light up in different colors according to the severity and type of the quality problems sent by the central control system. The counter communicates with the central control system in real time, accumulates the number of quality problems, and stores and uploads the data.

[0029] For the priority sorting of quality issues, a sorting model based on the long short-term memory network (LSTM) is adopted. The quality issue feature vector is input, and the priority score is calculated through the LSTM unit gating mechanism, and the issues are sorted according to the score.

[0030] Furthermore, in step S4, the quality problem handling tracking system includes:

[0031] Set up a user input interface on the production site terminal device or mobile application;

[0032] The processing personnel input the processing start time, the central control system calculates the processing response time and displays the processing information in real time on the engineering TV board through the data synchronization module and WebSocket technology;

[0033] After the processing is completed, the processing completion information is input, and the central control system calculates the processing time and stores the processing data;

[0034] Analyze processing efficiency and generate reports using data analysis algorithms and report generation tools;

[0035] A neural network-based time series prediction model is introduced to evaluate processing efficiency; the time series prediction model includes a hybrid model of MLP and LSTM;

[0036] A deep Q network model (DQN) based on reinforcement learning is used to simulate and predict the processing process, and the optimal processing strategy is found through training.

[0037] Furthermore, in step S5, the quality problem handling tracking system includes:

[0038] After chip packaging, the final test is carried out to screen out low-quality batches according to the chip failure rate formula; the substrate coordinates of low-quality batch chips are determined, and sets are built in the X and Y directions according to the substrate coordinates and the pass rate is calculated;

[0039] A CNN-based regression model is used to train historical data to predict the current batch pass rate, and the Adam optimizer is used for training;

[0040] Calculate the average pass rate and deviation value of the corresponding set of substrates within the preset time, and use the ensemble learning method to determine the threshold to judge the low-quality problems;

[0041] Calculate the average pass rate of the X and Y directions to determine the process type;

[0042] in P Ai A is the X-direction set i The pass rate of the chip in Bi is the Y direction set B i The passing rate of the chips;

[0043] The problem is diagnosed using a neural network model based on the attention mechanism, and the process is optimized using an optimization model based on a generative adversarial network (GAN); the optimization model is:

[0044]

[0045] Where G is the generator, D is the discriminator, x is the real process data, z is random noise, p date(x) is the actual data distribution, p z (z) is the noise distribution and E is the expectation operator.

[0046] Further, in step S6,

[0047] Install high-precision sensors, industrial cameras and spectrum analyzer acquisition devices at multiple equipment nodes in LED chip production to obtain chip process data and three-dimensional morphology detection images; the chip process data includes wafer size accuracy;

[0048] Clean, normalize and standardize the chip process parameters and extract key features. Pre-process the 3D shape detection images using wavelet transform denoising, histogram equalization enhancement, threshold segmentation or deep learning semantic segmentation methods.

[0049] Use decision tree, random forest or support vector machine machine learning classification model to determine whether the process segment corresponding to the device node is an image detection process segment;

[0050] For the image detection process, the 3D shape detection image and chip process parameters are fused using a multimodal data fusion algorithm based on an attention mechanism, and then input into a chip process detection model based on a CNN and RNN hybrid model.

[0051] The input layer of the chip process detection model further processes and extracts features from the fused data. The hidden layer learns nonlinear relationships through the fully connected layer and activation function. The output layer uses the softmax function to calculate the process yield of the device node and output it.

[0052] The adversarial training mechanism is used to introduce GAN to improve the robustness and generalization ability of the model; based on the weight data and process yield of each device node, the process pass rate of the target LED chip is calculated.

[0053] Correspondingly, an electronic device includes a processor and a memory, wherein the processor is used to execute the above-mentioned chip manufacturing quality detection and control method, and the memory is used to store programs and data required to execute the method.

[0054] Correspondingly, a computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the above-mentioned chip manufacturing quality detection and control method.

[0055] Compared with the prior art, the present invention has at least the following beneficial effects:

[0056] This solution integrates deep learning models and big data technology, uses a variety of neural network models to automatically analyze defect characteristics, and uses deep learning models combined with statistical methods to determine chip process problems, significantly improving analysis efficiency and accuracy. It can also provide timely feedback and adjustment suggestions for the production line, reduce manual intervention, and enhance the scientificity and timeliness of quality control.

[0057] With the help of neural network models, quality problems are monitored in real time, reports are automatically generated and alarm warning mechanisms are introduced. Combined with the processing tracking system, the process is automatically planned, which effectively solves the problems of difficult quality problem tracking and low processing efficiency, and ensures the efficiency and stability of the production process.

[0058] In the chip packaging stage, neural network algorithms are used to monitor processing efficiency and optimize the process. In the packaging and testing stage, specific chip detection models are used in combination with statistical methods to calculate process yield, determine grades and test performance, reduce defective rates and improve quality. Machine learning models are used to provide decision-making guidance in multiple fields, which is widely used to enhance corporate competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a flow chart of an embodiment of the present invention;

[0060] Figure 2 is a diagram of an electronic device provided by an embodiment of the present invention; DETAILED DESCRIPTION

[0061] The present invention is further described in detail below with reference to the accompanying drawings and specific examples. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the present invention. The above is only a description of the preferred embodiment of the present invention, and is not any limitation of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

[0062] like Figure 1 As shown, the present invention provides a chip manufacturing quality detection and control method, comprising:

[0063] S1: Establish a data collection and processing system to automatically collect chip production data from each site in real time, and perform statistics on defect rate and number of defect occurrences;

[0064] S2: Set multi-level defect rate thresholds and defect occurrence thresholds. When the thresholds are reached, use the neural network model to predict and classify quality problems and automatically generate quality problem reports;

[0065] S3: Equipped with quality problem feedback and warning mechanism, the development trend of quality problems is analyzed in real time through the neural network model, and corresponding alarms and warnings are triggered;

[0066] S4: Provide a quality problem processing tracking system, record processing information, calculate response time and processing time, and use neural network models to predict and optimize processing efficiency;

[0067] S5: Carry out final testing on the chip packaging process, screen out low-quality batches, combine substrate coordinates and test information, and use a neural network model to analyze packaging process problems;

[0068] S6: In LED chip production, obtain the process data of each device node, calculate the process yield through the chip process detection model combined with the neural network model, determine the product grade, and perform electrical testing.

[0069] In step S1, when constructing the data acquisition and processing system, high-precision sensors are deployed at each chip production site. The sensors can keenly sense various physical parameters and status information in the chip production process, such as temperature, pressure, humidity, equipment operating current and voltage, etc., as well as key characteristic data of the chip at different process stages. The intelligent controller coordinates the data collection rhythm according to the preset time interval and data importance level, and performs preliminary screening and sorting of the collected data. Through a high-speed and stable network transmission channel, such as a low-latency industrial Ethernet or a 5G private network, the data is safely and reliably transmitted to the data storage module, which adopts a distributed storage architecture to ensure massive storage and fast reading and writing of data.

[0070] In this embodiment, in the defect rate statistics link, one hour is used as a statistical cycle, and the data of each site is calculated. The time weighting factor ω(t) is introduced. Assuming that in the early stage of production, in order to pay more attention to the impact of recent data on the defect rate, ω(t i )=1+0.1×(i-1)(i is the serial number of the data collection time point). As production progresses, the weight function can be dynamically adjusted according to the stability of the data and the maturity of the production process. At the same time, the data is analyzed again in combination with the anomaly detection model of deep learning. The anomaly detection model adopts a convolutional neural network (CNN) architecture. Its convolution layer is configured with convolution kernels of different sizes such as 3x3 and 5x5 to fully extract the local features of the data. The pooling layer uses maximum pooling or average pooling operations for downsampling to effectively reduce the amount of calculation. The fully connected layer deeply integrates and classifies the features. During the model training process, a large amount of historical production data is collected and divided into training set, validation set and test set in a ratio of 7:2:1. The stochastic gradient descent (SGD) algorithm is combined with the momentum optimizer to continuously adjust the network parameters so that the model can accurately identify abnormal data points and ensure the accuracy of defect rate statistics.

[0071] In step S2, when setting a multi-level defect rate threshold and a defect occurrence threshold system, the autoencoder is used to reduce the dimension and extract features of the data, and the high-dimensional and complex data is mapped to a low-dimensional space, and then combined with a clustering algorithm (such as K-Means clustering), the data is divided into different clusters according to the distribution law and feature similarity of the data, and then the threshold ranges of different levels are determined. For example, for the defect rate threshold, it is divided into multiple levels such as 3%, 6%, 10%, 15% after analysis, and the defect occurrence threshold is set to 1 time, 3 times, 5 times, etc. according to the severity and frequency of the defect type.

[0072] In this embodiment, when the defect rate is greater than or equal to the set threshold, the quality problem report generation process is automatically triggered. In the report generation process, the text generation model based on the recurrent neural network (RNN) plays a key role. Its hidden layer saves historical information through memory units. After receiving the problem feature vector, it generates a quality problem report described in natural language based on the input problem feature vector and the current hidden state. For example, when it is detected that the chip defect rate of a certain site reaches 10%, the model will comprehensively analyze the relevant data, such as the product model involved, the production time period, and the process links that may be affected, and generate a report content similar to "the [product model] chip produced in [specific time period] has a high defect rate problem at [site name], and the possible reason is [list several potential reasons], and the number of defects is [specific number], accounting for 10% of the total production quantity, which needs to be paid attention to and investigated in time." Provide a detailed reference for subsequent problem handling.

[0073] In step S3, the line with quality problems is equipped with an intelligent alarm. When the central control system receives the quality problem signal, it sends a control signal to the alarm according to the severity and type of the quality problem based on the pre-set rules. For example, if the defective rate exceeds 15% and involves key process links, the alarm light will light up red; if the defective rate is between 10%-15%, the alarm light will be yellow; if the defective rate is between 3%-10%, the alarm light will be green. The counter maintains real-time communication with the central control system. Whenever a new quality problem occurs, the number of quality problems of the line is quickly accumulated, and the data is stored in the local cache and uploaded to the remote server for subsequent data analysis and statistics.

[0074] In this embodiment, in terms of the priority sorting of quality problems, a sorting model based on a long short-term memory network (LSTM) is adopted. The model inputs the characteristic vector of the quality problem, including the type of problem (such as electrical performance problems, physical structure defects, etc.), severity (measured by defective rate or number of defective occurrences), frequency of occurrence, scope of impact (number of product batches or equipment involved), etc. Through the gating mechanism of the LSTM unit, information is selectively retained and updated to calculate the priority score. For example, for a problem that affects multiple batches of products and the defective rate continues to rise, its priority score will be higher, ensuring that key issues can be dealt with first, effectively improving the pertinence and efficiency of problem handling.

[0075] In step S4, a user-friendly input interface is set on the production site terminal device (such as an industrial tablet) or mobile application. When the processing personnel arrive at the problem site and are ready to deal with the quality problem, they can conveniently enter the processing start time through the input interface. The central control system uses the timestamp recording function to obtain the time, and combines it with the time when the quality problem is generated to accurately calculate the processing response time. At the same time, the system uses efficient data synchronization modules and WebSocket technology to display the processing information (such as processing personnel information, current processing steps, measures taken, etc.) in real time on the engineering TV board, ensuring that engineering personnel can understand the progress of problem handling in real time.

[0076] In this embodiment, after the processing is completed, the processing personnel promptly input the processing completion information, the central control system quickly calculates the processing time, and stores all the data in the processing process (including response time, processing time, processing steps, tools and materials used, problems encountered and solutions, etc.) in a relational database. Using powerful data analysis algorithms (such as trend prediction algorithms based on time series analysis) and professional report generation tools (such as JasperReports), a comprehensive statistical analysis of the processing efficiency is performed to generate a detailed report containing the average response time, average processing time, comparison of different types of problem processing efficiency, and the trend of processing efficiency over time. In the process of processing efficiency evaluation, a time series prediction model based on a neural network is introduced, such as a hybrid model combining a multi-layer perceptron (MLP) and LSTM. Input historical processing efficiency data, problem type, processing personnel experience level and other information, the MLP layer extracts and transforms the input data, and the LSTM layer models the time series information, predicts future processing efficiency, and provides strong data support for the adjustment of production plans and the rational allocation of resources. In addition, a deep Q network (DQN) model based on reinforcement learning is used to simulate and predict the processing process. The processing process is regarded as a Markov decision process. The state space covers various information in the processing process, such as the current processing step, the elapsed time, the change of the problem state, etc. The action space is the possible processing operations (such as changing equipment, adjusting process parameters, adopting new detection methods, etc.). The optimal processing strategy is found through the intelligent agent to further optimize the problem processing process.

[0077] In step S5, after the chip is packaged, it is immediately sent to the final test stage equipped with test instruments and automated test processes. The test instruments strictly follow international standards and internal corporate specifications to conduct comprehensive performance tests on the chip, including precise electrical parameter tests (such as voltage accuracy up to ±0.01V, current accuracy up to ±0.001A, and resistance accuracy up to

[0078] ±0.1Ω, capacitance accuracy can reach ±0.01pF, etc.), functional testing (such as the integrity of logical functions, accuracy and stability of signal transmission, etc.) and reliability testing (such as temperature cycle testing from -40℃ to 125℃, 1000 hours of testing in an environment with 85% humidity, etc.), and record the performance data of the chip in each test in detail. According to the chip failure rate formula (chip failure rate = (number of failed chips / total number of test chips) × 100%), the chip failure rate is greater than or equal to the preset failure threshold (through statistical analysis of a large number of test data of the same type of chips and quality standard setting, generally 4%-6%). The low-quality batches are selected as the target batches to be analyzed.

[0079] For the target batch to be analyzed, the specially designed chip information reading device is used to read the die identification information (such as die ID) stored in the register of the die contained in the chip, and the substrate coordinates of the chip are accurately determined by combining the pre-established correspondence between the identification information and the substrate coordinates (stored in the database or configuration file of the packaging factory). Using professional data processing software and image processing algorithms, the chips are respectively set up according to the arrangement direction (X direction and Y direction) on the substrate based on the substrate coordinates of the chip. For example, in the X direction, a set A1 (X1Y1, X2Y1, ..., XmY1), A2 (X1Y2, X2Y2, ..., XmY2), ..., An (X1Yn, X2Yn, ..., XmYn) is established, and in the Y direction, a set B1 (X1Y1, X1Y2, ..., X1Yn), B2 (X2Y1, X2Y2, ..., X2Yn), ..., Bm (XmY1, XmY2, ..., XmYn) is established, and each set covers all chip data in that direction. Combined with the test information, the pass rate of the chips in each set is calculated, and the calculation formula is: set pass rate = (the number of chips that passed the test in the set / the total number of chips in the set) × 100%.

[0080] A CNN-based regression model is used to train historical chip packaging data (including substrate coordinates, test information, pass rate, etc.) to predict the pass rate of the current batch of chips. During the model training process, an adaptive learning rate adjustment algorithm, such as the Adam optimizer, is used to set the initial learning rate to 0.001. The learning rate is dynamically adjusted according to the gradient change during the model training process. After every 100 training batches, if the gradient change is less than 0.0001, the learning rate decays to 0.9 times the original, thereby improving the efficiency and accuracy of model training. According to the pass rate of chips in the corresponding set of all substrates within a preset period of time (such as one month), the average pass rate and deviation value of each set are calculated using statistical analysis methods and machine learning algorithms. Based on the average pass rate and deviation value of each set, an integrated learning method is used to combine the prediction results of multiple machine learning models (such as decision trees, neural networks, support vector machines, etc.), and the threshold corresponding to the set is determined by weighted average. For example, 50 decision tree models are constructed using the random forest algorithm, and weights are assigned to each decision tree according to its accuracy on the validation set, and the final threshold is calculated to improve the accuracy and stability of threshold determination and reduce the risk of misjudgment caused by single model errors.

[0081] Compare the pass rate of the chips in each set with the corresponding threshold. If there is a set where the pass rate of the chips is less than the corresponding threshold, it is determined that the target batch to be analyzed has a low yield problem caused by packaging. Further analyze the type of packaging process with problems. After determining that the low yield problem is caused by packaging, calculate the average pass rate T(PA) of the set in the X direction and the average pass rate T(PB) of the set in the Y direction respectively. If T(PA) > T(PB), it is judged that there is a problem with the cutting alignment accuracy; if T(PA) < T(PB), it is judged that there is a problem with the etching rate.

[0082] Use a neural network model based on the attention mechanism to diagnose problems. After inputting process parameters and chip test data, this model automatically focuses on key information through the attention mechanism. For example, for the cutting process, it focuses on analyzing factors such as the wear degree, cutting speed, and accuracy of the cutting tool, as well as the failure mode of the chip in the X direction, so as to improve the diagnostic accuracy and efficiency. Use an optimization model based on the generative adversarial network (GAN) to optimize the process, where the optimization model is:

[0083]

[0084] Where G is the generator, D is the discriminator, x is the real process data, z is the random noise, p date(x) is the real data distribution, p z (z) is the noise distribution, and E is the expectation operator. During the training process, the generator continuously tries to generate improved process parameters or operation plans, while the discriminator tries to determine whether they are effective. Through the adversarial training of the two, the process is continuously optimized to improve the chip packaging quality.

[0085] In step S6, in the production of LED chips, high-precision sensors, industrial cameras, spectrometers and other acquisition devices are installed at multiple equipment nodes to obtain chip manufacturing process data (such as the wafer size accuracy can reach ±0.001mm, etc.) and three-dimensional topography detection images.

[0086] After removing noise and outliers from the process parameters using the 3σ principle, use Z-score standardization and PCA to extract key features; for images, use wavelet transform (db4 wavelet, 3 layers) for denoising, histogram equalization for enhancement, threshold segmentation or deep learning semantic segmentation of the U-Net architecture for preprocessing.

[0087] Use decision tree and other models to determine whether the process segment is an image detection process segment, and use 10-fold cross validation to adjust parameters during training. For the image detection process segment, the image and parameters are fused using an attention-based algorithm and input into the CNN and RNN hybrid model. The input layer of this model extracts image features through 3 convolutional layers (3x3, 5x5, 3x3) and 2 maximum pooling layers (2x2), and uses fully connected layers and RNN layers to process process parameter features. The hidden layer contains 4 fully connected layers (128, 64, 32, 16 neurons) and ReLU functions, and the output layer uses a softmax function to calculate the process yield.

[0088] The adversarial training mechanism is used to introduce GAN to improve the model performance. The device node weights are determined based on AHP or PCA. The process pass rate of the target LED chip is calculated according to the process pass rate, and then the chip situation is determined.

[0089] Obviously, the above embodiments are only examples for clear explanation, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

[0090] Figure 2 A schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention, such as Figure 2 As shown, the electronic device may include: a processor 401, a communication interface 402, a memory 403 and a bus 404, wherein the processor 401, the communication interface 402, and the memory 403 communicate with each other through the bus 404. The communication interface 402 can be used for information transmission of the electronic device. The processor 401 can call the logic instructions in the memory 403 to execute the methods provided in each embodiment.

[0091] In addition, the logic instructions in the above-mentioned memory 403 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the above-mentioned method embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0092] On the other hand, an embodiment of the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the methods provided in the above embodiments.

[0093] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0094] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

Claims

1. A chip manufacturing quality detection and control method, characterized in that: The following steps are involved: S1: Establish a data collection and processing system to automatically collect chip production data from each site in real time, and perform statistics on defect rate and number of defect occurrences; S2: Set multi-level defect rate thresholds and defect occurrence thresholds. When the thresholds are reached, use the neural network model to predict and classify quality problems and automatically generate quality problem reports; S3: Equipped with quality problem feedback and warning mechanism, the development trend of quality problems is analyzed in real time through the neural network model, and corresponding alarms and warnings are triggered; S4: Provide a quality problem processing tracking system, record processing information, calculate response time and processing time, and use neural network models to predict and optimize processing efficiency; S5: Carry out final testing on the chip packaging process, screen out low-quality batches, combine substrate coordinates and test information, and use a neural network model to analyze packaging process problems; S6: In LED chip production, obtain the process data of each device node, calculate the process yield through the chip process detection model combined with the neural network model, determine the product grade, and perform electrical testing.

2. The chip manufacturing quality detection and control method according to claim 1, characterized in that: In step S1, Build a data collection and processing system to sense various physical parameters and status information in the chip production process in real time through sensors. The intelligent controller is responsible for coordinating the data collection rhythm and preliminary processing, and stably transmits the collected data to the data storage module; The defect rate of each site data is counted, and the time weighting factor is introduced to give different weights to the data at different time points. where t i is the data collection time point, ω(t i ) is the weight function at the corresponding time point; The data is analyzed again in combination with the anomaly detection model of deep learning. The anomaly detection model adopts the convolutional neural network (CNN) architecture. Its convolution layer extracts local features of the data through convolution kernels of different sizes, the pooling layer performs downsampling to reduce the amount of calculation, and the fully connected layer integrates and classifies the features. The loss function adopts the cross entropy function: where y i is the true label, To predict the label, N is the number of samples, and the network parameters are continuously adjusted through the back-propagation algorithm so that the model can accurately identify abnormal data points.

3. The chip manufacturing quality detection and control method according to claim 1, characterized in that: In step S2, Set up a multi-level defect rate threshold and defect occurrence threshold system, analyze historical production data through deep neural networks, use a combination of autoencoders and clustering algorithms to mine the inherent laws of the data, and determine the threshold ranges of different levels; When the defect rate is greater than or equal to the set threshold, a quality problem report is automatically generated. The report content includes the severity of the problem, possible causes and related data statistics; In the report generation process, a text generation model based on a recurrent neural network (RNN) is used. Its hidden layer saves historical information through memory units and generates a quality problem report described in natural language based on the input problem feature vector and the current hidden state. The formula is: h t =tanh(W hh h t-1 +W xh x t +b h ) y t =W hy h t +b y where h t is the current hidden state, h t-1 is the hidden state at the previous moment, x t is the current input feature vector, W hh , W xh , W hy is the weight matrix, b h 、b y is the bias vector, y t The generated text output.

4. The chip manufacturing quality detection and control method according to claim 1, characterized in that: In step S3, the quality problem feedback and warning mechanism includes: Intelligent alarms are equipped for lines with quality problems. The alarm lights light up in different colors according to the severity and type of the quality problems sent by the central control system. The counter communicates with the central control system in real time, accumulates the number of quality problems, and stores and uploads the data. For the priority sorting of quality issues, a sorting model based on the long short-term memory network (LSTM) is adopted. The quality issue feature vector is input, and the priority score is calculated through the LSTM unit gating mechanism, and the issues are sorted according to the score.

5. The chip manufacturing quality detection and control method according to claim 1, characterized in that: In step S4, the quality problem handling tracking system includes: Set up a user input interface on the production site terminal device or mobile application; The processing personnel input the processing start time, the central control system calculates the processing response time and displays the processing information in real time on the engineering TV board through the data synchronization module and WebSocket technology; After the processing is completed, the processing completion information is input, and the central control system calculates the processing time and stores the processing data; Analyze processing efficiency and generate reports using data analysis algorithms and report generation tools; A neural network-based time series prediction model is introduced to evaluate processing efficiency; the time series prediction model includes a hybrid model of MLP and LSTM; A deep Q network model (DQN) based on reinforcement learning is used to simulate and predict the processing process, and the optimal processing strategy is found through training.

6. The chip manufacturing quality detection and control method according to claim 1, characterized in that: In step S5, the quality problem handling tracking system includes: After chip packaging, the final test is carried out to screen out low-quality batches based on the chip failure rate formula; Determine the substrate coordinates of the low-quality batch of chips, create a set in the X and Y directions according to the substrate coordinates, and calculate the pass rate; A CNN-based regression model is used to train historical data to predict the current batch pass rate, and the Adam optimizer is used for training; Calculate the average pass rate and deviation value of the corresponding set of substrates within the preset time, and use the ensemble learning method to determine the threshold to judge the low-quality problems; Calculate the average pass rate of the X and Y directions to determine the process type; in P Ai A is the X-direction set i The pass rate of the chip in Bi is the Y direction set B i The passing rate of the chip in the figure, n is the number of sets in the X direction, and m is the number of sets in the Y direction; The problem is diagnosed using a neural network model based on the attention mechanism, and the process is optimized using an optimization model based on a generative adversarial network (GAN); the optimization model is: Where G is the generator, D is the discriminator, x is the real process data, z is random noise, p date(x) is the actual data distribution, p z (z) is the noise distribution and E is the expectation operator.

7. The chip manufacturing quality detection and control method according to claim 1, characterized in that: In step S6, Install high-precision sensors, industrial cameras and spectrum analyzer acquisition devices at multiple equipment nodes in LED chip production to obtain chip process data and three-dimensional morphology detection images; the chip process data includes wafer size accuracy; Clean, normalize and standardize the chip process parameters and extract key features. Pre-process the 3D shape detection images using wavelet transform denoising, histogram equalization enhancement, threshold segmentation or deep learning semantic segmentation methods. Use decision tree, random forest or support vector machine machine learning classification model to determine whether the process segment corresponding to the device node is an image detection process segment; For the image detection process, the 3D shape detection image and chip process parameters are fused using a multimodal data fusion algorithm based on an attention mechanism, and then input into a chip process detection model based on a CNN and RNN hybrid model. The input layer of the chip process detection model further processes and extracts features from the fused data. The hidden layer learns nonlinear relationships through the fully connected layer and activation function. The output layer uses the softmax function to calculate the process yield of the device node and output it. The adversarial training mechanism is introduced into GAN to improve the robustness and generalization ability of the model; Based on the weight data of each device node and the process yield, the process pass rate of the target LED chip is calculated.

8. An electronic device, characterized in that: It comprises a processor and a memory, wherein the processor is used to execute the chip manufacturing quality detection and control method according to any one of claims 1 to 7, and the memory is used to store programs and data required to execute the method.

9. A computer-readable storage medium, characterized in that: A computer program is stored, the computer program including program instructions, and when the program instructions are executed by a processor, the processor is caused to execute the chip manufacturing quality detection and control method according to any one of claims 1 to 7.

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