Package structure, chip stack structure, electronic device, and packaging method

Abstract

The present disclosure relates to a packaging structure, a chip stacking structure, an electronic device and a packaging method, the packaging structure comprising a first chip and a second chip arranged in a stacked manner, the first chip being internally provided with a first element and a shielding element; wherein the second chip is arranged opposite to an active surface of the first chip, and in the thickness direction of the packaging structure, the shielding element is arranged between the first element and the second chip, and the shielding element is used to reduce signal interference of the second chip on the first element. The packaging structure of the present disclosure, by arranging the first element and the shielding element in the first chip, and arranging the shielding element between the first element and the second chip in the thickness direction of the packaging structure, so that the signal interference of the second chip on the first element can be reduced by using the shielding element, thereby improving the signal quality of the first element and improving the signal quality of the packaging structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to a packaging structure, a chip stacking structure, an electronic device and a packaging method. BACKGROUND

[0002] Three-dimensional stacked chips not only can realize high-density vertical interconnection between chips through Hybrid Bonding and other methods, improve the equivalent two-dimensional integration density of the chip, but also can integrate heterogeneous integration under different process nodes, improve the functional density of the system, and meet the growing demand for computing power. However, stacking chips with high integration density results in a small distance between chips, and high-speed signals inside different chips will interfere with each other, affecting the integrity of the high-speed signals. SUMMARY

[0003] In a first aspect, the present disclosure provides a packaging structure to improve the signal quality of the packaging structure.

[0004] The packaging structure of the present disclosure includes a first chip and a second chip stacked with each other, the first chip is provided with a first element and a shielding element; wherein the second chip is arranged opposite to the active surface of the first chip, and in the thickness direction of the packaging structure, the shielding element is arranged between the first element and the second chip, and the shielding element is used to reduce the signal interference of the second chip to the first element.

[0005] Optionally, the first chip includes a plurality of first wiring layers, and the plurality of first wiring layers are arranged in the thickness direction of the packaging structure, at least one of the first wiring layers is a top layer, the top layer is arranged closer to the second chip than the remaining first wiring layers in the thickness direction of the packaging structure, and the shielding element is at least partially arranged in the top layer.

[0006] Optionally, at least one of the first wiring layers forms a sub-top layer, the sub-top layer is arranged on the side of the top layer away from the second chip in the thickness direction of the packaging structure, and is arranged adjacent to the top layer, and the first element is at least partially arranged in the sub-top layer.

[0007] Optionally, at least two of the first wiring layers form the sub-top layer.

[0008] Optionally, the orthogonal projection of the shielding element in the direction towards the first element at least partially covers the first element.

[0009] Optionally, the area of the orthogonal projection of the shielding element in the direction towards the first element is greater than the area of the region where the first element is located.

[0010] Optionally, the first chip is provided with a plurality of first electrical connectors, and the second chip is provided with a plurality of second electrical connectors, the second electrical connectors being connected with the first electrical connectors.

[0011] Optionally, the first chip and the second chip are electrically connected by a hybrid bonding method.

[0012] Optionally, the shielding element comprises a metal layer.

[0013] Optionally, the metal density of the region where the metal layer is located is 30-50%.

[0014] Optionally, the shielding element comprises a first shielding part and a second shielding part, the first shielding part and the second shielding part are both comb-shaped; the first shielding part comprises a plurality of first metal strips arranged side by side, the second shielding part comprises a plurality of second metal strips arranged side by side, and the first metal strips and the second metal strips are alternately and spacedly arranged.

[0015] Optionally, the first chip comprises a logic chip, and the second chip comprises a memory chip; or, the first chip and the second chip are both logic chips.

[0016] Optionally, the first chip is connected with a circuit board away from the second chip.

[0017] Optionally, the shielding element is grounded or connected with a power supply.

[0018] In a second aspect, the present disclosure provides a packaging method.

[0019] The packaging method of the present disclosure is used for forming the packaging structure described in any one of the above, and the packaging method comprises:

[0020] a first element and a shielding element are arranged on the first chip;

[0021] the first chip and the second chip are stacked, wherein the shielding element is arranged between the first element and the second chip, the second chip is arranged opposite to the active surface of the first chip, and the shielding element is used for reducing the signal interference of the second chip on the first element.

[0022] Optionally, the first chip is provided with a first element and a shielding element, and the method comprises:

[0023] at least one first wiring layer is formed on the active surface of the first chip, the first wiring layer being arranged along the thickness direction of the packaging structure;

[0024] the first element is formed by the at least one first wiring layer;

[0025] The shielding element is formed by at least one of the first wiring layers.

[0026] Optionally, at least one of the first wiring layers is a top layer, which is arranged closer to the second chip than the rest of the first wiring layers in the thickness direction of the packaging structure, and the shielding element is at least partially arranged in the top layer.

[0027] Optionally, at least one of the first wiring layers forms a sub-top layer, which is arranged on the side of the top layer away from the second chip and adjacent to the top layer in the thickness direction of the packaging structure, and the first element is at least partially arranged in the sub-top layer.

[0028] In a third aspect, the present disclosure provides a chip stack structure.

[0029] The chip stack structure of the present disclosure comprises a substrate and the packaging structure of any one of the above, which is arranged on the substrate.

[0030] In a fourth aspect, the present disclosure provides an electronic device.

[0031] The electronic device of the present disclosure comprises a printed circuit board and the packaging structure of any one of the above, which is connected to the printed circuit board.

[0032] The packaging structure of the present disclosure, by arranging the first element and the shielding element in the first chip and arranging the shielding element between the first element and the second chip in the thickness direction of the packaging structure, can reduce the signal interference of the second chip to the first element by using the shielding element, thereby improving the signal quality of the first element and the signal quality of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a cross-sectional view of the packaging structure of an embodiment of the present disclosure.

[0034] Figure 2 is a partial cross-sectional view of the packaging structure of an embodiment of the present disclosure.

[0035] Figure 3 is a cross-sectional view of a chip of another embodiment of the present disclosure.

[0036] Figure 4 is Figure 3 is an enlarged view of A in FIG.

[0037] Figure 5 is a structural schematic diagram of a shielding element of a chip of another embodiment of the present disclosure.

[0038] Figure 6 is a structural schematic diagram of a shielding element and a first element of a chip of another embodiment of the present disclosure.

[0039] Figure 7 This is a schematic diagram of the shielding element of a chip according to yet another embodiment of the present disclosure.

[0040] Figure 8 This is a schematic diagram of the shielding element of a chip according to another embodiment of the present disclosure.

[0041] Figure 9 This is a schematic diagram of the shielding element of a chip according to another embodiment of the present disclosure.

[0042] Figure label:

[0043] 10. Packaging structure;

[0044] 1. First chip; 11. First component; 12. Shielding component; 121. First shielding part; 1211. First metal strip; 122. Second shielding part; 1221. Second metal strip; 123. Shielding part; 1231. Metal strip; 13. First electrical connector; 14. First through hole; 101. First wiring layer; 1011. Top layer; 1012. Secondary top layer; 102. First line;

[0045] 2. Second chip; 21. Second electrical connector; 22. Second via; 201. Second wiring layer; 2011. Second line;

[0046] 100. Package structure; 1001. First chip; 1002. Second chip; 1003. Inductor; 1004. Circuit. Detailed Implementation

[0047] Embodiments of this disclosure are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting it.

[0048] like Figure 1 and Figure 2 The present disclosure provides an embodiment of the encapsulation structure 100. Figure 1 and Figure 2In the example, inductor 1003 requires a certain size of clearance area to prevent other traces from affecting its Q value and inductance. Because the active surfaces of the first chip 1001 and the second chip 1002 in the package structure 100 are connected by a hybrid bonding method, the distance L between the first chip 1001 and the second chip 1002 is only a few micrometers. The inductor 1003 in the first chip 1001 cannot achieve the required clearance area, and the traces 1004 on the second chip 1002 will interfere with the inductor 1003 in the first chip 1001, reducing the signal quality of the inductor 1003 and further affecting the operation of the first chip 1001. This is especially true in high-speed scenarios, such as transmission speeds exceeding 10 BPS, where the inductor 1003 is more susceptible to the influence of the second chip 1002. Therefore, improving the signal quality of the inductor 1003 in the first chip 1001 is a pressing technical problem that needs to be solved.

[0049] like Figure 3 and Figure 4 As shown, the packaging structure 10 of this embodiment includes a first chip 1 and a second chip 2 stacked on top of each other. The first chip 1 contains a first element 11 and a shielding element 12. The second chip 2 is disposed opposite to the active surface of the first chip 1. In the thickness direction of the packaging structure 10, the shielding element 12 is disposed between the first element 11 and the second chip 2. The shielding element 12 is used to reduce signal interference from the second chip 2 to the first element 11.

[0050] It should be noted that the chip in the embodiments of this disclosure can be a die (also called a particle or bare chip) or a chip wafer. It is understood that after growing an epitaxial layer on a wafer, the chip wafer is formed, and the chip wafer is then diced to obtain a bare chip. Dies can be bonded to each other (die-to-die bonding, D2D bonding). Chip-wafer bonding is called wafer-to-wafer bonding (W2W bonding). Multiple dies stacked on a chip wafer constitute a structure called die-to-wafer bonding (D2W bonding). The packaging of this disclosure can also be at least one of chip-to-wafer (C2W) bonding, die-to-wafer (D2C) bonding, and chip-to-chip (C2C) bonding.

[0051] The number of stacked chips in the chip stacking structure is not limited in the present disclosure, and the number of stacked chips can be set according to application requirements. In addition, the chip described above can be a storage chip, a logic chip, or a chip with other functions.

[0052] The packaging structure 10 of the embodiment of the present disclosure, by setting the first element 11 and the shielding element 12 in the first chip 1, and setting the shielding element 12 between the first element 11 and the second chip 2 in the thickness direction of the packaging structure 10, so that the signal interference of the second chip 2 to the first element 11 can be reduced by using the shielding element 12, thereby improving the signal quality of the first element 11 and improving the signal quality of the packaging structure 10.

[0053] Optionally, the first chip 1 includes a logic chip, and the second chip 2 includes a storage chip. Alternatively, the first chip 1 and the second chip 2 are both logic chips.

[0054] Among them, the logic chip can be an application chip, and the storage chip can be a dynamic random storage chip.

[0055] In the embodiment of the present disclosure, the first element 11 can include an element with a specific function, i.e., a functional element.

[0056] Optionally, the first element 11 includes an inductor. It can be understood that the first element 11 can also be other functional devices affected by the second chip 2, such as sensors, capacitors, etc.

[0057] In the present disclosure, the inductor element is very susceptible to the influence of the second chip 2, and the present application scheme can be preferably used in the scenario where the first element 11 is an inductor.

[0058] By setting the shielding element 12, the signal interference of the second chip 2 to the inductor, sensor, or capacitor can be reduced or even avoided, and the signal quality of the packaging structure 10 is improved.

[0059] In order to make the technical scheme of the present disclosure easier to be understood, the thickness direction of the packaging structure 10 is taken as an example, and the technical scheme of the present disclosure is further described below. Among them, the up-down direction is as shown in Figure 3 and Figure 4 .

[0060] For example, the first chip 1 is arranged on the lower side of the second chip 2, and the first element 11 is arranged on the lower side of the shielding element 12.

[0061] Optionally, as shown in Figure 3 and Figure 4As shown, the first chip 1 includes a plurality of first wiring layers 101 arranged along the thickness direction of the packaging structure 10. At least one of the first wiring layers 101 is a top layer 1011 arranged closer to the second chip 2 than the rest of the first wiring layers 101 in the thickness direction of the packaging structure 10. The shielding element 12 is at least partially arranged in the top layer 1011.

[0062] In the embodiment, the shielding element 12 is at least partially arranged in the top layer 1011, which can be understood as that a part of the shielding element 12 is arranged in the top layer 1011, and another part of the shielding element 12 is arranged in other first wiring layers 101 except the top layer 1011; or the shielding element 12 is entirely arranged in the top layer 1011.

[0063] For example, the plurality of first wiring layers 101 are arranged along the up-down direction. One of the first wiring layers 101 is the top layer 1011, and the top layer 1011 is located at the uppermost side among the plurality of first wiring layers 101.

[0064] In the embodiment, the closer the first wiring layer 101 is to the second chip 2, the greater the thickness of the first wiring layer 101 is, and the smaller the resistance of the first wiring layer 101 is.

[0065] By arranging the shielding element 12 at least partially in the top layer 1011, the first element 11 can be arranged in the first wiring layer 101 with relatively large thickness, thereby reducing the parasitic resistance of the first element 11, improving the Q value of the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0066] Optionally, as shown in Figure 3 and Figure 4 At least one of the first wiring layers 101 forms a sub-top layer 1012. The sub-top layer 1012 is arranged on the side of the top layer 1011 away from the second chip 2 in the thickness direction of the packaging structure 10, and is arranged adjacent to the top layer 1011. The first element 11 is at least partially arranged in the sub-top layer 1012.

[0067] In the embodiment, the first element 11 is at least partially arranged in the sub-top layer 1012, which can be understood as that a part of the first element 11 is arranged in the sub-top layer 1012, and another part of the first element 11 is arranged in other first wiring layers 101 except the top layer 1011 and the sub-top layer 1012; or the first element 11 is entirely arranged in the top layer 1011.

[0068] As described above, the closer the first wiring layer 101 is to the second chip 2, the greater the thickness of the first wiring layer 101 is, and the smaller the resistance of the first wiring layer 101 is.

[0069] By setting the first element 11 at least partially in the sub-top layer 1012, the parasitic resistance of the first element 11 can be reduced, the Q value of the first element 11 is improved, and the signal quality of the first element 11 is further improved, and the signal quality of the packaging structure 10 is improved.

[0070] Optionally, the at least two first wiring layers 101 form the sub-top layer 1012.

[0071] For example, the number of the first wiring layers 101 is three, the uppermost first wiring layer 101 is the top layer 1011, and the two first wiring layers 101 below the top layer 1011 form the sub-top layer 1012, that is, the two first wiring layers 101 are combined to form the sub-top layer 1012, so as to increase the thickness of the sub-top layer 1012.

[0072] By forming the sub-top layer 1012 by the at least two first wiring layers 101, the thickness of the sub-top layer 1012 can be reduced, so as to reduce the parasitic resistance of the first element 11 arranged in the sub-top layer 1012, further improve the Q value of the first element 11, improve the signal quality of the first element 11, and improve the signal quality of the packaging structure 10.

[0073] Optionally, as shown in Figure 3 , the first chip 1 further comprises a first circuit 102, and the first circuit 102 is arranged on at least one side of the first element 11 in a preset direction, and the preset direction is perpendicular to the thickness direction of the packaging structure 10.

[0074] In order to make the technical scheme of the present disclosure easier to be understood, the technical scheme of the present disclosure is further described below taking the case that the preset direction is consistent with the left-right direction as an example. Wherein, the left-right direction is as shown in Figure 3 and Figure 4 .

[0075] For example, the first circuit 102 is arranged on the left and right sides of the first element 11 in the left-right direction.

[0076] By arranging the first circuit 102 on at least one side of the first element 11 in the preset direction, compared with arranging the first circuit 102 on the side of the first element 11 away from the shielding element 12 in the preset direction, the interference of the first circuit 102 to the first element 11 can be reduced, the signal quality of the first element 11 is further improved, and the signal quality of the packaging structure 10 is improved.

[0077] Optionally, as shown in Figure 3 and Figure 4 , the second chip 2 comprises a plurality of second wiring layers 201, and the plurality of second wiring layers 201 are arranged along the thickness direction of the packaging structure 10, and at least one second wiring layer 201 is provided with a second circuit 2011.

[0078] For example, the second chip 2 includes three second wiring layers 201, the three second wiring layers 201 are arranged along the up-down direction, and each second wiring layer 201 is provided with a second line 2011.

[0079] Optionally, as shown in Figure 3 and Figure 4 , the first chip 1 is provided with a plurality of first electrical connection pieces 13, and the second chip 2 is provided with a plurality of second electrical connection pieces 21, the second electrical connection pieces 21 correspond to the first electrical connection pieces 13 one by one and are electrically connected. At least one first electrical connection piece 13 is grounded and electrically connected with the shielding element 12.

[0080] As shown in Figure 3 , the first chip 1 is provided with a first through hole 14, and the first electrical connection piece 13 extends to the line of the first chip 1 through the first through hole 14. The second chip 2 is provided with a second through hole 22, and the second electrical connection piece 21 extends to the line of the second chip 2 through the second through hole 22.

[0081] By grounding at least one first electrical connection piece 13 and electrically connecting it with the shielding element 12, it is convenient to realize that the shielding element 12 is grounded.

[0082] Optionally, the first chip 1 and the second chip 2 are electrically connected by a hybrid bonding method.

[0083] The first chip 1 and the second chip 2 are connected by a hybrid bonding method, which can realize higher density and greater bandwidth of the packaging structure 10.

[0084] Optionally, the shielding element 12 includes a shielding layer made of electromagnetic shielding material.

[0085] Optionally, the shielding element 12 includes a metal layer.

[0086] It can be understood that the shielding element 12 in the present disclosure is not limited to a metal layer or an electromagnetic shielding layer, but also to other elements with electromagnetic shielding function.

[0087] By setting the shielding element 12 to include a metal layer, the signal shielding effect of the shielding element 12 can be improved, further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0088] Optionally, the metal density of the area where the metal layer is located is 30%-50%.

[0089] For example, as shown in Figure 5 , the area of the dashed box is the area where the shielding element 12 is located, and the area ratio of the metal layer to the dashed box is the metal density of the area where the metal layer is located.

[0090] By setting the metal density of the region where the metal layer is located to 30%-50%, the metal amount of the shielding element 12 can be reduced to lower the cost of the packaging structure 10 while ensuring the shielding effect of the shielding element 12.

[0091] Optionally, the shielding element 12 is grounded or connected to a power supply.

[0092] For example, the shielding element 12 is electrically connected to the first wiring layer 101, and the first wiring layer 101 is grounded or connected to a power supply, so as to realize the grounding or connection to the power supply of the shielding element 12.

[0093] By grounding the shielding element 12, the signal shielding effect of the shielding element 12 can be improved, the signal interference generated by the second chip 2 to the first element 11 can be reduced, and the signal quality of the packaging structure 10 can be further improved.

[0094] Optionally, as shown in Figures 5 to 7 , the shielding element 12 includes at least one shielding portion 123, and the shielding portion 123 is comb-shaped.

[0095] For example, as shown in Figure 5 and Figure 6 , the shielding element 12 includes two shielding portions 123, and both of the two shielding portions 123 are comb-shaped.

[0096] By setting the shielding portion 123 of the shielding element 12 to be comb-shaped, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference generated to the first element 11 can be reduced, and the signal quality of the packaging structure 10 can be further improved.

[0097] Optionally, as shown in Figure 5 and Figure 6 , the shielding element 12 includes a plurality of shielding portions 123, at least one shielding portion 123 is a first shielding portion 121, and at least one shielding portion 123 is a second shielding portion 122. The first shielding portion 121 includes a plurality of first metal strips 1211 arranged side by side, the second shielding portion 122 includes a plurality of second metal strips 1221 arranged side by side, and the first metal strips 1211 and the second metal strips 1221 are alternately and spaced arranged.

[0098] For example, as shown in Figure 5 and Figure 6 , the first shielding portion 121 is arranged at the front side of the second shielding portion 122, and the plurality of first metal strips 1211 and the plurality of second metal strips 1221 are alternately and spaced arranged along the left-right direction. Wherein, the front-rear direction is as shown in Figure 5 and Figure 6 , and the left-right direction is as shown in Figure 5 and Figure 6 .

[0099] By setting the shielding element 12 to the above structure, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference on the first element 11 is reduced, the signal quality of the first element 11 is further improved, and the signal quality of the packaging structure 10 is improved.

[0100] Optionally, as shown in Figure 5 and Figure 6 , the width of the first metal strip 1211 and the second metal strip 1221 is 0.4-12.5 μm.

[0101] For example, as shown in Figure 5 , the width of the first metal strip 1211 and the second metal strip 1221 is K1, and K1 is 1.8 μm.

[0102] By setting the width of the first metal strip 1211 and the second metal strip 1221 to 0.4-12.5 μm, the processing and manufacturing of the shielding element 12 are facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10, and the cost of the packaging structure 10 is reduced.

[0103] Optionally, as shown in Figure 5 and Figure 6 , the spacing between the first metal strip 1211 and the second metal strip 1221 is 0.4-25 μm.

[0104] For example, as shown in Figure 5 , the spacing between the first metal strip 1211 and the second metal strip 1221 is K2, and K2 is 2.7 μm.

[0105] By setting the spacing between the first metal strip 1211 and the second metal strip 1221 to 0.4-25 μm, the processing and manufacturing of the shielding element 12 are facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10, and the cost of the packaging structure 10 is reduced.

[0106] Optionally, as shown in Figure 8 , the shielding element 12 includes a plurality of shielding portions 123, the plurality of shielding portions 123 are uniformly arranged along the circumference of the preset rectangular frame, and the shielding portion 123 includes a plurality of V-shaped metal strips 1231. The plurality of metal strips 1231 of the same shielding portion 123 are arranged in an interval in the inward and outward directions, and the length of the metal strip 1231 located on the outer side is less than the length of the metal strip 1231 located on the inner side. Wherein, Figure 8 the dashed box in the above is a preset rectangular frame.

[0107] Wherein, inward can be understood as: in the plane where the shielding element 12 is located, the direction close to the center of the rectangular frame; outward can be understood as: in the plane where the shielding element 12 is located, the direction away from the center of the rectangular frame.

[0108] By setting the shielding element 12 to the above structure, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference on the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0109] Optionally, as shown in Figure 8 , the number of shielding parts 123 is four, and the included angle of the metal strips 1231 is 90°.

[0110] By setting the number of shielding parts 123 to four and the included angle of the metal strips 1231 to 90°, the processing and manufacturing of the shielding element 12 are facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10, and the cost of the packaging structure 10 is reduced.

[0111] Optionally, as shown in Figure 9 , the shielding element 12 is a rectangular pulse signal waveform.

[0112] By setting the shielding element 12 to the above structure, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference on the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved. In addition, the shielding element 12 is set to a rectangular pulse signal waveform, which facilitates the processing and manufacturing of the shielding element 12, thereby facilitating the processing and manufacturing of the packaging structure 10, and the cost of the packaging structure 10 is reduced.

[0113] Optionally, as shown in Figure 3 , Figure 4 and Figure 6 , the orthographic projection of the shielding element 12 in the direction towards the first element 11 at least partially covers the first element 11.

[0114] The orthographic projection of the shielding element 12 in the direction towards the first element 11 at least partially covers the first element 11, which can be understood as that the orthographic projection of the shielding element 12 in the direction towards the first element 11 entirely covers the first element 11, or that a part of the orthographic projection of the shielding element 12 in the direction towards the first element 11 covers the first element 11, and another part of the orthographic projection of the shielding element 12 in the direction towards the first element 11 does not cover the first element 11.

[0115] By setting the orthographic projection of the shielding element 12 in the direction towards the first chip 1 to at least partially cover the first element 11, the signal shielding effect of the shielding element 12 can be improved, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0116] Optionally, as shown in Figure 6As shown, the area of the orthogonal projection of the shielding element 12 in the direction towards the first chip 1 is greater than the area of the region where the first element 11 is located. That is, the orthogonal projection of the shielding element 12 in the direction towards the first element 11 covers not only the entire first element 11, but also the edge region of the first element 11, so as to cover more signals generated by the first element 11.

[0117] By making the area of the orthogonal projection of the shielding element 12 in the direction towards the first chip 1 greater than the area of the region where the first element 11 is located, the signal shielding effect of the shielding element 12 can be further improved, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0118] Optionally, the side of the first chip 1 away from the second chip 2 is connected to a circuit board.

[0119] For example, the lower side of the first chip 1 is connected to a circuit board.

[0120] The packaging structure 10 of the embodiment of the present disclosure can reduce the signal interference of the second chip 2 to the first element 11 and the interference of the first element 11 to the circuit of the second chip 2 by arranging the first element 11 and the shielding element 12 on the first chip 1 and arranging the shielding element 12 between the first element 11 and the second chip 2, thereby improving the signal quality of the first element 11 and improving the signal quality of the packaging structure 10.

[0121] The packaging method of the embodiment of the present disclosure is used for the packaging structure 10 of any one of the above embodiments, and the packaging method comprises:

[0122] arranging the first element 11 and the shielding element 12 on the first chip 1;

[0123] stacking the first chip 1 and the second chip 2, wherein the shielding element 12 is arranged between the first element 11 and the second chip 2, the second chip 2 is arranged opposite to the active surface of the first chip 1, and the shielding element 12 is used to reduce the signal interference of the second chip 2 to the first element 11.

[0124] Optionally, the first chip 1 is arranged with the first element 11 and the shielding element 12, and the arrangement comprises:

[0125] forming at least one first wiring layer 101 on the active surface of the first chip 1, wherein the first wiring layer 101 is arranged along the thickness direction of the packaging structure 10;

[0126] forming the first element 11 through the at least one first wiring layer 101;

[0127] forming the shielding element 12 through the at least one first wiring layer 101.

[0128] Optionally, the at least one first wiring layer 101 is a top layer 1011, the top layer 1011 is arranged closer to the second chip 2 in the thickness direction of the packaging structure 10 than the rest of the first wiring layers 101, and the shielding element 12 is at least partially arranged in the top layer 1011.

[0129] Optionally, the at least one first wiring layer 101 forms a sub-top layer 1012, the sub-top layer 1012 is arranged on the side away from the second chip 2 of the top layer 1011 in the thickness direction of the packaging structure 10, and is arranged adjacent to the top layer 1011, and the first element 11 is at least partially arranged in the sub-top layer 1012.

[0130] The chip stacking structure of the embodiments of the present disclosure comprises a substrate and the packaging structure 10 of any of the above embodiments, and the packaging structure 10 is arranged on the substrate.

[0131] The electronic device of the embodiments of the present disclosure comprises a printed circuit board and the packaging structure 10 of any of the above embodiments, and the packaging structure 10 is connected to the printed circuit board.

[0132] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0133] In addition, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0134] In the present disclosure, unless otherwise specifically defined and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected or can communicate with each other; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication or interaction relationship of two elements, unless otherwise specifically limited. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0135] In the present disclosure, unless specifically stated and limited otherwise, a first feature "on" or "under" a second feature can be directly contacting the first and second features, or indirectly contacting the first and second features through an intermediate medium. Also, the first feature "over", "above" and "on top of" the second feature can be directly above or diagonally above the second feature, or simply means that the first feature is horizontally higher than the second feature. The first feature "under", "below" and "underneath" the second feature can be directly below or diagonally below the second feature, or simply means that the first feature is horizontally lower than the second feature.

[0136] In the present disclosure, the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" mean that a particular feature, structure, material or characteristic is included in at least one embodiment or example of the present disclosure. In the specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the described specific features, structures, materials or characteristics can be combined in any suitable manner in any one or more embodiments or examples. In addition, different embodiments or examples described in the specification and features of different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0137] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present disclosure, and that changes, modifications, replacements and variations of the above-described embodiments made by those skilled in the art are within the scope of protection of the present disclosure.

Claims

1. A packaging structure, characterized in that, include A first chip and a second chip are stacked on top of each other, wherein the first chip contains a first element and a shielding element; In this embodiment, the active surfaces of the second chip and the first chip are disposed opposite each other. In the thickness direction of the package structure, the shielding element is disposed between the first element and the second chip. The shielding element is used to reduce the signal interference of the second chip to the first element. The first chip includes a plurality of first wiring layers, which are arranged along the thickness direction of the package structure. Among the plurality of first wiring layers, the first wiring layer closer to the second chip has a larger thickness. At least one first wiring layer is a top layer, which is disposed closer to the second chip in the thickness direction of the package structure than the other first wiring layers. The shielding element is disposed on the top layer.

2. The packaging structure according to claim 1, characterized in that, At least one of the first wiring layers forms a sub-top layer, the sub-top layer being disposed on the side of the top layer away from the second chip in the thickness direction of the package structure and adjacent to the top layer, and the first element being at least partially disposed in the sub-top layer.

3. The packaging structure according to claim 2, characterized in that, At least two of the first wiring layers form the subtop layer.

4. The packaging structure according to claim 1, characterized in that, The shielding element, when projected orthogonally toward the first element, at least partially covers the first element.

5. The packaging structure according to claim 4, characterized in that, The area of ​​the shielding element projected in the direction toward the first element is greater than the area of ​​the region where the first element is located.

6. The packaging structure according to claim 1, characterized in that, The first chip has multiple first electrical connectors, and the second chip has multiple second electrical connectors, which are interconnected with the first electrical connectors.

7. The packaging structure according to claim 6, characterized in that, The first chip and the second chip are electrically connected by a hybrid bonding method.

8. The packaging structure according to any one of claims 1-7, characterized in that, The shielding element includes a metal layer.

9. The packaging structure according to claim 8, characterized in that, The metal density in the region where the metal layer is located is 30% to 50%.

10. The packaging structure according to claim 8, characterized in that, The shielding element includes a first shielding part and a second shielding part, both of which are comb-shaped. The first shielding part includes a plurality of first metal strips arranged side by side, and the second shielding part includes a plurality of second metal strips arranged side by side, wherein the first metal strips and the second metal strips are arranged alternately and at intervals.

11. The packaging structure according to any one of claims 1-7, characterized in that, The first chip includes a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

12. The packaging structure according to any one of claims 1-7, characterized in that, The side of the first chip furthest from the second chip is connected to the circuit board.

13. The packaging structure according to any one of claims 1-7, characterized in that, The shielding element is grounded or connected to a power source.

14. A packaging method, characterized in that, The encapsulation method is used to form the encapsulation structure according to any one of claims 1-12, the encapsulation method comprising: A first component and a shielding component are configured on the first chip; The first chip and the second chip are stacked, wherein the shielding element is disposed between the first chip and the second chip, and the active surfaces of the second chip and the first chip are disposed opposite each other. The shielding element is used to reduce the signal interference of the second chip to the first chip.

15. The packaging method according to claim 14, characterized in that, The first chip is provided with a first element and a shielding element, including: At least one first wiring layer is formed on the active surface of the first chip, and the first wiring layer is arranged along the thickness direction of the package structure. The first element is formed through at least one of the first wiring layers; The shielding element is formed through at least one layer of the first wiring layer.

16. The packaging method according to claim 15, characterized in that, At least one of the first wiring layers is a top layer, which is disposed closer to the second chip in the thickness direction of the package structure than the remaining first wiring layers, and the shielding element is at least partially disposed on the top layer.

17. The packaging method according to claim 16, characterized in that, At least one of the first wiring layers forms a sub-top layer, the sub-top layer being disposed on the side of the top layer away from the second chip in the thickness direction of the package structure and adjacent to the top layer, and the first element being at least partially disposed in the sub-top layer.

18. A chip stacking structure, characterized in that, It includes a substrate and a packaging structure according to any one of claims 1-13, wherein the packaging structure is disposed on the substrate.

19. An electronic device, characterized in that, It includes a printed circuit board and a packaging structure according to any one of claims 1-13, wherein the printed circuit board is connected to the packaging structure.

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