PCI express internal card adapter cable for supporting multi-port memory systems

Abstract

An adapter cable may include: a receptacle connector including contact pins defined for a peripheral component interconnect express (PCIe) connector; an edge connector having an edge pin defined for a PCIe interposer card (AIC); and connectors connecting the socket connector to the edge connectors, each of the connectors connecting one of the contact pins to one of the edge pins.

Description

Technical Field

[0001] The present application relates to an adapter cable for peripheral component interconnect express (PCIe) applications. Background Art

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard. PCIe provides a common motherboard interface for graphics cards, sound cards, hard drive host adapters, solid-state drives, Wi-Fi, and Ethernet hardware connections in computer systems. The Non-Volatile Memory Express (NVMe) protocol can use PCIe as a transport in storage systems. Summary of the invention

[0003] Aspects of the present disclosure provide an adapter cable. The adapter cable may include a socket connector including contact pins defined for a peripheral component interconnect express (PCIe) connector, an edge connector having edge pins defined for a PCIe add-in card (AIC), and connectors connecting the socket connector to the edge connector, each connector connecting one of the contact pins to one of the edge pins.

[0004] Aspects of the present disclosure provide an adapter cable for connecting a PCIe AIC to a PCIe connector. The adapter cable may include a socket connector for receiving a PCIe AIC, the socket connector including contact pins defined for the PCIe connector; an edge connector for mounting to the PCIe connector, one of the edge connectors having edge pins defined for the PCIe AIC; and connectors connecting the socket connector to the edge connectors, each connector connecting one of the contact pins to one of the edge pins.

[0005] In an embodiment, a first contact pin of the socket connector corresponding to at least one PCIe channel is connected to a first edge pin of a first edge connector of the edge connectors via a first connector of the connectors. A second contact pin of the socket connector corresponding to at least one other PCIe channel and different from the first contact pin is connected to a second edge pin of a second edge connector of the edge connectors. For one of the edge connectors, a third contact pin of the socket connector is connected to a third edge pin of the corresponding edge connector via a connector of the connectors, and the third edge pin corresponds to a reset signal defined in PCIe. For one of the edge connectors, a pair of fourth contact pins of the socket connector is connected to a pair of fourth edge pins of the corresponding edge connector via a connector of the connectors, and the pair of fourth pins corresponds to a pair of reference clock signals defined in PCIe.

[0006] In an embodiment, the socket connector is an x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is an x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; the first contact pins are pins 14, 15, 19 and 20 on the B side of the socket connector connected to the first edge pins and pins 16, 17, 21 and 22 on the A side, the first edge pins are pins 14, 15, 19 and 20 on the B side of the first edge connector and pins 16, 17, 21 and 22 on the A side; the second contact pins are pins 23, 24, 27 and 28 on the B side of the socket connector connected to the second edge pins and pins 25, 26, 29 and 30 on the A side, the second edge pins are pins 14, 15, 19 and 20 on the B side of the second edge connector and pins 16, 17, 21 and 22 on the A side; for the first edge connector, pin 11 of the A side of the socket connector corresponding to the first reset signal defined in PCIe is connected to pin 11 of the A side of the first edge connector; for the second edge connector, pin 32 of the A side of the socket connector corresponding to the reserved pin defined in PCIe is connected to pin 11 of the A side of the second edge connector; for the first edge connector, pins 13 and 14 of the A side of the socket connector corresponding to a pair of reference clock signals defined in PCIe are connected to pins 13 and 14 of the first edge connector; and for the second edge connector, pins 35 and 36 of the A side of the socket connector corresponding to the PCIe channel defined in PCIe are connected to pins 13 and 14 of the second edge connector.

[0007] In an embodiment, the socket connector is an x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is an x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and a reserved pin on the A side of the socket connector defined in PCIe is connected to pin 11 on the A side of the second edge connector corresponding to a reset signal defined in PCIe.

[0008] In an embodiment, the socket connector is an x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is an x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and the pin on the A side of the socket connector corresponding to the PCIe channel defined in PCIe is connected to pin 11 on the A side of the second edge connector corresponding to the reset signal defined in PCIe.

[0009] In an embodiment, the socket connector is an x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is an x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and two contact pins of the socket connector corresponding to signals of one or more PCIe channels are connected to pins 13 and 14 of the second edge connector corresponding to a pair of clock reference signals defined in PCIe.

[0010] In an embodiment, the number of contact pins in the socket connector is less than the number of contact pins defined in the PCIe connector. In an embodiment, the number of edge pins in the corresponding edge connector is less than the number of edge pins defined in the corresponding PCIe AIC.

[0011] In an embodiment, the receptacle connector is one of a x4 PCIe connector, a x8 PCIe connector, and a x16 PCIe connector, and one of the edge connectors is one of a x1 PCIe connector, a x4 PCIe connector, a x8 PCIe connector, and a x16 PCIe connector. In some embodiments, the total number of pins of one of the edge connectors is less than the total number of pins of the receptacle connector. In an embodiment, the number of edge connectors is one of 2, 4, and 8.

[0012] Aspects of the present disclosure provide a storage system. The storage system may include a PCIe AIC, including a multi-port memory system supporting a multi-port function, wherein the multi-port function enables a computer system to simultaneously access the same namespace of the multi-port memory system; a computer system, each including a PCIe connector; and an adapter cable, connecting the PCIe AIC to the PCIe connector of the computer system. The adapter cable includes a socket connector for receiving the PCIe AIC, the socket connector including contact pins defined for the PCIe connector; an edge connector for mounting to the PCIe connector, respectively, one of the edge connectors having an edge pin defined for the PCIe AIC; and a connector, connecting the socket connector to the edge connector, each connector connecting one of the contact pins to one of the edge pins.

[0013] In an embodiment, the multi-port memory system is a PCIe-based solid-state drive (SSD) that includes a memory controller that implements Non-Volatile Memory Express (NVMe) dual-port functionality.

[0014] Aspects of the present disclosure provide a method for setting up a storage system. The method may include connecting a PCIe AIC to a PCIe connector distributed on at least two system boards of a computer system by using an adapter cable. The PCIe AIC includes a multi-port memory system that supports a multi-port function, and the multi-port function enables the computer system to simultaneously access the same namespace of the multi-port memory system. The adapter cable may include a socket connector for receiving the PCIe AIC, the socket connector including contact pins defined for the PCIe connector; an edge connector for being respectively mounted to the PCIe connector, one of the edge connectors having an edge pin defined for the PCIe AIC; and a connector connecting the socket connector to the edge connector, each connector connecting one of the contact pins to one of the edge pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be increased or reduced for clarity of discussion.

[0016] Figure 1 A testing system 100 according to an embodiment of the present disclosure is shown.

[0017] Figures 2A-2DThe pinouts for x1, x4, x8, and x16 Peripheral Component Interconnect Express (PCIe) connectors defined in the PCIe standard in Table 200 are shown.

[0018] Figure 3A-3B Shows Figure 1 Table 300 of the pinout of the PCIe receptacle connector 131 (CN1) of the PCIe add-in card (AIC) adapter cable 130 in FIG.

[0019] Figure 4 Shows Figure 1 Table 400 of the pinout of the PCIe edge connector 132 (CN2) of the PCIe add-in card (AIC) adapter cable 130 in FIG.

[0020] Figure 5 Shows Figure 1 Table 500 of the pinout of the PCIe edge connector 133 (CN3) of the PCIe add-in card (AIC) adapter cable 130 in FIG.

[0021] Figure 6 A method 600 of configuring a storage system using the PCIe AIC adapter cable disclosed herein is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Figure 1 A test system 100 according to an embodiment of the present disclosure is shown. The test system 100 may be configured to perform a test of dual-port functionality of a memory system (e.g., a solid-state drive (SSD)). The test system 100 may include a peripheral component interconnect express (PCIe) add-in card (AIC) 110, two computers 140 and 145, and a specially designed PCIe AIC adapter cable.

[0023] The memory system 111 may be implemented on the PCIe AIC 110. The memory system 111 may include a memory controller 112 and one or more memory devices (not shown), such as NAND flash memory devices. Therefore, the memory system 111 may be an SSD whose operation is controlled by the memory controller 112. Figure 1In the example of , the memory controller 112 adopts the fast non-volatile memory (NVMe) protocol to implement the dual-port function. For example, the memory controller 112 can be configured to establish two NVMe controllers 113-114 to implement the dual-port function. In order to support the NVMe dual-port function, the PCIe interface 115 of the memory controller 112 can be configured to operate as two independent ports 116-117. The two independent ports 116-117 can provide two independent PCIe links. The two independent PCIe links are used as two separate transmissions for accessing the two NVMe controllers 113-114.

[0024] exist Figure 1 In the test setup of , the PCIe AIC 110 is used as an evaluation board (EVB) for testing various functions of the NVMe SSD controller 112. The PCIe AIC 110 is configured with a PCIe edge connector 118. Generally, it is desirable to configure the memory controller EVB with a PCIe AIC interface because the PCIe AIC interface is ubiquitous and the test environment based on the PCIe AIC is easy to establish. For testing the single-port function of NVMe on PCIe transmission, the PCIe AIC interface is sufficient. For example, the NVMe SSD PCIe AIC can be directly inserted into the PCIe socket connector on the system board of the host computer. However, the existing PCIe AIC interface cannot support the dual-port function of NVMe on PCIe transmission. For example, the signal generated from the PCIe interface 115 that implements the dual-port PCIe function cannot be transmitted to the two computers 140 and 145 via any existing PCIe AIC connector (e.g., PCIe socket connector or PCIe edge connector).

[0025] One solution to the above problem is to use a U.2 or U.3 interface. For example, the memory controller EVB interface can be changed from a PCIe AIC interface to a U.2 or U.3 interface. The modified EVB is then verified with custom equipment (such as a U.2 / U.3-based test platform).

[0026] The present disclosure provides an alternative solution. A specially configured PCIe AIC adapter cable 130 is used to connect the PCIe AIC 110 to two computers 140 - 145 to support dual port functional testing.

[0027] The PCIe AIC adapter cable 130 may include a PCIe socket connector 131, a first PCIe edge connector 132, and a second PCIe edge connector 133. The three connectors may be represented by CN1, CN2, and CN3, respectively, where "CN" stands for "connector." The socket connector 131 is electrically coupled to the two edge connectors 132-133 via a conductive cable 134 (providing an electrical connector 134). The conductive cable 134 may include two branches 134A and 134B. A first portion of the pins of CN1 131 is connected to a pin of CN2 132 via branch 134A. A second portion of the pins of CN1 131 is connected to a pin of CN3 133 via branch 134B. The two portions of the pins may overlap. The conductive cable 134 may take various suitable forms. For example, the conductive cable 134 may be a ribbon cable having two branches.

[0028] exist Figure 1 In the example of , CN1 131 can be a PCIe x8 socket connector defined in the PCIe standard. Therefore, CN1 131 can support 8 PCIe channels defined in the PCIe standard. CN2 and CN3 can each be a PCIex4 edge connector defined in the PCIe standard. Therefore, CN2 or CN3 can each support 4 PCIe channels defined in the PCIe standard. Examples of PCIe standards can include PCI Express Base Specification Revisions 4.0, 5.0 and 6.0, and PCI Express Card Electromechanical Specification Revisions 3.0, 4.0 and 5.0. These PCIe standards are developed and maintained by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). In the PCIe standard, the PCIe socket connector mentioned in this disclosure is referred to as a PCIe connector. The PCIe edge connector mentioned in this disclosure corresponds to a set of edge fingers (gold fingers) of the PCIe AIC defined in the PCIe standard.

[0029] As shown, the PCIe AIC adapter cable 130 is configured to support the transmission of x4 signals (signals of 4 PCIe channels) between CN1 131 on one side and CN2 132 and CN3 133 on the other side. Specifically, the pins (contact pins) of channel 0, channel 1, RefClk0 (reference clock signal 0) and PERST0 (reset signal 0) at CN1 131 are connected to the pins (edge ​​pins) of channel 0, channel 1, RefClk (reference clock signal) and PERST (reset signal) at CN2 132. The pins (contact pins) of channel 2, channel 3, RefClk1 (reference clock signal 1) and PERST1 (reset signal 1) at CN1 131 are connected to the pins (edge ​​pins) of channel 0, channel 1, RefClk and PERST at CN3 133.

[0030] The test system 100 is configured as a high availability storage system. The PCIe edge connector 118 of the PCIe AIC 110 can be inserted into the PCIe socket connector 131 of the PCIe AIC adapter cable 130. The two computers 140 and 145 can each be configured with a PCIe socket connector 141 and 142, respectively. The PCIe edge connectors 132-133 of the PCIe AIC adapter cable 130 can be inserted into the PCIe socket connectors 141-142, respectively. The two computers 140 and 145 can be referred to as host computers or hosts.

[0031] During operation, two independent PCIe links may be established: a first PCIe link between the PCIe interface 115 and the PCIe root complex of the computer 140, and a second PCIe link between the PCIe interface 115 and the PCIe root complex of the computer 145. The first PCIe link may pass through the port 116, the PCIe edge connector 118, the PCIe socket connector 131, the cable break 134A, the CN2 132, and the PCIe socket connector 141. The second PCIe link may pass through the port 117, the PCIe edge connector 118, the PCIe socket connector 131, the cable break 134B, the CN3 133, and the PCIe socket connector 142. The computer 140 (host computer 140) may communicate with the NVMe controller 114 via the first PCIe link. The computer 145 (host computer 145) may communicate with the NVMe controller 113 via the second PCIe link.

[0032] In an embodiment, the NVMe controllers 113-114 can share the same namespace (the same set of memory devices or memory cells). Two host computers 140 and 145 can access the same namespace at the same time for read or write operations. In this dual-port configuration, if one of the two PCIe links fails or one of the two hosts 140 and 145 fails, at least one of the two hosts 140 and 145 can still access the shared namespace, thereby providing high availability. In an example, the PCIe AIC adapter cable 130 can support at least the fifth generation PCIe transfer rate, such as 32.0GT / s (gigabit transfers per second) per channel in each direction.

[0033] Compared with U.2 and U.3 based solutions, the PCIe AIC based solution using the PCIe AIC adapter cable 130 has several advantages. First, the AIC interface can be used to verify the PCIe dual-port function without being limited by the U.2 / U.3 interface and customized verification equipment. Second, the adapter cable 130 is cheap, a common motherboard can be used to perform the verification process, and no customized U.2 / U.3 test equipment is required, thereby significantly reducing costs. Third, the test system can be easily set up at the user's workstation. Working with a large server rack of the U.2 / U.3 interface can be avoided. Fourth, the EVB maintains the AIC interface, which facilitates PCIe CTS (Compliance Test Specification) consistency testing.

[0034] Figures 2A-2D The pinouts for the x1, x4, x8, and x16 PCIe connectors defined in the PCIe standard are shown in Table 200. Table 200 has 5 columns. The first column shows the pin numbers of the pins of the PCIe connectors in both the A side and the B side. The second column shows the names of the signals on the B side associated with the corresponding pins on the B side. The third column shows a brief description of each signal on the B side. The fourth column shows the names of the signals on the A side associated with the corresponding pins on the A side. The fifth column shows a brief description of each signal on the A side.

[0035] The signals of the listed pins include two types of signals: PCIe signals and auxiliary signals. The signal names and descriptions of the auxiliary signals are identified in the shaded area. These auxiliary signals are used to facilitate the interface connection between the system board and the add-in card.

[0036] For each of the A and B sides of the PCIe connector, the pins listed are numbered from 1 to 82. The PCI Express interface pins PETpx, PETnx, PERpx, and PERnx are named with the following convention: "PE" stands for PCI Express High Speed, "T" stands for Transmitter, "R" stands for Receiver, "p" stands for Positive (+), and "n" stands for Negative (-). By default, the PETpx and PETnx pins (the transmitter differential pair of the connector) can be connected to the PCI Express transmitter differential pair on the system board, and to the PCI Express receiver differential pair on the add-in card. By default, the PERpx and PERnx pins (the receiver differential pair of the connector) can be connected to the PCI Express receiver differential pair on the system board, and to the PCI Express transmitter differential pair on the add-in card.

[0037] Additionally, the connector and add-in card are keyed (at the location of the mechanical key between pins 11 and 12) so that a smaller add-in card can fit into a larger connector. For example, a x1 card can plug into a x4, x8, and x16 connector. This is called up-plugging. Adjacent differential pairs are separated by two ground pins to manage connector crosstalk. Power pins (+3.3V, +3.3Vaux, and +12V) are defined.

[0038] Auxiliary signals are provided on the PCIe connector to assist certain system-level functions. These signals may not be used for data transmission in the PCIe architecture. Auxiliary signals may include differential reference clock signals REFCLK- / REFCLK+, reset signals PERST#, wake-up signals WAKE#, system management bus (SMBus) interface clock signals SMBCLK, SMBus interface address / data signals, JTAG signals (TRST#, TCLK, TDI, TDO, and TMS), AIC presence detection signals PRSNT1# and PRSNT2#, +3.3Vaux power rail signals, etc. PCIe AIC can use the reference clock on the PCIe connector. When PERST# is valid, all PCIe functions can remain reset.

[0039] Figure 3A / 3B / 4 / 5 shows Figure 1Tables 300-500 of the pin assignments of the PCIe receptacle connector 131 (CN1), the PCIe edge connector 132 (CN2), and the PCIe edge connector 133 (CN3) of the PCIe AIC adapter cable 130. In each of the tables 300 to 500, the first column shows the pin number of the B side, the second column shows the signal name of the B side, the third column is blank, the fourth column shows the pin number of the A side, and the fifth column shows the signal name of the A side.

[0040] CN1 131 physically has a x8 link width and has a sufficient number of pins to support 8 channels. CN2 132 and CN3 132 each physically have a x4 link width and can support 4 channels. Figure 1 or Figure 3A In the example of / 3B / 4 / 5, not all pins in each of CN1 131, CN2 132, or CN3 133 are used. Figure 3A As shown in Table 3B / 4 / 5, for pins without signal names, no signal will pass through the pins. For example, among many unused pins, pins 33-34 on the B side in Table 300 and pins 29-30 on the A side in Table 400 are not used and are not associated with signals.

[0041] The signals of the pins used in Tables 300-500 can be divided into two groups. The first group includes signals similar to the signals defined in Table 200 with respect to the corresponding pin numbers. The second group includes signals with respect to the corresponding pin numbers that are defined differently from the signals defined in Table 200. These differently defined signals are identified in the shaded areas in Tables 300 and 500.

[0042] Specifically, for the pin assignment of x8 CN1 131 in Table 300, by Figures 2A-2D By comparing the signals of the x8 connector shown in Table 200, it can be seen that, except for pins 32 (PERST#), 35 (REFCLK1+) and 36 (REFCLK1-) on the A side, the other used pins can be associated with signals similar to the signals indicated in the PCIe standard in whole or in part. Pin 32 on the A side is retained in Table 200 and is now used for the second reset signal PERST1# in Table 300. Pin 11 on the A side in Table 300 provides the first reset signal PERST#. Pins 35 and 36 on the A side are used for the signals of the receiver differential pair of channel 4 in Table 200, and are now used for the second pair of reference clock signals REFCLK1+ / -. Pins 13 and 14 on the A side in Table 300 provide the first pair of clock signals REFCLK+ / -.

[0043] For the pinout of x4 CN2 132 in Table 400, by Figures 2A-2D By comparing the signals of the x4 connector shown in , it can be seen that the pins used can be associated with signals similar to the signals indicated in the PCIe standard in whole or in part. When configuring the PCIe AIC adapter cable 130, the pins used in table 400 can be connected with the corresponding used pins in table 300 based on the pin number. For example, a pair of used pins with the same pin number in tables 400 and 300 can be connected through the electrical connection of cable 134.

[0044] For the pinout of x4 CN3 133 in Table 500, pins 14-15 and 19-20 used by the B side and pins 11, 13-14, 16-17 and 21-22 used by the A side have signals belonging to the second group of signals. These pins are associated with signals that are different from the signals defined in the PCIe standard. Pins 14-15 on the B side and pins 16-17 on the A side are used for PETp0, PETn0, PERp0 and PERn0 (which are signals for channel 0) in Table 200, and are now used for PETp2, PETn2, PERp2 and PERn2 (which are signals for channel 2). Therefore, in the PCIe AIC adapter cable 130, pins 14-15 on the B side of CN3 and pins 16-17 on the A side can be connected to pins 23-24 on the B side of CN1 and pins 25-26 on the A side, respectively, to facilitate the transmission of channel 2 signals. Similarly, in PCIe AIC adapter cable 130, pins 19-20 on the B side and pins 21-22 on the A side of CN3 can be connected to pins 27-28 on the B side and pins 29-30 on the A side of CN1, respectively, to facilitate transmission of channel 3 signals.

[0045] As shown in table 500, pin 11 of the A side of CN3 is associated with the second reset signal PERST1#. Therefore, when configuring the PCIe AIC adapter cable 130, pin 11 of the A side of CN3 is connected to pin 32 of the A side of CN1. Similarly, pins 13-14 of the A side of CN3 can be connected to pins 35-36 of the A side of CN3 to facilitate the transmission of the second pair of reference clock signals.

[0046] The remaining used pins in table 500 belong to the first group of signals. When configuring PCIe AIC adapter cable 130, these used pins can be connected to the corresponding used pins of CN1 in table 300. For example, a pair of pins with the same pin number in tables 500 and 300 can be connected.

[0047] Although the PCIe AIC adapter cable disclosed in this article is introduced in the context of SSD memory controller EVB testing, the application of the PCIe AIC adapter cable is not limited to the test environment. For example, the PCIe AIC adapter cable can be applied to storage systems in data centers or other suitable scenarios. Instead of PCIe AIC 110 and computers 140 and 145, PCIe AIC and computers in real-world applications can be configured to form a working system based on the PCIe AIC adapter cable disclosed in this article. In addition, instead of the SSD memory system, other types of memory systems implemented in the PCIe AIC can also utilize the PCIe AIC adapter cable, such as main memory, cache memory, backup memory, redundant memory, etc. The computer connected to the PCIe AIC via the PCIe AIC adapter cable can be a mobile phone, a laptop computer, a desktop computer, a server, a workstation, etc.

[0048] In addition, in addition to storage systems, PCIe AIC adapter cables can also be used for other types of systems, such as graphics cards, sound cards, network adapter cards, etc. In general, the PCIe AIC adapter cables disclosed herein can be useful for any system that implements PCIe AIC and uses PCIe as a transmission for connecting devices to multiple hosts. In some specific cases, the adapter cables disclosed herein are combined with communication protocols other than the PCIe protocol. For example, a device that implements a protocol other than PCIe can use the adapter cables disclosed herein to connect to multiple devices that implement the same protocol.

[0049] In various embodiments, the PCIe AIC adapter cable can have various variations. For example, for a PCIe socket connector (such as CN1 131) in a PCIe AIC adapter cable, any unused pins (e.g., pins 37 and 38 on the B side or pins 43 and 44 on the A side) can be used to transmit one or more reset signals (PERST#) or one or more pairs of reference clock signals (REFCLK+ / -). These pins are then connected to appropriate pins of one or more PCIe edge connectors (such as CN2 132 or CN3 133) in the PCIe AIC adapter cable. For example, pins 39 and 40 on the A side can be used to transmit reference clock signals REFCLK1+ / -. Pins 45 or 46 can be used to transmit reset signals PERST1#.

[0050] For another example, connectors 131-133 may be physically different from connectors defined in the PCIe standard. For example, unused pins may not exist in the connector. The size and / or shape of the connector may be different from that specified in the PCIe standard.

[0051] For dual-port applications, there can be various combinations of PCIe receptacle connectors (represented by CN-1) and PCIe edge connectors (represented by CN-2) with respect to link width. For example, in addition to Figure 1 In addition to the example combination of one x8 CN-1 to two x4 CN-2s, other combinations could include:

[0052] One x4 CN-1 to two x1 CN-2 (2 channels for dual port),

[0053] One x16 CN-1 to two x4 CN-2s (8 channels for dual port).

[0054] In addition, the PCIe AIC adapter cable disclosed herein is not limited to dual-port applications. For example, the PCIe AIC adapter cable can be used for applications such as 3 ports, 4 ports, 5 ports, 6 ports, 7 ports, 8 ports, etc. For example, for an N-port configuration in which a device implemented in the PCIe AIC is connected to N hosts, each host can be connected to a link width of at least one channel, and each host can be connected to at least one reset signal and a pair of reference clock signals. As long as CN-1 has a sufficient number of pins to support these signals, the PCIe AIC adapter cable can be appropriately configured to support N-port applications.

[0055] For example, in an 8-port application, CN-1 of a PCIe AIC adapter cable may be a x16 socket connector. The CN-2 connectors of a PCIe AIC adapter cable may each be a x1 or x4 edge connector. 8 channels are supported for connecting an 8-port device to 8 hosts. Each host is connected to a link of 1 channel. Eight groups of auxiliary signals may be connected from CN-1 to eight CN-2 connectors, respectively. Each group of auxiliary signals may include a reset signal PERST# and a pair of differential reference clock signals REFCLK+ / -.

[0056] Another possible variation of the PCIe AIC adapter cable disclosed herein may be that, instead of the connector (CN-1 or CN-2) given in the PCIe AIC adapter cable, another connector with a larger link width may be used to form a new PCIe AIC adapter cable. Figure 3A A PCIe AIC adapter cable defined by the signals in / 3B / 4 / 5 (which uses an x8 receptacle connector as CN-1) may alternatively use an x16 receptacle connector in place of the x8 receptacle connector. Alternatively, in the same example, an x8 edge connector may be used in place of the x4 edge connector for the x4 edge connector used as CN-2, assuming that the receptacle connector of the host computer can be adapted to receive the x8 edge connector.

[0057] In another example, multiple PCIe AIC adapter cables can be cascaded to match application scenarios. For example, the first PCIe AIC adapter cable C1 includes a x16 socket connector and two x8 edge connectors for transmission of 8 channels in two links each having a x4 width. The second PCIe AIC adapter cable C2 and the third PCIe AIC adapter cable C3 each include an x8 socket connector and two x4 edge connectors, similar to Figure 3A / 3B / 4 / 5. C1 can be connected to C2 and C3. For example, the two x8 edge connectors of C1 can be connected to the two x8 socket connectors of C2 and C3. For this application, the socket connectors of C2 and C3 can each have Figure 3A-3B The pinout of Table 300 in FIG. 300 is shown in FIG. 300 , where the auxiliary signals on pins 32, 35, and 35 can be provided from the x16 socket connector of C1. Therefore, the PCIe AIC adapter cable C1 can be configured to be able to transmit 4 sets of auxiliary signals, each set including a reset signal PERST# and a pair of differential reference clock signals REFCLK+ / -.

[0058] Figure 6 A method 600 for setting up a storage system using the PCIe AIC adapter cable disclosed herein according to an embodiment of the present disclosure is shown. The method 600 includes a step marked as S610. The method 600 starts from S601.

[0059] At S610, by using an adapter cable, the PCIe AIC can be connected to multiple PCIe connectors distributed on at least two system boards of a computer system. The PCIe AIC includes a multi-port memory system that supports a multi-port function. The multi-port function enables the computer system to simultaneously access the same namespace of the multi-port memory system. The adapter cable may include a socket connector for receiving the PCIe AIC. The socket connector includes contact pins defined for the PCIe connector.

[0060] The adapter cable also includes a plurality of edge connectors for mounting to the plurality of PCIe connectors, respectively. Each edge connector may have edge pins defined for the PCIe AIC. The adapter cable also includes electrical connectors for connecting the socket connector to the plurality of edge connectors. Each electrical connector connects one of the contact pins to one of the edge pins. Method 600 terminates at S699.

[0061] Although the various aspects of the present disclosure have been described in conjunction with the specific embodiments of the present disclosure proposed as examples, the examples may be substituted, modified and varied. Therefore, the embodiments set forth herein are intended to be illustrative rather than restrictive. Changes may be made without departing from the scope of the claims set forth below.

Claims

1. An adapter cable, comprising: a socket connector including contact pins defined for a peripheral component interconnect express (PCIe) connector; an edge connector having edge pins defined for a PCIe add-in card (AIC); and A connector connects the socket connector to the edge connector, each connector connecting one of the contact pins to one of the edge pins.

2. The adapter cable according to claim 1, wherein: The adapter cable is configured to connect a PCIe AIC to a plurality of PCIe connectors, the receptacle connector is configured to receive the PCIe AIC, and the edge connector is configured to mount to the PCIe connectors.

3. The adapter cable of claim 2, wherein: A first contact pin of the socket connector corresponding to at least one PCIe channel is connected to a first edge pin of a first edge connector of the edge connectors via a first connector of the connectors, A second contact pin of the socket connector that is different from the first contact pin and corresponds to at least one other PCIe channel is connected to a second edge pin of a second edge connector among the edge connectors, For one of the edge connectors, the third contact pin of the socket connector is connected to a third edge pin of the corresponding edge connector via one of the connectors, the third edge pin corresponding to a reset signal defined in PCIe, and For one of the edge connectors, a pair of fourth contact pins of the socket connector are connected to a pair of fourth edge pins of the corresponding edge connector via a connector in the connector, and the pair of fourth pins corresponds to a pair of reference clock signals defined in PCIe.

4. The adapter cable of claim 3, wherein: The receptacle connector is a x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is a x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; The first contact pins are pins 14, 15, 19 and 20 on the B side and pins 16, 17, 21 and 22 on the A side of the receptacle connector connected to the first edge pins, and the first edge pins are pins 14, 15, 19 and 20 on the B side and pins 16, 17, 21 and 22 on the A side of the first edge connector; The second contact pins are pins 23, 24, 27 and 28 on the B side and pins 25, 26, 29 and 30 on the A side of the receptacle connector connected to the second edge pins, and the second edge pins are pins 14, 15, 19 and 20 on the B side and pins 16, 17, 21 and 22 on the A side of the second edge connector; For the first edge connector, the pin 11 on the A side of the socket connector corresponding to the first reset signal defined in PCIe is connected to the pin 11 on the A side of the first edge connector; For the second edge connector, the pin 32 on the A side of the socket connector corresponding to the reserved pin defined in PCIe is connected to the pin 11 on the A side of the second edge connector; For the first edge connector, pins 13 and 14 of the A side of the socket connector corresponding to a pair of reference clock signals defined in PCIe are connected to pins 13 and 14 of the first edge connector; and For the second edge connector, pins 35 and 36 of the A side of the receptacle connector corresponding to the PCIe lane defined in PCIe are connected to pins 13 and 14 of the second edge connector.

5. The adapter cable of claim 3, wherein: The receptacle connector is a x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is a x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and The reserved pin on the A side of the socket connector defined in PCIe is connected to the pin 11 on the A side of the second edge connector corresponding to the reset signal defined in PCIe.

6. The adapter cable of claim 3, wherein: The receptacle connector is a x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is a x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and The pin on the A side of the socket connector corresponding to the PCIe channel defined in PCIe is connected to the pin 11 on the A side of the second edge connector corresponding to the reset signal defined in PCIe.

7. The adapter cable of claim 3, wherein: the receptacle connector is a x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is a x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and Two contact pins of the socket connector corresponding to signals of one or more PCIe lanes are connected to pins 13 and 14 of the second edge connector corresponding to a pair of clock reference signals defined in PCIe.

8. The adapter cable of claim 3, wherein: The number of contact pins in the socket connector is less than the number of contact pins defined in the PCIe connector.

9. The adapter cable of claim 3, wherein: The number of edge pins in the corresponding edge connector is less than the number of edge pins defined in the corresponding PCIe AIC.

10. The adapter cable of claim 3, wherein: The socket connector is one of a x4 PCIe connector, a x8 PCIe connector, and a x16 PCIe connector, and One of the edge connectors is one of a x1 PCIe connector, a x4 PCIe connector, a x8 PCIe connector, and a x16 PCIe connector.

11. The adapter cable of claim 3, wherein: The total number of pins of one of the edge connectors is less than the total number of pins of the receptacle connector.

12. The adapter cable of claim 3, wherein: The number of the edge connectors is one of 2, 4, and 8.

13. A storage system comprising: A peripheral component interconnect express (PCIe) add-in card (AIC) comprising a multi-port memory system supporting a multi-port function, the multi-port function enabling a computer system to simultaneously access a same namespace of the multi-port memory system; The computer systems each include a PCIe connector; as well as An adapter cable, the adapter cable connecting the PCIe AIC to the PCIe connector of the computer system, the adapter cable comprising: a socket connector including contact pins defined for a PCIe connector; an edge connector having edge pins defined for a PCIe AIC; and A connector connects the socket connector to the edge connector, each connector connecting one of the contact pins to one of the edge pins.

14. The storage system according to claim 13, wherein: The multi-port memory system is a PCIe-based solid-state drive (SSD) that includes a memory controller that implements Non-Volatile Memory Express (NVMe) dual-port functionality.

15. The storage system according to claim 13, wherein: A first contact pin of the socket connector corresponding to at least one PCIe channel is connected to a first edge pin of a first edge connector of the edge connectors via a first connector of the connectors, A second contact pin of the socket connector that is different from the first contact pin and corresponds to at least one other PCIe channel is connected to a second edge pin of a second edge connector among the edge connectors, For one of the edge connectors, the third contact pin of the socket connector is connected to a third edge pin of the corresponding edge connector via one of the connectors, the third edge pin corresponding to a reset signal defined in PCIe, and For one of the edge connectors, a pair of fourth contact pins of the socket connector are connected to a pair of fourth edge pins of the corresponding edge connector via a connector in the connector, and the pair of fourth pins corresponds to a pair of reference clock signals defined in PCIe.

16. The storage system according to claim 15, wherein: The receptacle connector is a x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is a x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; The first contact pins are pins 14, 15, 19 and 20 on the B side and pins 16, 17, 21 and 22 on the A side of the receptacle connector connected to the first edge pins, and the first edge pins are pins 14, 15, 19 and 20 on the B side and pins 16, 17, 21 and 22 on the A side of the first edge connector; The second contact pins are pins 23, 24, 27 and 28 on the B side and pins 25, 26, 29 and 30 on the A side of the receptacle connector connected to the second edge pins, and the second edge pins are pins 14, 15, 19 and 20 on the B side and pins 16, 17, 21 and 22 on the A side of the second edge connector; For the first edge connector, the pin 11 on the A side of the socket connector corresponding to the first reset signal defined in PCIe is connected to the pin 11 on the A side of the first edge connector; For the second edge connector, the pin 32 on the A side of the socket connector corresponding to the reserved pin defined in PCIe is connected to the pin 11 on the A side of the second edge connector; For the first edge connector, pins 13 and 14 of the A side of the socket connector corresponding to a pair of reference clock signals defined in PCIe are connected to pins 13 and 14 of the first edge connector; and For the second edge connector, pins 35 and 36 of the A side of the receptacle connector corresponding to the PCIe lane defined in PCIe are connected to pins 13 and 14 of the second edge connector.

17. The storage system according to claim 15, wherein: The receptacle connector is a x8 PCIe connector having 49 pins numbered from 1 to 49 on each of the A side and the B side, and one of the first edge connector and the second edge connector is a x4 PCIe connector having 32 pins numbered from 1 to 32 on each of the A side and the B side; and The reserved pin on the A side of the socket connector defined in PCIe is connected to the pin 11 on the A side of the second edge connector corresponding to the reset signal defined in PCIe.

18. A method for setting a storage system, comprising: A peripheral component interconnect express (PCIe) add-in card (AIC) is connected to a PCIe connector distributed on at least two system boards of a computer system by using an adapter cable, wherein: The PCIe AIC includes a multi-port memory system supporting a multi-port function, wherein the multi-port function enables the computer system to simultaneously access the same namespace of the multi-port memory system, and The adapter cable includes: a socket connector for receiving the PCIe AIC, the socket connector comprising contact pins defined for a PCIe connector; edge connectors for mounting to the PCIe connectors, respectively, one of the edge connectors having edge pins defined for the PCIe AIC; and A connector connects the socket connector to the edge connector, each connector connecting one of the contact pins to one of the edge pins.

19. The method according to claim 18, wherein: The multi-port memory system is a PCIe-based solid-state drive (SSD) that includes a memory controller that implements Non-Volatile Memory Express (NVMe) dual-port functionality.

20. The method according to claim 18, wherein: A first contact pin of the socket connector corresponding to at least one PCIe channel is connected to a first edge pin of a first edge connector of the edge connectors via a first connector of the connectors, A second contact pin of the socket connector that is different from the first contact pin and corresponds to at least one other PCIe channel is connected to a second edge pin of a second edge connector among the edge connectors, For one of the edge connectors, the third contact pin of the socket connector is connected to a third edge pin of the corresponding edge connector via one of the connectors, the third edge pin corresponding to a reset signal defined in PCIe, and For one of the edge connectors, a pair of fourth contact pins of the socket connector are connected to a pair of fourth edge pins of the corresponding edge connector via a connector in the connector, and the pair of fourth pins corresponds to a pair of reference clock signals defined in PCIe.

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