Wireless charging transmitter device

Abstract

The invention relates to a wireless charging transmitter device. The wireless charging transmitter device comprises a square wave signal generation circuit. The square wave signal generation circuit includes a first PMOS transistor switching circuit having a set of PMOS performance transistors and at least one PMOS functional transistor, and a second NMOS transistor switching circuit having a set of NMOS performance transistors and at least one NMOS functional transistor.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French patent application No. 2312033, filed on November 6, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to wireless charging circuits, and more particularly, wireless charging using near field communication (NFC) technology. Background Art

[0004] Wireless charging enables electronic devices to be charged using energy received not from a physical plug but from a magnetic field.

[0005] Using NFC technology for wireless charging has the advantage of not requiring too much space and allowing the use of antennas on printed circuit boards.

[0006] Wireless charging using NFC technology enables charging of wireless electronic devices to be performed within a short distance (eg, approximately 10 cm).

[0007] NFC technology is an open technology platform standardized in the standards ISO / IEC 18092 and ISO / IEC 21481, but combines many existing standards, such as, for example, the Type A and Type B protocols defined in the standard ISO-14443, which may be communication protocols that can be used in NFC technology. Wireless charging using NFC technology is defined by the NFC WLC ("Wireless Charging") specification version 2.0 published by the NFC Forum in October 2021.

[0008] In particular, NFC wireless charging enables charging of relatively small electronic devices such as wireless headphones and smart watches, fitness monitoring devices, or other electronic devices of the Internet of Things. For example, the electronic device can be charged by NFC wireless charging from a smart phone or from a dedicated charging station.

[0009] More specifically, NFC wireless charging is based on a charging transmitter device (also called a "poller") and on a power receiver device (also called a "listener"). The charging transmitter device is used to charge the power receiver device. As indicated above, the charging transmitter device can be, for example, a smartphone or a dedicated charging station.

[0010] The speed of wireless charging (especially NFC) depends on the power of the charging signal generated by the charging transmitter device. The more powerful the charging signal generated by the charging transmitter device, the faster the charging of the power receiver device is completed. It is particularly preferred to generate a charging signal with a relatively high power of between 1 Watt and 3 Watts.

[0011] In order to charge the charging receiver device, the charging signal is generated over a relatively long period during the service life of the charging transmitter, in particular more than 20,000 hours (i.e. 6 hours per day for 10 years). Thus, the charging signal may be generated over a period of several years during the service life of the charging transmitter, whereas the NFC communication is in the order of several hundred hours.

[0012] However, the fact that a charging signal with high power is generated for a long period of time may degrade components of a circuit that generates a charging signal for a charging transmitter device, and the degradation of these components may degrade the performance of wireless charging.

[0013] The power of the charging signal is defined by the current and voltage supplied to the antenna of the charging transmitter. The current is defined according to the impedance of the antenna and therefore cannot be increased. Furthermore, increasing the current involves increasing the temperature generated by the circuit that generates the charging signal. Therefore, in order to increase the power of the charging signal, the voltage supplied to the antenna of the charging transmitter should be increased.

[0014] Therefore, high voltage tolerant components should be used to increase the power of the charging signal. However, as we have seen before, the performance of these components will degrade over time.

[0015] In particular, the circuit for generating the charging signal includes a circuit for generating a differential square wave signal of a given frequency (in particular, 13.56 MHz in the context of NFC charging). The square wave signal corresponds to the charging signal after being shaped by an electromagnetic interference (EMI) filter. The circuit for generating the square wave signal includes a metal oxide semiconductor field effect transistor (MOSFET). These MOSFET devices are controlled in such a way as to generate the square wave signal.

[0016] These MOSFET devices are generally designed to obtain a relatively low impedance as the output of the charging signal generating circuit. However, such transistors are not configured to withstand high drain-source voltages, which would shorten their lifetime.

[0017] In order to reduce the loss of transistor performance over time, the length of the transistor's channel can be increased. However, this solution involves increasing the size of the charging signal generating circuit.

[0018] Therefore, there is a need to propose a solution for providing a charging signal with relatively high power while reducing the performance degradation of the circuit generating such a charging signal over time. Summary of the invention

[0019] According to one aspect, a wireless charging transmitter device is proposed, which includes: a generating circuit configured to generate a charging signal of a given frequency; an antenna configured to transmit the charging signal, the generating circuit including at least one square wave signal generating circuit, the square wave signal generating circuit including: a first PMOS transistor switching circuit including a group of PMOS performance transistors and at least one PMOS functional transistor, the at least one PMOS functional transistor having an output impedance greater than the output impedance of the PMOS performance transistor; a second NMOS transistor switching circuit including a group of NMOS performance transistors and at least one NMOS functional transistor, the at least one NMOS functional transistor having an output impedance greater than the output impedance of the NMOS performance transistor.

[0020] The PMOS and NMOS functional transistors are used to ensure the transition of the charging signal between the high state and the low state. These functional transistors are configured to withstand a relatively high drain-source voltage, for example, about 7.5 volts.

[0021] PMOS and NMOS performance transistors are used to ensure that the generating circuit has a relatively low output impedance.

[0022] In an advantageous embodiment, the PMOS performance transistor has a source configured to receive a power supply voltage, a drain connected to the drain of the NMOS performance transistor, and a gate configured to receive a first control signal. In addition, the NMOS performance transistor also has a source connected to a reference (e.g., ground) point and a gate configured to receive a second control signal.

[0023] Advantageously, the at least one PMOS functional transistor has a source configured to receive a power supply voltage, a drain connected to the drain of the at least one NMOS functional transistor, and a gate configured to receive a third control signal. In addition, the at least one NMOS functional transistor also has a source connected to a reference (ground) point and a gate configured to receive the third control signal.

[0024] In an advantageous embodiment, the PMOS performance transistor and the NMOS performance transistor are offset controlled relative to the at least one PMOS functional transistor and the at least one NMOS functional transistor to prevent simultaneous application of drain-source voltages and gate-source voltages greater than voltage thresholds defined on the PMOS performance transistor and the NMOS performance transistor.

[0025] The fact that the PMOS and NMOS performance transistors are controlled in an offset manner relative to the at least one PMOS functional transistor and the at least one NMOS functional transistor makes it possible to protect the performance transistors from the effects of high voltages. Thus, the drain-source voltage of the at least one PMOS functional transistor and the at least one NMOS functional transistor can be increased. In particular, the drain-source voltage can be increased over a long duration without significantly affecting the life of these functional transistors. Therefore, the functional transistors have a longer length relative to the performance transistors. This enables them to be more robust to aging, thereby maintaining good performance over time. Therefore, this makes it possible to increase the life of these functional transistors. The performance transistors themselves have a shorter length to minimize the surface area they occupy. The functional transistors occupy a smaller surface area relative to the entire generating circuit. Therefore, although the length of the functional transistor is longer than the length of the performance transistor, this does not result in a significant increase in the surface area of ​​the generating circuit.

[0026] Advantageously, the voltage threshold is between 0.4 Volt and 1 Volt.

[0027] Preferably, the wireless charging transmitter device further comprises a control circuit configured to generate a first control signal, a second control signal and a third control signal.

[0028] Advantageously, the wireless charging transmitter device further comprises a circuit for generating an initial clock signal. In addition, the control circuit comprises: a first delay circuit configured to receive the initial clock signal as an input and generate a first intermediate clock signal as an output that is time-shifted relative to the initial clock signal, the first intermediate clock signal corresponding to the third control signal; a second delay circuit configured to receive the first intermediate clock signal as an input and generate a second intermediate clock signal as an output that is time-shifted relative to the first intermediate clock signal; a first edge selection circuit configured to generate a first control signal by alternately selecting the initial clock signal and the second intermediate clock signal; and a second edge selection circuit configured to generate a second control signal by alternately selecting the initial clock signal and the second intermediate clock signal, the selection being inverted relative to the first edge selection circuit.

[0029] Preferably, the NMOS performance transistor has an output impedance between 0.5 ohm and 1 ohm.

[0030] Advantageously, the NMOS performance transistor has a channel length longer than or equal to 0.72 microns.

[0031] Preferably, the PMOS performance transistor has an output impedance between 0.5 ohm and 1 ohm.

[0032] Advantageously, the PMOS performance transistor has a channel length longer than or equal to 0.72 microns.

[0033] Preferably, the at least one NMOS functional transistor has an output impedance between 5 ohms and 10 ohms.

[0034] Advantageously, said at least one NMOS functional transistor has a channel length longer than or equal to 1.44 micrometers, in particular two to three times longer than the channel length of an NMOS performance transistor.

[0035] Preferably, the at least one PMOS functional transistor has an output impedance between 5 ohms and 10 ohms.

[0036] Advantageously, said at least one PMOS functional transistor has a channel length longer than or equal to 1.44 micrometers, in particular two to three times longer than the channel length of a PMOS performance transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other advantages and features of the invention will become apparent from a reading of the detailed description of the embodiments (which are not limiting in any sense) and of the accompanying drawings, in which:

[0038] Figure 1 An embodiment of a wireless charging transmitter device is illustrated;

[0039] Figure 2 An embodiment of a charging signal generating circuit is illustrated;

[0040] Figure 3 An embodiment of a square wave signal generating circuit is illustrated;

[0041] Figure 4 An embodiment of a control circuit is illustrated; and

[0042] Figure 5 Signal waveforms of a clock signal and a square wave signal generated by a square wave signal generating circuit are shown. DETAILED DESCRIPTION

[0043] Figure 1 An embodiment of a wireless charging transmitter device WLCD is illustrated.

[0044] The charging transmitter device WLCD includes a power source (not shown), a circuit CGSR for generating a charging signal, an electromagnetic interference filter FLT, an impedance matching circuit IMTCH, and an antenna ANT.

[0045] The power source may be, for example, a battery.

[0046] The charging signal generating circuit CSGR is configured to generate a charging signal from a power source. The charging signal includes two square wave signals with opposite phases, which are transmitted to the antenna ANT via the electromagnetic interference filter FLT and then the impedance matching circuit IMTCH.

[0047] The electromagnetic interference filter FLT is a circuit configured to attenuate or even eliminate electromagnetic interference in the square wave signal generated by the charging signal generating circuit CSGR.

[0048] The impedance matching circuit IMTCH is configured to match the impedance seen by the antenna ANT.

[0049] The antenna ANT is configured to transmit the charging signal generated by the charging signal generating circuit CSGR.

[0050] The charging signal may be received by the charging receiver device LST, thereby enabling wireless charging of the battery of the charging receiver device LST.

[0051] Figure 2 An embodiment of a charging signal generating circuit CSGR as described above is illustrated. The generating circuit CSGR comprises two square wave signal generating circuits ECRCT1, ECRCT2 with opposite phases. The circuits ECRT1 and ECRCT2 are configured to generate square wave signals RFO1 and RFO2 with opposite phases, respectively. These square wave signals RFO1 and RFO2 form the charging signal which is then transmitted by the antenna ANT in a sinusoidal shape after filtering.

[0052] Each circuit ECRCT1, ECRCT2 corresponds to a circuit of an inverter chain. Therefore, each square wave signal generating circuit ECRCT1, ECRCT2 includes a PMOS transistor switch circuit PCOM and an NMOS transistor switch circuit NCOM. A PMOS transistor is a P-type metal oxide semiconductor field effect transistor (MOSFET). An NMOS transistor is an N-type MOSFET.

[0053] Figure 3 An embodiment of the final stage of these circuits ECRCT1 and ECRCT2 is shown.

[0054] In particular, the PMOS transistor switch circuit PCOM includes a first group of PMOS transistors, referred to as performance transistors PMOSP, and a PMOS transistor referred to as function transistors PMOSF.

[0055] In particular, the function transistor PMOSF is used to ensure the transition of the charging signal between the low state and the high state. The function transistor PMOSF has a relatively high impedance. For example, the function transistor PMOSF has an output impedance between 5 ohms and 10 ohms, such as about 8 ohms. In order to obtain such an output impedance, the function transistor PMOSF has a channel length longer than or equal to 1.44 microns.

[0056] The performance transistor PMOSP is configured to improve the performance of the switch circuit. The performance transistor PMOS has a relatively low impedance. For example, the performance transistor PMOSP has an output impedance between 0.5 ohms and 1 ohm, such as about 0.5 ohms. In order to obtain such an output impedance, each performance transistor PMOSP has a channel length longer than or equal to 0.72 microns, in particular, two to three times shorter than the channel length of the functional transistor PMOSF.

[0057] The NMOS transistor switch circuit includes a first group of NMOS transistors (referred to as performance transistors NMOSP), and at least one other NMOS transistor (referred to as function transistor NMOSF).

[0058] In particular, a function transistor NMOSF is also used to ensure the transition between the low state and the high state of the charging signal. The function transistor NMOSF has a relatively high impedance. For example, the function transistor NMOSF has an output impedance between 5 ohms and 10 ohms, for example, about 8 ohms. In order to obtain such an output impedance, the function transistor NMOSF has a channel length longer than or equal to 1.44 microns.

[0059] The performance transistor NMOSP is configured to improve the performance of the switch circuit. The performance transistor NMOSP has a relatively low impedance. For example, the performance transistor NMOSP has an output impedance between 0.5 ohms and 1 ohm, such as about 0.5 ohms. In order to obtain such an output impedance, each performance transistor NMOSP has a channel length longer than or equal to 0.72 microns, in particular, two to three times shorter than the channel length of the functional transistor PMOSF.

[0060] Function transistor PMOSF and function transistor NMOSF are configured to switch with respect to performance transistor PMOSP and performance transistor NMOSP offset. In this way, function transistor PMOSF and function transistor NMOSF can withstand high drain-source voltage and gate-source voltage at the same time. However, function transistor PMOSF and function transistor NMOSF are configured to withstand such high voltage. In fact, function transistor PMOSF and function transistor NMOSF have larger gate size to withstand aging.

[0061] The function transistor PMOSF has a source, a drain and a gate. The source of the function transistor PMOSF is connected to the power supply VDD. The gate of the function transistor PMOSF is configured to receive the signal DCLK1.

[0062] The function transistor NMOSF has a source, a drain and a gate. The drain of the function transistor NMOSF is connected to the drain of the function transistor PMOSF. The drain of each function transistor NMOSF is connected to the drain of the function transistor PMOSF. The source of the function transistor NMOSF is connected to a reference point, in particular to ground GND. The gate of the function transistor NMOSF is configured to receive a signal DCLK1.

[0063] The performance transistor PMOSP and the performance transistor NMOSP are configured to be switched offset relative to the functional transistor PMOSF and the functional transistor NMOSF. In this way, the performance transistor PMOSP and the performance transistor NMOSP are not subjected to high drain-source voltages and gate-source voltages at the same time. This makes it possible to prevent operating conditions that may cause hot carrier injection, which may degrade the performance of the performance transistor PMOSP and the performance transistor NMOSP.

[0064] The performance transistor PMOSP has a source, a drain and a gate. The source of the performance transistor PMOSP is connected to a power supply VDD. The gate of the performance transistor PMOS is configured to receive a signal DCLK0.

[0065] The performance transistor NMOSP has a source, a drain and a gate. The drain of each performance transistor NMOSP is connected to the drain of the performance transistor PMOSP. The source of the performance transistor NMOSP is connected to a reference point, in particular to ground GND. The gate of the performance transistor NMOSP is configured to receive a signal DCLK2.

[0066] The charging signal generating circuit further comprises a control circuit COMC configured to control transistors PMOSP, PMOSF and NMOSP, NMOSF in the switch circuits PCOM, NCOM.

[0067] Figure 4 An embodiment of the control circuit COMC is illustrated. The control circuit COMC is configured to receive a clock signal CLK_RFO1. The clock signal CLK_RFO1 may be provided by a radio frequency oscillator of the wireless charging transmitter device WLCD. The radio frequency oscillator may include a phase locked loop.

[0068] The control circuit COMC comprises a first delay circuit DLY1. The first delay circuit DLY1 is configured to receive the clock signal CLK_RFO1 and generate a signal DCLK1 offset by a duration t1 relative to the clock signal CLK_RFO1. The duration t1 can be adjusted via a first digital control signal PDLY1. The duration t1 can be between 0.5 nanoseconds and 10 nanoseconds.

[0069] The control circuit includes a second delay circuit DLY2. The second delay circuit DLY2 is configured to receive the signal DCLK1 and generate a signal TCLK2 that is offset by a duration t2 relative to the signal DCLK1 and by a sum of durations t1 and t2 relative to the clock signal CLK_RFO1. The duration t2 can be adjusted via a digital control signal PDLY2. The duration t2 can be between 0.5 nanoseconds and 10 nanoseconds.

[0070] As described below, the duration t1 makes it possible to prevent cross conduction between the performance transistors PMOSP, NMOSP and the functional transistors PMOSF, NMOSF of each square wave signal generating circuit ECRCT. The duration t2 makes it possible to improve the life of the performance transistors PMOSP, NMOSP and the functional transistors PMOSF, NMOSF of each square wave signal generating circuit by preventing relatively high drain-source voltages and gate-source voltages from being provided simultaneously.

[0071] The control circuit further comprises a first edge selection circuit EDGS1. The first edge selection circuit is configured to receive a clock signal CLK_RFO1 and a signal TCLK2. The first edge selection circuit EDGS1 is configured to deliver as an output a signal DCLK0 corresponding to either the clock signal CLK_RFO1 or the signal TCLK2. In particular, the first edge selection circuit EDGS1 comprises a set of logic gates for generating the signal DCLK0.

[0072] The control circuit further comprises a second edge selection circuit EDGS2. The second edge selection circuit EDGS2 is configured to receive the clock signal CLK_RFO1 and the signal TCLK2. The second edge selection circuit EDGS2 is configured to deliver as an output a signal DCLK2 corresponding to either the clock signal CLK_RFO1 or the signal TCLK2. In particular, the second edge selection circuit EDGS2 comprises a set of logic gates for generating the signal DCLK2.

[0073] The control circuit includes a first buffer circuit BUF0. The first buffer circuit is configured to receive an unbuffered signal DCLK0 and deliver the buffered signal DCLK0 on a gate of a performance transistor PMOS.

[0074] The control circuit includes a second buffer circuit BUF1. The second buffer circuit is configured to receive an unbuffered signal DCLK1 and deliver the buffered signal DCLK1 on a gate of a function transistor PMOSF and a gate of a function transistor NMOSF.

[0075] The control circuit includes a third buffer circuit BUF2. The third buffer circuit is configured to receive the unbuffered signal DCLK2 and deliver the buffered signal DCLK2 on the gate of the performance transistor NMOSP.

[0076] Therefore, the control circuit generates three control signals DCLK0, DCLK1 and DCLK2. Signal DCLK0 is used to control the performance transistor PMOSP. Signal DCLK1 is used to control the function transistor PMOSF and control the function transistor NMOSF. Signal DCLK2 is used to control the performance transistor NMOSP.

[0077] Figure 5 Signals DCLK0 , DCLK1 , and DCLK2 are shown, as well as a square wave signal generated by a square wave signal generating circuit during a clock cycle.

[0078] If the Figure 5 As shown in FIG. 1 , at each clock cycle CLK_RFO1, the control circuit is configured to generate a signal DCLK0 having:

[0079] - delaying the falling edge FE1 of the signal DCLK1 by the duration t2 and delaying the falling edge FE0 of the signal DCLK2 by the sum of the durations t1 and t2 (thus generating the signal DCLK0 by selecting the falling edge of the signal TCLK2 and then generating the signal DCLK2 by selecting the falling edge FCLK0 of the signal CLK_RFO1), and

[0080] - Advance rising edge RE0 by the duration t1 relative to rising edge RE1 of signal DLCK1 and by the sum of durations t1 and t2 relative to rising edge RE2 of signal DCLK2 (thus, signal DCLK0 is generated by selecting rising edge RCLK0 of signal CLK_RFO1 and then signal DCLK2 is generated by selecting rising edge of signal TCLK2).

[0081] Therefore, before the falling edge FE2 of the signal DCLK2, the output impedance IMP of the square wave signal generating circuit corresponds to the output impedance of the performance transistor, and is therefore a relatively low impedance LIMP. Between the falling edge FE2 of the signal DCLK2 and the falling edge FE0 of the signal DCLK0, the output impedance IMP of the square wave signal generating circuit corresponds to the medium impedance MIMP between the output impedance of the functional transistor and the output impedance of the performance transistor. Between the falling edge FE0 of the signal DCLK0 and the rising edge RE0 of the signal DCLK0, the output impedance IMP of the square wave signal generating circuit corresponds to the output impedance of the performance transistor, and is therefore a relatively low impedance LIMP. Between the rising edge RE0 of the signal DCLK0 and the rising edge RE2 of the signal DCLK2, the output impedance IMP of the square wave signal generating circuit corresponds to the medium impedance MIMP between the output impedance of the functional transistor and the output impedance of the performance transistor. After the rising edge RE2 of the signal DCLK2, the output impedance IMP of the square wave signal generating circuit corresponds to the output impedance of the performance transistor, and is therefore a relatively low impedance LIMP.

[0082] In this way, the functional transistor PMOSF and the functional transistor NMOSF are configured to receive a relatively high drain-source voltage and a gate-source voltage at the same time. Therefore, the functional transistor PMOSF and the functional transistor NMOSF can operate under conditions that may cause hot carrier injection. However, the functional transistor PMOSF and the functional transistor NMOSF are configured to withstand these operating conditions. In fact, these functional transistors NMOSF, PMOSF have a gate size large enough to withstand these operating conditions.

[0083] The performance transistor PMOSP and the performance transistor NMOSP are configured to prevent receiving a relatively high drain-source voltage and a gate-source voltage at the same time. Therefore, the performance transistor PMOSP and the performance transistor NMOSP are prevented from operating under conditions that may cause hot carrier injection. Therefore, performance transistors with relatively high output impedance can be used. This enables the use of performance transistors NMOSP, PMOSP with reduced length relative to the functional transistors NMOSF, PMOSF.

[0084] In this way, the voltage of the charging signal generated by the circuit CSGR can be increased. Thus, a charging signal with a relatively high power can be transmitted, for example between 1 Watt and 3 Watts. Thus, this power can be obtained with a charging signal generation circuit having transistors with an average relatively short channel length. In fact, in such a generation circuit, only the functional transistors NMOSF, PMOSF have a sufficiently long channel length to withstand the relatively high gate-source voltage and drain-source voltage at the same time, and the performance transistors NMOSP, PMOSP have a shorter channel length.

Claims

1. A wireless charging transmitter device, comprising: A signal generating circuit configured to generate a charging signal of a given frequency; as well as an antenna configured to transmit the charging signal; The signal generating circuit includes at least one square wave signal generating circuit, including: a first PMOS transistor switch circuit including a group of PMOS performance transistors and at least one PMOS functional transistor, the at least one PMOS functional transistor having an output impedance greater than an output impedance of the PMOS performance transistor; as well as The second NMOS transistor switch circuit includes a group of NMOS performance transistors and at least one NMOS functional transistor, wherein the at least one NMOS functional transistor has an output impedance greater than an output impedance of the NMOS performance transistor.

2. The device according to claim 1: wherein the PMOS performance transistor has a source configured to receive a power supply voltage, a drain, and a gate configured to receive a first control signal; and The NMOS performance transistor has a source connected to a reference point, a drain connected to the drain of the PMOS performance transistor, and a gate configured to receive a second control signal.

3. The device according to claim 2: wherein the at least one PMOS functional transistor has a source configured to receive a power supply voltage, a drain, and a gate configured to receive a third control signal; and The at least one NMOS functional transistor has a source connected to a reference point, a drain connected to a drain of the at least one PMOS functional transistor, and a gate configured to receive the third control signal.

4. The apparatus according to claim 3, further comprising a control circuit configured to: The PMOS performance transistor and the NMOS performance transistor are offset controlled relative to the at least one PMOS functional transistor and the at least one NMOS functional transistor to prevent simultaneous application of a drain-source voltage and a gate-source voltage greater than at least one voltage threshold defined on the PMOS performance transistor and the NMOS performance transistor. The device of claim 4 , wherein the voltage threshold is between 0.4 volts and 1 volt. 6 . The apparatus of claim 3 , further comprising a control circuit configured to generate the first control signal, the second control signal, and the third control signal.

7. The apparatus of claim 6, wherein the control circuit comprises: a first delay circuit configured to receive an initial clock signal and generate a first intermediate clock signal shifted in time relative to the initial clock signal, the first intermediate clock signal corresponding to a third control signal; a second delay circuit configured to receive the first intermediate clock signal and generate a second intermediate clock signal shifted in time relative to the first intermediate clock signal; A first edge selection circuit configured to generate a first control signal by alternately selecting an initial clock signal and a second intermediate clock signal; as well as a second edge selection circuit configured to generate a second control signal by alternately selecting the initial clock signal and the second intermediate clock signal; Wherein the alternating selection for the second edge selection circuit is inverted relative to the alternating selection for the first edge selection circuit.

8. The apparatus of claim 1, wherein the NMOS performance transistor has an output impedance between 0.5 ohms and 1 ohm.

9. The apparatus of claim 8, wherein the NMOS performance transistor has a channel length longer than or equal to 0.72 microns.

10. The apparatus of claim 1, wherein the PMOS performance transistor has an output impedance between 0.5 ohms and 1 ohm.

11. The device of claim 10, wherein the PMOS performance transistor has a channel length longer than or equal to 0.72 microns.

12. The apparatus of claim 1, wherein the at least one NMOS functional transistor has an output impedance between 5 ohms and 10 ohms.

13. The device of claim 12, wherein the at least one NMOS functional transistor has a channel length longer than or equal to 1.44 microns.

14. The apparatus of claim 1, wherein the at least one PMOS functional transistor has an output impedance between 5 ohms and 10 ohms.

15. The apparatus of claim 14, wherein the at least one PMOS functional transistor has a channel length longer than or equal to 1.44 microns.

16. An apparatus comprising: an output node configured to output a charging signal for application to the first terminal of the antenna; a first inverter circuit including a PMOS performance transistor switch coupled in series with an NMOS performance transistor switch at an output node, wherein a gate of the PMOS performance transistor switch is driven by a first clock signal and a gate of the NMOS performance transistor switch is driven by a third clock signal; a second inverter circuit including a PMOS functional transistor switch coupled in series with the NMOS functional transistor switch at an output node, wherein a gate of the PMOS functional transistor switch and a gate of the NMOS functional transistor switch are driven by a second clock signal; as well as A control circuit is configured to generate a first clock signal, a second clock signal and a third clock signal according to a reference clock signal, wherein: A leading edge of the second clock signal is delayed relative to a leading edge of the first clock signal, and a leading edge of the third clock signal is delayed relative to a leading edge of the second clock signal; as well as A trailing edge of the first clock signal is delayed relative to a trailing edge of the second clock signal, and a trailing edge of the second clock signal is delayed relative to a trailing edge of the third clock signal.

17. The device according to claim 16, wherein: The PMOS functional transistor switch has an output impedance greater than an output impedance of the PMOS performance transistor switch; and The NMOS functional transistor switch has an output impedance greater than the output impedance of the NMOS performance transistor switch.

18. The device according to claim 16: wherein the sources of the PMOS performance transistor switch and the NMOS performance transistor switch are coupled to a power supply voltage node and a reference voltage node, respectively; and The sources of the PMOS functional transistor switch and the NMOS functional transistor switch are coupled to the power supply voltage node and the reference voltage node respectively.

19. The apparatus of claim 16, wherein the delay of the leading edge and the delay of the trailing edge of the first clock signal, the second clock signal, and the third clock signal are configured to prevent simultaneous application of a drain-source voltage and a gate-source voltage greater than at least one voltage threshold defined on a PMOS performance transistor switch and an NMOS performance transistor switch.

20. The apparatus of claim 16, wherein the control circuit comprises: a first delay circuit configured to receive a reference clock signal and generate a first intermediate clock signal shifted in time relative to an initial clock signal, wherein the third control signal is derived from the first intermediate clock signal; a second delay circuit configured to receive the first intermediate clock signal and generate a second intermediate clock signal shifted in time relative to the first intermediate clock signal; a first edge selection circuit configured to generate a first control signal by alternately selecting a reference clock signal and a second intermediate clock signal; as well as a second edge selection circuit configured to generate a second control signal by alternately selecting the reference clock signal and the second intermediate clock signal; Wherein the alternating selection for the second edge selection circuit is inverted relative to the alternating selection for the first edge selection circuit.

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