A method for suppressing bus current ripple in a four-inverter system

Abstract

The present invention discloses a method for suppressing bus current ripple in a four-inverter system, which relates to the field of power electronics technology. The suppression method includes collecting load currents for each inverter, determining zero vectors and active vectors; adjusting the vector action sequence to obtain 16 combinations; after shifting the fundamental waves of any two inverters by 60°, updating the zero vectors according to the bus currents generated by the first active vector and the second active vector to obtain the 17th combination; for all combinations, shifting the carrier phases of two inverters and then obtaining the same number of combinations; using the effective value cost function of the bus current to traverse all combinations and selecting the combination that minimizes its value to suppress the bus current ripple. The suppression method can fully suppress the bus current ripple in the four-inverter system, greatly reduce the volume of the DC bus capacitor in the four-inverter system, and improve the power density and reliability of the four-inverter system.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and particularly to a method for suppressing bus current ripple in a four-inverter system. Background Art

[0002] With the increasing requirements for power levels in some applications, the limitations of traditional single-inverter systems have gradually emerged. Therefore, four-inverter systems have been applied in fields with relatively high requirements for power levels, such as aerospace, rail transit, low-altitude economic aircraft, ship propulsion, and wind power generation.

[0003] Compared with single-inverter systems, four-inverter systems have the following advantages:

[0004] (1) Achieving high-power output with low-power power electronic device ratings:

[0005] Due to the limitation of single-phase current, the power of a single-inverter system is restricted by the voltage level. If the power level is to be increased, higher requirements are imposed on the withstand voltage level of the inverter. In contrast, a four-inverter system can increase the power level of the drive system by increasing the number of phases under the condition of limited single-phase current.

[0006] (2) Using different modulation strategies for different inverters to achieve better performance:

[0007] The modulation strategy used in a single-inverter system is unique, which restricts the performance improvement of the drive system. In contrast, different inverters in a four-inverter system can use different modulation strategies to achieve better performance, such as high power quality and high power density.

[0008] (3) High reliability:

[0009] When a certain phase winding or power electronic device in the inverter system fails, the remaining windings cannot construct an equivalent rotating magnetic motive force, and immediate shutdown or an additional auxiliary circuit is required for fault-tolerant control. In contrast, when a certain phase winding or power electronic device in a four-inverter system fails, the system can ensure fault-tolerant operation only by changing the control algorithm without adding an auxiliary circuit.

[0010] The DC bus capacitor is an important part of the four-inverter system, which plays a role in stabilizing the DC bus voltage, absorbing ripple current, and suppressing voltage spikes. However, the DC bus capacitor is bulky, which will reduce the power density of the drive system.

[0011] For a four-inverter system, when using traditional modulation strategies, the DC bus current ripple is four times that of a single-inverter system, requiring a larger volume of capacitors, which further reduces the power density. In addition, the DC bus capacitor is a device prone to failure, and the heating problem caused by the large DC bus current ripple is the main reason for the failure of the DC bus capacitor.

[0012] Therefore, a suitable modulation strategy needs to be used to reduce the DC bus current ripple to improve the lifespan of the DC bus capacitor. To reduce the DC bus current ripple, it is mainly achieved by staggering the carrier phases of different inverters or adjusting the vector order of different inverters.

[0013] However, existing research focuses on dual-inverter drive systems. For a four-inverter system, the existing technology uses a method of staggering the carrier phases by 90° in sequence to reduce the DC bus current ripple. In this suppression method, only carrier phase shift is considered, and the DC bus current ripple of the four-inverter system cannot be fully suppressed.

[0014] In summary, the means used in the existing technology to suppress the DC bus current ripple in a four-inverter system are relatively single, and the suppression effect is poor. Summary of the Invention

[0015] To solve the above technical problems existing in the prior art, the present invention aims to provide a method that can effectively suppress the DC bus current ripple in a four-inverter system. Therefore, the present invention proposes a method for suppressing the bus current ripple in a four-inverter system, which fully suppresses the DC bus current ripple without increasing the switching frequency through two-step prediction of the DC bus current effective value.

[0016] Specifically, the present invention provides a method for suppressing the bus current ripple in a four-inverter system, and the technical solution includes:

[0017] In a four-inverter system, the DC buses connected to the DC terminals of each inverter are connected in parallel, and the AC terminals are connected to a load; a capacitor is connected in parallel with the DC power supply;

[0018] The method for suppressing the bus current ripple includes the following steps:

[0019] Step S1: For each inverter, collect the load current, determine the zero vector, the first active vector, and the second active vector; adjust the vector action order in each inverter to obtain 16 candidate pulse combinations;

[0020] Step S2: After shifting the fundamental wave of the load current of any two inverters by 60°, obtain the load current relationship of the four inverters;

[0021] Update the first active vector and the second active vector of each inverter according to the load current relationship, and update the zero vector according to the bus currents generated by the first active vector and the second active vector respectively, so as to obtain the 17th candidate pulse combination;

[0022] Step S3: For all candidate pulse combinations, select two inverters to perform a 90° carrier phase shift, and then obtain the same number of candidate pulse combinations;

[0023] Step S4: Use the bus current RMS value function F i Traverse all candidate pulse combinations, and select the candidate pulse combination that minimizes the bus current RMS value function to suppress the bus current ripple of the four-inverter system.

[0024] Compared with the prior art, the technical solution provided by the present invention fully considers three degrees of freedom, namely the vector action order, the fundamental wave phase of the load current, and the carrier phase in the four-inverter system. By traversing the DC bus current RMS value function, the optimal pulse combination is determined and applied to the inverter, which can fully suppress the bus current ripple of the four-inverter system, greatly reduce the volume of the DC bus capacitor of the four-inverter system, and improve the power density and reliability of the four-inverter system. Brief Description of the Drawings

[0025] Figure 1 It is a topological schematic diagram of a four-inverter system in an embodiment of the present invention.

[0026] Figure 2 It is a flowchart of a method for suppressing bus current ripple in a four-inverter system in an embodiment of the present invention.

[0027] Figure 3 It is a space vector diagram of the first inverter in an embodiment of the present invention.

[0028] Figure 4 It is a switching pulse diagram of the first inverter without adjusting the vector action order within one switching period in an embodiment of the present invention.

[0029] Figure 5 It is a switching pulse diagram of the 17th candidate pulse combination within one switching period in an embodiment of the present invention.

[0030] Figure 6 It is a switching pulse diagram of the 4th candidate pulse combination within one switching period in an embodiment of the present invention.

[0031] Figure 7 It is a carrier diagram of different inverters after carrier phase shift in an embodiment of the present invention.

[0032] Figure 8This is the DC bus current diagram generated by the 17th candidate pulse combination within one switching cycle in an embodiment of the present invention. Detailed implementation manners

[0033] Hereinafter, the technical solutions provided by the present invention will be further elaborated in detail in conjunction with embodiments and drawings.

[0034] Embodiment 1:

[0035] The topology of the four-inverter system adopted in this embodiment is as Figure 1 shown.

[0036] The four-inverter system includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The four inverters share a DC power supply U dc and a DC bus capacitor C . The DC buses of the first inverter, the second inverter, the third inverter, and the fourth inverter are respectively connected in parallel, and the capacitor C is connected in parallel with the DC power supply. i dc1 , i dc2 , i dc3 and i dc4 are respectively the DC bus currents generated by the four inverters, i dc is the total DC bus current, I dc is the input current of the DC power supply. The AC terminals of the first inverter, the second inverter, the third inverter, and the fourth inverter are connected with a load, and the load is an inductive load or a motor. Among them, R is the load resistance, L is the load inductance.

[0037] The four-inverter system can supply power to four independent inductive loads or motors. The load voltage and load current expressions are:

[0038] ;

[0039] ;

[0040] In the formula, x is the serial number of the inverter, x = 1, 2, 3, 4; u Ax is the phase A voltage of the load corresponding to the x th inverter, u Bx is the phase B voltage of the load corresponding to the x th inverter,u Cx is the C-phase voltage of the load corresponding to the x th inverter, i Ax is the A-phase current of the load corresponding to the x th inverter, i Bx is the B-phase current of the load corresponding to the x th inverter, i Cx is the C-phase current of the load corresponding to the xth inverter; U and I are the amplitudes of the phase voltage and the phase current respectively, is the angular frequency of the load current, , f is the fundamental frequency of the load current, is the angle between the phase voltage and the phase current.

[0041] The flowchart of the method for suppressing the bus current ripple of the four-inverter system is as Figure 2 shown.

[0042] First, 17 candidate pulse combinations of the four inverters need to be determined. Taking the first inverter as an example, the vectors of the first inverter are S A1 S B1 S C1 = 100, 110, 010, 011, 001, 101, 000 and 111, S k (k = A1, B1, C1) represents the states of the switching tubes of each phase leg. S k = 1 indicates that the upper switching tube is on and the lower switching tube is off. S k = 0 indicates that the lower switching tube is on and the upper switching tube is off.

[0043] The DC bus current i dc1 generated by the first inverter has the following expression:

[0044] ;

[0045] Based on the above expression, substituting different S A1 S B1 S C1 gives the expressions of the corresponding DC bus current i dc1 as shown in Table 1.

[0046] Table 1 Relationship Table between DC Bus Current and Switching States of Bridge Arm Switch Tubes

[0047] 。

[0048] To better illustrate the generation mechanism of the DC bus current, take f = 100 Hz, cos = 0.95, ωt = 5π / 8 as an example. Substitute ωt and into the load current expression to calculate and obtain i A1 、 i B1 、 i C1 to be 0.997 I 、 -0.434 I 、 -0.563 I 。

[0049] Furthermore, determine the sector and active vectors according to SVPWM (Space Vector Pulse Width Modulation). The space vector diagram of the first inverter is as shown in Figure 3 . It can be seen that the space vector diagram is composed of six sectors, namely Sector - Ⅰ, Sector - Ⅱ, Sector - Ⅲ, Sector - Ⅳ, Sector - Ⅴ, and Sector - Ⅵ. Within each sector, the reference voltage vector is synthesized by two adjacent active vectors and the zero vector. To determine the active vector and zero vector used in the current switching period, it is necessary to judge the sector where the reference voltage vector is located. Let the component of the reference voltage vector on the αβ axis be u α and u β , and define three intermediate variables U ref1 , U ref2 , U ref3 :

[0050] ;

[0051] ;

[0052] ;

[0053] Define three variables U 、 V 、 W , and their values satisfy the following formula:

[0054] If U ref1 > 0, then U = 1, otherwise U = 0; If U ref2 > 0, then V = 1, otherwise V = 0; If U ref3 > 0, then W = 1, otherwise W = 0.

[0055] Let J = 4 W + 2 V + U , to obtain J The relationship with the sector is shown in Table 2.

[0056] Table 2 Sector Correspondence Table

[0057] .

[0058] Taking the modulation index as 0.9, U dc = 80V as an example. When the modulation index is 0.9, the amplitude of the reference voltage when using space vector pulse width modulation is 80×0.577×0.9 = 41.544V.

[0059] Assume the d-axis voltage u d = 0V, and the q-axis voltage u q = 41.544V. Calculate the component of the reference voltage vector on the αβ axis, and the formula is as follows:

[0060] ;

[0061] In the formula, θ e is the electrical angle of the motor. In this embodiment, θ e = 13π / 8. Through the above formula, it can be calculated that: u α = 38.38V, u β = 15.9V.

[0062] Furthermore, three intermediate variables U ref1 > 0, U ref2 > 0,U ref3 <0, then J = 3, that is, the reference voltage is located in Sector - Ⅰ.

[0063] From Figure 3 it can be known that vectors 100 and 110 in Sector - Ⅰ are selected as active vectors, where vector 100 is the first active vector and vector 110 is the second active vector.

[0064] Furthermore, the durations of the first active vector and the second active vector T 100 and T 110 are respectively:

[0065] ;

[0066] It can be obtained that T 100 and T 110 are respectively 0.55 T s and 0.35 T s . Among them, T s is a switching period.

[0067] Therefore, ωt when = 5π / 8, the switching pulses of a switching period are as Figure 4 shown, and no adjustment is made to the switching sequence at this time.

[0068] According to Table 1, the i dc1 generated by the first active vector, the second active vector, and vector 000 are respectively i A1 , - i C1 and 0. Therefore, Figure 4 the i dc1 in regions - 1, - 2, and - 3 of are respectively 0, 0.997I, and 0.563I. It can be found that the magnitudes of the DC - bus current ripples in regions - 1, - 2, and - 3 are irregular.

[0069] Among them, after determining the vector action sequence, in a switching period, the DC - bus current generated by the vectors acting on both sides constitutes region - 1, the DC - bus current generated by the vectors acting in the middle constitutes region - 3, and other regions constitute region - 2, as Figure 4 shown.

[0070] The vector action sequence of different inverters will be adjusted, laying a foundation for suppressing the DC bus current ripple.

[0071] If the DC bus current within one switching period after adjustment satisfies Region - 1 ≥ Region - 2 ≥ Region - 3, it is defined as " i dc +", that is, the maximum DC bus current value is in the middle.

[0072] If the DC bus current within one switching period after adjustment satisfies Region - 1 ≤ Region - 2 ≤ Region - 3, it is defined as " i dc -", that is, the minimum DC bus current value is in the middle.

[0073] Since each inverter can operate in the " i dc +" state or the " i dc -" state, the four - inverter system thus has 2 4 = 16 possible candidate pulse combinations, as shown in Table 3.

[0074] Table 3 Possible Pulse Combinations after Adjusting the Vector Action Sequence

[0075] 。

[0076] Furthermore, determine the 17th candidate pulse combination.

[0077] After shifting the fundamental wave of the load current of the second inverter by 60°, the relationship between the load currents of the first inverter and the second inverter is:

[0078] ;

[0079] When the phase ωt of the first inverter is 5π / 8, the phase ωt of the second inverter is 7π / 24. Substituting ωt = 7π / 24 into the load current expression, we calculate i A2 、 i B2 、 i C2 to be 0.563I, - 0.997I, and 0.434I respectively. According to the SVPWM principle, ωt when it is 7π / 24, the reference voltage of the second inverter is in Sector VI. Select vectors 100 and 101 as active vectors, where vector 100 is the first active vector and vector 101 is the second active vector. At a modulation index of 0.9, the durations of the first active vector and the second active vectorT 100 and T 101 are 0.35 T s and 0.55 T s respectively. According to Table 1, the i dc2 generated by the first active vector and the second active vector are i A2 and - i B2 respectively.

[0080] Furthermore, it can be found that for the first inverter, the DC bus current generated by the first active vector i A1 is less than the DC bus current - i C1 generated by the second active vector. Therefore, 111 is selected as the zero vector. For the second inverter, the DC bus current generated by the first active vector i A2 is less than the DC bus current - i B2 generated by the second active vector. Therefore, 000 is selected as the zero vector.

[0081] Furthermore, the pulses of the third inverter are the same as those of the first inverter, and the pulses of the fourth inverter are the same as those of the second inverter, obtaining the 17th candidate pulse combination as shown in Figure 5 Figure.

[0082] It should be noted that the topology of the four-inverter system adopted in the present invention is fixed, and the positions of the first inverter, the second inverter, the third inverter, and the fourth inverter are equivalent. Therefore, a 60° phase shift of the fundamental wave of the load current can be performed for any two inverters, and then the load current relationship with the remaining two inverters can be determined one by one.

[0083] After determining the 17 candidate pulse combinations, in order to prevent the candidate pulse combinations that increase the switching frequency from entering the next prediction of the effective value of the DC bus current, the value function F s is first used to preliminarily screen the candidate pulse combinations. The value function F s expression is:

[0084] ;

[0085] In the formula, y is the phase sequence number, f c is the control frequency, Ky is the number of switch actions. As long as it makes F s not equal to 0, that is, the candidate pulse combination that will increase the switching frequency will be eliminated. Taking the candidate pulse combination -4 as an example, the switching pulses of different inverters are as Figure 6 shown.

[0086] When the control frequency f c is 10 kHz, the number of switch actions of the A-phase inverter is 1, the number of switch actions of the B-phase inverter is 2, and the number of switch actions of the C-phase inverter is 0. It is calculated that F s = 3.33. So the candidate pulse combination -4 is eliminated because it will make F s not equal to 0 and does not participate in the next prediction of the effective value of the DC bus current. For the candidate pulse combination -17 in Figure 6 , one switch action occurs in two phases of each inverter, and no switch action occurs in one phase. It is calculated that F s is equal to 0 and is retained for the next prediction of the effective value of the DC bus current.

[0087] After traversing the value function in the first step, the remaining n kinds of candidate pulse combinations can enter the next prediction of the effective value of the DC bus current. In order to fully suppress the DC bus current ripple, shifting the carrier phases of two inverters in the four-inverter system by 90° can obtain n kinds of candidate pulse combinations, and use the value function F i to traverse 2n kinds of candidate pulse combinations. The carriers of different inverters after carrier phase shift are as Figure 7 shown.

[0088] Among them, for the 1st to 16th candidate pulse combinations, if the vector action sequences of the 4 inverters are the same, then shift the carrier phases of any 2 inverters by 90°; otherwise, shift the carrier phases of any 2 inverters with different vector action sequences by 90°; for the 17th candidate pulse combination, otherwise shift the carrier phases of any 2 inverters with different fundamental wave phases by 90°.

[0089] After determining all 2 n kinds of candidate pulse combinations participating in the prediction of the effective value of the DC bus current, use the value function F i to traverse. The expression of the DC bus current value function F i is:

[0090] ;

[0091] In the formula, z is the serial number of the DC bus current, N is the number of different DC bus currents within one switching period, x is the serial number of the inverter, T z is the action time of the z-th DC bus current, T s is the switching period, S Ax-z is for generating the z -th switching state of the switch tube on the A-phase bridge arm of the x -th inverter when generating the DC bus current, S Bx-z is for generating the z -th switching state of the switch tube on the B-phase bridge arm of the x -th inverter when generating the DC bus current, S Cx-z is for generating the z -th switching state of the switch tube on the C-phase bridge arm of the x -th inverter when generating the DC bus current.

[0092] Taking the candidate pulse combination -17 as an example, the generated DC bus current ripple is as Figure 8 shown. It can be seen that there are three values for the DC bus current i dc within one switching period, which are 1.994 I , 3.12 I and 3.988 I respectively, and the corresponding T z also contains three. Further, using the formula F i the effective value of the DC bus current of the current candidate pulse combination can be calculated. When the traversal of 2 n kinds of candidate pulse combinations is completed, making F i achieve the minimum value S and applying the pulse combination to the inverter can fully suppress the bus current ripple of the four-inverter system.

[0093] Optionally, the candidate pulse combinations that will increase the switching frequency can be excluded without using the switching frequency cost function F s , and the DC bus current cost function F i can be directly used to select the most suitable pulse combination.

[0094] As can be seen from the above embodiments, compared with the prior art, the technical solution provided by the present invention fully considers three degrees of freedom, namely the vector action sequence, the fundamental wave phase of the load current, and the carrier phase, in the four-inverter system. By traversing the value function of the effective value of the DC bus current, the optimal pulse combination is determined to act on the inverter, which can fully suppress the bus current ripple of the four-inverter system, greatly reduce the volume of the DC bus capacitor of the four-inverter system, and improve the power density and reliability of the four-inverter system. Further, by traversing the value function of the switching frequency, the pulse combinations that cause an increase in the switching frequency are eliminated, which can reduce the cost consumption and computational complexity of the four-inverter system.

Claims

1. A bus current ripple suppression method for a four-inverter system, characterized in that: In the four-inverter system, the DC busbars connected to the DC ends of the inverters are connected in parallel, and the AC ends are connected to the loads; the capacitors are connected in parallel to the DC power supply; and the following steps are included: Step S1: for each inverter, collect the load current, determine the zero vector, the first active vector and the second active vector; adjust the vector action sequence in each inverter to obtain 16 candidate pulse combinations; Step S2: After the load current fundamental waves of any two inverters are phase-shifted by 60°, the load current relationship of the four inverters is obtained; updating a first active vector and a second active vector of each inverter according to the load current relationship, and updating a zero vector according to bus currents generated by the first active vector and the second active vector, so as to obtain a 17th candidate pulse combination; Step S3: for all candidate pulse combinations, select two inverters to perform a 90° carrier phase shift, and then obtain the same number of candidate pulse combinations; Step S4: Use bus current effective value function F i Traversing all candidate pulse combinations, selecting the candidate pulse combination that minimizes the bus current effective value value function, so as to suppress the bus current ripple of the four-inverter system; The vector action sequence in each inverter is adjusted to obtain 16 candidate pulse combinations, including: For each inverter, by adjusting the action order of the zero vector, the first active vector and the second active vector, two kinds of pulses are obtained, namely, the maximum DC bus current value is centered and the minimum DC bus current value is centered; Select one pulse from each inverter to combine, and get 16 candidate pulse combinations; The updating of the zero vector according to the bus currents generated by the first active vector and the second active vector specifically includes: For each inverter, when the DC bus current generated by the first active vector is greater than that of the second active vector, 000 is selected as the zero vector; when the DC bus current generated by the first active vector is less than that of the second active vector, 111 is selected as the zero vector; when the DC bus current generated by the first active vector is equal to the second active vector, if the inverter does not perform load current fundamental phase shift, 000 is selected as the zero vector, otherwise 111 is selected as the zero vector; The bus current effective value function F i The expression is as follows: ； In the formula, z is the DC bus current serial number, N is the number of different DC bus currents in one switching cycle, x is the inverter serial number, T z For the z The action time of the DC bus current is T s is the switching cycle, S Ax-z To produce the z The DC bus current x The on / off state of the switch tube on the A phase bridge arm of each inverter, S Bx-z To produce the z The DC bus current x The on / off state of the switch tube on the B phase bridge arm of each inverter, S Cx-z To produce the z The DC bus current x The on / off status of the switch tube on the C-phase bridge arm of each inverter; i Ax For the x The A-phase current of the load corresponding to each inverter, i Bx For the x The B-phase current of the load corresponding to each inverter, i Cx For the x The C-phase current of the load corresponding to each inverter; Among them, if the upper switch tube in a certain phase bridge arm is turned on and the lower switch tube is turned off, the switching state is 1; if the upper switch tube in a certain phase bridge arm is turned off and the lower switch tube is turned on, the switching state is 0.

2. A bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: The zero vector, the first active vector and the second active vector are all represented by 3-bit binary numbers, corresponding to the on / off states of the switch tubes on the A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm of the inverter; For any phase bridge arm, if the upper switch is turned on and the lower switch is turned off, the value of the corresponding digit is 1; If the upper switch is turned off and the lower switch is turned on, the value of the corresponding digit is 0.

3. The bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: The selecting of two inverters to perform a 90° carrier phase shift specifically includes: For the 1st to 16th candidate pulse combinations, if the vector action order of the four inverters is the same, the carrier phases of any two inverters are shifted by 90°, otherwise the carrier phases of any two inverters with different vector action orders are shifted by 90°; For the 17th candidate pulse combination, the carrier phases of any two inverters with different fundamental wave phases are shifted by 90°.

4. The bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: After step S2, the method further includes: using a switching frequency value function F s Traverse 17 candidate pulse combinations; for any candidate pulse combination, if F s ≠0, then remove it.

5. A bus current ripple suppression method for a quad-inverter system according to claim 4, characterized in that: The switching frequency value function F s The expression is as follows: ； In the formula, x is the inverter serial number, y is the phase sequence number, f c To control the frequency, K y is the number of switching actions of the corresponding inverter in one switching cycle.

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