Configurable control of two-level and three-level buck converters

Abstract

The invention relates to configurable control of two-level and three-level buck converters. Apparatuses, devices, and methods for operating a voltage converter are described. The semiconductor device may include a switching circuit and a controller. The switching circuit may include a plurality of switching elements. The controller may determine an operating mode of the switching circuit. In response to the operating mode indicating a two-level operating mode, the controller may program the switching circuit to operate as a two-level voltage converter. In response to the operating mode indicating a three-level operating mode, the controller may program the switching circuit to operate as a three-level translator.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and more particularly to topologies and methods for a controller that can be programmed to operate a voltage converter circuit as a two-level buck converter or a three-level buck converter. Background Art

[0002] Voltage converters, such as buck converters and boost converters, can be used to convert an input voltage into an output voltage with different voltage levels. Buck converters or buck converters can be used in applications where a direct current (DC) voltage needs to be reduced. Buck converters can receive an input voltage and provide a buck output voltage. Boost converters or boost converters can be used in applications where a DC voltage needs to be increased. Boost converters can receive an input voltage and provide a boosted output voltage. The voltage converter can include a plurality of switches at the input of the voltage converter, wherein the switches can be turned on and off by a pulse width modulation (PWM) control signal. The duty cycle of the PWM control signal can determine the output voltage of the voltage converter. When the switches are turned on and off, they modulate the DC input voltage, and the modulated voltage can be provided to the inductor. The inductor can be connected to a capacitor, and the modulated voltage can be a time-varying voltage that causes the inductor to create a time-varying current. The interaction of the inductor and capacitor with the time-varying voltage and current can produce an almost constant output voltage with a DC level different from the input voltage.

[0003] A voltage converter with two switches can switch an inductor between two voltages - an input voltage and ground. A multi-level voltage converter can include more than two switches and can switch an inductor between more than two voltages - an input voltage, at least one intermediate voltage between the input voltage and ground, and ground. For example, a three-level voltage converter can include four switches and can switch an inductor between three voltages: an input voltage, an intermediate voltage equivalent to half the input voltage, and ground. A multi-level voltage converter includes at least one flying capacitor that switches between two states - a charged state and a discharged state. Summary of the invention

[0004] In one embodiment, a semiconductor device is generally described. The semiconductor device may include a switching circuit and a controller. The controller may be configured to determine an operating mode of the switching circuit. The controller may be further configured to program the switching circuit to operate as a two-level voltage converter in response to an operating mode indicating a two-level operating mode. The controller may be further configured to program the switching circuit to operate as a three-level voltage converter in response to an operating mode indicating a three-level operating mode.

[0005] In one embodiment, a semiconductor device is generally described. The semiconductor device may include a modulator configured to generate a plurality of control signals to operate a switch circuit. The semiconductor device may also include a flying capacitor balancer configured to control a flying capacitor voltage of a flying capacitor connected to the switch circuit. The semiconductor device may also include a controller configured to determine an operating mode of the switch circuit. The controller may be further configured to program the modulator to generate a first group of control signals for operating the switch circuit as a two-level voltage converter in response to an operating mode indicating a two-level operating mode. The controller may be further configured to connect the flying capacitor balancer to the modulator in response to an operating mode indicating a three-level operating mode to control the flying capacitor voltage of the flying capacitor, and program the modulator to generate a second group of control signals for operating the switch circuit as a three-level voltage converter.

[0006] In one embodiment, a method for configuring a voltage converter is described. The method may include determining an operating mode of a switching circuit. The method may also include, in response to the operating mode indicating a two-level operating mode, programming the switching circuit to operate as a two-level voltage converter. The method may also include, in response to the operating mode indicating a three-level operating mode, programming the switching circuit to operate as a three-level converter.

[0007] Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings.In the drawings, like reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is an exemplary diagram of a semiconductor device that can implement configurable control of a two-level buck converter and a three-level buck converter in one embodiment.

[0009] Figure 1B An example integrated circuit that can implement configurable control of a two-level buck converter and a three-level buck converter in one embodiment.

[0010] Figure 1C is a diagram of another integrated circuit that can implement configurable control of a two-level buck converter and a three-level buck converter in one embodiment.

[0011] Figure 2 is an example diagram showing details of a controller that may be used for configurable control of a two-level buck converter and a three-level buck converter in one embodiment.

[0012] Figure 3 is a flow chart illustrating a process of implementing configurable control of a two-level buck converter and a three-level buck converter in one embodiment. DETAILED DESCRIPTION

[0013] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0014] Figure 1A is an example diagram of a semiconductor device that can implement configurable control of a two-level buck converter and a three-level buck converter in one embodiment. Figure 1A . The system 100 may include at least a switch circuit 104, a controller 120, and a gate driver 122. The system 100 may be implemented in a semiconductor package including a semiconductor device. The controller 120 may be, for example, a microcontroller including processing hardware and a storage device. The controller 120 may include a modulator 130 configured to generate one or more pulse width modulation (PWM) signals PWM1, PWM2, PWM3, PWM4.

[0015] The switch circuit 104 may include four transistors Q1, Q2, Q3, Q4, an inductor L1, and a flying capacitor Cfly. The transistors Q1, Q2, Q3, Q4 may be metal oxide semiconductor field effect transistors (MOSFETs), gallium nitride (GaN) transistors, or similar transistors. In one embodiment, depending on the number of switches and various internal signals and components in the switch circuit 104, the controller 120, and / or the modulator 130, the switch circuit 104 may implement more than one multi-level buck converter (e.g., a step-down DC-DC voltage converter).

[0016] The controller 120 may include a modulator 130 configured to generate PWM signals PWM1, PWM2, PWM3, PWM4. The controller 120 may be configured to provide the PWM signals PWM1, PWM2, PWM3, PWM4 to the gate driver 122. The gate driver 122 may be configured to generate a plurality of drive signals S1, S2, S3, S4 using PWM1, PWM2, PWM3, PWM4, respectively. The drive signals S1, S2, S3, S4 may be voltage signals representing voltage levels that may turn on or off the transistors Q1, Q2, Q3, Q4. The gate driver 122 may apply the drive signals S1, S2, S3, S4 to the gates of the transistors Q1, Q2, Q3, Q4 to drive the transistors Q1, Q2, Q3, Q4, respectively.

[0017] exist Figure 1A In one embodiment shown, the switch circuit 104 may further include switch elements or switches labeled SW1 and SW2. The controller 120 may be configured to control the switches SW1 and SW2 to implement the switch circuit 104 as a two-level buck converter or a three-level buck converter. The controller 120 may turn on the switch SW1 and turn off the switch SW2 to implement the switch circuit 104 as a three-level buck converter, so that the switch node between the transistors Q2 and Q3 may be connected to the inductor L. The controller 120 may turn off the switch SW1 and turn on the switch SW2 to implement the switch circuit 104 as a two-level buck converter, so that the switch node between the transistors Q1 and Q2 may be connected to the inductor L. In addition, when the switch circuit 104 is implemented as a two-level buck converter, the PWM signals PWM3 and PWM4 may be constant high (HIGH) voltages, which may maintain the transistors Q3 and Q4 in an on state (e.g., Q3 and Q4 will not switch), so that a conductive path may be formed between Vin and the transistor Q2. In another embodiment, when the switch circuit 104 is implemented as a two-level buck converter, Vin may be directly connected to the drain of Q2 , and the gates of transistors Q3 , Q4 may be left floating.

[0018] In one embodiment, when the switch circuit 104 implements a two-level buck converter, the transistors Q1 and Q2 can be switched at different times to generate a desired voltage level and output the desired voltage level as the output voltage Vout. The voltage at the switch node between the internal transistors Q1 and Q2 can alternate between Vin and ground (GND) or 0V.

[0019] In one embodiment, when the switch circuit 104 implements a three-level buck converter, the transistors Q1, Q2, Q3, and Q4 can be switched at different times to generate a desired voltage level and output the desired voltage level as the output voltage Vout. The timing and duty cycle of the drive signals S1, S2, S3, and S4 can control and maintain the flying capacitor voltage VCfly (e.g., the voltage across the flying capacitor Cfly) at half of the input voltage Vin, such as Vin / 2. By maintaining the flying capacitor voltage at Vin / 2, the voltage at the switch node between the internal transistors Q2 and Q3 can alternate between Vin, Vin / 2, and ground (GND) or 0V.

[0020] In conventional systems, in order to configure the voltage converter to operate as a two-level buck converter or a three-level buck converter, a separate controller is required to control and operate the voltage converter in two different buck converter modes. For example, a conventional system uses a controller capable of generating a PWM signal to operate the voltage converter as a two-level buck converter, and uses a different controller capable of generating a PWM signal to operate the voltage converter as a three-level buck converter. Note that different controllers are used in such conventional systems because conventional controllers are typically not designed to control two-level buck converters and three-level buck converters. For example, a controller for controlling a two-level buck converter may not be able to control the flying capacitor voltage, which is critical to the operation of a three-level buck converter. Conventional controllers can typically only control one of a two-level buck converter and a three-level buck converter.

[0021] In order to construct an integrated circuit (IC) that can be configured to implement a two-level buck converter or a three-level buck converter, the modulator 130 of the controller 120 can be configured or modified to allow the controller 120 to operate the two-level buck converter and the three-level buck converter through flying capacitor voltage control. In one aspect, the modulator 130 can be a modulator with relatively fast transient response, variable switching frequency during load transients, and improved light load efficiency due to its ability to automatically change the switching frequency. The modulator 130 can be configured to respond to input voltage and output load transients while controlling the switching frequency and duty cycle of the PWM signal generated by the modulator 130. In order to simultaneously control the switching frequency and duty cycle of the PWM signal, the modulator 130 may include a voltage window generator 132 for controlling the on and off times and the switching frequency of the PWM signal.

[0022] For example, the modulator 130 may synthesize an alternating current (AC) signal representing the output inductor ripple current at the inductor L1 and use a voltage window generator 132 for the AC signal. When the AC signal reaches an upper limit of the voltage window set by the voltage window comparator 132, the modulator 130 may turn off the PWM control signal, and when the AC signal reaches a lower limit of the voltage window, the modulator 130 may turn on the PWM control signal. The voltage window may depend on a compensation signal, such as Figure 1B and Figure 1CThe AC signal is a signal marked as COMP in FIG. Since the AC signal is a composite signal, the AC signal can have a relatively large amplitude and can be noise-free. Therefore, the modulator 130 can operate with lower phase jitter than a conventional hysteresis mode modulator. In addition, when the compensation signal rises during the dynamic response, the modulator 130 can change the switching frequency by temporarily turning on the PWM signal earlier and more frequently, which allows a higher control loop bandwidth than a conventional fixed frequency PWM modulator at the same steady-state switching frequency.

[0023] In order to configure the controller 120 to have the ability to operate a two-level buck converter and a three-level buck converter, the modulator 130 may include a Cfly balancer 134, which may be a circuit configured to generate an offset voltage. The Cfly balancer 134 may provide an offset voltage to the voltage window generator 132 to modify the voltage window. The modified voltage window may allow the modulator 130 to control VCfly so as to maintain VCfly at Vin / 2. In addition, the Cfly balancer 134 may be connected or disconnected to the modulator 130 depending on a programming pin on the controller 120 that indicates the operating mode of the switching circuit 104. In one embodiment, the controller 120, the flying capacitor balancer 134, and the voltage window 132 may be monolithically integrated in a single die. Reference Figure 1B and Figure 1C , the programming pin marked PROG can be connected to the programming resistor R P The controller 120 can be configured to measure R by reading the programming pin PROG. P , and based on R P To determine whether to operate the switch circuit 104 as a two-level buck converter or a three-level buck converter. For example, the first register 150 in the controller 120 may store a first R corresponding to operating the switch circuit 104 as a two-level buck converter. P The second register 152 in the controller 120 may store a second R value corresponding to operating the switch circuit 104 as a three-level buck converter. P In response to reading R from the programming pin PROG P , the controller 120 can read the R P The first register 150 and / or the second register 152 are compared. If the R P is approximately equal to the first value stored in the first register 150, the controller 120 may program or configure the switch circuit 104 as a two-level buck converter and disconnect the Cfly balancer 134 from the modulator 130. Pis approximately equal to the second value stored in the second register 152 , the controller 120 may program or configure the switch circuit 104 as a three-level buck converter and connect the Cfly balancer 134 to the modulator 130 .

[0024] Furthermore, in one embodiment, the switch circuit 104 can be configured to operate as a two-level buck converter or a three-level buck converter during the design phase of the printed circuit board (PCB) layout. Therefore, once the switch circuit 104 is programmed as a two-level buck converter or a three-level buck converter, the resistor R at the programming pin PROG P Can be fixed and can be constant. Figure 1B In the example embodiment shown, the switch circuit 104 is configured to operate as a three-level buck converter. Figure 1C In the example embodiment shown, the switch circuit 104 is configured to operate as a two-level buck converter.

[0025] Figure 2 is an example diagram showing details of a controller that may be used for configurable control of a two-level buck converter and a three-level buck converter in one embodiment. Figure 2 The description can refer to the components of Figure 1. Figure 2 In the illustrated embodiment, the modulator 130 of the controller 120 in FIG. 1 may include at least a voltage window generator 132, a Cfly balancer 134, a loop selector 206, an SR latch 208, and a PWM signal generator 220. The loop selector 206 may be a circuit configured to receive various parameters (such as an input voltage Vin, an output voltage Vout, an inductor current through the inductor L1, and a switch node voltage from the switch circuit 104), and generate a compensation signal Vcomp. The window generator 132 may use Vcomp to set a voltage window ranging between an upper limit Vwin+ and a lower limit Vwin-. The current flowing through the inductor L, designated as IL, may be fed back to the controller 120 and / or the modulator 130, and the gain amplifier gm may convert IL into a voltage Vgm. The SR latch 208 may be configured to control the timing of the PWM generator 220 generating the PWM signal so that there are no multiple PWM signals in one PWM cycle. The PWM generator 220 may be configured to generate PWM signals in a specific sequence depending on whether the switch circuit 104 is programmed as a two-level buck converter or a three-level buck converter. When Vgm reaches the upper limit Vwin+ of the voltage window, the modulator 130 may attenuate the control signal generated by the PWM generator 220, and when Vgm reaches the lower limit Vwin- of the voltage window, the modulator 130 may increase or strengthen the control signal generated by the PWM generator 220.

[0026] In one embodiment, the Cfly balancer 134 may be configured to generate a signal V3 having an offset voltage, wherein the duty cycle of the signal V3 may depend on the flying capacitor voltage VCfly. Thus, the signal V3 may vary according to the variation of VCfly. The Cfly balancer 134 may include a comparator 216 that may determine the difference between VCfly and Vin / 2 and output the difference as an error voltage V E The Cfly balancer 134 can generate the signal V3 as a E and a predefined proportional voltage V S The amplitude of the PWM signal varies between S The amplitude of the signal V3 can be defined. The scaled voltage V S Can be fixed, error voltage V E Can change with VCfly.

[0027] As described above, the controller 120 may read R P The controller 120 may receive the resistance value of R and compare it with the register values ​​stored in the registers 150 and 152 to determine the operation mode of the switch circuit 104. The first operation mode corresponding to the register 150 may be to operate the switch circuit 104 as a two-level buck converter. The second operation mode corresponding to the register 152 may be to operate the switch circuit 104 as a three-level buck converter. P , read register 150, and set R P is compared with the value read from register 150 and determines R P Is the value the same as or different from the value read from register 150? The controller 120 may also receive R P , read register 152, and set R P is compared with the value read from register 152 and determines R P Whether it is the same as or different from the value read from register 152.

[0028] In response to R PThe controller 120 may operate the switch circuit 104 as a three-level buck converter, the same as the value read from the register 152. To operate the switch circuit 104 as a three-level buck converter, the controller 120 may turn off or on the switch 202 to connect the Cfly balancer 134 to the voltage window generator 132, and turn off or on the switch 204 to connect the SR latch 208 to the PWM generator 220 using two signal paths from the Q output of the SR latch 208. In response to connecting the Cfly balancer 134 to the window generator 132, the Cfly balancer 134 may send V3 to the window generator 132. The voltage V3 may be received by the window generator 132 and used as an additional voltage source between Vwin+ and the SR latch 208, so that the upper limit Vwin+ of the voltage window may be modified, and the voltage window may be set to a range between the modified voltage levels of Vwin- and Vwin+. In response to switches 202, 204 being turned on, PWM generator 220 may generate PWM signals PWM1, PWM2, PWM3, PWM4 in a sequence determined by a voltage window modified using an offset voltage in signal V3. For example, if VCfly is greater than Vin / 2, the offset voltage in signal V3 may adjust Vwin+ by decreasing Vwin+, and PWM signals PWM1, PWM2, PWM3, PWM4 may discharge Cfly. If VCfly is less than Vin / 2, the offset voltage in signal V3 may adjust Vwin+ by increasing Vwin+, and PWM signals PWM1, PWM2, PWM3, PWM4 may charge Cfly.

[0029] In response to R P The controller 120 may operate the switch circuit 104 as a two-level buck converter, the same as the value read from the register 150. To operate the switch circuit 104 as a two-level buck converter, the controller 120 may open or close the switch 202 to disconnect the Cfly balancer 134 from the voltage window generator 132, and open or close the switch 204 to disconnect one of the two paths connecting the Q output of the SR latch 208 to the PWM generator 220. In response to the switches 202, 204 being turned off, the PWM generator 220 may generate PWM signals PWM1, PWM2 based on a voltage window ranging between Vwin- and Vwin+. In one embodiment, in response to the switches 202, 204 being turned off, the PWM generator 220 may additionally generate PWM3, PWM4 as constant high voltage signals to maintain Q3, Q4 in an on state so that Vin may be provided to Q2.

[0030] Figure 3302, 304, and / or 306. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation.

[0031] Process 300 may be performed by controller 120 as described herein. Process 300 may start at block 302. At block 302, the controller may determine an operating mode of the switching circuit. In one embodiment, the controller may obtain a resistance value from an input pin of the controller. The controller may additionally read a register value to determine the operating mode. The controller may additionally compare the resistance value to the register value to determine the operating mode. In one embodiment, the two-level voltage converter may be a two-level buck converter, and the three-level voltage converter may be a three-level buck converter.

[0032] Process 300 may proceed from block 302 to block 304. At block 304, in response to the operating mode indicating a two-level operating mode, the controller may program the switch circuit to operate as a two-level voltage converter. Process 300 may proceed from block 302 to block 306. At block 306, in response to the operating mode indicating a three-level operating mode, the controller may program the switch circuit to operate as a three-level converter.

[0033] In one embodiment, the controller may operate the modulator to generate a first set of control signals to operate a portion or subset of the plurality of switch elements in the switch circuit in a first switching sequence in response to the operation mode indicating a two-level operation mode. The controller may further operate the modulator to generate a second set of control signals to operate the plurality of switch elements in the switch circuit in a second switching sequence in response to the operation mode indicating a three-level operation mode.

[0034] In one embodiment, the controller may activate the flying capacitor balancer to control the flying capacitor voltage of the flying capacitor connected to the switching circuit in response to the operation mode indicating the three-level operation mode.

[0035] In one embodiment, the controller may disconnect the flying capacitor balancer from the voltage window generator in response to the operation mode indicating a two-level operation mode. The flying capacitor balancer may be configured to generate an offset voltage based on the voltage of the flying capacitor voltage connected to the switching circuit. The voltage window generator may be configured to set a voltage window that controls a plurality of control signals for operating the switching converter. The controller may further connect the flying capacitor balancer to the voltage window generator in response to the operation mode indicating a three-level operation mode to modify the voltage window using the offset voltage. In one embodiment, the controller, the flying capacitor balancer, and the voltage window are monolithically integrated in a single die.

[0036] The flow chart and block diagram in the figure illustrate the architecture, functionality and operation of the possible implementation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each block in the flow chart or block diagram can represent a module, fragment or part of an instruction, which includes one or more executable instructions for implementing a specified logical function (one or more). In some alternative embodiments, the function marked in the block may not occur in the order marked in the figure. For example, the two blocks shown in succession can actually be implemented substantially at the same time, or these blocks can sometimes be implemented in reverse order, depending on the functionality involved. It will also be noted that each block in the block diagram and / or the flow chart diagram and the combination of the blocks in the block diagram and / or the flow chart diagram can be implemented by a system based on special-purpose hardware, which performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0037] The terms used herein are used only to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0038] The corresponding structures, materials, actions and equivalents of all equipment or step-plus-function elements (if any) in the following claims are intended to include any structure, material or action for performing a function, as well as other claimed elements specifically claimed for protection. For the purpose of illustration and description, the disclosed embodiments of the present invention have been presented, but these embodiments are not intended to be exhaustive or limit the present invention to the disclosed form. Without departing from the scope and spirit of the present invention, many modifications and variations are apparent to those of ordinary skill in the art. These embodiments are selected and described in order to best explain the principles and practical applications of the present invention, and to enable other persons of ordinary skill in the art to understand that the various embodiments of the present invention with various modifications are suitable for the intended specific use.

Claims

1. A semiconductor device comprising: A switching circuit including a plurality of switching elements; as well as The controller is configured as: determining an operating mode of the switching circuit; In response to the operating mode indicating a two-level operating mode, programming the switch circuit to operate as a two-level voltage converter; as well as In response to the operating mode indicating a three-level operating mode, the switch circuit is programmed to operate as a three-level voltage converter.

2. The semiconductor device according to claim 1, wherein the controller is configured to: obtaining a resistance value from an input pin of the controller; reading a register value to determine the operating mode; and The resistance value is compared to the register value to determine the operating mode.

3. The semiconductor device according to claim 1, wherein the controller is configured to: In response to the operating mode indicating the two-level operating mode, operating a modulator to generate a first set of control signals to operate a subset of the plurality of switching elements in the switching circuit in a first switching sequence; and In response to the operation mode indicating the three-level operation mode, the modulator is operated to generate a second set of control signals to operate the plurality of switching elements in the switch circuit in a second switching sequence.

4. The semiconductor device according to claim 1, further comprising: a flying capacitor connected to the switching circuit; as well as Flying capacitor balancer, The controller is configured to activate the flying capacitor balancer to control a flying capacitor voltage of the flying capacitor in response to the operation mode indicating the three-level operation mode.

5. The semiconductor device according to claim 1, further comprising: a flying capacitor balancer configured to generate an offset voltage based on a voltage of a flying capacitor voltage connected to the switching circuit; as well as a voltage window generator configured to set a voltage window for controlling a plurality of control signals for operating the switching converter, The controller is configured as follows: disconnecting the flying capacitor balancer from the voltage window generator in response to the operating mode indicating the two-level operating mode; as well as In response to the operating mode indicating the three-level operating mode, the flying capacitor balancer is connected to the voltage window generator to modify the voltage window using the offset voltage.

6. The semiconductor device according to claim 1, further comprising: a flying capacitor balancer configured to generate an offset voltage based on a voltage of a flying capacitor voltage connected to the switching circuit; as well as Voltage Window Generator, configured as: In response to the operation mode indicating the two-level operation mode, setting the voltage window to a first range including an upper limit and a lower limit; and In response to the operation mode indicating the three-level operation mode, the voltage window is set to a second range including the lower limit and a modified upper limit, wherein the modified upper limit is dependent on the offset voltage. 7 . The semiconductor device of claim 6 , wherein the controller, the flying capacitor balancer, and the voltage window are monolithically integrated in a single die.

8. The semiconductor device according to claim 1, wherein the two-level voltage converter is a two-level buck converter, and The three-level voltage converter is a three-level buck converter.

9. A semiconductor device comprising: a modulator configured to generate a plurality of control signals to operate the switching circuit; a flying capacitor balancer configured to control a flying capacitor voltage of a flying capacitor connected to the switching circuit; as well as The controller is configured as: determining an operating mode of the switching circuit; In response to the operating mode indicating a two-level operating mode, programming the modulator to generate a first set of control signals for operating the switching circuit as a two-level voltage converter; as well as In response to the operation mode indicating a three-level operation mode: connecting the flying capacitor balancer to the modulator to control the flying capacitor voltage of the flying capacitor; as well as The modulator is programmed to generate a second set of control signals for operating the switching circuit as a three-level voltage converter.

10. The semiconductor device according to claim 9, wherein the controller is configured to: obtaining a resistance value from an input pin of the controller; reading a register value to determine the operating mode; and The resistance value is compared to the register value to determine the operating mode.

11. The semiconductor device according to claim 9, wherein the controller is configured to: In response to the operating mode indicating the two-level operating mode, operating the modulator to generate the first set of control signals to operate a subset of the plurality of switching elements in the switching circuit in a first switching sequence; and In response to the operation mode indicating the three-level operation mode, the modulator is operated to generate a second set of control signals to operate the plurality of switching elements in the switch circuit in a second switching sequence.

12. The semiconductor device according to claim 9, wherein the flying capacitor balancer is configured to generate an offset voltage based on the flying capacitor voltage, and wherein the modulator comprises a voltage window generator, the voltage window generator being configured to: In response to the operation mode indicating the two-level operation mode, setting the voltage window to a first range including an upper limit and a lower limit; and In response to the operation mode indicating the three-level operation mode, the voltage window is set to a second range including the lower limit and a modified upper limit, wherein the modified upper limit is dependent on the offset voltage. 13 . The semiconductor device of claim 12 , wherein the modulator, the controller, and the flying capacitor balancer are monolithically integrated in a single die.

14. The semiconductor device according to claim 9, wherein the two-level voltage converter is a two-level buck converter, and The three-level voltage converter is a three-level buck converter.

15. A method for programming a voltage converter, the method comprising: determining that the operating mode of the switching circuit indicates a two-level operating mode; In response to the operating mode indicating the two-level operating mode, programming the switch circuit to operate as a two-level voltage converter; determining that the operating mode of the switching circuit indicates a three-level operating mode; as well as In response to the operating mode indicating the three-level operating mode, the switching circuit is programmed to operate as a three-level converter.

16. The method of claim 15, wherein determining the operating mode comprises: Get the resistance value from the input pin; reading a register value to determine the operating mode; as well as The resistance value is compared to the register value to determine the operating mode.

17. The method according to claim 15, wherein the two-level voltage converter is a two-level buck converter, and The three-level voltage converter is a three-level buck converter.

18. The method according to claim 15, further comprising: In response to the operating mode indicating the two-level operating mode, operating a modulator to generate a first set of control signals to operate a subset of the plurality of switching elements in the switching circuit in a first switching sequence; as well as In response to the operation mode indicating the three-level operation mode, the modulator is operated to generate a second set of control signals to operate the plurality of switching elements in the switch circuit in a second switching sequence.

19. The method according to claim 15, further comprising: In response to the operation mode indicating the three-level operation mode, a flying capacitor balancer is activated to control a flying capacitor voltage of a flying capacitor connected to the switching circuit.

20. The method of claim 15, further comprising: disconnecting a flying capacitor balancer from a voltage window generator in response to the operation mode indicating the two-level operation mode, wherein disconnecting the flying capacitor balancer from the voltage window generator causes the voltage window generator to be configured to set a first voltage window that controls a plurality of control signals for operating the switching converter as a two-level voltage converter; as well as In response to the operating mode indicating the three-level operating mode, the flying capacitor balancer is connected to the voltage window generator, wherein connecting the flying capacitor balancer to the voltage window generator causes the voltage window generator to set a second voltage window, and the second voltage window controls the multiple control signals used to operate the switching converter as a three-level voltage converter.

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