A spatial domain adaptive filtering method and device based on FPGA and power inversion criterion

Abstract

The application discloses a kind of space adaptive filtering method and device based on FPGA and power inversion criterion, design signal processing field.It includes array signal data preprocessing module, autocovariance matrix calculation module, cross-covariance matrix calculation module, optimal weight vector calculation module, floating-point number to fixed-point number module, optimal weight vector weighting module;It can form deep notch in the direction of suppressive jamming signal, effectively filter out the suppressive jamming signal in communication process, retain expected signal;The application has high calculation accuracy, less resource occupation and strong real-time processing capability, and the module integration is high, convenient for transplantation on existing spread spectrum communication receiver, still has efficient interference suppression capability in complex or dynamic change interference environment.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of array signal processing, and particularly relates to a spatial domain adaptive filtering FPGA algorithm acceleration module and device based on a power inversion criterion. BACKGROUND

[0002] In a spread spectrum communication system, electromagnetic interference threats are a major challenge to communication integrity and reliability, especially intentional suppressive interference, which seriously affects the performance of the spread spectrum communication system, increases the error code probability of the spread spectrum communication system, and even causes the spread spectrum communication system to lose lock.

[0003] Spatial domain adaptive filtering is a technology that combines adaptive signal processing and array antenna technology. In the case that the directions of useful signals and interference signals are different, the weight parameters of each array antenna are controlled to adaptively adjust the antenna pattern, form nulls in the direction of the interference, and ensure that the gain of the useful signal is not affected, so as to reduce the power of the interference signal entering the receiver, improve the signal-to-noise ratio of the system, and achieve the purpose of eliminating interference.

[0004] Spatial domain adaptive filtering based on the power inversion criterion is suitable for processing signals with a low expected level and a signal-to-interference ratio (SINR) lower than 0 dB, and minimizes the total output power by appropriately adjusting the weight of the array antenna. In a spread spectrum communication system, the power of the expected signal is very low and is almost submerged in the environmental noise. By minimizing the output power, the algorithm suppresses the interference signal with stronger power. Deep nulls are formed in the direction from which the interference signal comes, while a relatively flat response is maintained in the direction of the useful signal. This means that the interference signal is effectively suppressed, while the useful signal is kept as much as possible. Thereafter, the spread spectrum communication receiver further enhances the signal through subsequent processing steps such as despreading, thereby improving the final signal-to-interference ratio. Meanwhile, spatial domain adaptive filtering based on the power inversion criterion does not need to know the exact structure or angle of arrival of the signal in advance, which makes it particularly suitable for scenarios where signal parameters may be unknown or difficult to predict, such as in a complex or dynamically changing interference environment.

[0005] The spatial domain adaptive filtering algorithm includes sampling signal covariance matrix calculation, optimal weight vector calculation, and sampling signal weighting steps. Most current spatial domain adaptive filtering algorithms are implemented on CPUs and DSP processors. Due to the limitation of serial computing speed, such processors cannot meet the real-time requirements of the algorithm. With the development of semiconductor technology, FPGA integrates more and more configurable logic resources, various external bus interfaces, and rich internal RAM resources. Meanwhile, its parallel running characteristics make it more flexible in implementing various algorithms. Therefore, using FPGA to accelerate the implementation of spatial domain adaptive filtering algorithms has gradually become a trend. SUMMARY

[0006] In view of the poor real-time performance of the existing spatial adaptive filtering algorithm, the application provides a spatial adaptive filtering FPGA algorithm acceleration module and device based on a power inversion criterion, which combines the structural characteristics of the spatial adaptive filtering algorithm, fully utilizes the parallel operation characteristics of the FPGA, ensures the real-time performance of the spatial adaptive filtering algorithm without losing data accuracy, and effectively suppresses the suppressive interference.

[0007] To achieve the above-mentioned application purposes, the following technical solutions are adopted:

[0008] A spatial adaptive filtering method based on FPGA and power inversion criterion, comprising the following steps:

[0009] Step 1: converting the radio frequency signals received by the array antenna into digital intermediate frequency signals, and converting the obtained digital intermediate frequency signals from fixed-point numbers into single-precision floating-point numbers;

[0010] Step 2: calculating the cross-covariance matrix of the digital intermediate frequency signal of the first array element of the array antenna and the digital intermediate frequency signals of other array elements and the autocovariance matrix of the digital intermediate frequency signals of other array elements

[0011] Step 3: calculating the inverse matrix of the autocovariance matrix obtained in step 2 by using the LDL matrix decomposition inversion method

[0012] Step 4: multiplying the inverse matrix obtained in step 3 the cross-covariance matrix obtained in step 2 to calculate the optimal weight vector w of the array antenna according to the power inversion criterion;

[0013] Step 5: weighting the received digital intermediate frequency signals by using the optimal weight vector w of the array antenna obtained in step 4 to realize the suppression of the interference signals.

[0014] Further, the specific process of step 1 is as follows:

[0015] S11, by configuring each array antenna radio frequency front-end chip, the radio frequency signals received by the array antenna are converted into digital intermediate frequency signals, and a set of I / Q signal data is generated for each array antenna; the signal data received by the array antenna is represented as x(n), wherein x(n)=[x1(n) x2(n) … x M (n)] T is composed of the received signals of M array antennas, and x i (n) represents the signal received by the i-th array antenna; ​

[0016] S12, the I / Q signal data corresponding to each array antenna is converted into single-precision floating-point data by a fixed-point to single-precision floating-point module, a corresponding cache area is opened for each array antenna signal data by using the on-chip block RAM of the FPGA, and the signal data with a length of N shots is stored from the starting address of each cache area.

[0017] Further, the step 2 is specifically as follows:

[0018] S21, the signal data in the cache area corresponding to the first array antenna is recorded as matrix X1, and the signal data in the cache area corresponding to the other array antennas is recorded as matrix X2, wherein

[0019] X1 = [x1(1) x1(2) … x1(N)]

[0020]

[0021] The cross-covariance matrix of the digital intermediate frequency signal of the first array element and the digital intermediate frequency signals of the other array elements is calculated Wherein N represents the sampling snapshot number of the array antenna receiving signal; since There is only one column, when calculating the multiplication of matrix X2 and matrix X1 on the FPGA, only the multiplication and accumulation of each row data of matrix X2 and the column data of X1 are calculated, and the calculated matrix Element data is stored in the on-chip block RAM of the FPGA;

[0022] S22, since the FPGA has the characteristics of parallel operation, while calculating , the parallel calculation is also performed on the FPGA according to the principle of matrix multiplication, so that X2 and The corresponding rows and columns are multiplied and accumulated, and the calculated matrix Element data is also stored in the on-chip block RAM of the FPGA.

[0023] Further, the step 3 is specifically as follows:

[0024] S31, the self-covariance matrix is calculated, and then the principle of matrix LDL decomposition is used Wherein, if

[0025]

[0026] Then

[0027]

[0028] a jj as the calculation djj , represents the matrix element in the jth row, jth column of the diagonal matrix D obtained by matrix LDL decomposition;

[0029] l jk , d kk is used to recursively calculate d jj and l ij ; wherein, l jk represents the matrix element in the jth row, kth column of the lower triangular matrix L obtained by matrix LDL decomposition; represents the conjugate transpose of l jk ; d kk represents the diagonal matrix element in the kth row, kth column of the diagonal matrix D obtained by matrix LDL decomposition;

[0030] d jj is used to construct the diagonal matrix D and calculate l ij , represents the diagonal matrix element in the jth row, jth column of the diagonal matrix D obtained by matrix LDL decomposition;

[0031] a i1 , as a basis value for calculating l i1 , represents the matrix element in the ith row, 1st column of the matrix ;

[0032] l i1 , l ij are used to construct the lower triangular matrix L. Wherein, l i1 represents the matrix element in the ith row, 1st column of the lower triangular matrix L obtained by matrix LDL decomposition; l ij represents the matrix element in the ith row, jth column of the lower triangular matrix L obtained by matrix LDL decomposition;

[0033] Two cache areas are opened for the lower triangular matrix L and the diagonal matrix D using the on-chip block RAM of FPGA. When defining the RAM cache area, the element value in the diagonal line position of the lower triangular matrix L is set to 1. Since the matrix D is a diagonal matrix, only the diagonal line elements of the matrix D need to be cached in the form of a vector;

[0034] According to the above formula, when calculating the lower triangular matrix L and the diagonal matrix D in FPGA, the calculation starts from the first column j = 1 of the L and D matrices. When the variable k accumulates from 0 to j-1, the corresponding matrix data is constantly taken out from the RAM area of FPGA to calculate the cumulative sum After that, the value of d jj can be calculated and stored in the RAM cache area of the matrix D;

[0035] ​At this point, the calculation begins from the (i=j+1)th row of the lower triangular matrix L. As the variable k accumulates from 0 to (j-1), the corresponding matrix data is continuously retrieved from the FPGA's RAM area, and the cumulative sum is calculated. Then, calculate l ij The value of is stored in the RAM cache of matrix L. Let i increment, and calculate l in the above manner. ij Continue calculating until i = M-1; calculate the second column j = 2 matrix data of L and D matrices in the above manner until the last column j = M-1 matrix data of L and D matrices are calculated.

[0036] S32. Calculate the inverse matrix L of the lower triangular matrix L using the formula for finding the inverse of a lower triangular matrix L. -1

[0037]

[0038] In the formula

[0039]

[0040] r ij Used to construct the inverse matrix L -1 , representing the inverse matrix L -1 The matrix element in the i-th row and j-th column,

[0041] l ii As a calculation r ij The basic value represents the diagonal element in the i-th row and i-th column of the lower triangular matrix L.

[0042] l ik r kj Used for recursive calculation of r ij , l ik r represents the element in the i-th row and k-th column of the lower triangular matrix L; kj L represents the inverse matrix -1 The matrix element in the k-th row and j-th column.

[0043] Using the on-chip RAM of the FPGA as the inverse matrix L -1 After allocating a buffer area, start from L -1 The calculation begins with the first row of the matrix (i=1) and the first column (j=1). As the variable k accumulates from 0 to i-1, the corresponding matrix data is continuously retrieved from the FPGA's RAM area to calculate the cumulative sum. Then, r is calculated. ij The value is stored in matrix L. -1 In the RAM cache, let j increment, and calculate r in the manner described above. ij Continue calculating until j = i - 1; calculate L in the manner described above. -1The second row i=2 of the matrix is the matrix data until the L is calculated -1 The last row i=M-1 of the matrix is the matrix data;

[0044] S33, since the FPGA has the characteristic of parallel operation, the inverse matrix L -1 of the lower triangular matrix L is calculated at the same time, and the inverse matrix D -1 of the diagonal matrix D is calculated in parallel. -1 The inverse matrix D -1 is the reciprocal of the diagonal elements of the D matrix, that is

[0045]

[0046] After a cache area is opened for the inverse matrix D -1 in the on-chip block RAM of the FPGA, the diagonal element values of the matrix D are taken out from the RAM area of the FPGA in sequence, and after the reciprocal is calculated, the result is stored in the RAM cache area of the matrix D -1 ;

[0047] S34, the inverse matrix L -1 and D -1 are calculated, and the inverse matrix of is represented as The element values of the matrix (L H ) -1 and the element values of D -1 are taken out from the RAM area of the FPGA in sequence, and the operation is performed according to the principle of matrix multiplication, so that (L H ) -1 is multiplied and accumulated with the corresponding rows and columns of D -1 , and the result is temporarily stored in the on-chip block RAM area of the FPGA. After the matrix multiplication of (L H ) -1 and D -1 is calculated, the obtained matrix is multiplied with L -1 again according to the principle of matrix multiplication, and the element data of the calculated matrix is stored in the on-chip block RAM of the FPGA.

[0048] Further, the step 4 is specifically as follows:

[0049] S41, the optimal weight vector w is obtained according to the power inversion criterion, and the values of the matrices and are taken out from the RAM area of the FPGA, and the operation is performed according to the principle of matrix multiplication, so that is multiplied and accumulated with the corresponding rows and columns of , and the obtained optimal weight vector w is obtained.

[0050] S42, the optimal weight vector w is converted to a single-precision floating-point number and stored in the register resource of the FPGA.

[0051] Further, the step 5 is specifically as follows:

[0052] S51, the signal data received by the array antenna is weighted by the optimal weight vector w, that is, each array element is multiplied by the corresponding optimal weight and then added to obtain the output signal, that is, the output signal y(n) = w H (n)x(n).

[0053] A spatial domain adaptive filtering device based on FPGA and power inversion criterion, the device comprises: a front-end radio frequency chip, an FPGA algorithm acceleration module, a signal demodulation module, the front-end radio frequency chip transmits the received signal to the FPGA algorithm acceleration module for filtering, and then transmits the filtered signal to the signal demodulation module for demodulation.

[0054] The FPGA algorithm acceleration module comprises: an array signal data preprocessing module, a self-covariance matrix calculation module, a self-covariance matrix inversion module, a cross-covariance matrix calculation module, an optimal weight vector calculation module, a floating-point number to fixed-point number module, and an optimal weight vector weighting module.

[0055] The front-end radio frequency chip transmits the received signal to the array signal data preprocessing module and the optimal weight vector weighting module; the array signal data preprocessing module converts the received radio frequency signal into a digital intermediate frequency signal, and then transmits the digital intermediate frequency signal to the self-covariance matrix calculation module and the cross-covariance matrix calculation module; the self-covariance matrix calculation module calculates the self-covariance of the signal and transmits the result to the self-covariance matrix inversion module; the outputs of the self-covariance matrix inversion module and the cross-covariance matrix calculation module are transmitted to the optimal weight vector calculation module; the output of the optimal weight vector calculation module is transmitted to the floating-point number to fixed-point number module; the optimal weight vector weighting module weights the signal received by the front-end radio frequency chip and the output of the floating-point number to fixed-point number module and then outputs to the signal demodulation module.

[0056] Compared with the prior art, the present application has the following advantages: the hardware acceleration is performed on the spatial adaptive filtering algorithm based on the power inversion criterion in array signal processing, the interference suppression with low power consumption, high energy efficiency and strong real-time performance is realized according to the high parallelism of FPGA, the sampling autocorrelation matrix inversion is calculated, the LDL matrix decomposition inversion principle is used to decompose the sampling matrix into a lower triangular matrix L and a diagonal matrix D and then to calculate the inverse matrix, the complexity of hardware implementation is greatly reduced, the fixed-point data is converted into floating-point data in the whole calculation process, and the accuracy of data in the calculation process is ensured, the FPGA algorithm acceleration module and device of the present application are easy to integrate and have small resource consumption, and the interference suppression is performed before the received signal demodulation, and the sensitivity of the receiver is improved. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 It is a FPGA algorithm acceleration device structure schematic diagram based on the spatial adaptive filtering based on the power inversion criterion provided by the present application.

[0058] Figure 2 It is an array antenna arrangement schematic diagram with 10-unit linear array as an example.

[0059] Figure 3 It is a signal data preprocessing module structure diagram of the present application.

[0060] Figure 4 It is a autocorrelation matrix inversion module structure diagram of the present application.

[0061] Figure 5 It is an FPGA implementation flowchart of the LDL matrix decomposition of the present application.

[0062] Figure 6 It is an FPGA implementation flowchart of the L matrix inversion of the present application.

[0063] Figure 7 It is an FPGA implementation flowchart of the matrix multiplication module in the autocorrelation matrix inversion module of the present application.

[0064] Figure 8 It is a structure diagram of the optimal weight vector weighting module of the present application.

[0065] Figure 9 It is a directivity diagram of the optimal weight vector calculated under an example of the present application.

[0066] Figure 10 It is the original signal spectrum of the received signal under an example of the present application.

[0067] Figure 11 It is the signal spectrum of the received signal after the spatial adaptive filtering under an example of the present application.

[0068] Figure 12 is the result of demodulating the signal after spatial domain adaptive filtering of the received signal in one example of the present application.

[0069] Figure 13 is the resource consumption of the FPGA algorithm acceleration module in one example of the present application. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments of the present application.

[0071] As shown in Figure 1 , a spatial domain adaptive filtering FPGA algorithm acceleration device result schematic diagram based on a power inversion criterion, taking a 10-element linear array as an example, as shown in Figure 2 , the array spacing d is half of the wavelength of the received signal, and the method comprises the following steps:

[0072] First step: transmitting a spread spectrum communication signal, the center frequency is 2.361 GHz, the bandwidth is 1.023 MHz, the general environmental noise power is-110 dBm, the measurement and control signal power is generally about 20 dB lower than the noise power, so the measurement and control signal power is-130 dBm, and the incident angle of the signal is 10°; transmitting a single-tone interference signal, the center frequency is 2.362 GHz, the single-tone interference signal power is-60 dBm, and the single-tone interference signal is incident to the array element from a direction of 50°; transmitting a wideband interference signal, the center frequency is 2.361 GHz, the bandwidth is 1 MHz, and the wideband interference signal power is-60 dBm, and the wideband interference signal is incident to the array element from a direction of-30°.

[0073] Second step: performing array antenna signal data preprocessing, the signal data preprocessing structure is as shown in Figure 3 , by configuring the AD9361 radio frequency chip under each array antenna, the radio frequency signal received by the array antenna is converted into a digital intermediate frequency signal, at this time the digital intermediate frequency signal is a 12-bit fixed point number, and then the 12-bit fixed point number obtained by each array antenna is converted into a 32-bit single-precision floating point number, a corresponding cache area is opened for each array antenna signal data by using the on-chip block RAM of the FPGA, and the signal data with a length of the number of snapshots N=32 is stored from the starting address of each cache area.

[0074] Third step: sequentially taking out the corresponding data from the signal data cache area of the first array element and the signal data cache areas of other array elements, and simultaneously calculating the cross-covariance matrix of the signal data of the first array element and the signal data of other array elements and the autocovariance matrix of the signal data of other array elements

[0075] Fourth step: using the LDL matrix decomposition to inverse the autocovariance matrix obtained in the third step Calculate its inverse matrix As shown in Figure 4 , the specific steps include: LDL matrix decomposition, L matrix inversion, D matrix inversion, and matrix multiplication.

[0076] Specifically, the calculation flowchart of the FPGA implementing LDL matrix decomposition is shown in Figure 5 ; the calculation flowchart of the FPGA implementing L matrix inversion is shown in Figure 6 ; and the calculation flowchart of the FPGA implementing matrix multiplication is shown in Figure 7 .

[0077] Since the D matrix is a diagonal matrix, its inverse matrix D -1 is the reciprocal of the diagonal elements. The diagonal element values of the matrix D -1 are taken out from the RAM area of the FPGA, and after calculating the reciprocal, the result is stored in the RAM buffer area of the matrix D

[0078] Fifth step: calculating the optimal weight vector according to the power inversion criterion The values of the matrices and are taken out from the RAM area of the FPGA, and according to the principle of matrix multiplication, the corresponding rows and columns of and are multiplied and accumulated to obtain the optimal weight vector w. After the optimal weight vector w is converted to a fixed point from a single-precision floating point number, it is stored in the register resources of the FPGA.

[0079] Sixth step: weighting the signal data received by the array antenna using the optimal weight vector w, as shown in Figure 8 , that is, after multiplying each array with the corresponding optimal weight, the sum is calculated and accumulated to obtain an output signal, which is transmitted to the signal demodulation module.

[0080] Figures 9-10 The frequency spectrum of the received signal before and after spatial domain adaptive filtering, at this time, the single-tone interference and the wideband interference are filtered out, and the spread spectrum communication signal is submerged in the noise; Figure 11 The directivity pattern of the optimal weight vector calculated in this example, in the incident direction of the single-tone interference, has a null depth of -86.15 dB, and in the incident direction of the wideband interference, has a null depth of -60.38 dB; Figure 12 The result of demodulating the spread spectrum communication signal after spatial domain adaptive filtering, the weighted and filtered signal can be captured and tracked, and the original data is recovered.

[0081] In order to further illustrate the performance of the FPGA algorithm acceleration device provided by the present application, the receiver selects the KCU105 development board of Xilinx Company, and the FPGA chip model is XCKU040. Table 1 shows the comparison of the results obtained by the PC host (CPU model is Intel(R) Core(TM) i7-8750H CPU, clock frequency is 2.21 GHz) and the processing results of the present application in one 10-element linear array optimal weight calculation, and the calculation speed of the algorithm of the present application is 26 times that of the PC host calculation speed under the condition of ensuring data accuracy. At the same time, the resource consumption of the FPGA algorithm acceleration module is shown in Table 2, and the entire lookup table LUT consumption accounts for 5%, the flip-flop FF consumption accounts for 5%, the on-chip BRAM consumption accounts for 5%, the digital signal processor DSP consumption accounts for 5%, and the required resources are very few. Figure 13

[0082] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0083] Table 1 is a comparison table of the performance of the spatial adaptive filtering algorithm based on the power inversion criterion of the PC host and the present application under one example.

[0084] ​

Claims

1. A space domain adaptive filtering method based on FPGA and power inversion criterion, comprising the following steps: Step 1: converting the radio frequency signals received by the array antenna into digital intermediate frequency signals, and converting the obtained digital intermediate frequency signals from fixed-point numbers into single-precision floating-point numbers; Step 2: Calculate the cross-covariance matrix of the digital intermediate frequency signal of the first array element of the array antenna and the digital intermediate frequency signals of the other array elements and the auto-covariance matrix of the digital intermediate frequency signals of the other array elements Step 3: Inverse the auto-covariance matrix obtained in Step 2 using LDL matrix factorization Compute its inverse matrix Step 4: Inverse the matrix obtained in Step 3 Step 2: Obtain the cross-covariance matrix Calculate the optimal weight vector w of the array antenna according to the power inversion criterion. S41. The optimal weight vector can be obtained according to the power inversion criterion. Retrieve the matrix from the FPGA's RAM region and The value of is calculated according to the principle of matrix multiplication, so that... and The optimal weight vector w is obtained by multiplying and summing the corresponding rows and columns. S42, after converting the obtained optimal weight vector w into single-precision floating-point numbers, storing it by using the register resources of the FPGA; Step 5: weighting the array antenna optimal weight vector w obtained in step 4 on the received digital intermediate frequency signals to realize the suppression of the interference signals.

2. The method of claim 1, wherein the FPGA-based spatial adaptive filtering method is based on a power inversion criterion. The specific process of the step 1 is as follows: S11, converting the radio frequency signals received by the array antennas into digital intermediate frequency signals by configuring each array antenna radio frequency front end chip, each array antenna corresponding to generate a set of I / Q signal data; the signal data received by the array antennas is represented as x(n), wherein x(n)=[x1(n) x2(n) … xM(n) M (n)] T The received signal of the M array antennas is composed of x i (n) represents the signal received by the i-th array antenna; S12, the I / Q signal data corresponding to each array antenna is converted into single-precision floating-point numbers by using the on-chip block RAM of the FPGA, and a corresponding cache area is opened for each array antenna signal data, and the signal data with a length of N shots is stored from the starting address of each cache area.

3. The method of claim 1, wherein the FPGA-based spatial adaptive filtering method is based on a power inversion criterion. The specific process of the step 2 is as follows: S21, the signal data in the cache area corresponding to the first array antenna is recorded as matrix X1, and the signal data in the cache area corresponding to the other array antennas is recorded as matrix X2, wherein X1=[x1(1) x1(2) … x1(N)] The cross-covariance matrix of the digital intermediate frequency signal of the first array element and the digital intermediate frequency signals of other array elements is calculated Wherein N represents the sampling fast array number of the array antenna received signal; since There is only one column, when the FPGA calculates the matrix X2 multiplied by the matrix X1, only the multiplication and accumulation of the data of each row of the matrix X2 and the column data of X1 are calculated, and the calculated matrix The element data is stored in the on-chip block RAM of the FPGA; S22. Due to the parallel computing characteristics of the FPGA, the calculation in step S21 is performed... At the same time, parallel computing The same matrix multiplication principle is applied on the FPGA to make X2 and... Multiply the corresponding rows and columns and sum them to obtain the matrix. The element data is also stored in the on-chip RAM of the FPGA.

4. The method of claim 1, wherein the FPGA-based spatial adaptive filtering method is based on a power inversion criterion. The specific process of the step 3 is as follows: S31, compute the auto-covariance matrix After that, the matrix LDL decomposition principle is used wherein, if Then a jj As a basis value for calculating d jj , the diagonal matrix element of the matrix in the jth row and jth column; l jk 、 d kk for the recursive computation of d jj and l ij ; wherein l jk denotes the matrix element of the j-th row, k-th column of the lower triangular matrix L resulting from the matrix LDL decomposition; denotes the conjugate transpose of l jk ; d kk denotes the diagonal matrix element of the k-th row, k-th column of the diagonal matrix D resulting from the matrix LDL decomposition; d jj for constructing the diagonal matrix D and computing l ij denotes the diagonal matrix element of the j-th row, j-th column in the diagonal matrix D obtained by the matrix LDL decomposition; a i1 as a basis value for calculating l i1 represents the matrix element of the matrix in the i-th row and the 1-st column. l i1 , l ij for constructing the lower triangular matrix L, l i1 denotes the matrix element of the i-th row, 1-st column in the lower triangular matrix L obtained by matrix LDL decomposition; l ij denotes the matrix element of the i-th row, j-th column in the lower triangular matrix L obtained by matrix LDL decomposition; The on-chip block RAM of the FPGA is used to open two cache areas for the lower triangular matrix L and the diagonal matrix D, and when defining the RAM cache area, the element value of the diagonal line position of the lower triangular matrix L is 1, and since the matrix D is a diagonal matrix, only the diagonal element of the matrix D needs to be cached in the form of a vector; According to the above formula, when the lower triangular matrix L and the diagonal matrix D are calculated in the FPGA, the first column j = 1 of the L and D matrices is calculated first, and when the variable k is accumulated from 0 to j-1, the corresponding matrix data is continuously taken out from the RAM area of the FPGA, and the accumulated sum is calculated Then, the value of d jj can be calculated and stored in the RAM buffer area of the matrix D. At this time, the calculation is started from the i = j + 1 row of the lower triangular matrix L, and during the accumulation of the variable k from 0 to j - 1, the corresponding matrix data is continuously fetched from the RAM area of the FPGA, and the accumulated sum is calculated Afterwards, the value of l ij is calculated and stored in the RAM buffer area of the matrix L, i is incremented, and l ij is calculated in the above manner until i = M - 1 is calculated; the second column j = 2 matrix data of the L, D matrix is calculated in the above manner until the last column j = M - 1 matrix data of the L, D matrix is calculated; S32, according to the lower triangular matrix inversion formula, calculate the inverse matrix L of the lower triangular matrix L -1 In the formula r ij for constructing the inverse matrix L -1 , denotes the matrix element of the inverse matrix L -1 in the i-th row and j-th column, l ii As a basis value for calculating r ij represents the diagonal matrix element of the i-th row, i-th column in the lower triangular matrix L, l ik , r kj for the recursive computation of r ij , l ik denotes the matrix element of the lower triangular matrix L in the i-th row and k-th column; r kj denotes the matrix element of the inverse matrix L -1 in the k-th row and j-th column; In the FPGA on-chip block RAM for inverse matrix L -1 After opening a block of cache, first from L -1 The first row of the matrix i = 1, the first column j = 1, when the variable k from 0 accumulated to i-1 process, constantly from the FPGA RAM area corresponding to the matrix data, calculation and accumulation After, calculate the value of r ij , stored in the RAM cache area of L -1 , let j increment, according to the above method to calculate r ij , until the calculation to j = i-1; according to the above method to calculate L -1 The second row of the matrix i = 2 matrix data, until the calculation of L -1 The last row of the matrix i = M-1 matrix data; S33. Due to the parallel computing characteristics of FPGA, when calculating the inverse matrix L of the lower triangular matrix L... -1 Simultaneously, the inverse matrix D of the diagonal matrix D is computed in parallel. -1 Inverse matrix D -1 The reciprocal of the diagonal elements of matrix D, i.e. The on-chip RAM of the FPGA is the inverse matrix D. -1 After allocating a buffer area, the diagonal elements of matrix D are retrieved sequentially from the FPGA's RAM area. Their reciprocals are calculated, and the results are stored in matrix D. -1 In the RAM cache area; S34, the inverse matrix L is calculated -1 and D -1 After that, the inverse matrix is expressed as The matrix (L H ) -1 element values of D -1 are operated according to the principle of matrix multiplication, so that (L H ) -1 is multiplied with the corresponding row and column of D -1 , and the result is temporarily stored in the on-chip block RAM area of the FPGA. After the matrix multiplication of (L H ) -1 and D -1 , the obtained matrix is multiplied with L -1 again according to the principle of matrix multiplication, and the matrix element data obtained by the calculation is stored in the on-chip block RAM of the FPGA.

5. The FPGA and power inverse criterion based spatial adaptive filtering method according to claim 1, wherein, The specific process of the step 5 is as follows: The signal data received by the array antenna is weighted by the optimal weight vector w, that is, each array element is multiplied by the corresponding optimal weight and then added to obtain the output signal, that is, the output signal y(n) = w H (n)x(n).

6. An apparatus for the FPGA and power inverse criterion based spatial adaptive filtering method as claimed in claim 1, the apparatus comprising: The front-end radio frequency chip, the FPGA algorithm acceleration module, and the signal demodulation module, after the front-end radio frequency chip receives signals, the signals are transmitted to the FPGA algorithm acceleration module for filtering, and then the filtered signals are transmitted to the signal demodulation module for demodulation; The FPGA algorithm acceleration module comprises: an array signal data preprocessing module, a self-covariance matrix calculation module, a self-covariance matrix inversion module, a mutual covariance matrix calculation module, an optimal weight vector calculation module, a floating-point number to fixed-point number conversion module, and an optimal weight vector weighting module.

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