A low-power high-voltage switching circuit suitable for thin gate oxide process

Abstract

The present invention relates to a low-power high-voltage switch circuit suitable for thin gate oxide process, belonging to the field of high-voltage domain analog integrated circuits, comprising: a charge pump, a time-delayed self-locking switch, and a high-voltage switch; the charge pump, the time-delayed self-locking switch, and the high-voltage switch are connected in sequence; the charge pump is used to sample the source voltage of the high-voltage switch and generate a corresponding boost control signal; the time-delayed self-locking switch is used to output a gate control signal according to the boost control signal to control the on and off of the high-voltage switch; the time-delayed self-locking switch is provided with a short-circuit switch module; the short-circuit switch module is used to short-circuit the gate and source terminals of the high-voltage switch to turn off the high-voltage switch, and discharge after the high-voltage switch is turned off. When the high-voltage switch is turned off, the present invention first quickly shorts the gate and source terminals of the high-voltage switch through the short-circuit switch module built into the time-delayed self-locking switch, and then slowly discharges the circuit, thereby solving the voltage withstand problem of the pure charge pump structure in the high-voltage switch shutdown action and achieving rapid shutdown of the high-voltage switch.

Description

Technical Field

[0001] The present invention belongs to the field of high-voltage domain analog integrated circuits, and in particular relates to a low-power high-voltage switching circuit suitable for a thin gate oxide layer process. Background Art

[0002] In high-voltage analog integrated circuit design, the design of clocked high-voltage switches is often required, such as switches for high-voltage signal sampling or periodic power drive switches. The use of high-voltage switches can eliminate the complex signal step-down, transmission, and boost process in the high-voltage domain, significantly improving circuit performance and efficiency.

[0003] Traditional high-voltage switch implementations fall into two main categories: the first involves conventional switch connections based on thick-gate oxide processes, and the second involves high-voltage switch designs utilizing thin-gate oxide processes. Thick-gate oxide processes suffer from high manufacturing costs, high switching threshold voltages, and poor switching performance, leading to low market acceptance. Traditional high-voltage switch designs based on thin-gate oxide processes also suffer from technical drawbacks. Firstly, the gate-source withstand voltage of high-voltage transistors in thin-gate oxide processes is only 5V, making them impractical for traditional switch designs and requiring the design of complex boost clamping circuits. Secondly, the level shift circuits and operational amplifiers in floating clamp circuits within traditional high-voltage switch units result in large circuit size and high power consumption, as well as significant switching delays, making rapid shutdown difficult. Therefore, a new type of high-voltage switch suitable for thin-gate oxide processes is needed. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-power high-voltage switching circuit suitable for thin gate oxide layer technology. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a low-power high-voltage switching circuit suitable for a thin gate oxide process, comprising: a charge pump, a time-delayed self-locking switch, and a high-voltage switch; wherein the charge pump, the time-delayed self-locking switch, and the high-voltage switch are connected in sequence; the charge pump is used to sample the source voltage of the high-voltage switch and obtain a boost control signal according to the source voltage of the high-voltage switch; the time-delayed self-locking switch is used to output a gate control signal according to the boost control signal to control the on and off of the high-voltage switch; the time-delayed self-locking switch is provided with a short-circuit switch module; the short-circuit switch module is used to short-circuit the gate and source terminals of the high-voltage switch to turn off the high-voltage switch, and discharge after the high-voltage switch is turned off.

[0006] In one embodiment of the present invention, the charge pump includes: an inverter INV1, an N-type field effect transistor MN3, an N-type field effect transistor MN4, an N-type field effect transistor MN5, an N-type field effect transistor MN6, a diode D1, a diode D2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a capacitor C3; wherein the input end of the inverter INV1 inputs a clock control signal, and the output end is respectively connected to the gate end of the N-type field effect transistor MN3, the lower plate of the capacitor C1 and the lower plate of the capacitor C3; the source end of the N-type field effect transistor MN3 is connected to the ground end, and the drain end is respectively connected to the source end of the N-type field effect transistor MN4 and the lower plate of the capacitor C2; the source end of the N-type field effect transistor MN5, the source end of the N-type field effect transistor MN6 and the diode The input ends of D2 are all connected to the power supply voltage end; the gate end of the N-type field effect transistor MN5, the gate end of the N-type field effect transistor MN6, and the output end of the diode D2 are all connected to the upper plate of the capacitor C1; the drain end of the N-type field effect transistor MN5 is connected to the first end of the resistor R1; the drain end of the N-type field effect transistor MN6 is respectively connected to the first end of the resistor R2 and the input end of the diode D1; the second end of the resistor R1 is respectively connected to the second end of the resistor R2, the first end of the resistor R3, and the output end of the diode D1; the input end and the output end of the diode D1 are both connected to the delayed self-locking switch; the upper plate of the capacitor C3 is connected to the second end of the resistor R3; the drain end of the N-type field effect transistor MN4 is connected to the source end of the high-voltage switch, and the gate end is connected to the gate end of the high-voltage switch.

[0007] In one embodiment of the present invention, the delayed self-locking switch includes: a P-type field effect transistor MP1 and a short-circuit switch module; wherein the source end of the P-type field effect transistor MP1 is connected to the input end of the diode D1, the gate end is connected to the output end of the diode D1, and the drain end is connected to the short-circuit switch module; the short-circuit switch module is respectively connected to the gate end and source end of the high-voltage switch.

[0008] In one embodiment of the present invention, the short-circuit switch module includes: an inverter INV2, an N-type field effect transistor MN7, an N-type field effect transistor MN8, an N-type field effect transistor MN9, a resistor R4, a resistor R5, a resistor R6 and a P-type field effect transistor MP2; wherein the input end of the inverter INV2 inputs a clock control signal, and the output end is connected to the gate end of the N-type field effect transistor MN7 and the gate end of the N-type field effect transistor MN9 respectively; the source end of the N-type field effect transistor MN7 and the source end of the N-type field effect transistor MN9 are both connected to the ground end; the drain end of the N-type field effect transistor MN7 is connected to the second end of the resistor R5; The first end of the resistor R5 is respectively connected to the second end of the resistor R4 and the gate end of the P-type field effect transistor MP2; the source end of the P-type field effect transistor MP2 is respectively connected to the first end of the resistor R4 and the drain end of the N-type field effect transistor MN8; the drain end of the P-type field effect transistor MP2 is respectively connected to the gate end of the N-type field effect transistor MN8 and the first end of the resistor R6; the second end of the resistor R6 is respectively connected to the source end of the N-type field effect transistor MN8 and the drain end of the N-type field effect transistor MN9; the drain end of the N-type field effect transistor MN8 is connected to the gate end of the high-voltage switch, and the source end is connected to the source end of the high-voltage switch.

[0009] In one embodiment of the present invention, the high-voltage switch includes: an N-type field-effect transistor MN1 and an N-type field-effect transistor MN2; the gate terminal of the N-type field-effect transistor MN1 is connected to the gate terminal of the N-type field-effect transistor MN2 and serves as the gate terminal of the high-voltage switch; the source terminal of the N-type field-effect transistor MN1 is connected to the source terminal of the N-type field-effect transistor MN2 and serves as the source terminal of the high-voltage switch.

[0010] In one embodiment of the present invention, the drain end of the N-type field effect transistor MN1 serves as the input end of a low-power high-voltage switching circuit suitable for a thin gate oxide process, and the drain end of the N-type field effect transistor MN2 serves as the output end of the low-power high-voltage switching circuit suitable for a thin gate oxide process.

[0011] In one embodiment of the present invention, the high-voltage switch further includes: a clamping protection module, which is connected in series between the gate terminal and the source terminal of the N-type field effect transistor MN1 and the N-type field effect transistor MN2 to form a discharge path to prevent the N-type field effect transistor MN1 and the N-type field effect transistor MN2 from breaking down.

[0012] In one embodiment of the present invention, the clamping protection module includes: a Zener diode Z1; wherein the first end of the Zener diode Z1 is respectively connected to the source end of the N-type field effect transistor MN1 and the source end of the N-type field effect transistor MN2, and the second end is respectively connected to the gate end of the N-type field effect transistor MN1 and the gate end of the N-type field effect transistor MN2.

[0013] In one embodiment of the present invention, the charge pump and the delayed self-locking switch are both controlled by a clock control signal.

[0014] In one embodiment of the present invention, when the clock control signal turns high, the short-circuit switch module is turned off, the charge pump samples the source voltage of the high-voltage switch, and after boosting, inputs the voltage to the gate of the high-voltage switch through the delayed self-locking switch to turn on the high-voltage switch; when the clock control signal turns low, the short-circuit switch module is turned on to short-circuit the gate and source terminals of the high-voltage switch, so that the high-voltage switch is turned off.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The present invention's low-power, high-voltage switching circuit, suitable for thin-gate oxide processes, utilizes a delayed self-locking switch to ensure the feasibility of a charge pump-based sampling structure within the high-voltage switching circuit. Compared to conventional high-voltage switching circuits that only shut down the high-voltage switch by discharging the gate terminal to the conduction threshold voltage, the delayed self-locking switch's built-in short-circuit switch module quickly shorts the gate and source terminals of the high-voltage switch before slowly discharging the voltage. This solves the voltage withstand issue associated with pure charge pump structures during high-voltage switch shutdown, enabling rapid high-voltage switch shutdown.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic structural diagram of a low-power, high-voltage switching circuit suitable for a thin gate oxide process, provided by an embodiment of the present invention;

[0019] Figure 2 Schematic diagram of the structure of the charge pump and the delayed self-locking switch provided by the embodiment of the present invention;

[0020] Figure 3 Schematic diagram of the structure of the short-circuit switch module in the delayed self-locking switch provided by an embodiment of the present invention;

[0021] Figure 4 This is a structural diagram of a high-voltage switch provided by an embodiment of the present invention;

[0022] Figure 5 This is a turn-on timing diagram of a low-power high-voltage switching circuit suitable for thin gate oxide process provided by an embodiment of the present invention.

[0023] Icon: 100-charge pump; 200-delay self-locking switch; 210-short-circuit switch module; 300-high-voltage switch; 310-clamping protection module. DETAILED DESCRIPTION

[0024] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a low-power high-voltage switching circuit suitable for thin gate oxide layer technology proposed in accordance with the present invention in combination with the accompanying drawings and specific implementation methods.

[0025] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0026] Example 1

[0027] In view of the disadvantages of high power consumption and large size of traditional high voltage switches and the disadvantage that the gate and source of high voltage transistors in thin gate oxide process cannot withstand high voltage, this embodiment provides a low power consumption high voltage switch circuit suitable for thin gate oxide process, such as Figure 1 As shown, Figure 1 The present invention provides a schematic structural diagram of a low-power high-voltage switching circuit suitable for thin gate oxide process.

[0028] In this embodiment, a low-power high-voltage switch circuit suitable for a thin gate oxide process includes: a charge pump 100, a delayed self-locking switch 200, and a high-voltage switch 300; wherein the charge pump 100, the delayed self-locking switch 200, and the high-voltage switch 300 are connected in sequence; the charge pump 100 is used to sample the source voltage of the high-voltage switch 300 and obtain a boost control signal based on the source voltage of the high-voltage switch; the delayed self-locking switch 200 is used to output a gate control signal VG based on the boost control signal to control the on and off of the high-voltage switch 300; the delayed self-locking switch 200 is provided with a short-circuit switch module 210; the short-circuit switch module 210 is used to short-circuit the gate and source terminals of the high-voltage switch 300 to turn off the high-voltage switch 300, and discharge after the high-voltage switch 300 is turned off.

[0029] It is worth noting that the charge pump 100 and the delayed self-locking switch 200 are both controlled by a clock control signal, and their turn-on timing is as follows: Figure 5 As shown, Figure 5 This is a turn-on timing diagram of a low-power high-voltage switching circuit suitable for thin gate oxide process provided by an embodiment of the present invention.

[0030] Specifically, when the clock control signal turns high, the short-circuit switch module 210 is turned off, the charge pump 100 samples the source voltage of the high-voltage switch 300, and after boosting, inputs it to the gate terminal of the high-voltage switch 300 through the delayed self-locking switch 200 to turn on the high-voltage switch 300; when the clock control signal turns low, the short-circuit switch module 210 is turned on to short-circuit the gate terminal and the source terminal of the high-voltage switch 300, so that the high-voltage switch 300 is turned off.

[0031] The operating principle of the low-power high-voltage switch circuit suitable for thin gate oxide processes in this embodiment is as follows: when the clock control signal VC goes high, the charge pump 100 samples the source voltage VS of the high-voltage switch 300 and boosts it to VS+VCC (source voltage+power supply voltage), which is then transmitted to the gate of the high-voltage switch 300 through the delayed self-locking switch 200. At the same time, the N-type field-effect transistor MN1 and the N-type field-effect transistor MN2 in the high-voltage switch 300 are both turned on, completing the conduction of the high-voltage switch 300. When the clock control signal VC goes low, the delayed self-locking switch 200 short-circuits the gate and source of the high-voltage switch 300 through the gate control signal VG, thereby completing the shutdown of the high-voltage switch 300.

[0032] like Figure 2 As shown, Figure 2 It is a structural diagram of a charge pump and a delayed self-locking switch provided by an embodiment of the present invention.

[0033] In this embodiment, the charge pump 100 includes: an inverter INV1, an N-type field effect transistor MN3, an N-type field effect transistor MN4, an N-type field effect transistor MN5, an N-type field effect transistor MN6, a diode D1, a diode D2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, and a capacitor C3; wherein the input end of the inverter INV1 inputs the clock control signal VC, and the output end is respectively connected to the gate end of the N-type field effect transistor MN3, the lower plate of the capacitor C1, and the lower plate of the capacitor C3; the source end of the N-type field effect transistor MN3 is connected to the ground end, and the drain end is respectively connected to the source end of the N-type field effect transistor MN4 and the lower plate of the capacitor C2; the source end of the N-type field effect transistor MN5 and the source end of the N-type field effect transistor MN6 are connected to the ground end. and the input end of the diode D2 are all connected to the power supply voltage end; the gate end of the N-type field effect transistor MN5, the gate end of the N-type field effect transistor MN6 and the output end of the diode D2 are all connected to the upper plate of the capacitor C1; the drain end of the N-type field effect transistor MN5 is connected to the first end of the resistor R1; the drain end of the N-type field effect transistor MN6 is respectively connected to the first end of the resistor R2 and the input end of the diode D1; the second end of the resistor R1 is respectively connected to the second end of the resistor R2, the first end of the resistor R3 and the output end of the diode D1; the input end and the output end of the diode D1 are both connected to the delayed self-locking switch 200; the upper plate of the capacitor C3 is connected to the second end of the resistor R3; the drain end of the N-type field effect transistor MN4 is connected to the source end of the high-voltage switch 300, and the gate end is connected to the gate end of the high-voltage switch 300.

[0034] In this embodiment, the delayed self-locking switch 200 includes: a P-type field effect transistor MP1 and a short-circuit switch module 210; wherein the source end of the P-type field effect transistor MP1 is connected to the input end of the diode D1, the gate end is connected to the output end of the diode D1, and the drain end is connected to the short-circuit switch module 210; the short-circuit switch module 210 is respectively connected to the gate end and the source end of the high-voltage switch 300.

[0035] like Figure 2 As shown, the working principle of the charge pump 100 and the delayed self-locking switch 200 of this embodiment is that:

[0036] When the clock control signal VC turns high, the short-circuit switch module 210 turns off, and the output signal V1 of the inverter INV1 turns low; the upper plate voltage of the capacitor C1 is charged to the source voltage VCC by the diode D2, and the N-type field effect transistors MN3, MN5, and MN6 are all turned off; because the voltage across the capacitor cannot change suddenly, the upper plate voltage of the capacitor C3 is pulled down to the ground voltage GND, and the gate voltage V3 of the P-type field effect transistor MP1 is also pulled down to close to the ground voltage GND. Further, by setting the resistance values ​​of the resistors R1, R2, and R3, the P-type field effect transistor MP1 can be turned on in the above situation, and the gate control signal VG is pulled up to the power supply voltage VCC by the capacitor C2; the N-type field effect transistor MN4 is turned on, and the source terminal of the high-voltage switch 300 is connected to the lower plate of the capacitor C2. The gate control signal VG is now VS+VCC, causing the high-voltage switch 300 to be turned on.

[0037] After the high-voltage switch 300 is turned on, the high-voltage signals at the input port A and the output port B of the high-voltage switch 300 are transmitted to its source end. Due to the bootstrap effect of the capacitor C2, the gate-end control signal VG is always maintained at VS+VCC, so that the high-voltage switch 300 remains turned on.

[0038] When the clock control signal VC turns low, the short-circuit switch module 210 turns on, short-circuiting the source and gate terminals of the high-voltage switch 300 and discharging it to ground voltage GND. The N-type field-effect transistor MN4 turns off. The output signal V1 of the inverter INV1 turns high, the N-type field-effect transistor MN3 turns on, and the voltage on the lower plate of the capacitor C2 is pulled down to ground voltage GND. At the same time, the voltage on the upper plate of the capacitor C1 is automatically boosted to twice the power supply voltage VCC. The N-type field-effect transistors MN5 and MN6 are both turned on, and the voltage on the upper plate of the capacitor C2 is also pulled up and charged to the power supply voltage VCC. The voltage on the upper plate of the capacitor C3 is also automatically boosted to the power supply voltage VCC, thereby quickly turning off the P-type field-effect transistor MP1.

[0039] It is worth noting that the diode D1 is provided to prevent the P-type field effect transistor MP1 from breaking down due to an excessive gate-source voltage during the operation of the charge pump 100 .

[0040] like Figure 3 As shown, Figure 3 It is a structural diagram of a short-circuit switch module in a delayed self-locking switch provided by an embodiment of the present invention.

[0041] In this embodiment, the short-circuit switch module 210 includes: an inverter INV2, an N-type field effect transistor MN7, an N-type field effect transistor MN8, an N-type field effect transistor MN9, a resistor R4, a resistor R5, a resistor R6, and a P-type field effect transistor MP2; wherein the input end of the inverter INV2 inputs a clock control signal, and the output end is connected to the gate end of the N-type field effect transistor MN7 and the N-type field effect transistor MN9 respectively; the source end of the N-type field effect transistor MN7 and the N-type field effect transistor MN9 are both connected to the ground end; the drain end of the N-type field effect transistor MN7 is connected to the second end of the resistor R5. ; The first end of the resistor R5 is respectively connected to the second end of the resistor R4 and the gate end of the P-type field effect transistor MP2; the source end of the P-type field effect transistor MP2 is respectively connected to the first end of the resistor R4 and the drain end of the N-type field effect transistor MN8; the drain end of the P-type field effect transistor MP2 is respectively connected to the gate end of the N-type field effect transistor MN8 and the first end of the resistor R6; the second end of the resistor R6 is respectively connected to the source end of the N-type field effect transistor MN8 and the drain end of the N-type field effect transistor MN9; the drain end of the N-type field effect transistor MN8 is connected to the gate end of the high-voltage switch 300, and the source end is connected to the source end of the high-voltage switch 300.

[0042] like Figure 3 As shown, the working principle of the short-circuit switch module 210 of this embodiment is:

[0043] When the clock control signal VC turns high, the output signal of the inverter INV2 turns low. When the high-voltage switch 300 needs to be turned on, the N-type field effect transistors MN7, MN8 and MN9 are all turned off, and the P-type field effect transistor MP2 is also turned off.

[0044] During the high-voltage switch conduction operation of the charge pump 100 and the delayed self-locking switch 200, the gate-end control signal VG is always higher than the source-end voltage VS of the high-voltage switch 300, and the short-circuit switch module 210 always disconnects the gate and source ends of the high-voltage switch 300 to avoid interference with the high-voltage signal transmitted thereto.

[0045] When the clock control signal VC turns low, the output of the inverter INV2 turns high, and the high-voltage switch 300 needs to be turned off. The N-type field-effect transistor MN7 turns on, and the resistors R4 and R5 discharge the gate terminal of the high-voltage switch 300. The voltage drop across the resistor R4 turns on the P-type field-effect transistor MP2. The discharge current generated by the P-type field-effect transistor MP2 and the N-type field-effect transistor MN9 forms a voltage difference across the resistor R6, turning on the N-type field-effect transistor MN8, thereby quickly shorting the gate terminal and the source terminal of the high-voltage switch 300, thereby turning off the high-voltage switch 300. Finally, the N-type field-effect transistors MN7 and MN9 discharge the gate control signal VG and the source terminal voltage VS of the high-voltage switch 300 to the ground voltage GND.

[0046] It is worth noting that the feasibility of applying the charge pump 100 to the high-voltage switch circuit is ensured by the delayed self-locking switch 200. When the high-voltage switch 300 is turned off, the short-circuit switch module 210 built into the delayed self-locking switch 200 first quickly short-circuits the gate control signal VG and the source voltage VS of the high-voltage switch 300 and then slowly discharges. This process can perfectly solve the voltage resistance problem in the turn-off action of applying a pure charge pump structure to the high-voltage switch, and also realizes the rapid shutdown of the high-voltage switch.

[0047] In this embodiment, the high-voltage switch 300 includes: an N-type field-effect transistor MN1 and an N-type field-effect transistor MN2; the gate terminal of the N-type field-effect transistor MN1 is connected to the gate terminal of the N-type field-effect transistor MN2 and serves as the gate terminal of the high-voltage switch 300; the source terminal of the N-type field-effect transistor MN1 is connected to the source terminal of the N-type field-effect transistor MN2 and serves as the source terminal of the high-voltage switch 300.

[0048] Specifically, the drain end of the N-type field effect transistor MN1 serves as the input end or output end of the low-power high-voltage switching circuit suitable for the thin gate oxide layer process; correspondingly, the drain end of the N-type field effect transistor MN2 serves as the output end or input end of the low-power high-voltage switching circuit suitable for the thin gate oxide layer process.

[0049] In an optional embodiment, the high-voltage switch 300 further includes: a clamping protection module 310, which is connected in series between the gate terminal and the source terminal of the N-type field effect transistor MN1 and the N-type field effect transistor MN2 to form a discharge path to prevent the N-type field effect transistor MN1 and the N-type field effect transistor MN2 from breaking down.

[0050] like Figure 4 As shown, Figure 4 It is a structural schematic diagram of a high-voltage switch provided by an embodiment of the present invention.

[0051] Specifically, the clamping protection module 310 includes: a Zener diode Z1; wherein the first end of the Zener diode Z1 is respectively connected to the source end of the N-type field effect transistor MN1 and the N-type field effect transistor MN2, and the second end is respectively connected to the gate end of the N-type field effect transistor MN1 and the N-type field effect transistor MN2.

[0052] The principle is that the clamping protection module 310 detects the voltage difference between the gate control signal VG and the source voltage VS of the high-voltage switch 300. When VG-VS exceeds the gate-source withstand voltage of the N-type field-effect transistor MN1 and the N-type field-effect transistor MN2, it conducts to form a discharge path from the gate of the high-voltage switch 300 to its source, thereby protecting the functions of the N-type field-effect transistor MN1 and the N-type field-effect transistor MN2. Taking the Zener diode Z1 as an example, when VG-VS exceeds 5.5V, the Zener diode Z1 conducts in reverse, generating a current discharge from the gate of the high-voltage switch 300 to its source, thereby clamping VG-VS to 5.5V.

[0053] The present invention's low-power, high-voltage switching circuit, suitable for thin-gate oxide processes, utilizes a delayed self-locking switch to ensure the feasibility of a charge pump-based sampling structure within the high-voltage switching circuit. Compared to conventional high-voltage switching circuits that only shut down the high-voltage switch by discharging the gate terminal to the conduction threshold voltage, the delayed self-locking switch's built-in short-circuit switch module quickly shorts the gate and source terminals of the high-voltage switch before slowly discharging the voltage. This solves the voltage withstand issue associated with pure charge pump structures during high-voltage switch shutdown, enabling rapid high-voltage switch shutdown.

[0054] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0055] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A low-power high-voltage switching circuit suitable for thin gate oxide process, characterized in that: include: A charge pump (100), a time-delayed self-locking switch (200), and a high-voltage switch (300); Wherein, the charge pump (100), the time-delay self-locking switch (200) and the high-voltage switch (300) are connected in sequence; The charge pump (100) is used to sample the source terminal voltage of the high-voltage switch (300) and obtain a boost control signal according to the source terminal voltage of the high-voltage switch (300); The delayed self-locking switch (200) is used to output a gate control signal according to the boost control signal to control the opening and closing of the high-voltage switch (300); The time-delay self-locking switch (200) is provided with a short-circuit switch module (210); the short-circuit switch module (210) is used to short-circuit the gate terminal and the source terminal of the high-voltage switch (300) to turn off the high-voltage switch (300), and to discharge after the high-voltage switch (300) is turned off; The charge pump (100) and the delayed self-locking switch (200) are both controlled by a clock control signal; when the clock control signal turns high, the short-circuit switch module (210) turns off, the charge pump (100) samples the source terminal voltage of the high-voltage switch (300), and after boosting, inputs the voltage to the gate terminal of the high-voltage switch (300) through the delayed self-locking switch (200) to turn on the high-voltage switch (300); when the clock control signal turns low, the short-circuit switch module (210) turns on to short-circuit the gate terminal and the source terminal of the high-voltage switch (300), so that the high-voltage switch (300) is turned off.

2. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 1, characterized in that: The charge pump (100) comprises: an inverter INV1, an N-type field effect transistor MN3, an N-type field effect transistor MN4, an N-type field effect transistor MN5, an N-type field effect transistor MN6, a diode D1, a diode D2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a capacitor C3; The input end of the inverter INV1 inputs a clock control signal, and the output end is connected to the gate end of the N-type field effect transistor MN3, the lower plate of the capacitor C1 and the lower plate of the capacitor C3 respectively; The source terminal of the N-type field effect transistor MN3 is connected to the ground terminal, and the drain terminal is respectively connected to the source terminal of the N-type field effect transistor MN4 and the lower plate of the capacitor C2; the source terminal of the N-type field effect transistor MN5, the source terminal of the N-type field effect transistor MN6, and the input terminal of the diode D2 are all connected to the power supply voltage terminal; the gate terminal of the N-type field effect transistor MN5, the gate terminal of the N-type field effect transistor MN6, and the output terminal of the diode D2 are all connected to the upper plate of the capacitor C1; The drain end of the N-type field effect transistor MN5 is connected to the first end of the resistor R1; the drain end of the N-type field effect transistor MN6 is respectively connected to the first end of the resistor R2 and the input end of the diode D1; the second end of the resistor R1 is respectively connected to the second end of the resistor R2, the first end of the resistor R3, and the output end of the diode D1; The input end and the output end of the diode D1 are both connected to the delayed self-locking switch (200); The upper plate of the capacitor C3 is connected to the second end of the resistor R3; The drain terminal of the N-type field effect transistor MN4 is connected to the source terminal of the high-voltage switch (300), and the gate terminal is connected to the gate terminal of the high-voltage switch (300).

3. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 2, characterized in that: The delayed self-locking switch (200) comprises: a P-type field effect transistor MP1 and a short-circuit switch module (210); wherein the source end of the P-type field effect transistor MP1 is connected to the input end of the diode D1, the gate end is connected to the output end of the diode D1, and the drain end is connected to the short-circuit switch module (210); The short-circuit switch module (210) is respectively connected to the gate terminal and the source terminal of the high-voltage switch (300).

4. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 3, characterized in that: The short-circuit switch module (210) comprises: an inverter INV2, an N-type field effect transistor MN7, an N-type field effect transistor MN8, an N-type field effect transistor MN9, a resistor R4, a resistor R5, a resistor R6, and a P-type field effect transistor MP2; The input terminal of the inverter INV2 inputs a clock control signal, and the output terminal is respectively connected to the gate terminals of the N-type field effect transistor MN7 and the N-type field effect transistor MN9; the source terminals of the N-type field effect transistor MN7 and the N-type field effect transistor MN9 are both connected to the ground terminal; the drain terminal of the N-type field effect transistor MN7 is connected to the second terminal of the resistor R5; the first terminal of the resistor R5 is respectively connected to the second terminal of the resistor R4 and the gate terminal of the P-type field effect transistor MP2; The source terminal of the P-type field effect transistor MP2 is respectively connected to the first end of the resistor R4 and the drain terminal of the N-type field effect transistor MN8; the drain terminal of the P-type field effect transistor MP2 is respectively connected to the gate terminal of the N-type field effect transistor MN8 and the first end of the resistor R6; The second end of the resistor R6 is connected to the source end of the N-type field effect transistor MN8 and the drain end of the N-type field effect transistor MN9 respectively; The drain terminal of the N-type field effect transistor MN8 is connected to the gate terminal of the high-voltage switch (300), and the source terminal is connected to the source terminal of the high-voltage switch (300).

5. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 1, characterized in that: The high-voltage switch (300) comprises: an N-type field effect transistor MN1 and an N-type field effect transistor MN2; The gate terminal of the N-type field effect transistor MN1 is connected to the gate terminal of the N-type field effect transistor MN2 and serves as the gate terminal of the high-voltage switch (300); The source terminal of the N-type field effect transistor MN1 is connected to the source terminal of the N-type field effect transistor MN2 and serves as the source terminal of the high-voltage switch (300).

6. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 5, characterized in that: The drain end of the N-type field effect transistor MN1 serves as the input end of the low-power high-voltage switching circuit suitable for thin gate oxide layer technology, and the drain end of the N-type field effect transistor MN2 serves as the output end of the low-power high-voltage switching circuit suitable for thin gate oxide layer technology.

7. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 5, characterized in that: The high-voltage switch (300) further comprises: a clamping protection module (310), the clamping protection module (310) being connected in series between the gate terminal and the source terminal of the N-type field effect transistor MN1 and the N-type field effect transistor MN2, and being used to form a discharge path to prevent the N-type field effect transistor MN1 and the N-type field effect transistor MN2 from breaking down.

8. The low-power high-voltage switching circuit suitable for thin gate oxide process according to claim 7, characterized in that: The clamping protection module (310) comprises: a Zener diode Z1; wherein the first end of the Zener diode Z1 is respectively connected to the source end of the N-type field effect transistor MN1 and the source end of the N-type field effect transistor MN2, and the second end is respectively connected to the gate end of the N-type field effect transistor MN1 and the gate end of the N-type field effect transistor MN2.

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