Pixel-level analog-to-digital converter applied to infrared focal plane reading circuit
By introducing a CLK generator into the pixel-level ADC circuit, controlling the working time and delay units of the comparison circuit, the problems of high power consumption and poor linearity of the traditional pixel-level ADC circuit are solved, and a pixel-level analog-to-digital converter with lower power consumption and higher readout performance are realized.
Patent Information
- Application Number
- CN202510085336.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-20
- Publication Date
- 2025-05-06
AI Technical Summary
Traditional pixel-level ADC circuits have large average power consumption, and the input-output linearity difference caused by comparator power consumption limitation cannot be applied to infrared reading circuits of large-surface arrays.
The CLK generator is introduced, and the opening and closing of the tail current of the subsequent comparison circuit is controlled through the CLK generator, which reduces the working time of the comparison circuit, and uses the CLK generator as a delay unit in the input stage circuit to avoid adding the delay unit in the subsequent stage of the comparison circuit.
It greatly reduces the average power consumption of pixel units, solves the problem of poor input-output linearity, and has certain optimization in area, and is suitable for large-surface infrared focal infrared reading circuits.
Smart Images
Figure CN119945443A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of infrared focal plane readout circuits and relates to a pixel-level analog-to-digital converter applied to infrared focal plane readout circuits. Background Art
[0002] Since the detection of infrared radiation does not require auxiliary means such as external lighting and is not easily restricted by conditions such as climate, region, and electromagnetic interference, it was first developed for military needs such as battle monitoring and missile guidance. Later, with the advancement and promotion of microelectronics technology, it was gradually used in traditional fields such as medical imaging, meteorological monitoring, and industrial production.
[0003] Nowadays, the development direction of infrared focal plane readout circuits tends to be digital. By integrating ADC (analog-to-digital converter) into the pixel unit, advantages such as high readout and low noise can be obtained. However, the pixel-level digital readout circuit needs to integrate signal preprocessing circuit, sampling circuit, analog-to-digital conversion circuit and corresponding storage structure within a limited pixel area, which has high requirements for power consumption and layout design. However, with the development of CMOS technology in recent years, several pixel-level ADCs suitable for this structure have gradually emerged. The performance of the pixel-level ADC determines the performance of the entire infrared detection system. The pixel-level ADC of the current infrared focal plane array readout circuit needs to be improved.
[0004] Traditional pixel-level ADC circuit structure, such as Figure 1 As shown, it includes a comparator, an input stage circuit, a counter circuit, and a feedback circuit. The upper plate of the integral capacitor FD is connected to the positive end of the comparator, and the reference level is connected to the negative end of the comparator. The input of the comparator is connected to the input end of the counter and the gate of the reset switch tube through the inverter chain. Its working principle is as follows: before the exposure stage begins, the integral capacitor C1 resets the voltage of the FD node to VDD through the reset tube. When the exposure stage begins, the photodiode is sensitive to light and generates a photocurrent. The integral capacitor C1 begins to integrate the voltage of the FD node and keeps decreasing. At this time, the FD node voltage is connected to the positive end of the comparator composed of M1-M5. When the FD node voltage drops below the reference level, the output of the comparator flips to generate a low-level signal, which outputs the Vpulse signal through the inverter chain composed of M7-M15 to start counting the counter, and at the same time, the reset tube M17 is turned on to reset the FD node voltage to VDD. At this time, the output result of the comparator becomes a high level, which turns off the reset tube M17, and the integration-reset process is repeated continuously during the exposure stage.
[0005] For the traditional pixel-level ADC circuit, when the light intensity increases or the pixel array increases, the frequency and number of comparator flips during the exposure time increase. At the same time, since the comparator in this structure can only use a static comparator, it means that the static power consumption will always exist during the exposure time and the dynamic power consumption will also increase with the change of the band. The comparator used in the traditional pixel-level ADC is a subthreshold comparator. By adding the same bias to the gate of the M5 tube and the M6 tube, the input tubes M1 and M2 work in the subthreshold region. At the same time, the inverter composed of M7 and M8 is limited. This can shape the output signal of the amplifier on the one hand, and control the leakage current caused by the slowly changing signal on the other hand, thereby effectively reducing power consumption. However, the average power consumption of this structure is large, and the limitation of power consumption will also deteriorate the input-output linearity of the comparator and affect the readout performance, so it cannot be applied to the infrared readout circuit of a large array. Summary of the invention
[0006] The purpose of the present invention is to provide a pixel-level analog-to-digital converter applied to an infrared focal plane readout circuit, which solves the problems of large average power consumption of traditional pixel-level ADC circuits and poor input-output linearity caused by comparator power consumption limitations in the prior art.
[0007] The technical solution adopted by the present invention is a pixel-level analog-to-digital converter applied to an infrared focal plane readout circuit, comprising an input stage circuit, the input stage circuit is connected to the input end of a CLK generator, the output end of the CLK generator is connected to the input end of a comparison circuit, and the output end of the comparison circuit is connected to a counter.
[0008] The present invention is also characterized in that: The input stage circuit is composed of a photodiode PD and a transmission tube M0. The cathode of the photodiode PD is connected to the drain of the transmission tube M0, the anode of the photodiode PD is connected to GND, the source of the transmission tube M0 is connected to the upper plate FD of the integration capacitor FD, the source of the transmission tube M0 is also connected to the CLK generator, the gate of the transmission tube M0 is connected to the bias voltage VBais, the source of the transmission tube M0 is also connected to the drain of the reset tube M17, the source of the reset tube M17 is connected to VDD, and the gate of the reset tube M17 is connected to the output end of the comparison circuit.
[0009] The CLK generator comprises a bias circuit, the bias circuit is connected with a starvation inverter, the upper plate of the integral capacitor FD is connected with the starvation inverter, the starvation inverter is connected with an output shaping circuit, and the output shaping circuit is connected with the input end of the comparison circuit.
[0010] The bias circuit includes transistors M1 to M4, the gate of transistor M1 is connected to an external bias voltage Vb, the drain of transistor M1 is connected to the gate of transistor M2, the gates of transistor M2 and transistor M3 are connected to VDD and GND respectively, the drain of transistor M2 is connected to the source of transistor M3, the drain of transistor M4 is connected to the drain of transistor M3, the source of transistor M4 is connected to VDD, and the gate of transistor M4 is connected to the starved inverter and the drain of transistor M3.
[0011] The starved inverter includes transistors M5 to M8, the gate of transistor M4 is connected to the gate of transistor M5, the source of transistor M5 is connected to VDD, the drain of transistor M5 is connected to the source of transistor M6, the gates of transistor M6 and transistor M7 are connected and connected to the upper plate of the integrating capacitor FD, the drains of transistor M6 and transistor M7 are connected and connected to the output shaping circuit, the source of transistor M7 is connected to the drain of transistor M8, the source of transistor M8 is connected to GND, and the gate of transistor M8 is connected to the external bias voltage Vb.
[0012] The output shaping circuit includes a transistor M9 and a transistor M10, wherein the gates of the transistor M9 and the transistor M10 are connected to each other and are connected to the drains of the transistor M6 and the transistor M7, the drains of the transistor M9 and the transistor M10 are connected to each other and are connected to the comparison circuit, and the sources of the transistor M9 and the transistor M10 are connected to VDD and GND respectively.
[0013] The comparison circuit includes an op amp input switch tube M11 and an op amp circuit. The source of the op amp input switch tube M11 is connected to the input signal Vin, and the gate of the op amp input switch tube M11 is connected to the output end of the CLK generator, that is, the gate of the op amp input switch tube M11 is connected to the drains of the transistor M9 and the transistor M10, and the drain of the op amp input switch tube M11 is connected to the op amp circuit.
[0014] The operational amplifier circuit includes an operational amplifier input tube M12, an operational amplifier input tube M13, an operational amplifier input tube M14, an operational amplifier input tube M15, and a tail current tube M16. The gate of the operational amplifier input tube M12 is connected to the drain of the operational amplifier input switch tube M11, the drain of the operational amplifier input tube M12 is connected to the source of the operational amplifier input tube M13, the drain of the operational amplifier input tube M13 is connected to VDD, the gate of the operational amplifier input tube M13 is connected to the drain of the operational amplifier input tube M12 and the gate of the operational amplifier input tube M14, the source of the operational amplifier input tube M14 is connected to VDD, the drain of the operational amplifier input tube M14 is connected to the drain of the operational amplifier input tube M15, and the operational amplifier input tube The gate of M15 is connected to the reference level Vref, the drain of the tail current tube M16 is connected to the source of the op amp input tube M15 and the op amp input tube M112, the source of the tail current tube M16 is connected to GND, the gate of the tail current tube M16 is connected to the output end of the CLK generator, that is, the drain of the transistor M9 and the transistor M10, the drain of the op amp input tube M15 and the op amp input tube M14 is connected to the counter, and then connected to the gate of the reset tube M17 after passing through the counter, that is, the drain of the op amp input tube M15 and the op amp input tube M14 generates a pulse voltage Vpulse, which is connected to the gate of the reset tube M17 after passing through the counter.
[0015] When reading out, at the beginning of the exposure time, the input stage circuit is first used to make the integrating capacitor start to integrate the upper plate FD voltage and connect it to the input end of the CLK generator. At this time, the output signal of the CLK generator is low level, and the tail current tube M16 connected to the comparison circuit is turned off. When the integrating capacitor continues to integrate, the voltage value of the upper plate FD of the integrating capacitor is less than the threshold voltage of the transistor M7 in the CLK generator, and the output voltage of the CLK generator becomes high level, so that the tail current tube M16 of the comparison circuit is turned on, the comparison circuit works normally, and the input signal switch tube of the comparison circuit works normally; when the comparison circuit works normally, the input signal Vi The voltage on the upper plate of the integrating capacitor is connected to the positive end of the comparison circuit, that is, the gate of the input tube M12 of the operational amplifier, through the switch tube M11 at the input end of the operational amplifier. The reference level Vref is connected to the negative end of the comparison circuit, that is, the gate of the input tube M15 of the operational amplifier. When the voltage on the upper plate of the integrating capacitor drops below the reference level Vref, the output signal of the comparison circuit is reversed, causing the counter to start counting and the reset tube M17 to turn on and reset the integrating capacitor to a high level. The output of the CLK generator becomes a low level, causing the tail current tube M16 of the comparison circuit to turn off and the output of the comparison circuit to be reversed. The above process is repeated continuously during the exposure time until the exposure time ends.
[0016] The beneficial effects of the present invention are: The present invention reduces the working time of the comparison circuit by introducing a CLK generator, and controls the opening and closing of the tail current of the subsequent comparison circuit through the CLK generator. At the same time, the CLK generator also controls the input end of the comparison circuit so that the delay unit does not need to be added after the comparison circuit is generated at this level to ensure the reset of the integration capacitor. Compared with the traditional structure, this structure greatly reduces the average power consumption of the pixel unit, and solves the problem of input-output linearity difference caused by the power consumption limitation of the comparator, and has certain optimization in terms of area. The pixel-level ADC is used in the large-area array infrared focal infrared readout circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a diagram of the traditional pixel-level ADC circuit structure; Figure 2 It is a circuit diagram of a pixel-level analog-to-digital converter of the present invention applied to an infrared focal plane readout circuit; Figure 3 It is a diagram of the output result of the comparison circuit when the pixel-level analog-to-digital converter of the infrared focal plane readout circuit of the present invention is used for reading.
[0018] In the figure: 1. Input stage circuit, 2. CLK generator, 3. Comparison circuit, 4. Counter. DETAILED DESCRIPTION
[0019] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
[0020] Example 1 A pixel-level analog-to-digital converter is used in an infrared focal plane readout circuit, and its circuit is as follows Figure 1 As shown, it includes an input stage circuit 1, the input stage circuit 1 is connected to the input end of a CLK generator 2, the output end of the CLK generator 2 is connected to the input end of a comparison circuit 3, and the output end of the comparison circuit 3 is connected to a counter 4.
[0021] That is, based on the pixel-level ADC circuit, the present invention adds a CLK generator circuit at the front end of the comparison circuit to control the opening and closing of the comparison circuit.
[0022] Example 2 On the basis of Example 1, the input stage circuit 1 is composed of a photodiode PD and a transmission tube M0, the cathode of the photodiode PD is connected to the drain of the transmission tube M0, the anode of the photodiode PD is connected to GND, the source of the transmission tube M0 is connected to the upper plate FD of the integration capacitor FD, the source of the transmission tube M0 is also connected to the CLK generator 2, the gate of the transmission tube M0 is connected to the bias voltage VBais, the source of the transmission tube M0 is also connected to the drain of the reset tube M17, the source of the reset tube M17 is connected to VDD, and the gate of the reset tube M17 is connected to the output end of the comparison circuit 3. When the exposure stage starts, the photodiode PD receives the infrared signal to generate photocurrent, and at the same time the CLK generator 2 turns on the pixel-level ADC to start working.
[0023] Example 3 Based on Example 2, the CLK generator 2 includes a bias circuit, the bias circuit is connected to a starved inverter, the upper plate of the integrating capacitor FD is connected to the starved inverter, the starved inverter is connected to an output shaping circuit, and the output shaping circuit is connected to the input end of the comparison circuit 3.
[0024] The bias circuit includes transistors M1 to M4, the gate of transistor M1 is connected to an external bias voltage Vb, the drain of transistor M1 is connected to the gate of transistor M2, the gates of transistor M2 and transistor M3 are connected to VDD and GND respectively, the drain of transistor M2 is connected to the source of transistor M3, the drain of transistor M4 is connected to the drain of transistor M3, the source of transistor M4 is connected to VDD, and the gate of transistor M4 is connected to the starved inverter and the drain of transistor M3.
[0025] The starved inverter includes transistors M5 to M8, the gate of transistor M4 is connected to the gate of transistor M5, the source of transistor M5 is connected to VDD, the drain of transistor M5 is connected to the source of transistor M6, the gates of transistor M6 and transistor M7 are connected and connected to the upper plate of the integrating capacitor FD, the drains of transistor M6 and transistor M7 are connected and connected to the output shaping circuit, the source of transistor M7 is connected to the drain of transistor M8, the source of transistor M8 is connected to GND, and the gate of transistor M8 is connected to the external bias voltage Vb.
[0026] The output shaping circuit includes a transistor M9 and a transistor M10, wherein the gates of the transistor M9 and the transistor M10 are connected to each other and are connected to the drains of the transistor M6 and the transistor M7, the drains of the transistor M9 and the transistor M10 are connected to each other and are connected to the comparison circuit 3, and the sources of the transistor M9 and the transistor M10 are connected to VDD and GND respectively.
[0027] The bias circuit provides bias control for the current flowing through the branch of transistors M5 to M8. The gates of transistors M9 and M10 are connected to the drains of transistors M6 and M7 to form a starvation inverter to shape the output of the CLK generator. The output of the CLK generator is connected to the gate of the input switch tube M11 of the comparison circuit 3.
[0028] When the exposure phase begins, the photodiode PD receives the infrared signal and generates photocurrent, while the transistor M1 turns on the pixel-level ADC and starts working.
[0029] Example 4 On the basis of Embodiment 3, the comparison circuit 3 includes an op amp input switch tube M11 and an op amp circuit, the source of the op amp input switch tube M11 is connected to the input signal Vin, the gate of the op amp input switch tube M11 is connected to the output end of the CLK generator 2, that is, the gate of the op amp input switch tube M11 is connected to the drains of the transistor M9 and the transistor M10, and the drain of the op amp input switch tube M11 is connected to the op amp circuit.
[0030] The operational amplifier circuit includes an operational amplifier input tube M12, an operational amplifier input tube M13, an operational amplifier input tube M14, an operational amplifier input tube M15, and a tail current tube M16. The gate of the operational amplifier input tube M12 is connected to the drain of the operational amplifier input switch tube M11, the drain of the operational amplifier input tube M12 is connected to the source of the operational amplifier input tube M13, the drain of the operational amplifier input tube M13 is connected to VDD, the gate of the operational amplifier input tube M13 is connected to the drain of the operational amplifier input tube M12 and the gate of the operational amplifier input tube M14, the source of the operational amplifier input tube M14 is connected to VDD, the drain of the operational amplifier input tube M14 is connected to the drain of the operational amplifier input tube M15, and the operational amplifier input tube M The gate of the tail current tube M15 is connected to the reference level Vref, the drain of the tail current tube M16 is connected to the source of the operational amplifier input tube M15 and the operational amplifier input tube M112, the source of the tail current tube M16 is connected to GND, the gate of the tail current tube M16 is connected to the output end of the CLK generator, that is, the drain of the transistor M9 and the transistor M10, the drain of the operational amplifier input tube M15 and the operational amplifier input tube M14 is connected to the counter 4, and then connected to the gate of the reset tube M17 after passing through the counter 4, that is, the drain of the operational amplifier input tube M15 and the operational amplifier input tube M14 generates a pulse voltage Vpulse, which is connected to the gate of the reset tube M17 after passing through the counter 4.
[0031] Example 5 When the pixel-level analog-to-digital converter used in the infrared focal plane readout circuit in Example 4 is used for reading, at the beginning of the exposure time, the input stage circuit 1 is first used to make the integrating capacitor start to integrate the upper plate FD voltage and connect it to the input end of the CLK generator 2. At this time, the output signal of the CLK generator 2 is low level, and the tail current tube M16 connected to the comparison circuit turns off. When the integrating capacitor continues to integrate so that the voltage value of the upper plate FD of the integrating capacitor is less than the threshold voltage of the transistor M7 in the CLK generator, the output voltage of the CLK generator becomes high level, so that the tail current tube M16 of the comparison circuit is turned on, the comparison circuit 3 works normally, and the input signal switch tube of the comparison circuit 3 works normally; when When the comparison circuit 3 works normally, the input signal Vin, the voltage on the upper plate of the integrating capacitor, is connected to the positive end of the comparison circuit 3, that is, the gate of the op amp input tube M12, through the op amp input switch tube M11, and the reference level Vref is connected to the negative end of the comparison circuit, that is, the gate of the op amp input tube M15. When the voltage on the upper plate of the integrating capacitor drops below the reference level Vref, the output signal of the comparison circuit is reversed, causing the counter to start counting and the reset tube M17 to turn on and reset the integrating capacitor to a high level. The output of the CLK generator 2 becomes a low level, causing the tail current tube M16 of the comparison circuit to turn off and the output of the comparison circuit to be reversed. The above process is repeated continuously during the exposure time until the exposure time ends.
[0032] Example 6 On the basis of Example 5, M0, M1, M2, M7, M8, M10, M11, M12, M15, and M16 use NMOS tubes, and M3, M4, M5, M6, M9, M13, M14, and M17 use PMOS tubes.
[0033] Example 7 On the basis of Example 6, the present invention uses the input stage circuit 1 to make the integrating capacitor start to integrate the upper plate voltage and connect it to the input end of the CLK generator. At this time, the output signal of the CLK generator is low level, and the tail current tube M16 connected to the comparison circuit makes the tail current tube turned off. When the integrating capacitor continues to integrate and makes the upper plate voltage value of the integrating capacitor less than the threshold voltage of the NMOS tube (transistor M7) in the CLK generator, the output voltage of the CLK generator becomes high level, making the tail current tube M16 of the comparison circuit turned on, the comparison circuit works normally, and the op amp input switch tube M11 of the comparison circuit 3 works normally.
[0034] When the comparison circuit works normally, the voltage on the upper plate of the input signal integration capacitor is connected to the positive terminal of the comparison circuit, and the reference level is connected to the negative terminal of the comparison circuit. When the voltage on the upper plate of the integration capacitor drops below the reference level, the output signal of the comparison circuit flips, causing the counter to start counting and turning on the reset tube M7 to reset the integration capacitor to a high level. The output of the CLK generator becomes a low level, causing the tail current tube M16 of the comparison circuit to turn off and the output of the comparison circuit to flip. The above process is repeated during the exposure time until the exposure time ends.
[0035] During the circuit operation, the present invention introduces a CLK generator based on the traditional structure, and uses the CLK generator as a delay unit without adding a delay unit in the later stage of the comparison circuit, thereby optimizing the area without excessive area overhead.
[0036] The threshold voltage of the NMOS tube (transistor M7) of the CLK generator introduced in the present invention is higher than the reference level connected to the negative end of the comparison circuit (that is, the reference level in the comparison circuit is set lower than the threshold voltage of the transistor M7 during operation, that is, the reference voltage connected from the outside is lower than the threshold voltage of the transistor M7 during operation). During the exposure process, a preliminary comparison is first performed through CLK, and then the comparison circuit is allowed to make a comparison to reduce the working time of the comparison circuit. Through the above method, a pixel-level analog-to-digital converter with lower power consumption and better readout performance applied to an infrared focal plane readout circuit is obtained, which provides a specific and feasible implementation plan for the application of pixel-level ADC in a large-array infrared focal plane readout circuit.
Claims
1. A pixel-level analog-to-digital converter for an infrared focal plane readout circuit, characterized in that: The invention comprises an input stage circuit (1), wherein the input stage circuit (1) is connected to the input end of a CLK generator (2), the output end of the CLK generator (2) is connected to the input end of a comparison circuit (3), and the output end of the comparison circuit (3) is connected to a counter (4).
2. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 1, characterized in that: The input stage circuit (1) is composed of a photodiode PD and a transmission tube M0, wherein the cathode of the photodiode PD is connected to the drain of the transmission tube M0, the anode of the photodiode PD is connected to GND, the source of the transmission tube M0 is connected to the upper plate FD of the integration capacitor FD, the source of the transmission tube M0 is also connected to the CLK generator (2), the gate of the transmission tube M0 is connected to the bias voltage VBais, the source of the transmission tube M0 is also connected to the drain of the reset tube M17, the source of the reset tube M17 is connected to VDD, and the gate of the reset tube M17 is connected to the output end of the comparison circuit (3).
3. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 2, characterized in that: The CLK generator (2) comprises a bias circuit, the bias circuit is connected to a starvation inverter, the upper plate of the integral capacitor FD is connected to the starvation inverter, the starvation inverter is connected to an output shaping circuit, and the output shaping circuit is connected to an input end of the comparison circuit (3).
4. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 3, characterized in that: The bias circuit includes transistors M1 to M4, the gate of the transistor M1 is connected to an external bias voltage Vb, the drain of the transistor M1 is connected to the gate of the transistor M2, the gates of the transistors M2 and M3 are connected to VDD and GND respectively, the drain of the transistor M2 is connected to the source of the transistor M3, the drain of the transistor M4 is connected to the drain of the transistor M3, the source of the transistor M4 is connected to VDD, and the gate of the transistor M4 is connected to the starved inverter and the drain of the transistor M3.
5. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 4, characterized in that: The starved inverter includes transistors M5 to M8, the gate of the transistor M4 is connected to the gate of the transistor M5, the source of the transistor M5 is connected to VDD, the drain of the transistor M5 is connected to the source of the transistor M6, the gates of the transistor M6 and the transistor M7 are connected and connected to the upper plate of the integrating capacitor FD, the drains of the transistor M6 and the transistor M7 are connected and connected to the output shaping circuit, the source of the transistor M7 is connected to the drain of the transistor M8, the source of the transistor M8 is connected to GND, and the gate of the transistor M8 is connected to the external bias voltage Vb.
6. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 5, characterized in that: The output shaping circuit comprises a transistor M9 and a transistor M10, wherein the gates of the transistor M9 and the transistor M10 are connected to each other and are simultaneously connected to the drains of the transistor M6 and the transistor M7, the drains of the transistor M9 and the transistor M10 are connected to each other and are simultaneously connected to a comparison circuit (3), and the sources of the transistor M9 and the transistor M10 are respectively connected to VDD and GND.
7. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 6, characterized in that: The comparison circuit (3) comprises an operational amplifier input end switch tube M11 and an operational amplifier circuit, wherein the source of the operational amplifier input end switch tube M11 is connected to the input signal Vin, the gate of the operational amplifier input end switch tube M11 is connected to the output end of the CLK generator (2), and the drain of the operational amplifier input end switch tube M11 is connected to the operational amplifier circuit.
8. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 7, characterized in that: The gate of the switch tube M11 at the input end of the operational amplifier is connected to the drains of the transistor M9 and the transistor M10.
9. The pixel-level analog-to-digital converter for infrared focal plane readout circuit according to claim 7, characterized in that: The operational amplifier circuit includes an operational amplifier input tube M12, an operational amplifier input tube M13, an operational amplifier input tube M14, an operational amplifier input tube M15, and a tail current tube M16. The gate of the operational amplifier input tube M12 is connected to the drain of the operational amplifier input switch tube M11, the drain of the operational amplifier input tube M12 is connected to the source of the operational amplifier input tube M13, the drain of the operational amplifier input tube M13 is connected to VDD, the gate of the operational amplifier input tube M13 is connected to the drain of the operational amplifier input tube M12 and the gate of the operational amplifier input tube M14, the source of the operational amplifier input tube M14 is connected to VDD, the drain of the operational amplifier input tube M14 is connected to the drain of the operational amplifier input tube M15, and the operational amplifier input tube M13 is connected to the drain of the operational amplifier input tube M15. The gate of the tail current tube M15 is connected to the reference level Vref, the drain of the tail current tube M16 is connected to the source of the operational amplifier input tube M15 and the operational amplifier input tube M112, the source of the tail current tube M16 is connected to GND, the gate of the tail current tube M16 is connected to the output end of the CLK generator, that is, the drain of the transistor M9 and the transistor M10, the drain of the operational amplifier input tube M15 and the operational amplifier input tube M14 is connected to the counter (4), and is connected to the gate of the reset tube M17 after passing through the counter (4), that is, the drain of the operational amplifier input tube M15 and the operational amplifier input tube M14 generates a pulse voltage Vpulse and is connected to the gate of the reset tube M17 after passing through the counter (4).
10. The pixel-level analog-to-digital converter used in an infrared focal plane readout circuit according to claim 9, characterized in that: When reading out, at the beginning of the exposure time, the input stage circuit (1) is used to make the integration capacitor start to integrate the voltage of the upper plate FD and connect it to the input end of the CLK generator (2). At this time, the output signal of the CLK generator (2) is at a low level, and the tail current tube M16 connected to the comparison circuit is turned off. When the integration capacitor continues to integrate and the voltage value of the upper plate FD of the integration capacitor is less than the threshold voltage of the transistor M7 in the CLK generator, the output voltage of the CLK generator becomes a high level, so that the tail current tube M16 of the comparison circuit is turned on, and the comparison circuit (3) works normally. At the same time, the input signal switch tube of the comparison circuit (3) works normally. When the comparison circuit (3) works normally, The input signal Vin, the voltage on the upper plate of the integrating capacitor, is connected to the positive terminal of the comparison circuit (3), i.e., the gate of the input tube M12 of the operational amplifier, through the input switch tube M11 of the operational amplifier. The reference level Vref is connected to the negative terminal of the comparison circuit, i.e., the gate of the input tube M15 of the operational amplifier. When the voltage on the upper plate of the integrating capacitor drops below the reference level Vref, the output signal of the comparison circuit is reversed, so that the counter starts counting and the reset tube M17 is turned on to reset the integrating capacitor to a high level. The output of the CLK generator (2) becomes a low level, so that the tail current tube M16 of the comparison circuit is turned off, and the output of the comparison circuit is reversed. The above process is repeated continuously during the exposure time until the exposure time ends.