Coding method, decoding method, device, equipment, system and readable storage medium

Abstract

The invention discloses a coding method and device, a decoding method and device, equipment, a system and a readable storage medium, and relates to the technical field of communication. The method comprises: obtaining a plurality of first code blocks, each of the plurality of first code blocks comprising a load and at least one type of bit, the plurality of first code blocks comprising at least one of a control code block or a data code block; and encoding the plurality of first code blocks to obtain a second code block, the second code block comprising A type bits, M-A indication bits and loads of the plurality of first code blocks, and the M-A indication bits being used for indicating the number of the plurality of first code blocks or indicating at least one of types of each of the plurality of first code blocks. According to the method, a plurality of first code blocks can be coded, and M-A indication bits included in a second code block obtained through coding can indicate the number of the plurality of first code blocks or indicate the type of each first code block in the plurality of first code blocks. The method can encode a plurality of first code blocks to obtain a second code block.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an encoding method, a decoding method, an apparatus, a device, a system and a readable storage medium. Background Art

[0002] In the field of communication technology, the application scope of encoding methods and decoding methods is becoming wider and wider. For example, the signal transmitting end can encode the signal to be transmitted to obtain the encoding result, and transmit the encoding result to the signal receiving end. The signal receiving end restores the signal to be transmitted based on the received encoding result according to the decoding method corresponding to the encoding method. For another example, the processor can encode the data to be stored to obtain the encoding result, store the encoding result in the memory, and then, when the stored data needs to be obtained, the processor can obtain the encoding result from the memory, decode the encoding result according to the decoding method corresponding to the encoding method, and obtain the stored data. Summary of the invention

[0003] The present application proposes an encoding method, a decoding method, an apparatus, a device, a system and a readable storage medium for improving encoding and decoding efficiency.

[0004] In a first aspect, a coding method is provided, the method comprising: obtaining a plurality of first code blocks, wherein each of the plurality of first code blocks comprises a load and at least one type bit, and the plurality of first code blocks comprise at least one of a control code block or a data code block; encoding the plurality of first code blocks to obtain a second code block, wherein the second code block comprises A type bits, MA indication bits and the loads of the plurality of first code blocks, A is less than the sum of the number of type bits of the plurality of first code blocks, M is an integer greater than A, and the MA indication bits are used to indicate the number of the plurality of first code blocks or to indicate at least one of the types of each of the plurality of first code blocks.

[0005] The method can encode multiple first code blocks, and the MA indication bits included in the encoded second code block can indicate the number of multiple first code blocks or indicate the type of each first code block in the multiple first code blocks. For example, in the case where multiple first code blocks include a control code block, the MA indication bits of the second code block are used to indicate the type of each first code block in the multiple first code blocks. In the case where multiple first code blocks are all control code blocks or all data code blocks, the MA indication bits of the second code block are used to indicate the number of multiple first code blocks. In other words, the method can be applied to different situations of multiple first code blocks and has a wide range of applicability.

[0006] In some embodiments, M is less than the sum of the number of type bits included in the plurality of first code blocks. In this case, the overhead of the second code block is less than the sum of the overheads of the plurality of first code blocks, so that the overhead of the second code block is lower and the coding efficiency is higher.

[0007] In some embodiments, obtaining multiple first code blocks includes: continuously receiving MA code blocks; based on the MA code blocks including control code blocks and data code blocks, using the MA code blocks as multiple first code blocks; based on the MA code blocks being all data code blocks or control code blocks, continuing to receive code blocks until different types of code blocks are received or the number of received code blocks of the same type is equal to 2 M-A , the received code blocks are used as multiple first code blocks. Thus, when the MA code blocks received continuously include code blocks of different types, the MA code blocks can be subsequently encoded as first code blocks into fixed-length second code blocks. When the MA code blocks received continuously are all code blocks of the same type, code blocks can continue to be received, thereby increasing the number of code blocks used as first code blocks. Therefore, compared with the method of encoding the second code block obtained by encoding more than MA first code blocks to obtain the second code block, the number of bits used as overhead is reduced by a large amount.

[0008] In some embodiments, the plurality of first code blocks include a control code block and a data code block, and the method further includes: obtaining an occurrence probability of the control code block in the plurality of first code blocks; and determining, based on the occurrence probability, a value of M. Compared with the method of selecting any value greater than A as the value of M, the value of M can also be determined based on the occurrence probability of the control code block, and the method of determining the value of M is more flexible.

[0009] In some embodiments, obtaining the occurrence probability of a control code block in a plurality of first code blocks includes: obtaining the occurrence probability of a control code block in a plurality of first code blocks based on an Ethernet frame. Since 64B / 66B-encoded data code blocks and control code blocks can be obtained based on Ethernet frames, the occurrence probability of a 64B / 66B-encoded control code block in a plurality of code blocks obtained based on Ethernet frames can be determined. On this basis, regardless of whether the control code block as the first code block is a 64B / 66B-encoded code block or a code block obtained by encoding a 64B / 66B-encoded code block, the occurrence probability of the control code block as the first code block in a plurality of first code blocks can be calculated, and the method of obtaining the occurrence probability of a control code block is relatively convenient and quick.

[0010] In some embodiments, determining the value of M based on the probability of occurrence includes: obtaining the number of possible values ​​of each bit of the second code block; obtaining the logarithm of the reciprocal of the probability of occurrence with the number of possible values ​​as the base; and rounding the logarithm down to obtain the value of M. Since the probability of occurrence of the control code block is lower than the probability of occurrence of the data code block, the value of M obtained in this manner is larger. Thus, in the case of subsequently encoding greater than or equal to MA first code blocks, when A is fixed, the number of first code blocks can be larger. In the case of encoding multiple first code blocks to obtain the second code block, the effect of reducing overhead is better.

[0011] In some embodiments, the first code block includes 1 type bit and a 64*N bit payload, where N is a positive integer. For example, the 64*N bit payload includes data; or, the 64*N bit payload includes an information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data. In one possible implementation, obtaining a first code block from a plurality of first code blocks includes: obtaining a first reference code block, the first reference code block includes 2 type bits and a 64 bit payload, the first reference code block is a control code block or a data code block; compressing the type bit of the first reference code block to obtain a first code block including 1 type bit. That is, the first code block may be a code block obtained by compressing the type bit. In another possible implementation, obtaining a first code block from a plurality of first code blocks includes: obtaining N second reference code blocks, wherein N is greater than or equal to 2, each of the N second reference code blocks includes 2 type bits and 64 bits of payload, and the N second reference code blocks include at least one of a control code block or a data code block; encoding the N second reference code blocks to obtain a first code block. That is, the first code block may be any code block obtained by encoding a 64B / 66B-encoded code block. In other embodiments, the first code block is a 64B / 66B-encoded code block. Thus, the method can be applicable to different situations of the first code block and has a wide range of applicability.

[0012] In some embodiments, when multiple second code blocks are obtained by encoding, and multiple first code blocks obtained by encoding multiple second code blocks are all data code blocks or all control code blocks, after obtaining the second code blocks, the method further includes: encoding multiple second code blocks to obtain a third code block, wherein the third code block includes A type bits, SA indicator bits, and the indicator bits included in multiple second code blocks and the load of the first code block, and the SA indicator bits are used to indicate the number of multiple second code blocks, and S is an integer greater than A. In some other embodiments, when multiple second code blocks are obtained by encoding, and multiple first code blocks obtained by encoding multiple second code blocks include the data code block and the control code block, after obtaining the second code block, the method further includes: encoding multiple second code blocks to obtain a fourth code block, wherein the fourth code block includes A type bits, SA indicator bits, and the indicator bits included in multiple second code blocks and the load of the first code block, and the SA indicator bits are used to indicate the type of each second code block in the multiple second code blocks. That is, the operation of encoding multiple code blocks to obtain one code block can be performed iteratively, further reducing overhead and improving coding efficiency.

[0013] In a second aspect, a decoding method is provided, the method comprising: obtaining a second code block, wherein the second code block comprises A type bits, MA indicator bits and a load of multiple first code blocks, each of the multiple first code blocks comprises a load and at least one type bit, A is less than the sum of the number of type bits of the multiple first code blocks, M is an integer greater than A, MA indicator bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks, and the multiple first code blocks include at least one of a control code block or a data code block; decoding the second code block to obtain multiple first code blocks. The method can determine the decoding method for the second code block based on the A type bits and the MA indicator bits, and decode the second code block based on the loads of the multiple first code blocks to obtain multiple first code blocks.

[0014] In some embodiments, M is less than the sum of the number of type bits included in the plurality of first code blocks. In this case, the overhead of the second code block is less than the sum of the overheads of the plurality of first code blocks, the overhead of the second code block is lower, and the coding efficiency is higher.

[0015] In some embodiments, when A type bits indicate that multiple first code blocks are all data code blocks or are all control code blocks, MA indicator bits are used to indicate the number of multiple first code blocks; decoding the second code block to obtain multiple first code blocks includes: equally dividing the loads of the multiple first code blocks included in the second code block according to the number indicated by the MA indicator bits to obtain the loads of the multiple first code blocks; when the multiple first code blocks are all data code blocks, obtaining the multiple first code blocks according to the type bits corresponding to the data code blocks and the loads of the multiple first code blocks; when the multiple first code blocks are all control code blocks, obtaining the multiple first code blocks according to the type bits corresponding to the control code blocks and the loads of the multiple first code blocks. In other embodiments, when A type bits indicate that multiple first code blocks include control code blocks and data code blocks, MA indicator bits are used to indicate the type of each first code block in the multiple first code blocks; decoding the second code block to obtain multiple first code blocks includes: obtaining the type of each first code block based on MA indicator bits; obtaining the load of each first code block in the multiple first code blocks from the loads of the multiple first code blocks included in the second code block; obtaining the control code block included in the multiple first code blocks according to the load of the control code block and the type bit corresponding to the control code block; obtaining the data code block included in the multiple first code blocks according to the load of the data code block and the type bit corresponding to the data code block. This method can be applied to decoding second code blocks in different situations, and the decoding method is relatively flexible.

[0016] In some embodiments, obtaining a second code block includes: obtaining a third code block, wherein the third code block includes A type bits, SA indicator bits, and indicator bits included in multiple second code blocks and the load of the first code block, the SA indicator bits are used to indicate the number of multiple second code blocks, and S is an integer greater than A; decoding the third code block to obtain multiple second code blocks. In other embodiments, obtaining a second code block includes: obtaining a fourth code block, wherein the fourth code block includes A type bits, SA indicator bits, and indicator bits included in multiple second code blocks and the load of the first code block, the SA indicator bits are used to indicate the type of each second code block in the multiple second code blocks, and S is an integer greater than A; decoding the fourth code block to obtain multiple second code blocks. This method can be applied to decoding code blocks obtained by encoding second code blocks in different situations, and the method of obtaining second code blocks is more flexible and diverse.

[0017] In some embodiments, the first code block includes 1 type bit and 64*N bits of payload, where N is a positive integer. For example, the 64*N bits of payload include data; or, the 64*N bits of payload include information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data. In one possible implementation, the method further includes: decompressing 1 type bit of the first code block to obtain a first reference code block, the first reference code block includes 2 type bits and 64 bits of payload, and the first reference code block is a control code block or a data code block. That is, the first code block can be a code block obtained by compressing the type bit. In another possible implementation, the method further includes: decoding the first code block to obtain N second reference code blocks, the N second reference code blocks each include 2 type bits and 64 bits of payload, and the N second reference code blocks include at least one of a control code block or a data code block. That is, the first code block can be any code block obtained by encoding a 64B / 66B-encoded code block. In some other embodiments, the first code block is a 64B / 66B coded code block. This method can obtain a variety of first code blocks, is applicable to a variety of situations of the first code block, and has a wide range of applications.

[0018] In a third aspect, a coding device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method; and a processing module for performing other operations other than the operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method.

[0019] In a fourth aspect, a decoding device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method; and a processing module for performing other operations other than the operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method.

[0020] In a fifth aspect, an electronic device is provided, comprising a processor coupled to a memory, wherein the memory stores at least one program instruction or code, and the at least one program instruction or code is loaded and executed by the processor so that the electronic device implements any encoding method in the first aspect, or implements any decoding method in the second aspect.

[0021] In a sixth aspect, a computer-readable storage medium is provided, in which at least one program instruction or code is stored. When the program instruction or code is loaded and executed by a processor of a computer, the computer implements any encoding method in the first aspect, or implements any decoding method in the second aspect.

[0022] In a seventh aspect, a communication system is provided, the system comprising a first interface module and a second interface module, the first interface module being used to execute any encoding method in the first aspect, and the second interface module being used to execute any decoding method in the second aspect.

[0023] In an eighth aspect, another communication device is provided, the device comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals, and when the processor executes the instructions stored in the memory, the processor executes any encoding method in the first aspect, or executes any decoding method in the second aspect.

[0024] Illustratively, there are one or more processors and one or more memories.

[0025] For example, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0026] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0027] In the ninth aspect, a computer program or a computer program product is provided, wherein the computer program or the computer program product comprises: a computer program code, which, when executed by a computer, enables the computer to execute any encoding method in the first aspect, or execute any decoding method in the second aspect.

[0028] In a tenth aspect, a chip is provided, the chip comprising an interface module, the interface module being used to execute any encoding method in the first aspect, or to execute any decoding method in the second aspect.

[0029] In the eleventh aspect, a chip is provided, the chip including a processor, the processor is used to call and run instructions stored in the memory from the memory, so that a communication device equipped with the chip executes any encoding method in the first aspect, or executes any decoding method in the second aspect. Exemplarily, the chip also includes: an input interface, an output interface and a memory, and the input interface, the output interface, the processor and the memory are connected through an internal connection path.

[0030] It should be understood that the beneficial effects achieved by the technical solutions of the third to eleventh aspects of the present application and the corresponding possible implementation methods can be referred to the technical effects of the technical solutions of the first to second aspects and their corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of a 64B / 66B encoding format provided in an embodiment of the present application;

[0032] Figure 2 is a schematic diagram of compressing a sync field in a related art;

[0033] Figure 3 It is a schematic diagram of encoding n 64B / 66B code blocks in a related art;

[0034] Figure 4 It is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0035] Figure 5 It is a schematic diagram of a coding and decoding process provided by an embodiment of the present application;

[0036] Figure 6 is a schematic diagram of another encoding and decoding process provided by an embodiment of the present application;

[0037] Figure 7 is a flowchart of an encoding method provided in an embodiment of the present application;

[0038] Figure 8 It is a schematic diagram of encoding multiple 64B / 66B code blocks using related technology;

[0039] Fig. 9 is a flowchart of another encoding method provided in an embodiment of the present application;

[0040] Fig.10 is a schematic diagram of an encoding process provided in an embodiment of the present application;

[0041] Fig.11 is a schematic diagram of another encoding process provided in an embodiment of the present application;

[0042] Fig.12 is a schematic diagram of another encoding process provided in an embodiment of the present application;

[0043] Fig.13 is a flowchart of a decoding method provided in an embodiment of the present application;

[0044] Fig.14 is a schematic diagram of a process for decoding a second code block provided by an embodiment of the present application;

[0045] Fig.15 is another schematic diagram of a process for decoding a second code block provided by an embodiment of the present application;

[0046] Fig.16 is a schematic diagram of the structure of an encoding device provided in an embodiment of the present application;

[0047] Fig.17 is a structural diagram of a decoding device provided in an embodiment of the present application;

[0048] Fig.18 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0049] Fig.19 It is a structural diagram of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] As the application scope of encoding and decoding methods continues to expand, various encoding technologies have emerged. For example, 64-bit (bit, B) / 66B encoding is a commonly used encoding technology in Ethernet, which jointly encodes the 8-bit control signal and 64-bit data signal from the media independent interface (MII) into a 66-bit code block. Figure 164B / 66B encoding format provided by an embodiment of the present application. The 66-bit code blocks obtained by encoding are divided into two categories: data code blocks and control code blocks. The two types of code blocks are distinguished by the first 2 bits of the 66 bits. The first 2 bits are called the synchronization (sync) field. That is, the first bit to the 0th bit of the 66-bit code block are used as the sync field. Figure 1 As shown in FIG. 1 , when the 0th bit is 0 and the 1st bit is 1, the 66-bit code block is a data code block. When the 0th bit is 1 and the 1st bit is 0, the 66-bit code block is a control code block. Please continue to refer to Figure 1 In the case where the 66-bit code block is a control code block, the 9th to 2nd bits of the code block are used as a block type field, and different values ​​of the block type field indicate different types of control code blocks. For other contents of the 66-bit code block, please refer to the relevant contents of 64B / 66B encoding in the 802.3 standard of the Institute of Electrical and Electronics Engineers (IEEE), which will not be repeated here.

[0051] In 64B / 66B encoding, the 2 bits used as the sync field are called overhead, and the other 64 bits are called information, which is also called payload. The 66-bit code block is called a 64B / 66B encoded code block or a 64B / 66B code block. It can be seen that in a 66-bit code block, the overhead ratio is 3.03%. For scenarios with tight transmission bandwidth, the overhead of 64B / 66B encoding is high, so a coding method is needed to reduce the overhead ratio.

[0052] For example, in the scenario where 10 Gigabit Ethernet (GE) services are transmitted over an optical transport network (OTN), since the optical channel data unit (ODU) 2 payload bandwidth of OTN is slightly less than 10 Gigabit (G), the transmission bandwidth that OTN can provide is relatively tight. Therefore, a coding method for encoding a service code block based on 64B / 66B coding is proposed. The coding method improves coding efficiency and reduces the transmission bandwidth required for the service by encoding multiple 64B / 66B code blocks into one code block. Among them, the method of encoding the service code block includes but is not limited to encoding 8 64B / 66B code blocks into one code block based on 512B / 513B coding.

[0053] In a related technology, the coding efficiency is improved by compressing the sync field in the 64B / 66B code block. Figure 2 FIG. 1 is a schematic diagram of compressing the sync field in a related art. Figure 2 As shown, for the 64B / 66B encoded control code block and data code block, the 2 bits of the sync field are compressed into 1 bit. For example, the sync field of the control code block obtained by 64B / 66B encoding is compressed from 10 to 0, and the sync field of the data code block obtained by 64B / 66B encoding is compressed from 0 to 1. Thus, the 64B / 66B encoded code block is encoded into a 64B / 65B encoded code block, and the coding efficiency is improved from 96.97% of 64B / 66B encoding to 98.485% of 64B / 65B encoding. However, the improvement of coding efficiency by this related technology is relatively limited, and it is still difficult to meet the transmission bandwidth requirements for some scenarios where the transmission bandwidth is relatively tight.

[0054] In another related technology, by compressing the control word in the block type field of the 64B / 66B code block, n 64B / 66B code blocks are encoded into one (64*n) / (64*n+1) code block, where n is a positive integer less than or equal to 32. Among them, the (64*n) / (64*n+1) code block refers to a large code block with a length of (64*n+1) formed by the joint encoding of n 64B / 66B code blocks, and the first bit of the large code block is used to indicate the type of the large code block. For example, when the first bit is 0, the large code block is a control code block, that is, there is at least one 64B / 66B control code block among the n 64B / 66B code blocks constituting the large code block. When the first bit is 1, the large code block is a data code block, that is, the n 64B / 66B code blocks constituting the large code block are all 64B / 66B data code blocks. Typical values ​​of n can be 4, 8, 32, etc. When n=4, 4 64B / 66B code blocks are encoded into a 256B / 257B encoded code block; when n=8, 8 64B / 66B code blocks are encoded into a 512B / 513B encoded code block; when n is equal to 32, 32 64B / 66B code blocks are encoded into a 2048B / 2049B encoded code block. 2048B / 2049B encoded code blocks are also called 2048B / 2049B code blocks. The control word in the block type field can be found in the description of the control word for 64B / 66B encoding in the IEEE 802.3 standard, which will not be repeated here. 256B / 257B encoded code blocks are also called 256B / 257B code blocks, and 512B / 513B encoded code blocks are also called 512B / 513B code blocks.

[0055] Figure 3 This is a schematic diagram of encoding n 64B / 66B code blocks in a related art. Figure 3, n 64B / 66B code blocks are encoded into a (64*n)B / (64*n+1)B encoded code block, n≤32. Figure 3 As shown in (a), when n 64B / 66B code blocks include at least one control code block, the following four steps are performed to encode n 64B / 66B code blocks into a (64*n)B / (64*n+1)B encoded code block, wherein a (64*n)B / (64*n+1)B encoded code block is called a large code block. The four steps performed are as follows:

[0056] 1) Move all control code blocks to the front of the encoded code block, and put all data code blocks in sequence to the back of the encoded code block;

[0057] 2) compressing the control word in the payload of each control code block, and using the compressed 8-bit position as an information indicator, for example, the information indicator is used to indicate the position of the control code block in multiple 64B / 66B code blocks and the type of the control code block, and the remaining 56 bits are used as the compressed payload, so that the compressed control code block includes an 8-bit information indicator and a 56-bit payload;

[0058] 3) The first bit of the encoded large code block is set to 0, that is, the 0th bit is 0, wherein the first bit is 0 to indicate that there is at least one control code block among the n 64B / 66B code blocks corresponding to the large code block;

[0059] 4) The compressed control code block is placed after the 0th bit in the order of the code blocks; the load of each data code block remains unchanged and is placed at the end of the encoded large code block in the order of the code blocks.

[0060] like Figure 3 As shown in (a), the large code block with the first bit of 0 is called a control code block. Figure 3 ,like Figure 3 As shown in (b), when all n 64B / 66B code blocks are data code blocks, the first bit of the encoded large code block is set to 1, that is, the 0th bit is 1, where the first bit is 1 to indicate that the n 64B / 66B code blocks corresponding to the large code block are all data code blocks. And the payload of the data code block is placed at the end of the encoded large code block in the order of the code blocks. Figure 3 As shown in (b), the large code block with the first bit being 1 is called a data code block.

[0061] When n=4, 8, and 32, the coding efficiency of this related technology is 99.61%, 99.805%, and 99.95%, respectively. However, for some scenarios where the transmission bandwidth is relatively tight, it is still difficult to meet the transmission bandwidth requirements.

[0062] The embodiment of the present application provides a coding method for encoding fixed-length information, wherein the fixed-length information includes but is not limited to a code block obtained by encoding using a coding technique. The types of the encoded fixed-length information may be the same or different. For example, when the fixed-length information is a code block, the code block may be a control code block or a data code block. The control code block may be a control code block obtained by 64B / 66B encoding, and the data code block may be a data code block obtained by 64B / 66B encoding. Furthermore, in the case where the code block is a code block obtained by encoding a 64B / 66B code block, if the 64B / 66B code block obtained by encoding the code block includes a control code block, the encoded code block is also referred to as a control code block; if the 64B / 66B code blocks obtained by encoding the code block are all data code blocks, the encoded code block is also referred to as a data code block. In the case where the 64B / 66B code block obtained by encoding the code block includes both a control code block and a data code block, the encoded code block may also be referred to as a mixed code block.

[0063] Figure 4 is a schematic diagram of an implementation environment provided by an embodiment of the present application, and the method can be applied to Figure 4 The implementation environment shown. Figure 4 As shown, the implementation environment includes a first module 401 and a second module 402, and the first module 401 and the second module 402 are communicatively connected. For example, the first module 401 and the second module 402 are communicatively connected in a wired or wireless manner. The first module 401 and the second module may also be located in the same or different devices, which is not limited in the embodiments of the present application.

[0064] In a possible implementation, the first module 401 and the second module 402 are both located in a communication device, and the communication devices in which the first module 401 and the second module 402 are located may be the same or different. That is, the first module 401 and the second module 402 may be applied to a communication scenario, and the communication scenario may be a wired communication scenario or a wireless communication scenario. Exemplarily, the first module 401 and the second module 402 are interface modules of a communication device, and the interface module may be implemented in a hardware logic manner, for example, the interface module is a network card. The embodiment of the present application does not limit the type of communication device, for example, the communication device is any one of a switch, a router, or a wireless base station. In the case where the first module 401 and the second module 402 are both located in a communication device, the first module 401 may encode a plurality of first code blocks to obtain a second code block, transmit the second code block to the second module 402, and after receiving the second code block, the second module 402 decodes the second code block to obtain a plurality of first code blocks.

[0065] Exemplarily, in the method provided in the embodiment of the present application, the encoded code block is a code block obtained by encoding in the related art. For example, a plurality of code blocks are first obtained by encoding using the related art, and then the method provided in the embodiment of the present application is used to encode the plurality of code blocks obtained by using the related art, that is, the method provided in the embodiment of the present application and the encoding method in the related art can be reused. Figure 5 Schematic diagram of a coding and decoding process provided by an embodiment of the present application. Figure 5 As shown, the first module 401 is located in the first device, the first device also includes a third module and a sending module, the second module 402 is located in the second device, and the second device also includes a fourth module and a receiving module. Among them, the sending module and the receiving module are connected in communication, the third module is an encoding module for applying related technologies, and the fourth module is a decoding module for applying related technologies. Taking the first device as a sending end device and the second device as a receiving end device as an example, the encoding and decoding process is described.

[0066] See also Figure 5 , the first device obtains a code block stream obtained based on 64B / 66B encoding, encodes n 64B / 66B code blocks into a large code block through the third module, transmits multiple large code blocks to the first module 401 through the third module, and the multiple large code blocks are all used as first code blocks. Then, the first module 401 encodes multiple first code blocks to obtain a second code block, transmits the second code block to the sending module through the first module 401, and sends the second code block to the receiving module of the second device through the sending module. After receiving the second code block, the receiving module transmits the second code block to the second module 402, and decodes the second code block through the second module 402 to obtain multiple first code blocks, that is, multiple large code blocks. Then, the second module 402 transmits multiple large code blocks to the fourth module, and decodes multiple large code blocks through the fourth module to obtain a code block stream based on 64B / 66B encoding. Exemplarily, the sending module sends the second code block to the receiving module through a channel with strictly limited bandwidth, that is, the method can be applied to communication scenarios with limited transmission bandwidth.

[0067] In another possible implementation, the first module 401 and the second module 402 may also be devices in a data storage scenario or a data compression scenario, and the devices where the first module 401 and the second module 402 are located may be the same or different. Figure 6 Schematic diagram of another encoding and decoding process provided by an embodiment of the present application. Figure 6 As shown, the first module 401 and the second module 402 are applied to the data storage system, and the first module 401 and the second module 402 can both be processors that are communicatively connected to the memory. The first module 401 and the second module 402 can be located in the same or different devices as the memory, which is not limited in the embodiment of the present application. The embodiment of the present application does not limit the types of processors and memories.

[0068] See also Figure 6 , the first module 401 obtains a plurality of fixed-length data blocks distinguished by the first bit, for example, the fixed-length data block is any large code block obtained by encoding in the related art. Then, the first module 401 uses the plurality of fixed-length data blocks as a plurality of first code blocks, encodes the plurality of first code blocks to obtain a second code block, and stores the second code block in a memory. Afterwards, the second module 402 reads the second code block from the memory, decodes the second code block to obtain a plurality of first code blocks, that is, obtains a plurality of fixed-length data blocks distinguished by the first bit.

[0069] Exemplarily, when the overhead of the second code block is less than the sum of the overheads of multiple first code blocks, the process of encoding multiple first code blocks to obtain the second code block is also called a data compression process. In other words, the scenario in which the method is applied can also be called a data compression scenario.

[0070] The encoding method provided in the embodiment of the present application can be as follows Figure 7 As shown, next, combined Figure 4 The method is described in the implementation environment shown. The method can be applied to Figure 4 The first module 401 is shown. Figure 7 As shown, the method includes but is not limited to S701 and S702.

[0071] S701, obtaining a plurality of first code blocks, wherein each of the plurality of first code blocks comprises a payload and at least one type bit, and the plurality of first code blocks comprises at least one of a control code block or a data code block.

[0072] In one possible implementation, the first code block is a 64B / 66B encoded code block, that is, the first code block includes 2 type bits and a 64-bit payload. Among them, the 2 type bits are the first 2 bits used as the sync field. In another possible implementation, the first code block includes 1 type bit and a 64*N bit payload, where N is a positive integer. For example, the 64*N bit payload includes data; or, the 64*N bit payload includes information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data. In other words, the first code block can be a code block encoded in the related art.

[0073] For example, the first code block is a code block obtained by compressing the sync domain. Thus, obtaining the first code block of multiple first code blocks includes: obtaining a first reference code block, the first reference code block includes 2 type bits and 64 bits of payload, and the first reference code block is a control code block or a data code block; compressing the type bit of the first reference code block to obtain a first code block including 1 type bit. Among them, the 2 first type bits are the first 2 bits used as the sync domain. Exemplarily, this process of obtaining the first code block can refer to Figure 2 In the case where the first code block is obtained based on the first reference code block, if the first reference code block is a control code block encoded with 64B / 66B, the first code block obtained based on the first reference code block is also called a control code block; if the first reference code block is a data code block encoded with 64B / 66B, the first code block obtained based on the first reference code block is also called a data code block.

[0074] For another example, the first code block is a (64*n)B / (64*n+1)B encoded code block obtained by encoding a 64B / 66B encoded code block, where n≤32. Thus, obtaining a first code block from multiple first code blocks includes: obtaining N second reference code blocks, where N is greater than or equal to 2, each of the N second reference code blocks includes 2 type bits and 64 bits of payload, and the N second reference code blocks include at least one of a control code block or a data code block; encoding the N second reference code blocks to obtain a first code block including 1 type bit. In other words, multiple second reference code blocks are all 64B / 66B encoded code blocks. Exemplarily, this process of obtaining the first code block can refer to Figure 3 The process of obtaining large code blocks in .

[0075] In the case where the N second reference code blocks are all 64B / 66B encoded data code blocks, the first code block obtained based on the N second reference code blocks is also called a data code block. In the case where the N second reference code blocks include at least one 64B / 66B encoded control code block, the first code block obtained based on the N second reference code blocks is also called a control code block. That is to say, if the N second reference code blocks are all 64B / 66B encoded control code blocks, the first code block encoded based on the N second reference code blocks is called a control code block. If the N second reference code blocks include 64B / 66B encoded control code blocks and 64B / 66B encoded data code blocks, the first code block encoded based on the N second reference code blocks is still called a control code block. Furthermore, in the case where the N second reference code blocks include 64B / 66B encoded control code blocks and 64B / 66B encoded data code blocks, since the N second reference code blocks include both 64B / 66B encoded control code blocks and 64B / 66B encoded data code blocks, the first code block obtained based on the N second reference code blocks is also called a mixed code block.

[0076] When the first code block is a 256B / 257B code block, one type bit is the first bit of the 256B / 257B code block, when the bit is 0, the first code block is a control code block, when the bit is 1, the first code block is a data code block, and N is equal to 4. When the first code block is a 512B / 513B code block, one type bit is the first bit of the 512B / 513B code block, when the bit is 0, the first code block is a control code block, when the bit is 1, the first code block is a data code block, and N is equal to 8. When the first code block is other large code blocks obtained by encoding in the related art, one type bit is the first bit of the large code block, when the bit is 0, the first code block is a control code block, when the bit is 1, the first code block is a data code block, and N is less than or equal to 32.

[0077] Exemplarily, obtaining multiple first code blocks includes: continuously receiving MA code blocks; based on the MA code blocks including control code blocks and data code blocks, using the MA code blocks as multiple first code blocks; based on the MA code blocks being data code blocks or control code blocks, continuing to receive code blocks until different types of code blocks are received or the number of received code blocks of the same type is equal to 2 M-A , the received code blocks are taken as multiple first code blocks. In the embodiment of the present application, A is less than the sum of the number of type bits of the multiple first code blocks, and M is an integer greater than A. That is, when the received MA code blocks are all code blocks of the same type, code blocks can continue to be received until code blocks of different types are received or the number of code blocks of the same type is equal to 2 M-A , so the number of code blocks applicable to the encoding method is more flexible. Since the number of overheads of the second code blocks obtained by subsequent encoding is fixed, compared with the case of encoding MA first code blocks, the case of encoding more than MA first code blocks can reduce more bits used as overhead, that is, the effect of reducing overhead is better.

[0078] In some embodiments, the plurality of first code blocks include control code blocks and data code blocks, and the method further includes: obtaining the occurrence probability of the control code block in the plurality of first code blocks; and determining the value of M based on the occurrence probability. For example, obtaining the occurrence probability of the control code block in the plurality of first code blocks includes: obtaining the occurrence probability of the control code block in the plurality of first code blocks based on the Ethernet frame. Exemplarily, 64B / 66B encoding is performed based on the Ethernet frame to obtain 64B / 66B encoded control code blocks and data code blocks. In the case where the first code blocks are 64B / 66B encoded control code blocks and data code blocks, the occurrence probability of the control code block in the plurality of first code blocks is obtained based on the ratio of the number of control code blocks to the sum of the number of control code blocks and data code blocks. For the content of 64B / 66B encoding based on Ethernet frames, reference can be made to the relevant content of 64B / 66B encoding in the IEEE 802.3 standard, which will not be described in detail here. When the first code block is any large code block, combined with the description of the related technology in the previous text, the first code block is obtained by encoding the 64B / 66B code block. Therefore, for the encoded control code block, the probability of occurrence of the encoded control code block in the encoded multiple code blocks can be calculated.

[0079] Exemplarily, determining the value of M based on the occurrence probability includes: obtaining the number of possible values ​​of each bit of the second code block; obtaining the logarithm of the reciprocal of the occurrence probability with the number of possible values ​​as the base; and rounding down the logarithm to obtain the value of M. For example, M can be calculated according to the following formula:

[0080]

[0081] in, Express Round down, k represents the number of possible values ​​of each bit of the second code block, and P represents the probability of occurrence of the control code block in multiple first code blocks. For example, the number of possible values ​​of each bit of the second code block is 2, for example, the value of each bit of the second code block can be 0 or 1, then k is equal to 2, and M is less than or equal to An integer greater than A.

[0082] S702, encode multiple first code blocks to obtain a second code block, wherein the second code block includes A type bits, MA indicator bits and a load of the multiple first code blocks, A is less than the sum of the number of type bits of the multiple first code blocks, M is an integer greater than A, and the MA indicator bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks.

[0083] Exemplarily, M is less than the sum of the number of type bits included in the multiple first code blocks. The overhead of the second code block includes A type bits and MA indicator bits, that is, the overhead of the second code block includes M bits in total. The sum of the overheads of the multiple first code blocks is equal to the sum of the number of type bits included in the multiple first code blocks, so that when M is less than the sum of the number of type bits included in the multiple first code blocks, the overhead of the second code block is less than the sum of the overheads of the multiple first code blocks, and the second code block is obtained by encoding the multiple first code blocks, which can reduce the overhead and improve the coding efficiency. In a possible implementation, MA indicator bits are also used to indicate the position of the load of each first code block in the multiple first code blocks in the second code block. That is to say, an indicator bit is used to indicate the type of a first code block and the position of the load of the first code block in the second code block. Therefore, in the case where the first code block includes a control code block and a data code block, it can be known based on MA indicator bits where the load of the control code block is in the second code block and where the load of the data code block is in the second code block.

[0084] In some embodiments, according to different situations of the multiple first code blocks, encoding the multiple first code blocks to obtain the second code blocks includes but is not limited to the following situation A1 and situation A2.

[0085] In case A1, the plurality of first code blocks include a control code block and a data code block.

[0086] Exemplarily, in combination with the description of S701, in the case where multiple first code blocks include control code blocks and data code blocks, the number of first code blocks is equal to MA. For case A1, the A type bits in the second code block are used to indicate that multiple first code blocks include control code blocks and data code blocks, that is, the A type bits can be used to indicate that the second code block is obtained by encoding the control code block and the data code block. The specific values ​​of the A type bits can be set based on experience or actual needs. For example, taking A equal to 2 as an example, in the case where multiple first code blocks include control code blocks and data code blocks, the 2 type bits can be 00, that is, both type bits are 0. For another example, taking A equal to 1 as an example, in the case where the first code block includes a control code block and a data code block, this type bit can be 0.

[0087] In a possible implementation, when multiple first code blocks include control code blocks and data code blocks, MA indication bits are used to indicate the type of each first code block in the multiple first code blocks. For example, MA indication bits are used to indicate the type of each first code block in the multiple first code blocks in a bitmap manner. Exemplarily, one indication bit corresponds to one first code block, and when the first code block is a control code block, the value of the indication bit corresponding to the first code block is a first value, and when the first code block is a data code block, the indication bit corresponding to the first code block is a second value. The first value and the second value can be determined based on experience or actual needs, for example, the first value is 0 and the second value is 1.

[0088] In case A2, the multiple first code blocks are all control code blocks, or the multiple first code blocks are all data code blocks.

[0089] Among the multiple code blocks included in the actual business flow, data code blocks will account for the vast majority, so after the 64B / 66B code blocks are encoded using relevant technologies, data code blocks will also account for the majority, and multiple data code blocks will appear continuously. Figure 8 It is a schematic diagram of encoding multiple 64B / 66B code blocks using related technologies. Figure 8 As shown, the service flow before encoding includes multiple 64B / 66B code blocks. Assume that only the first 64B / 66B code block among the multiple 64B / 66B code blocks is a control code block, and the others are data code blocks. After encoding multiple 64B / 66B code blocks using relevant technologies, the first n 64B / 66B code blocks will be encoded into a control code block including 1+64*n bits, and the first bit of the control code block is represented by 0. Every other n 64B / 66B code blocks will be encoded into a data code block including 1+64*n bits, and the first bit of the data code block is represented by 1.

[0090] Since there will be many data code blocks in the encoded service flow after the relevant technology is used for encoding, and many data code blocks will appear continuously, the first bit of these data code blocks can be compressed, that is, the type bits of these data code blocks can be compressed. Similarly, in the case of multiple continuous control code blocks, the type bits of these control code blocks can also be compressed.

[0091] For example, in combination with the description of S701, when the plurality of first code blocks are all control code blocks or are all data code blocks, the number of the plurality of first code blocks is greater than or equal to MA and less than or equal to 2. M-AFor case A2, the A type bits in the second code block are used to indicate that the multiple first code blocks are all control code blocks or are all data code blocks, that is, the A type bits can be used to indicate that the second code block is obtained by encoding a pure control code block or by encoding a pure data code block. A pure control code block means that the multiple first code blocks are all control code blocks, and a pure data code block means that the multiple first code blocks are all data code blocks.

[0092] The specific values ​​of A type bits can be set based on experience or actual needs. For example, taking A equal to 2 as an example, when multiple first code blocks are control code blocks, the two type bits can be 01, that is, the two type bits are 0 and 1 respectively; when multiple first code blocks are data code blocks, the two type bits can be 10, that is, the two type bits are 1 and 0 respectively. In some embodiments, the operation of continuing to receive code blocks can also be performed only when MA consecutively received code blocks are all data code blocks, that is, multiple first code blocks in situation A2 are all data code blocks. Taking A equal to 1 as an example, the type bit included in the second code block can be 1.

[0093] In a possible implementation, when multiple first code blocks are all control code blocks or are all data code blocks, MA indication bits are used to indicate the number of first code blocks. For example, when the number of first code blocks is 8 and MA is equal to 3, the value indicated by the three type bits is 8, that is, the three type bits are all 1.

[0094] Exemplarily, in combination with the description in S701 and S702 above, the process of the encoding method provided in the embodiment of the present application includes first determining M, and then executing S701 and S702 after M is determined. Fig. 9 is a flowchart of another encoding method provided in an embodiment of the present application. Fig. 9 , continuously receive code blocks, where the code blocks may be 64B / 66B code blocks or (64*n)B / (64*n+1)B encoded code blocks, where n is a positive integer less than or equal to 32. In the process of receiving code blocks, determine whether MA code blocks have been received, and if MA code blocks have not been received, continue to receive code blocks until MA code blocks are received.

[0095] In the case of receiving MA code blocks, if the MA code blocks include control code blocks and data code blocks, the MA code blocks are encoded as multiple first code blocks to obtain a second code block, the second code block includes A type bits, MA indicator bits and a load of multiple first code blocks, and the MA indicator bits are used to indicate the type of each first code block. If the MA code blocks are all control code blocks or all data code blocks, continue to receive code blocks until different types of code blocks are received or the number of received code blocks of the same type is equal to 2 M-A, taking the received code blocks as multiple first code blocks, encoding the multiple first code blocks to obtain a second code block, the second code block includes A type bits, MA indication bits and the load of the multiple first code blocks, and the MA indication bits are used to indicate the number of the first code blocks.

[0096] That is, when the plurality of first code blocks include control code blocks and data code blocks, the length of the second code block is fixed, and the length is equal to M+(MA)*64*n, where n is a positive integer less than or equal to 32. When the plurality of first code blocks are all control code blocks or all data code blocks, the length of the second code block can be in the range of [M+64*n, M+64*n*2 (M-A) ] within this range. Fig.10 Schematic diagram of an encoding process provided by an embodiment of the present application. Fig.10 As shown, the input multiple code blocks are all (64*n)B / (64*n+1)B encoded code blocks, the multiple code blocks include a control code block and a data code block, a code block as a first code block is obtained from the multiple code blocks, and the multiple first code blocks are encoded to obtain a second code block, and the obtained second code block includes a control code block and a data code block. Among them, the control code block includes A type bits, MA indication bits and a load of multiple first code blocks, and the MA indication bits are used to indicate the type of each first code block. The data code block includes A type bits, MA indication bits and a load of multiple first code blocks, and the MA indication bits are used to indicate the number of first code blocks.

[0097] Fig.11 FIG. 1 is a schematic diagram of another encoding process provided in an embodiment of the present application. Fig.11 As shown, M is equal to 4, A is equal to 1, the number of first code blocks is 11, and the first code blocks are all (64*n)B / (64*n+1)B encoded code blocks, and the first bit of the first code block is the type bit, and the other bits in the first code block except the first bit are the load. Assume that the first code blocks are numbered 0 to 10, the length is 1+64*n bits, and the first code blocks are obtained by encoding 64B / 66B code blocks using related technologies. Among them, the first code block numbered 0 is a control code block, the first bit of the control code block is 0, and the other 10 first code blocks are data code blocks, and the first bit of the data code block is 1.

[0098] See also Fig.11, the first code blocks numbered 0 to 2 are encoded into a second code block, the first bit of the second code block is a type bit, the first bit is a third value, and the third value is used to indicate that the multiple first code blocks encoded to obtain the second code block include a control code block and a data code block. The three bits immediately following the first bit are indication bits, and these three bits indicate the type of each first code block in the multiple first code blocks in a bitmap manner. The loads of the three first code blocks are sequentially loaded at the end of the second code block, and the load of each first code block includes 64*n bits.

[0099] The eight first code blocks numbered 3 to 10 are all data code blocks. These eight data code blocks are encoded into a second code block. The first bit of the second code block is a type bit. The first bit is a fourth value. The fourth value is used to indicate that the multiple first code blocks encoded to obtain the second code block are all data code blocks. The third value and the fourth value can be set based on experience or actual needs. For example, the third value is 0 and the fourth value is 1. In the second code block obtained by encoding the first code blocks numbered 3 to 10, the three bits immediately following the first bit are indicator bits. These three bits are used to indicate the number of multiple first code blocks. Fig.11 As shown, these three bits are all 1, indicating that the number of first code blocks is 8. The payloads of 8 first code blocks are sequentially loaded at the tail of the second code block, and the payload of each first code block includes 64*n bits.

[0100] like Fig.11 As shown in the figure, among the 11 first code blocks, each first code block includes 1 type bit, so the 11 first code blocks include 11 bits of overhead in total. After encoding the 11 first code blocks to obtain 2 second code blocks, each second code block includes 1 type bit and 3 indicator bits, that is, each second code block includes 4 bits of overhead. The overhead before and after encoding is reduced from 11 bits to 8 bits, which reduces the encoding overhead and improves the encoding efficiency.

[0101] In some embodiments, multiple first code blocks are obtained, and the operation of encoding the multiple first code blocks to obtain second code blocks can be performed multiple times, thereby obtaining multiple second code blocks. In the case of obtaining multiple second code blocks, the multiple second code blocks can also be encoded based on the principle of encoding multiple first code blocks to obtain second code blocks. For example, in the case where multiple second code blocks are encoded, and multiple first code blocks that are encoded to obtain multiple second code blocks are all data code blocks or are all control code blocks, after obtaining the second code block, the method also includes: encoding the multiple second code blocks to obtain a third code block, wherein the third code block includes A type bits, SA indicator bits, and the indicator bits included in the multiple second code blocks and the load of the first code block, the SA indicator bits are used to indicate the number of multiple second code blocks, and S is an integer greater than A. Exemplarily, the number of multiple second code blocks is greater than or equal to 2 and less than or equal to 2 S-A. Wherein, S may be the same as or different from M, and the embodiments of the present application do not limit this. For example, obtain A type bits to indicate the occurrence probability of a second code block of a plurality of first code blocks including a control code block and a data code block in a plurality of second code blocks, and determine the value of S based on the occurrence probability. The method of determining the value of S based on the occurrence probability is the same in principle as the method of determining the value of M in S701, and will not be repeated here. Exemplarily, no matter which case the plurality of first code blocks obtained by encoding the plurality of second code blocks belong to, the plurality of second code blocks encoded have the same length. For example, in the case where there is a second code block with a shorter length among the plurality of second code blocks obtained by encoding, padding data is added to the second code block with a shorter length, so that the lengths of the plurality of second code blocks are all the first reference length, and the first reference length may be the length of the longest second code block among the plurality of second code blocks, and the padding data may be set according to experience or actual needs, and the embodiments of the present application do not limit this. The method of encoding the plurality of second code blocks to obtain the third code block is the same as the principle of encoding the plurality of first code blocks to obtain the second code block in S702, and will not be repeated here.

[0102] In a possible implementation, when multiple second code blocks are obtained by encoding, and multiple first code blocks obtained by encoding multiple second code blocks include data code blocks and control code blocks, after obtaining the second code blocks, the method further includes: encoding multiple second code blocks to obtain a fourth code block, wherein the fourth code block includes A type bits, SA indicator bits, and the indicator bits and the load of the first code block included in the multiple second code blocks, and the SA indicator bits are used to indicate the type of each second code block in the multiple second code blocks, and S is an integer greater than A. Exemplarily, the number of second code blocks is SA, and SA is greater than or equal to 2. In a possible implementation, SA indicator bits are also used to indicate the position of the indicator bits and the load of the first code block included in each second code block in the multiple second code blocks in the fourth code block. That is, one indicator bit is used to indicate the type of a second code block and the position of the indicator bits and the load of the first code block included in the second code block in the fourth code block. Exemplarily, the length of the second code block obtained by encoding the control code block and the data code block is fixed, for example, the length is M+(MA)*64*n. The lengths of multiple second code blocks obtained by encoding a pure data code block or a pure control code block may be different. If there are multiple second code blocks obtained by encoding a pure data code block or a pure control code block among the multiple second code blocks to be encoded, these second code blocks are processed so that the lengths of these second code blocks after processing are the same. For example, padding data is added to the shorter second code blocks among these second code blocks so that the lengths of these second code blocks are all the second reference length. The second reference length can be the length of the longest second code block among these second code blocks. The padding data can be set according to experience or actual needs, and this embodiment of the present application does not limit this. The method of encoding multiple second code blocks to obtain a fourth code block is the same as the principle of encoding multiple first code blocks to obtain second code blocks in S702, and will not be repeated here.

[0103] Fig.12 FIG. 1 is a schematic diagram of another encoding process provided in an embodiment of the present application. Fig.12 As shown, A is equal to 1, M is equal to 3, and S is equal to 3. Five second code blocks are obtained by encoding multiple first code blocks, wherein each first code block includes 1 type bit and 64*n bits of payload, and the multiple first code blocks include a control code block with a first bit of 0 and a data code block with a first bit of 1. Assuming that the five second code blocks obtained are numbered 0 to 4, and the first bit of the second code block numbered 0 is 0, it means that the multiple first code blocks obtained by encoding the second code block include a control code block and a data code block, and the 3 bits after the first bit represent the type of each first code block in the multiple first code blocks in a bitmap manner. For example, one of the three bits corresponds to a first code block. If the first code block is a control code block, the bit corresponding to the first code block is 0, and if the first code block is a data code block, the bit corresponding to the first code block is 1. The second code block also includes the payload of each first code block.

[0104] The first bits of the second code blocks numbered 1 to 4 are all 1, indicating that the multiple first code blocks from which the four second code blocks are obtained are all data code blocks. For any of the four second code blocks, the three bits after the first bit are used to indicate the number of the multiple first code blocks. Fig.12 As shown, the three bits are all 1. The four second code blocks are obtained by encoding the eight data code blocks, so the four second code blocks each include the payload of the eight data code blocks.

[0105] Then, the second code blocks numbered 0 to 1 are encoded to obtain a fourth code block, and the first bit of the fourth code block is 0, indicating that at least one second code block encoded to obtain the fourth code block is obtained by encoding a control code block and a data code block. The two bits after the first bit represent the type of each second code block in a bitmap manner. For example, one of the two bits corresponds to a second code block. If the multiple first code blocks encoded to obtain the second code block include data code blocks and control code blocks, the bit corresponding to the second code block is 0. If the multiple first code blocks encoded to obtain the second code block are all data code blocks, the bit corresponding to the second code block is 1. The fourth code block also includes the indication bit included in the second code block and the load of the first code block.

[0106] The third code block is obtained by encoding the second code blocks numbered 2 to 4. The first bit of the third code block is 1, indicating that the second code blocks of the third code block are obtained by encoding the data code blocks. The two bits after the first bit are used to indicate the number of the second code blocks. Fig.12 As shown, both of these two bits are 1, indicating that the third code block is obtained by encoding the three second code blocks. The third code block also includes the indication bits included in the three second code blocks and the payload of the first code block.

[0107] Whether the third code block is obtained by encoding multiple second code blocks or the fourth code block is obtained by encoding multiple second code blocks, when S is less than the sum of the number of bits used as overhead in the multiple second code blocks, the overhead is further reduced and the coding efficiency is improved by encoding the multiple second code blocks. In the embodiment of the present application, at least one of the third code block or the fourth code block can be further encoded, and the principle of encoding is the same as the principle of encoding the multiple second code blocks, which will not be repeated here.

[0108] In the method provided in the embodiment of the present application, multiple first code blocks can be encoded to obtain a second code block, wherein the second code block includes A type bits, MA indicator bits and the load of multiple first code blocks, and the MA indicator bits are used to indicate the number of multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks. When M is less than the sum of the number of type bits included in the multiple first code blocks, the overhead of the second code block is less than the sum of the overheads of the multiple first code blocks, so that the overhead of the second code block is low and the coding efficiency is high.

[0109] The above describes the embodiment of the present application from the perspective of the encoding method. The embodiment of the present application also provides a decoding method. Next, the decoding method is described. The decoding method can be as follows: Fig.13 This method can be applied to Figure 4 The second module 402 is shown, Fig.13 As shown, the method includes but is not limited to S1301 and S1302.

[0110] S1301, obtaining a second code block, wherein the second code block includes A type bits, MA indication bits and a load of multiple first code blocks, each of the multiple first code blocks includes a load and at least one type bit, A is less than the sum of the number of type bits of the multiple first code blocks, M is an integer greater than A, the MA indication bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks, and the multiple first code blocks include at least one of a control code block or a data code block.

[0111] In one possible implementation, obtaining a second code block includes: obtaining a third code block, the third code block including A type bits, SA indication bits, and indication bits included in multiple second code blocks and a load of the first code block, the SA indication bits are used to indicate the number of multiple second code blocks, and S is an integer greater than A; decoding the third code block to obtain multiple second code blocks.

[0112] For example, the lengths of multiple second code blocks are the same, and the third code block is decoded to obtain multiple second code blocks, including: based on SA indicator bits, obtaining the type of each second code block in the multiple second code blocks; equally dividing the indicator bits of the multiple second code blocks included in the third code block and the load of the first code block according to the number indicated by the SA indicator bits, to obtain the indicator bits included in the multiple second code blocks and the load of the first code block; obtaining each second code block according to the type bit corresponding to each second code block and the indicator bit included in each second code block and the load of the first code block.

[0113] In another possible implementation, obtaining a second code block includes: obtaining a fourth code block, wherein the fourth code block includes A type bits, SA indication bits, and the indication bits included in multiple second code blocks and the load of the first code block, the SA indication bits are used to indicate the type of each second code block in the multiple second code blocks, and S is an integer greater than A; decoding the fourth code block to obtain multiple second code blocks.

[0114] For example, decoding the fourth code block to obtain multiple second code blocks includes: obtaining the type of each second code block in the multiple second code blocks based on SA indicator bits; obtaining the indication bits included in each second code block in the multiple second code blocks and the load of the first code block from the indication bits of the multiple second code blocks included in the fourth code block and the load of the first code block; obtaining multiple second code blocks according to the type bits corresponding to each second code block in the multiple second code blocks and the indication bits included in each second code block and the load of the first code block.

[0115] For example, when the lengths of multiple second code blocks are the same, the indication bits included in each of the multiple second code blocks and the load of the first code block are obtained from the indication bits of the multiple second code blocks included in the fourth code block and the load of the first code block, including: dividing the indication bits of the multiple second code blocks included in the fourth code block and the load of the first code block into SA portions of bits, each portion of bits being the indication bits included in one second code block and the load of the first code block. If the lengths of the multiple second code blocks are not all the same, obtaining the indication bits included in each of the multiple second code blocks and the load of the first code block from the indication bits of the multiple second code blocks included in the fourth code block and the load of the first code block, including: based on the length corresponding to the second code block obtained by encoding the control code block and the data code block, obtaining the indication bits included in the second code block and the load of the first code block from the indication bits of the multiple second code blocks included in the fourth code block and the load of the first code block; based on the second reference length, obtaining the indication bits included in the second code block obtained by encoding a pure data code block or a pure control code block and the load of the first code block from the indication bits of the multiple second code blocks included in the fourth code block and the load of the first code block.

[0116] S1302: Decode the second code block to obtain multiple first code blocks.

[0117] Exemplarily, M is less than the sum of the number of type bits included in the multiple first code blocks, so that the overhead of the second code block is less than the sum of the overheads of the multiple first code blocks. In a possible implementation, when A type bits indicate that the multiple first code blocks are all data code blocks or are all control code blocks, MA indicator bits are used to indicate the number of the multiple first code blocks; decoding the second code block to obtain multiple first code blocks includes: equally dividing the loads of the multiple first code blocks included in the second code block according to the number indicated by the MA indicator bits to obtain the loads of the multiple first code blocks; when the multiple first code blocks are all data code blocks, according to the type bits corresponding to the data code blocks and the loads of the multiple first code blocks, multiple first code blocks are obtained; when the multiple first code blocks are all control code blocks, according to the type bits corresponding to the control code blocks and the loads of the multiple first code blocks, multiple first code blocks are obtained.

[0118] In another possible implementation, in the case where A type bits indicate that multiple first code blocks include control code blocks and data code blocks, MA indicator bits are used to indicate the type of each first code block in the multiple first code blocks; decoding the second code block to obtain multiple first code blocks includes: obtaining the type of each first code block based on MA indicator bits; obtaining the load of each first code block in the multiple first code blocks from the loads of the multiple first code blocks included in the second code block; obtaining the control code block included in the multiple first code blocks according to the load of the control code block and the type bit corresponding to the control code block; obtaining the data code block included in the multiple first code blocks according to the load of the data code block and the type bit corresponding to the data code block. For example, obtaining the load of each first code block in the multiple first code blocks from the load of the multiple first code blocks included in the second code block includes: dividing the load of the multiple first code blocks included in the second code block into MA portions of bits, each portion of bits being the load of one first code block.

[0119] Exemplarily, the first code block includes 1 type bit and a 64*N bit payload, where N is a positive integer. For example, the 64*N bit payload includes data; or, the 64*N bit payload includes an information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data. Exemplarily, the first code block is a 64-bit B / 66B encoded code block.

[0120] Fig.14 Schematic diagram of a decoding process of a second code block provided by an embodiment of the present application. Fig.14 As shown, the second code block is started to be received. After receiving A type bits of the second code block, it is determined based on the A type bits whether the multiple first code blocks encoded to obtain the second code block are all data code blocks or all control code blocks. In the case where the multiple first code blocks encoded to obtain the second code block include control code blocks and data code blocks, the subsequent MA indicator bits are continuously received, and the MA indicator bits are used to indicate the type of each first code block in the multiple first code blocks. Then, 64*n bits are continuously received, and the bits corresponding to the 64*n bits in the MA indicator bits are read to obtain the type bits of the first code block, and the 64*n bits are used as the load of the first code block, and the first code block is obtained based on the type bits and the load of the first code block.

[0121] Afterwards, continue to receive 64*n bits, and cyclically execute the process of obtaining the first code block based on 64*n bits and MA indicator bits, until a total of M+64*n*(MA) bits are received, and the decoding process of the second code block is terminated.

[0122] When the first code blocks obtained by encoding the second code block are all control code blocks or data code blocks, the subsequent MA indication bits are continuously received, and the MA indication bits are used to indicate the number of the first code blocks. Then, 64*n bits are continuously received. When the first code block is a control code block, the 64*n bits are used as the load of the first code block, and the type bit corresponding to the control code block is added before the load to obtain the first code block. When the first code block is a data code block, the 64*n bits are used as the load of the first code block, and the type bit corresponding to the data code block is added before the load to obtain the first code block.

[0123] After that, continue to receive 64*n bits, and cyclically execute the process of obtaining the first code block based on 64*n bits and the type bits corresponding to the first code block, until a total of M+C*64*n* bits are received, where C represents the number of first code blocks, and then the decoding process of the second code block is terminated.

[0124] Combination Fig.14 It can be seen from the decoding process shown that the type and length of the second code block can be determined based on the A type bits of the second code block. In addition, after decoding the second code block, multiple first code blocks of fixed length are output, each of which includes a type bit. Fig.15 FIG. 1 is another schematic diagram of a process for decoding a second code block provided by an embodiment of the present application. Fig.15 As shown, a plurality of second code blocks are decoded, wherein a second code block includes A type bits, MA indication bits and a load of a plurality of first code blocks, the MA indication bits are used to indicate the number of the plurality of first code blocks, and the second code block is as shown in FIG. Fig.15 The other second code blocks include A type bits, MA indication bits and a load of multiple first code blocks, where the MA indication bits are used to indicate the type of each first code block in the multiple first code blocks. Fig.15 As shown in the second code block 2 in . Fig.15 The numbers of the second code blocks 1 and the second code blocks 2 shown in the figure are only for illustration. No matter whether the second code block 1 or the second code block 2 is decoded, the first code blocks obtained include 1 type bit and 64*n bits of payload, that is, the first code blocks are all (64*n)B / (64*n+1)B encoded code blocks. Fig.15 As shown, the plurality of first code blocks include control code blocks and data code blocks.

[0125] Exemplarily, the method further includes a process of decoding the first code block. In a possible implementation, the method further includes: decompressing 1 type bit of the first code block to obtain a first reference code block, the first reference code block includes 2 type bits and a 64-bit payload, and the first reference code block is a control code block or a data code block. For example, the process of decoding the first code block can refer to the process of obtaining a 64B / 66B encoded code block based on a 64B / 65B encoded code block in the IEEE 802.3 standard. In another possible implementation, the method further includes: decoding the first code block to obtain N second reference code blocks, wherein N is greater than or equal to 2, the N second reference code blocks each include 2 type bits and a 64-bit payload, and the N second reference code blocks include at least one of a control code block or a data code block. For example, the process of decoding the first code block can refer to the process of obtaining a 64B / 66B encoded code block based on a (64*n)B / (64*n+1)B encoded code block in the IEEE 802.3 standard.

[0126] In the method provided by the embodiment of the present application, a plurality of first code blocks are obtained by decoding the second code block, wherein the second code block includes A type bits, MA indicator bits and the loads of the plurality of first code blocks, and the MA indicator bits are used to indicate the number of the plurality of first code blocks or indicate at least one of the types of each first code block in the plurality of first code blocks. When M is less than the sum of the number of type bits included in the plurality of first code blocks, the overhead of the second code block is less than the sum of the overheads of the plurality of first code blocks, so that the overhead of the second code block is low and the coding efficiency is high.

[0127] The embodiment of the present application also provides a coding device. Fig.16 is a schematic diagram of the structure of a coding device provided in an embodiment of the present application. The device is applied to Figure 4 The first module 401 shown is based on Fig.16 The multiple modules shown in the figure can perform Figure 7 It should be understood that the device may include more additional modules than the units shown or omit some of the modules shown therein, and the embodiments of the present application are not limited to this. Fig.16 As shown, the device includes an acquisition module 1601 and an encoding module 1602.

[0128] An acquisition module 1601 is used to acquire multiple first code blocks, wherein each of the multiple first code blocks includes a payload and at least one type bit, and the multiple first code blocks include at least one of a control code block or a data code block; an encoding module 1602 is used to encode the multiple first code blocks to obtain a second code block, wherein the second code block includes A type bits, MA indicator bits and the payload of the multiple first code blocks, A is less than the sum of the number of type bits of the multiple first code blocks, M is an integer greater than A, and the MA indicator bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks.

[0129] In some embodiments, M is smaller than the sum of the number of type bits included in the plurality of first code blocks.

[0130] In some embodiments, the acquisition module 1601 is used to continuously receive MA code blocks; based on the MA code blocks including control code blocks and data code blocks, the MA code blocks are used as multiple first code blocks; based on the MA code blocks being data code blocks or control code blocks, the code blocks are continued to be received until code blocks of different types are received or the number of code blocks of the same type received is equal to 2 M-A , taking the received code blocks as multiple first code blocks.

[0131] In some embodiments, the multiple first code blocks include control code blocks and data code blocks, and the acquisition module 1601 is further used to acquire the occurrence probability of the control code block in the multiple first code blocks; and determine the value of M based on the occurrence probability.

[0132] In some embodiments, the acquisition module 1601 is used to acquire the occurrence probability of the control code block in the multiple first code blocks based on the Ethernet frame.

[0133] In some embodiments, the acquisition module 1601 is used to obtain the number of possible values ​​for each bit of the second code block; obtain the logarithm of the inverse of the probability of occurrence with the number of possible values ​​as the base; and round the logarithm down to obtain the value of M.

[0134] In some embodiments, the first code block includes 1 type bit and a 64*N bit payload, where N is a positive integer. For example, the 64*N bit payload includes data; or, the 64*N bit payload includes an information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data.

[0135] In one possible implementation, the acquisition module 1601 is used to obtain a first reference code block, wherein the first reference code block includes 2 type bits and 64 bits of payload, and the first reference code block includes a control code block or a data code block; the type bit of the first reference code block is compressed to obtain a first code block including 1 type bit.

[0136] In another possible implementation, the acquisition module 1601 is used to obtain N second reference code blocks, where N is greater than or equal to 2, the N second reference code blocks each include 2 type bits and 64 bits of payload, and the N second reference code blocks include at least one of a control code block or a data code block; the N second reference code blocks are encoded to obtain a first code block including 1 type bit.

[0137] In some embodiments, the first code block is a 64B / 66B encoded code block.

[0138] In some embodiments, when multiple second code blocks are obtained by encoding, and multiple first code blocks obtained by encoding the multiple second code blocks are all data code blocks or are all control code blocks, the encoding module 1602 is also used to encode the multiple second code blocks to obtain a third code block, wherein the third code block includes A type bits, SA indicator bits and the indicator bits included in the multiple second code blocks and the load of the first code block, the SA indicator bits are used to indicate the number of the multiple second code blocks, and S is an integer greater than A.

[0139] In some embodiments, when multiple second code blocks are obtained by encoding, and multiple first code blocks obtained by encoding multiple second code blocks include data code blocks and control code blocks, the encoding module 1602 is also used to encode multiple second code blocks to obtain a fourth code block, wherein the fourth code block includes A type bits, SA indication bits and the indication bits included in the multiple second code blocks and the load of the first code block, and the SA indication bits are used to indicate the type of each second code block in the multiple second code blocks.

[0140] In the device provided in the embodiment of the present application, multiple first code blocks can be encoded to obtain a second code block, wherein the second code block includes A type bits, MA indicator bits and the load of multiple first code blocks, and the MA indicator bits are used to indicate the number of multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks. When M is less than the sum of the number of type bits included in the multiple first code blocks, the overhead of the second code block is less than the sum of the overheads of the multiple first code blocks, so that the overhead of the second code block is low and the coding efficiency is high.

[0141] The embodiment of the present application also provides another decoding device. Fig.17 is a schematic diagram of the structure of another decoding device provided in an embodiment of the present application. The device is applied to Figure 4 The second module 402 shown is based on Fig.17 The multiple modules shown in the figure can perform Fig.13It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the embodiments of the present application are not limited to this. Fig.17 As shown, the device includes an acquisition module 1701 and a decoding module 1702.

[0142] An acquisition module 1701 is used to acquire a second code block, wherein the second code block includes A type bits, MA indicator bits and a load of multiple first code blocks, each of the multiple first code blocks includes a load and at least one type bit, A is less than the sum of the number of type bits of the multiple first code blocks, M is an integer greater than A, and the MA indicator bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks, and the multiple first code blocks include at least one of a control code block or a data code block; a decoding module 1702 is used to decode the second code block to obtain multiple first code blocks.

[0143] In some embodiments, M is smaller than the sum of the number of type bits included in the plurality of first code blocks.

[0144] In some embodiments, when A type bits indicate that multiple first code blocks are all data code blocks or are all control code blocks, MA indicator bits are used to indicate the number of multiple first code blocks; the decoding module 1702 is used to equally divide the loads of multiple first code blocks included in the second code block according to the number indicated by the MA indicator bits to obtain the loads of multiple first code blocks; when multiple first code blocks are all data code blocks, multiple first code blocks are obtained according to the type bits corresponding to the data code blocks and the loads of the multiple first code blocks; when multiple first code blocks are all control code blocks, multiple first code blocks are obtained according to the type bits corresponding to the control code blocks and the loads of the multiple first code blocks.

[0145] In some embodiments, when A type bits indicate that multiple first code blocks include control code blocks and data code blocks, MA indication bits are used to indicate the type of each first code block in the multiple first code blocks; a decoding module 1702 is used to obtain the type of each first code block based on the MA indication bits; obtain the load of each first code block in the multiple first code blocks from the loads of the multiple first code blocks included in the second code block; obtain the control code block included in the multiple first code blocks according to the load of the control code block and the type bit corresponding to the control code block; obtain the data code block included in the multiple first code blocks according to the load of the data code block and the type bit corresponding to the data code block.

[0146] In some embodiments, the acquisition module 1701 is used to acquire a third code block, wherein the third code block includes A type bits, SA indication bits, and the indication bits included in multiple second code blocks and the load of the first code block, the SA indication bits are used to indicate the number of multiple second code blocks, and S is an integer greater than A; the third code block is decoded to obtain multiple second code blocks.

[0147] In some embodiments, the acquisition module 1701 is used to obtain a fourth code block, wherein the fourth code block includes A type bits, SA indication bits, and indication bits included in multiple second code blocks and the load of the first code block, the SA indication bits are used to indicate the type of each second code block in the multiple first code blocks, and S is an integer greater than A; the fourth code block is decoded to obtain multiple second code blocks.

[0148] In some embodiments, the first code block includes 1 type bit and a 64*N bit payload, where N is a positive integer. For example, the 64*N bit payload includes data; or, the 64*N bit payload includes an information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data.

[0149] In a possible implementation, the decoding module 1702 is further used to decompress one type bit of the first code block to obtain a first reference code block, wherein the first reference code block includes two type bits and a 64-bit payload, and the first reference code block is a control code block or a data code block.

[0150] In another possible implementation, the decoding module 1702 is further used to decode the first code block to obtain N second reference code blocks, where N is greater than or equal to 2, the N second reference code blocks each include 2 type bits and 64 bits of load, and the N second reference code blocks include at least one of a control code block or a data code block.

[0151] In some embodiments, the first code block is a 64B / 66B encoded code block.

[0152] In the device provided by the embodiment of the present application, the second code block is decoded to obtain multiple first code blocks, wherein the second code block includes A type bits, MA indicator bits and the load of multiple first code blocks, and the MA indicator bits are used to indicate the number of multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks. When M is less than the sum of the number of type bits included in the multiple first code blocks, the overhead of the second code block is less than the sum of the overheads of the multiple first code blocks, so that the overhead of the second code block is low and the coding efficiency is high.

[0153] It should be understood that the above Fig.16 and Fig.17When the device provided realizes its functions, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0154] See also Fig.18 , Fig.18 The following is a schematic diagram of the structure of a computer system provided in an embodiment of the present application. Fig.18 As shown, the computer system is a computer system 2000. The computer system 2000 may be a network device, a routing device or a switching device. Fig.18 The computer system 2000 shown is used to execute the above Figure 7 The encoding method shown or Fig.13 The operation of the decoding method shown in the figure. The computer system 2000 is, for example, a server, etc. The computer system 2000 can be implemented by a general bus architecture.

[0155] like Fig.18 As shown, the computer system 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0156] Processor 2001 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the method provided in the embodiment of the present application. For example, processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination of the above three. Processor 2001 can be a combination of various logic boxes, modules and circuits described in conjunction with the disclosure of the embodiment of the present application, or a combination of computing functions, such as a combination of one or more microprocessors, a combination of DSP and microprocessors, and the like.

[0157] Optionally, the computer system 2000 further includes a bus. The bus is used to transmit information between the components of the computer system 2000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.18 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0158] The memory 2003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0159] The communication interface 2004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, radio access network (RAN) or wireless local area network (WLAN), etc. The communication interface 2004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0160] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as Fig.18 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0161] In a specific implementation, as an embodiment, the computer system 2000 may include multiple processors, such as Fig.18 2001 and processor 2005 are shown in FIG. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0162] In a specific implementation, as an embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0163] In some embodiments, the memory 2003 is used to store program code 2010, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 itself may also store program code or instructions.

[0164] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the first module and / or the second module in the above-mentioned various method embodiments, and the first module and / or the second module may be implemented by the processor 2001 in the computer system 2000.

[0165] The computer system 2000 may also correspond to the above Fig.16 and Fig.17 The device shown, Fig.16 or Fig.17 Each functional module in the illustrated apparatus may be implemented by a circuit in the processor 2000 .

[0166] in, Figure 7 The encoding method shown or Fig.13 Each step of the decoding method shown is completed by a hardware integrated logic circuit in a processor of the computer system 2000. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware processor.

[0167] Fig.19is a schematic diagram of the structure of another computer system provided in an embodiment of the present application, the computer system is used to execute the above Figure 7 The encoding method shown or Fig.13 The operations in the decoding method shown. Exemplarily, the computer system is a server, and the server may have relatively large differences due to different configurations or performances. The computer system may include one or more processors 1901, and the one or more processors 1901 are used to implement the first module and / or the second module in the method embodiment. Fig.19 As shown, the computer system may further include one or more memories 1902, wherein at least one computer program is stored in the one or more memories 1902, and the at least one computer program is loaded and executed by one or more processors 1901. Exemplarily, the processor 1901 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the computer system may also include other components for realizing device functions, which will not be described in detail here.

[0168] The present application also provides a communication device, which includes: a transceiver module for executing Figure 7 The receiving and / or sending related operations in the encoding method shown; a processing module for performing Figure 7 The encoding method shown in the figure has other operations other than the operations related to receiving and / or sending. The embodiment of the present application also provides another communication device, which includes: a transceiver module, which is used to perform Fig.13 The receiving and / or sending related operations in the decoding method shown; a processing module for performing Fig.13 The decoding method shown includes other operations except the operations related to receiving and / or sending.

[0169] The present application embodiment provides a chip, which includes: an interface module, the interface module is used to execute Figure 7 The encoding method shown or Fig.13 The present application also provides another chip, which includes a processor, and the processor is used to call and execute instructions stored in the memory from the memory, so that the communication device equipped with the chip executes Figure 7 The encoding method shown or Fig.13 The decoding method shown. Exemplarily, the chip further includes: an input interface, an output interface and a memory, the input interface, the output interface, the processor and the memory are connected through an internal connection path, and the memory contains the above-mentioned program instructions or codes.

[0170] The embodiment of the present application also provides an electronic device, comprising: a processor, the processor is coupled to a memory, the memory stores at least one program instruction or code, the at least one program instruction or code is loaded and executed by the processor, so that the electronic device can realize Figure 7 The encoding method shown or Fig.13 The decoding method shown.

[0171] The embodiment of the present application also provides a communication system, the communication system includes a first interface module and a second interface module; the first interface module is used to execute Figure 7 The encoding method shown, the second interface module is used to execute Fig.13 The decoding method shown.

[0172] An embodiment of the present application also provides a computer-readable storage medium, in which at least one program instruction or code is stored. When the program instruction or code is loaded and executed by a processor of a computer, the computer implements the encoding method or decoding method in the method embodiment.

[0173] The embodiments of the present application further provide a computer program or a computer program product, wherein the computer program or the computer program product comprises: a computer program code, and when the computer program code is executed by a computer, the computer executes the encoding method or the decoding method in the method embodiment.

[0174] It should be understood that the processor may be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting an advanced RISC machines (ARM) architecture.

[0175] Further, in an optional embodiment, if one or more of the above-mentioned computer system, communication device, chip or communication system also includes a memory, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0176] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a ROM, a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (electrically EPROM, EEPROM) or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic random access memory, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM).

[0177] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program or a computer program product. A computer program or a computer program product includes one or more computer instructions. When loading and executing a computer program instruction on a computer, a process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, a computer instruction can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0178] In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0179] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of the storage device of general-purpose computer, special-purpose computer or other programmable annotation content, so that the program code, when being executed by the storage device of computer or other programmable annotation content, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on the remote computer or completely on the remote computer or server.

[0180] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, etc. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, etc.

[0181] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0182] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0183] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0184] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0185] In this application, the words such as "first", "second", etc. are used to distinguish the same or similar items with basically the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, the first module can be referred to as the second module, and similarly, the second module can be referred to as the first module.

[0186] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0187] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple range locks means two or more range locks. The terms "system" and "network" are often used interchangeably herein.

[0188] It should be understood that the terms used in the description of various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0189] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0190] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining that…” or “in response to determining that…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0191] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0192] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0193] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A coding method, characterized in that: The method comprises: Acquire a plurality of first code blocks, wherein each of the plurality of first code blocks comprises a payload and at least one type bit, and the plurality of first code blocks comprises at least one of a control code block or a data code block; Encode the multiple first code blocks to obtain a second code block, wherein the second code block includes A type bits, MA indication bits and a load of the multiple first code blocks, the A is less than the sum of the number of type bits of the multiple first code blocks, the M is an integer greater than the A, and the MA indication bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks.

2. The method according to claim 1, characterized in that The M is smaller than the sum of the number of type bits included in the plurality of first code blocks.

3. The method according to claim 1 or 2, characterized in that: The acquiring of the plurality of first code blocks comprises: continuously receiving MA code blocks; Based on the MA code blocks including control code blocks and data code blocks, using the MA code blocks as the multiple first code blocks; Based on the fact that the MA code blocks are all data code blocks or control code blocks, continue to receive code blocks until code blocks of different types are received or the number of received code blocks of the same type is equal to 2 M-A , taking the received code blocks as the multiple first code blocks.

4. The method according to any one of claims 1 to 3, characterized in that: The plurality of first code blocks include a control code block and a data code block, and the method further includes: Obtaining the occurrence probability of the control code block in the plurality of first code blocks; Based on the occurrence probability, the value of M is determined.

5. The method according to claim 4, characterized in that The obtaining the occurrence probability of the control code block in the plurality of first code blocks includes: Based on the Ethernet frame, the occurrence probability of the control code block in the plurality of first code blocks is obtained.

6. The method according to claim 4 or 5, characterized in that: The determining the value of M based on the occurrence probability includes: Obtaining the number of possible values ​​for each bit of the second code block; Obtaining the logarithm of the reciprocal of the occurrence probability with the number of possible values ​​as the base; The logarithm is rounded down to obtain the value of M.

7. The method according to any one of claims 1 to 6, characterized in that: The first code block includes 1 type bit and 64*N bits of payload, where N is a positive integer.

8. The method according to claim 7, characterized in that The 64*N bits of payload include data; Alternatively, the 64*N-bit payload includes an information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data.

9. The method according to claim 7 or 8, characterized in that: Acquiring a first code block from the plurality of first code blocks includes: Acquire a first reference code block, wherein the first reference code block includes 2 type bits and a 64-bit payload, and the first reference code block includes a control code block or a data code block; The type bit of the first reference code block is compressed to obtain the first code block including 1 type bit.

10. The method according to claim 7 or 8, characterized in that: Acquiring a first code block from the plurality of first code blocks includes: Acquire N second reference code blocks, wherein N is greater than or equal to 2, each of the N second reference code blocks includes 2 type bits and 64 bits of payload, and the N second reference code blocks include at least one of a control code block or a data code block; The N second reference code blocks are encoded to obtain the first code block including 1 type bit.

11. The method according to any one of claims 1 to 6, characterized in that: The first code block is a 64-bit B / 66B encoded code block.

12. The method according to any one of claims 1 to 11, characterized in that: In a case where a plurality of second code blocks are obtained by encoding, and a plurality of first code blocks obtained by encoding the plurality of second code blocks are all the data code blocks or are all the control code blocks, after obtaining the second code blocks, the method further includes: Encode the multiple second code blocks to obtain a third code block, wherein the third code block includes A type bits, SA indication bits, and the indication bits included in the multiple second code blocks and the load of the first code block, the SA indication bits are used to indicate the number of the multiple second code blocks, and S is an integer greater than A.

13. The method according to any one of claims 1 to 11, characterized in that: In the case where a plurality of second code blocks are obtained by encoding, and a plurality of first code blocks obtained by encoding the plurality of second code blocks include the data code block and the control code block, after obtaining the second code blocks, the method further includes: Encode the multiple second code blocks to obtain a fourth code block, wherein the fourth code block includes A type bits, SA indication bits, and the indication bits included in the multiple second code blocks and the load of the first code block, and the SA indication bits are used to indicate the type of each second code block in the multiple second code blocks.

14. A decoding method, characterized in that: The method comprises: Obtain a second code block, wherein the second code block includes A type bits, MA indication bits, and a payload of multiple first code blocks, each of the multiple first code blocks includes a payload and at least one type bit, the A is less than the sum of the number of type bits of the multiple first code blocks, the M is an integer greater than the A, the MA indication bits are used to indicate the number of the multiple first code blocks or indicate at least one of the types of each first code block in the multiple first code blocks, and the multiple first code blocks include at least one of a control code block or a data code block; The second code block is decoded to obtain the multiple first code blocks.

15. The method according to claim 14, characterized in that The M is smaller than the sum of the number of type bits included in the plurality of first code blocks.

16. The method according to claim 14 or 15, characterized in that In a case where the A type bits indicate that the plurality of first code blocks are all the data code blocks or are all the control code blocks, the MA indication bits are used to indicate the number of the plurality of first code blocks; and the decoding of the second code block to obtain the plurality of first code blocks includes: Dividing the loads of the multiple first code blocks included in the second code block equally according to the number indicated by the MA indication bits to obtain the loads of the multiple first code blocks; In a case where the multiple first code blocks are all the data code blocks, obtaining the multiple first code blocks according to the type bits corresponding to the data code blocks and the loads of the multiple first code blocks; In the case that the multiple first code blocks are all the control code blocks, the multiple first code blocks are obtained according to the type bits corresponding to the control code blocks and the loads of the multiple first code blocks.

17. The method according to claim 14 or 15, characterized in that In a case where the A type bits indicate that the plurality of first code blocks include the control code block and the data code block, the MA indication bits are used to indicate a type of each first code block in the plurality of first code blocks; and decoding the second code block to obtain the plurality of first code blocks includes: Obtaining the type of each first code block based on the MA indication bits; Acquire, from the payloads of the plurality of first code blocks included in the second code block, the payload of each first code block in the plurality of first code blocks; According to the load of the control code block and the type bit corresponding to the control code block, obtain the control code block included in the multiple first code blocks; According to the load of the data code block and the type bit corresponding to the data code block, the data code block included in the multiple first code blocks is obtained.

18. The method according to any one of claims 14 to 16, characterized in that: The obtaining of the second code block comprises: Acquire a third code block, wherein the third code block includes A type bits, SA indication bits, and indication bits included in a plurality of second code blocks and a load of the first code block, the SA indication bits are used to indicate the number of the plurality of second code blocks, and S is an integer greater than A; The third code block is decoded to obtain the multiple second code blocks.

19. The method according to any one of claims 14, 15 and 17, characterized in that: The obtaining of the second code block comprises: Obtain a fourth code block, wherein the fourth code block includes A type bits, SA indication bits, and indication bits included in multiple second code blocks and a load of the first code block, the SA indication bits are used to indicate a type of each second code block in the multiple second code blocks, and S is an integer greater than A; The fourth code block is decoded to obtain the multiple second code blocks.

20. The method according to any one of claims 14 to 19, characterized in that: The first code block includes 1 type bit and 64*N bits of payload, where N is a positive integer.

21. The method according to claim 20, characterized in that The 64*N bits of payload include data; Alternatively, the 64*N-bit payload includes an information indication and code block content, the code block content includes a compressed block type field, and the code block content also includes at least one of a control word or data.

22. The method according to claim 20 or 21, characterized in that The method further comprises: One type bit of the first code block is decompressed to obtain a first reference code block, wherein the first reference code block includes 2 type bits and 64 bits of payload, and the first reference code block is a control code block or a data code block.

23. The method according to claim 20 or 21, characterized in that The method further comprises: The first code block is decoded to obtain N second reference code blocks, wherein N is greater than or equal to 2, the N second reference code blocks each include 2 type bits and 64 bits of load, and the N second reference code blocks include at least one of a control code block or a data code block.

24. The method according to any one of claims 14 to 19, characterized in that: The first code block is a 64-bit B / 66B encoded code block.

25. An encoding device, characterized in that: The device comprises: A transceiver module, used to perform operations related to receiving and / or sending in any of the methods described in claims 1-13; A processing module, used to perform other operations in the method described in any one of claims 1-13 except for operations related to receiving and / or sending.

26. A decoding device, characterized in that: The device comprises: A transceiver module, used to perform the operations related to receiving and / or sending in any of the methods described in claims 14-24; A processing module, used to perform other operations in the method described in any one of claims 14-24 except for operations related to receiving and / or sending.

27. A chip, characterized in that: The chip comprises: an interface module, and the interface module is used to execute the encoding method as described in any one of claims 1-13, or the decoding method as described in any one of claims 14-24.

28. A chip, characterized in that: The chip includes a processor, which is used to call and execute instructions stored in the memory from the memory, so that a communication device equipped with the chip executes the encoding method as described in any one of claims 1-13, or the decoding method as described in any one of claims 14-24.

29. An electronic device, characterized in that: The electronic device includes: a processor, the processor is coupled to a memory, the memory stores at least one program instruction or code, and the at least one program instruction or code is loaded and executed by the processor so that the electronic device implements the encoding method as described in any one of claims 1 to 13, or the decoding method as described in any one of claims 14 to 24.

30. A communication system, characterized in that: The system comprises a first interface module and a second interface module, wherein the first interface module is used to execute the encoding method as described in any one of claims 1 to 13, and the second interface module is used to execute the decoding method as described in any one of claims 14 to 24.

31. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program instruction or code, and when the program instruction or code is loaded and executed by the computer processor, the computer implements the encoding method as described in any one of claims 1 to 13, or the decoding method as described in any one of claims 14 to 24.

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