Key sharing method and key sharing device

Abstract

The embodiment of the invention provides a key sharing method and a key sharing device. The key sharing method comprises the following steps: randomly initializing to obtain a key, and calculating to obtain at least part of configuration bit information for a receiving end based on the key by using a PUF generation array which shares a physical unclonable function (PUF) value with the receiving end, or randomly initializing to obtain the configuration bit information, using the PUF generation array to calculate and obtain a secret key for the receiving end based on the configuration bit information; and the configuration bit information is provided for the receiving end, so that the receiving end generates a key by using a PUF generation array based on the configuration bit information, the PUF generation array comprises a memristor array, the configuration bit information comprises information used for controlling which calculation units in the PUF generation array participate in key calculation, and the calculation comprises product accumulation calculation. The key sharing method is realized based on the memristor array, and the reliability and safety of information transmission between the key sending end and the key receiving end are effectively ensured.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a key sharing method and a key sharing device. Background Art

[0002] In the information society, information security is an indispensable part. When transmitting information, for security reasons, the sender encrypts and transmits the information, and the receiver obtains and decrypts the information. The encryption and decryption process requires a key. The traditional key storage method is to use firmware programming to store the key in a powered erasable programmable read-only memory. This method is difficult to prevent third parties from implanting Trojans during firmware programming, and the storage efficiency is not enough to match the scale of the IoT ecosystem.

[0003] A Physical Unclonable Function (PUF) is a hardware security primitive that generates and stores hardware identities. It uses random errors introduced by hardware circuits during manufacturing or initialization to generate multiple true random sequences. These sequences are efficient and unpredictable, similar to "fingerprints", and can be used as keys. In scenarios such as information transmission and multi-party communication, the sender, receiver, or multiple parties are often required to have the same key, so key sharing is proposed. The purpose of key sharing is to allow all parties to have the same key without leaking the key. If the key is sent directly by a third party, the key can be easily eavesdropped on the channel, which is unsafe. Therefore, a method needs to be implemented to allow multiple parties to generate the same key using their own PUF without leaking the key. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a key sharing method, which includes: randomly initializing to obtain a key, using a PUF generation array that shares a PUF value with a receiving end to calculate at least part of the configuration bit information for the receiving end based on the key, or randomly initializing to obtain the configuration bit information, using the PUF generation array to calculate the key for the receiving end based on the configuration bit information; and providing the configuration bit information to the receiving end so that the receiving end uses the PUF generation array to generate the key based on the configuration bit information, wherein the PUF generation array includes a memristor array, the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication-addition calculation.

[0005] For example, in the key sharing method provided in at least one embodiment of the present disclosure, it also includes receiving a PUF value for sharing of the PUF generation array from the receiving end, wherein the PUF value includes a numerical value for each PUF unit in the PUF generation array.

[0006] For example, in the key sharing method provided by at least one embodiment of the present disclosure, the configuration bit information includes first configuration bit information and second configuration bit information; the PUF generation array that uses the PUF value shared with the receiving end calculates at least part of the configuration bit information for the receiving end based on the key, including: randomly generating the first configuration bit information, wherein the first configuration bit information is configured to control which computing units in the PUF generation array participate in the key calculation; using the PUF generation array to calculate the second configuration bit information based on the first configuration bit information and the key, wherein the second configuration bit information is configured to indicate the difference between a first result calculated using the PUF generation array based on the first configuration bit information and the key.

[0007] For example, in the key sharing method provided by at least one embodiment of the present disclosure, the use of the PUF generation array to calculate the second configuration bit information based on the first configuration bit information and the key includes: using the PUF generation array to calculate a first result based on the first configuration bit information; comparing the first result with the key to obtain the second configuration bit information.

[0008] For example, in the key sharing method provided by at least one embodiment of the present disclosure, the memristor array includes 2n columns, each two columns form a group, the source line ends of the two columns in each group are respectively connected to the first input end and the second input end of the comparator, the second configuration bit information includes n bits, the key includes n bits, and n is a positive integer;

[0009] The using the PUF generation array to calculate the first result based on the first configuration bit information includes: using the first configuration bit information as a row control signal input of the PUF generation array, applying a read voltage to a bit line terminal of the PUF generation array to perform calculation; and each group of corresponding comparators compares a read current at the first input terminal with a read current at the second input terminal and outputs a comparison result, thereby obtaining an n-bit output result; and

[0010] The comparing the first result with the key to obtain the second configuration bit information includes: comparing the n-bit output result with the key bit by bit to obtain the second configuration bit information, wherein the bits with the first logic value in the second configuration bit information indicate that the values ​​of the key and the first result at the corresponding bits are different, the bits with the second logic value in the second configuration bit information indicate that the values ​​of the key and the first result at the corresponding bits are the same, and the first logic value is opposite to the second logic value.

[0011] At least one embodiment of the present disclosure provides a key sharing method, comprising: obtaining configuration bit information provided by a transmitting end, wherein at least part of the configuration bit information or a key is calculated based on a PUF generation array that shares a PUF value with the transmitting end; using the PUF generation array to calculate the key based on the obtained configuration bit information, wherein the PUF generation array includes a memristor array, the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication-addition calculation.

[0012] For example, in the key sharing method provided in at least one embodiment of the present disclosure, it also includes initializing the PUF generation array to obtain a PUF value for sharing, and providing the PUF value to the sending end.

[0013] For example, in the key sharing method provided by at least one embodiment of the present disclosure, the configuration bit information includes first configuration bit information and second configuration bit information; the use of the PUF generation array to calculate based on the acquired configuration bit information to obtain the key includes: using the PUF generation array to calculate based on the first configuration bit information to obtain a first result; processing the first result based on the second configuration bit information to obtain the key.

[0014] For example, in the key sharing method provided by at least one embodiment of the present disclosure, the memristor array includes 2n columns, each two columns form a group, the source line ends of the two columns in each group are respectively connected to the first input end and the second input end of the comparator, the second configuration bit information includes n bits, the key includes n bits, and n is a positive integer;

[0015] The bits of the second configuration bit information that are the first logic value indicate that the values ​​of the key and the first result at the corresponding bits are different, the bits of the second configuration bit information that are the second logic value indicate that the values ​​of the key and the first result at the corresponding bits are the same, and the first logic value is opposite to the second logic value;

[0016] The using the PUF generation array to calculate the first result based on the first configuration bit information includes: using the first configuration bit information as a row control signal input of the PUF generation array, applying a read voltage to a bit line terminal of the PUF generation array to perform calculation; and each group of corresponding comparators compares a read current at the first input terminal with a read current at the second input terminal and outputs a comparison result, thereby obtaining an n-bit output result; and

[0017] The processing of the first result based on the second configuration bit information to obtain the key includes: determining whether to perform a negation operation on the n-bit output result bit by bit based on the value of each bit in the second configuration bit information to obtain the key.

[0018] For example, in the key sharing method provided by at least one embodiment of the present disclosure, the PUF generation array also includes a two-to-one switch connected to the output end of each group of corresponding comparators, and the first output end of the two-to-one switch directly outputs, and the second output end of the two-to-one switch includes an inverter to invert the input signal and then output it; based on the value of each bit in the second configuration bit information, determining whether to perform an inversion operation on the n-bit output result bit by bit includes: based on the value of each bit in the second configuration bit information as the control signal of the two-to-one switch of the corresponding bit, determining whether to output directly or after inversion.

[0019] At least one embodiment of the present disclosure provides a key sharing device, comprising: an initialization unit, configured to obtain a key by random initialization; a PUF generation array, comprising a memristor array; a control device, configured to use the PUF generation array that shares a PUF value with a receiving end to calculate at least part of configuration bit information for the receiving end based on the key, or to obtain the configuration bit information by random initialization, and use the PUF generation array to calculate the key for the receiving end based on the configuration bit information, wherein the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication-addition calculation; and an output device, configured to provide the configuration bit information to the receiving end.

[0020] At least one embodiment of the present disclosure provides a key sharing device, comprising: a receiving unit, configured to obtain configuration bit information provided by a transmitting end, wherein at least part of the configuration bit information or the key is calculated based on a PUF generation array of a PUF value shared by the receiving end and the transmitting end; a PUF generation array, comprising a memristor array; and a control device, configured to use the PUF generation array to calculate the key based on the obtained configuration bit information, wherein the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication-addition calculation.

[0021] For example, in the key sharing device provided in at least one embodiment of the present disclosure, the memristor array includes a plurality of memristor units, and the plurality of memristor units are arranged into a plurality of memristor unit rows and a plurality of memristor unit columns along a first direction and a second direction, with each two columns forming a group, and each of the memristor units includes a memristor element and a switch element, and the first end of the memristor element is electrically connected to the first end of the switch element; the PUF generation array also includes: a plurality of comparators, and the first input end and the second input end of each of the plurality of comparators are respectively connected to the source line ends of the two columns in each group of the memristor array; a plurality of two-to-one switches, and each of the plurality of two-to-one switches is connected to the output end of the comparator corresponding to each group of the memristor array, and the first output end of the two-to-one switch is directly output, and the second output end of the two-to-one switch includes an inverter to invert the input signal and then output it.

[0022] For example, in the key sharing device provided in at least one embodiment of the present disclosure, the configuration bit information includes first configuration bit information and second configuration bit information; the control device is further configured to use the first configuration bit information to control which computing units in the PUF generation array participate in the key calculation, and provide the second configuration bit information to the control ends of the multiple two-to-one switches respectively to control whether the multiple two-to-one switches output directly or output after inversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1 A schematic flow chart of a key sharing method provided for at least one embodiment of the present disclosure;

[0025] Figure 2A A schematic diagram of a PUF generation array provided for at least one embodiment of the present disclosure;

[0026] Figure 2B A schematic diagram of a memristor array provided for at least one embodiment of the present disclosure;

[0027] Figure 3 A schematic flow chart of a key sharing method provided for at least one embodiment of the present disclosure;

[0028] Figure 4 A schematic flow chart of a key sharing method provided for at least one embodiment of the present disclosure;

[0029] Figure 5 A schematic flow chart of a key sharing method provided for at least one embodiment of the present disclosure;

[0030] Figure 6 A schematic block diagram of a key sharing device provided for at least one embodiment of the present disclosure; and

[0031] Figure 7 A schematic block diagram of a key sharing device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] The inventors of the present disclosure have noticed that the source of random entropy in an existing key sharing scheme based on a ring oscillator PUF circuit is the different delays of the inverters. PUF is generated by connecting inverters in series to form delay paths with different delays, and the configuration bits are used to control which inverter is placed on the delay path, thereby controlling the output result, i.e., the key. However, in the ring oscillator PUF circuit, it is impossible to accurately measure the specific delay of each delay node, and a machine learning method is required to convert the PUF into the configuration bits of the key, which results in low overall reliability.

[0036] At least in order to overcome the above-mentioned technical problems, at least one embodiment of the present disclosure provides a key sharing method, which is used, for example, at a key sending end, including: randomly initializing to obtain a key, using a PUF generation array that shares a PUF value with a receiving end to calculate at least part of the configuration bit information for the receiving end based on the key, or randomly initializing to obtain the configuration bit information, using the PUF generation array to calculate the key for the receiving end based on the configuration bit information; providing the configuration bit information to the receiving end so that the receiving end uses the PUF generation array to generate the key based on the configuration bit information, wherein the PUF generation array includes a memristor array, the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication and addition calculation.

[0037] In addition, at least in order to overcome the above-mentioned technical problems, at least another embodiment of the present disclosure also provides a key sharing method, which is used, for example, at a key receiving end, and includes: obtaining configuration bit information provided by a transmitting end, wherein at least part of the configuration bit information or the key is calculated based on a PUF generation array that shares a PUF value with the transmitting end; and obtaining the key by calculating based on the obtained configuration bit information using the PUF generation array, wherein the PUF generation array includes a memristor array, and the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication and addition calculation.

[0038] The key sharing method provided in the above-mentioned embodiment of the present disclosure is implemented based on a memristor array, and uses a key to calculate configuration bit information or uses configuration bit information to calculate a key, which effectively ensures the reliability and security of information transmission between a key sending end and a key receiving end.

[0039] The memristor array includes multiple rows and columns of computing units, each computing unit includes a memristor unit, and the memristor unit can be a 1T1R structure or a 2T2R structure, wherein the memristor unit of the 1T1R structure includes a switch element and a memristor element, and the first end of the memristor element is electrically connected to the first end of the switch element (such as the drain of the transistor), and the memristor unit of the 2T2R structure includes two switch elements and two memristor elements. The present disclosure has no restrictions on the type, structure, etc. of the memristor element. The memristor element used in the embodiments of the present disclosure can be, for example, a resistive memory, a phase change memory, a conductive bridge memory, or other memristor elements with the same characteristics. The switch element used in the embodiments of the present disclosure can be, for example, a thin film transistor, a field effect transistor, or other switch elements with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain thereof can be indistinguishable in structure.

[0040] A memristor element is a non-volatile device whose conductance state can be adjusted by applying external stimuli. As a two-terminal device, a memristor element has the characteristics of adjustable resistance and non-volatility, so it is widely used in storage and computing. Memristor elements can perform operations directly in the analog domain. For example, memristor elements can complete multiplication operations based on Ohm's law and addition operations based on Kirchhoff's current law. For example, according to Kirchhoff's law, by setting the state of the memristor element (for example, resistance value) and applying corresponding word line signals and bit line signals to the word line and bit line, the above-mentioned memristor array can complete multiplication and accumulation calculations in parallel, and storage and calculation occur in each element of the array.

[0041] The key sharing method provided according to the present disclosure is described below in a non-restrictive manner through multiple embodiments and examples thereof. As described below, different features in these specific examples or embodiments can be combined with each other without conflicting with each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0042] For ease of description, the following description will focus on the key sending end side, as follows.

[0043] Figure 1 A schematic flowchart of a key sharing method provided for at least one embodiment of the present disclosure.

[0044] like Figure 1As shown, at least one embodiment of the present disclosure provides a key sharing method, for example, for a key sending end. For example, in the embodiments of the present disclosure, the key sharing method can be applied to any application scenario requiring key sharing, for example, it can be applied to the field of network security, the field of digital copyright management, the field of identity authentication, distributed systems, etc., and can also be applied to other aspects, which are not limited by the embodiments of the present disclosure.

[0045] like Figure 1 As shown, the key sharing method provided by the embodiment of the present disclosure includes the following steps S101 to S102.

[0046] Step S101: randomly initialize to obtain a key, use a PUF generation array that shares a PUF value with the receiving end to calculate at least part of the configuration bit information for the receiving end based on the key, or randomly initialize to obtain configuration bit information, and use the PUF generation array to calculate the key for the receiving end based on the configuration bit information.

[0047] For example, the PUF generation array includes a memristor array, the configuration bit information includes information for controlling which computing units in the PUF generation array participate in key calculation, and the calculation includes multiplication and accumulation calculation.

[0048] For example, sharing a PUF value means that different receiving ends can use their own PUF generation arrays to generate different PUF values, and then provide the PUF value to the sending end. For example, the receiving end can provide its own PUF value to a trusted third party, and then the third party provides its stored PUF value to the sending end according to pre-set rules; for a certain receiving end, the sending end uses the PUF value of the receiving end to set one of its own PUF generation arrays, that is, writes the PUF value into the PUF generation array, which is equivalent to copying the PUF generation array of a receiving end.

[0049] For example, writing a PUF value into a PUF generation array can be achieved by performing set and reset operations on the memristor units that make up the memristor array. For example, the set operation can be to add a positive voltage pulse to the bit line and ground the source line, which can make the resistance value of the memristor unit lower; the reset operation can be to add a positive voltage pulse to the source line and ground the bit line, which can make the resistance value of the memristor unit higher. A set operation or a reset operation can be used as a write operation.

[0050] For example, the operation of reading the PUF value from the PUF generation array may be: applying a read voltage to the memristor unit, obtaining the current value output by the memristor unit under the action of the read voltage, and determining the current PUF value of the memristor unit according to the current value and the read voltage. For example, a read voltage may be applied to the source line, so that the PUF value of the memristor unit may be determined according to the current value output by the bit line using Ohm's law.

[0051] After the memristor unit is produced, it needs to be initialized. For example, the initialization operation can be to apply a higher voltage to the memristor unit, that is, to apply a positive voltage pulse on the bit line, and to ground the source line at the same time, and the amplitude and time of the positive voltage pulse are higher than the set operation. This operation will cause the resistance value of the memristor unit to change, so that it has an initial resistance value. Since the resistance value of the memristor unit is random, even under the same initialization conditions, the resistance value of each memristor unit will be different. In this example, the resistance value of each memristor unit can be regarded as the PUF value of the memristor unit. This PUF value is an analog quantity and is roughly normally distributed within a range.

[0052] For example, the transmitting end may be randomly initialized to obtain a key and part of the configuration bit information, and use the PUF generation array to calculate based on the key to obtain another part of the configuration bit information for the receiving end. Alternatively, the transmitting end may also be randomly initialized to obtain all the configuration bit information, and use the PUF generation array to calculate based on the configuration bit information to obtain the key for the receiving end. For example, random initialization to obtain the key or configuration bit information may be achieved by a pseudo-random number generator or a true random number generator, and the present disclosure does not limit this.

[0053] Step S102: providing the configuration bit information to the receiving end, so that the receiving end generates a key based on the configuration bit information using the PUF generation array.

[0054] For example, the sending end can send configuration bit information to the receiving end through a network protocol. When sending the configuration bit information, the configuration bit information can be encoded into a specific data format or encrypted into ciphertext form for transmission. When the receiving end receives the data, it needs to decode or decrypt it to restore the original configuration bit information. The present disclosure is not limited to the above method.

[0055] Figure 2A A schematic diagram of a PUF generation array provided in accordance with at least one embodiment of the present disclosure.

[0056] like Figure 2A As shown, the PUF generation array 100 includes a memristor array 101 , a plurality of comparators 102 , and a plurality of two-to-one switches 103 .

[0057] Figure 2B At least one embodiment of the present disclosure provides a method for Figure 2A Schematic diagram of the memristor array of the PUF generation array shown.

[0058] For example, Figure 2BAs shown, the memristor array 101 includes a plurality of memristor units 1011, and the plurality of memristor units 1011 are arranged into a plurality of memristor unit rows and a plurality of memristor unit columns along a first direction and a second direction, respectively, for example, constituting a memristor array 101 with m rows and 2n columns, where m and n are both positive integers (for example, greater than 2). Figure 2A In the illustrated case, every two columns in the memristor array form a group. Although the two columns in each group are shown as being arranged adjacently in the figure, in other examples, the two columns in each group may be arranged non-adjacently.

[0059] For example, in this example, each memristor unit 1011 in the memristor array 101 is a 1T1R structure, including a memristor element and a switch element.

[0060] like Figure 2B As shown, WL0, WL1...WLm-1 represent the word lines of the first row, the second row...the mth row, respectively, and the control end (e.g., the gate of the transistor) of the switch element in each row of the memristor unit is connected to the word line corresponding to the row; BL0, BL1...BL2n-1 represent the bit lines of the first row, the second row...the 2nth column, respectively, and the second end of the memristor element in the memristor unit of each column is connected to the bit line corresponding to the column; SL0, SL1...SL2n-1 represent the source lines of the first column, the second column...the 2nth column, respectively, and the second end (e.g., the source of the transistor) of the switch element in each column of the memristor unit is connected to the source line corresponding to the column. In this article, m, n, i, j, etc. represent positive integers, which will not be repeated later.

[0061] For example, in Figure 2A In at least one embodiment of the present disclosure shown, the first input terminal and the second input terminal of each of the plurality of comparators 102 are respectively connected to the source line terminals of two columns in each group of the memristor array 101 .

[0062] For example, in Figure 2A In at least one embodiment of the present disclosure shown, each of the multiple two-to-one switches 103 is connected to the output end of each corresponding comparator 102 of the memristor array 101, and the first output end of the two-to-one switch 103 is directly output, and the second output end of the two-to-one switch 103 includes an inverter to invert the input signal and then output it.

[0063] Figure 3 A schematic flow chart of a key sharing method provided for at least one embodiment of the present disclosure. Figure 3 , Figure 2A and Figure 2B , specifically describe the execution process of steps S201-S205.

[0064] Step S201: receiving a PUF value for sharing in a PUF generation array from a receiving end, wherein the PUF value includes a value for each PUF unit in the PUF generation array.

[0065] For example, the PUF value for sharing of the PUF generation array may be received from the receiving end through a network protocol, and the present disclosure is not limited in this regard.

[0066] Step S202: Randomly initialize to obtain a key.

[0067] like Figure 2B As shown, the memristor array in the PUF generation array includes 2n columns, each two columns form a group, and the key is an n-bit random 0 / 1 sequence, which corresponds to each group of the memristor array one by one, and is recorded as Key[0] to Key[n-1]. For example, the key can be obtained by random initialization through a pseudo-random number generator or a true random number generator, and the present disclosure does not limit this.

[0068] Step S203: randomly generate first configuration bit information, wherein the first configuration bit information is configured to control which computing units in the PUF generation array participate in key calculation.

[0069] like Figure 2B As shown, the memristor array in the PUF generation array includes m rows, and the first configuration bit information is an m-bit random 0 / 1 sequence, which corresponds to each row of the memristor array one by one, denoted as C[0]~C[m-1], and is used to control whether the corresponding row of the memristor array is turned on. For example, when C[i]=1, the i-th row of the memristor array is controlled to be turned on, so that the i-th row participates in the key calculation; when C[i]=0, the i-th row of the memristor array is controlled to be turned off, so that the i-th row does not participate in the key calculation; or, when C[i]=0, the i-th row of the memristor array is controlled to be turned on, so that the i-th row participates in the key calculation; when C[i]=1, the i-th row of the memristor array is controlled to be turned off, so that the i-th row participates in the key calculation. The present disclosure is not limited to this.

[0070] Step S204: using the PUF generation array to calculate second configuration bit information based on the first configuration bit information and the key, wherein the second configuration bit information is configured to indicate a difference between a first result calculated using the PUF generation array based on the first configuration bit information and the key.

[0071] For example, Figure 2B As shown, the memristor array in the PUF generation array includes 2n columns, each two columns form a group, and the second configuration bit information includes n bits, which correspond one-to-one to each group of the memristor array, recorded as CS[0]~CS[n-1].

[0072] For example, step S204 may include step S2041 and step S2042.

[0073] Step S2041: using the PUF generation array to calculate and obtain a first result based on the first configuration bit information.

[0074] For example, Figure 2A As shown, the first configuration bit information C[0]~C[m-1] is used as the row control signal input of the PUF generation array, and the read voltage Vread is applied to the bit line end of the PUF generation array for calculation; each group of corresponding comparators compares the read current I[0]~I[n-1] at the first input end and the read current I[0]'~I[n-1]' at the second input end and outputs the comparison result, thereby obtaining the n-bit output result R[0]~R[n-1].

[0075] For example, the first configuration bit information C[0]~C[m-1] is in the form of high and low levels, which can be generated by a driving circuit or by other circuit structures, and the present disclosure does not limit this. Taking C[i]=1 representing that the i-th row of the memristor array is turned on, and C[i]=0 representing that the i-th row of the memristor array is turned off as an example, the first input terminal and the second input terminal of the comparator are respectively connected to the left column and the right column of each group, then the comparator actually compares the sum of the resistances of all rows with C[i]=1 in the left column and the right column of each group, that is, when the sum of the resistances of the left column connected to the comparator is less than the sum of the resistances of the right column, the output result is 1, otherwise the output result is 0.

[0076] Step S2042: Compare the first result with the key to obtain second configuration bit information.

[0077] For example, the n-bit output results R[0]~R[n-1] are compared bit by bit with the keys Key[0]~Key[n-1] to obtain the second configuration bit information, wherein the bits with the first logic value in the second configuration bit information indicate that the values ​​of the key and the first result at the corresponding bits are different, and the bits with the second logic value in the second configuration bit information indicate that the values ​​of the key and the first result at the corresponding bits are the same, and the first logic value is opposite to the second logic value, for example, when the first logic value is 0, the second logic value is 1, and vice versa, when the first logic value is 1, the second logic value is 0.

[0078] For example, when CS[j]=0, it means Key[j]=R[j], and when CS[j]=1, it means Key[j]≠R[j]; or, when CS[j]=1, it means Key[j]=R[j], and when CS[j]=0, it means Key[j]≠R[j]. The present disclosure does not limit this.

[0079] Step S205: providing the configuration bit information to the receiving end, so that the receiving end generates a key using the PUF generation array based on the configuration bit information.

[0080] For example, the configuration bit information includes first configuration bit information and second configuration bit information. The specific implementation process of step S205 may be the same as the aforementioned step S102. The explanation of step S205 may refer to the explanation of step S102, which will not be repeated here.

[0081] For ease of description, the following description will focus on the receiving end side, as follows.

[0082] Figure 4 A schematic flowchart of a key sharing method provided for at least one embodiment of the present disclosure.

[0083] like Figure 4 As shown, at least one embodiment of the present disclosure provides a key sharing method. For example, in the embodiments of the present disclosure, the key sharing method can be applied to any application scenario requiring key sharing, for example, it can be applied to the field of network security, the field of digital rights management, the field of identity authentication, distributed systems, etc., and can also be applied to other aspects, which are not limited by the embodiments of the present disclosure.

[0084] like Figure 4 As shown, the key sharing method provided by the embodiment of the present disclosure may include the following steps S301 to S302.

[0085] Step S301: Acquire configuration bit information provided by a transmitting end, wherein at least part of the configuration bit information or a key is calculated based on a PUF generation array that shares a PUF value with the transmitting end.

[0086] For example, the PUF generation array includes a memristor array, and the configuration bit information includes information for controlling which computing units in the PUF generation array participate in the key calculation, and the calculation includes a multiplication and addition calculation. For example, the transmitting end can send the configuration bit information to the receiving end through a network protocol. When sending the configuration bit information, the configuration bit information can be encoded into a specific data format or encrypted into a ciphertext form for transmission. When the receiving end receives the data, it needs to decode or decrypt it to restore the original configuration bit information. The present disclosure is not limited to the above method.

[0087] For the description of the shared PUF value, the PUF generation array, the memristor array, etc., please refer to the description of the transmitting end side under step S101, which will not be repeated here.

[0088] Step S302: Calculate a key using the PUF generation array based on the acquired configuration bit information.

[0089] For example, different receiving ends use the configuration bit information they receive (for example, dedicated to the receiving end) to generate the keys they need. During the entire communication process, the only information that appears on the channel is the configuration bit information, and the key has never left the security domain. Therefore, even if an eavesdropper successfully intercepts the configuration bit, it cannot extract the key from it, which effectively ensures the security of key sharing.

[0090] Figure 5 A schematic flow chart of a key sharing method provided for at least one embodiment of the present disclosure. Figure 5 , Figure 2A and Figure 2B , specifically describe the execution process of steps S401-S404.

[0091] Step S401: Initialize the PUF generation array to obtain a PUF value for sharing, and provide the PUF value to the transmitting end.

[0092] The description of the initialization operation can be found in the description of step S101, which will not be repeated here.

[0093] Step S402: Acquire configuration bit information provided by the transmitting end, wherein at least part of the configuration bit information or the key is calculated based on a PUF generation array that shares a PUF value with the transmitting end.

[0094] For example, the configuration bit information includes first configuration bit information and second configuration bit information. The specific implementation process of step S402 may be the same as the aforementioned step S301. The explanation of step S402 may refer to the explanation of step S301, and will not be repeated here.

[0095] Step S403: using the PUF generation array to calculate and obtain a first result based on the first configuration bit information.

[0096] For example, Figure 2A As shown, the first configuration bit information C[0]~C[m-1] is used as the row control signal input of the PUF generation array, and the read voltage Vread is applied to the bit line end of the PUF generation array for calculation; each group of corresponding comparators compares the read current I[0]~I[n-1] at the first input end and the read current I[0]'~I[n-1]' at the second input end and outputs the comparison result, thereby obtaining the n-bit output result R[0]~R[n-1].

[0097] For example, the first configuration bit information C[0]~C[m-1] can be in the form of high or low levels, can be generated by a driver, or can be generated by other circuit structures, and the present disclosure does not limit this. Taking C[i]=1 representing that the i-th row of the memristor array is turned on, and C[i]=0 representing that the i-th row of the memristor array is turned off as an example, the first input terminal and the second input terminal of the comparator are respectively connected to the left column and the right column of each group, then the comparator actually compares the sum of the resistances of the rows with C[i]=1 in the left column and the right column of each group, that is, when the sum of the resistances of the left column connected to the comparator is less than the sum of the resistances of the right column, the output result is 1, otherwise the output result is 0.

[0098] Step S404: Process the first result based on the second configuration bit information to obtain a key.

[0099] For example, Figure 2B As shown, the memristor array in the PUF generation array includes 2n columns, with each two columns forming a group. The second configuration bit information includes n bits, corresponding one-to-one to each group of the memristor array, denoted as CS[0] to CS[n-1]. The key includes n bits, corresponding one-to-one to each group of the memristor array, denoted as Key[0] to Key[n-1].

[0100] For example, in step S404, based on the value of each bit in the second configuration bit information CS[0] to CS[n-1], determine whether to perform an inversion operation on the n-bit output result bit by bit to obtain the key. For example, a bit with a first logic value in the second configuration bit information indicates that the key and the first result have different values ​​at the corresponding bit, and a bit with a second logic value in the second configuration bit information indicates that the key and the first result have the same value at the corresponding bit, and the first logic value is opposite to the second logic value.

[0101] For example, when CS[j]=0, it means that the output result R[j] does not need to be inverted, and when CS[j]=1, it means that the output result R[j] needs to be inverted; or, when CS[j]=1, it means that the output result R[j] needs to be inverted, and when CS[j]=0, it means that the output result R[j] does not need to be inverted, and the present disclosure does not impose any restrictions on this.

[0102] For example, the above steps can be implemented based on a two-choice switch. Figure 2A As shown, the PUF generation array also includes a two-to-one switch connected to the output end of each group of corresponding comparators, and the first output end of the two-to-one switch is directly output, and the second output end of the two-to-one switch includes an inverter to invert the input signal before outputting.

[0103] For example, in step S404, based on the value of each bit in the second configuration bit information CS[0] to CS[n-1] as the control signal of the two-choice switch of the corresponding bit, it is determined whether to output directly or output after inversion. For example, when CS[j]=0, the two-choice switch corresponding to the j+1th group is controlled to output directly, and when CS[j]=1, the two-choice switch corresponding to the j+1th group is controlled to output after inversion; or, when CS[j]=0, the two-choice switch corresponding to the j+1th group is controlled to output after inversion, and when CS[j]=1, the two-choice switch corresponding to the j+1th group is controlled to output directly, and the present disclosure does not limit this.

[0104] Accordingly, at least one embodiment of the present disclosure further provides a key sharing device corresponding to the key sharing method described above. The specific implementation method thereof can refer to the relevant description of the key sharing method described above, which will not be repeated here.

[0105] For ease of description, the following description will focus on the sending end side, as follows.

[0106] Figure 6 A schematic block diagram of a key sharing device provided by at least one embodiment of the present disclosure. Figure 6 As shown, the key sharing device 600 includes an initialization unit 601, a PUF generation array 602, a control device 603 and an output device 604.

[0107] For example, in at least one embodiment of the present disclosure, the initialization unit 601 is configured to obtain a key by random initialization. For example, the initialization unit 601 can be implemented by a digital circuit.

[0108] For example, in at least one embodiment of the present disclosure, the PUF generation array 602 includes a memristor array, which can be seen in Figure 2B The examples shown are not repeated here.

[0109] For example, in at least one embodiment of the present disclosure, the control device 603 is configured to use a PUF generation array that shares a PUF value with the receiving end to calculate at least part of the configuration bit information for the receiving end based on the above-mentioned key, or to randomly initialize the configuration bit information and use the PUF generation array to calculate the key for the receiving end based on the configuration bit information.

[0110] For example, in at least one embodiment of the present disclosure, the control device 603 is further configured to use the first configuration bit information to control which computing units in the PUF generation array participate in the key calculation, and provide the second configuration bit information to the control ends of multiple two-to-one switches to control whether the multiple two-to-one switches output directly or output after inversion.

[0111] For example, in at least one embodiment of the present disclosure, the output device 604 is configured to provide the configuration bit information to the receiving end.

[0112] For example, the configuration bit information includes information for controlling which computing units in the PUF generation array participate in key calculation, where the calculation includes multiplication-addition calculation.

[0113] For ease of description, the following description will focus on the receiving end side, as follows.

[0114] Figure 7 A schematic block diagram of a key sharing device provided by at least one embodiment of the present disclosure. Figure 7 As shown, the key sharing device 700 includes a receiving unit 701, a PUF generation array 702 and a control device 703.

[0115] For example, in at least one embodiment of the present disclosure, the receiving unit 701 is configured to obtain configuration bit information provided by the transmitting end, wherein at least part of the configuration bit information or the key is calculated based on the PUF generation array of the PUF value shared by the receiving end and the transmitting end.

[0116] For example, in at least one embodiment of the present disclosure, the PUF generation array 702 includes a memristor array.

[0117] For example, in at least one embodiment of the present disclosure, the control device 703 is configured to use the PUF generation array to calculate and obtain a key based on the acquired configuration bit information.

[0118] For example, the configuration bit information includes information for controlling which computing units in the PUF generation array participate in key calculation, where the calculation includes multiplication-addition calculation.

[0119] It should be noted that the PUF generation array 602 on the transmitting end side and the PUF generation array 702 on the receiving end side may be the same, and their specific structures and connection methods may refer to Figure 2A The PUF generation array 100 in FIG. 1 is not described in detail here.

[0120] One or more embodiments of the present disclosure provide a key sharing method and a key sharing device corresponding to the method. In at least one embodiment, the key sharing method and the key sharing device have one or more of the following beneficial effects:

[0121] (1) The key sharing method provided in at least one embodiment of the present disclosure is implemented based on a memristor array, and uses a key to calculate configuration bit information or uses configuration bit information to calculate a key, which effectively ensures the reliability and security of information transmission between a key sending end and a key receiving end.

[0122] (2) The key sharing method provided by at least one embodiment of the present disclosure is based on a memristor array, has a simple circuit structure, and is easy to implement.

[0123] (3) The key sharing method provided by at least one embodiment of the present disclosure can generate multiple keys by applying a single stimulus, and the key generation speed is fast.

[0124] (4) The key sharing method provided by at least one embodiment of the present disclosure is reconfigurable, that is, by changing some randomly generated configuration bits, multiple keys can be shared, thereby ensuring security.

[0125] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0126] There are a few points to note about this disclosure:

[0127] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0128] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0129] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0130] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A key sharing method, comprising: A key is obtained by random initialization, and at least part of the configuration bit information for the receiving end is calculated based on the key using a physical unclonable function generation array that shares a physical unclonable function value with the receiving end, or the configuration bit information is obtained by random initialization, and the key for the receiving end is calculated based on the configuration bit information using the physical unclonable function generation array; as well as providing the configuration bit information to the receiving end, so that the receiving end generates the key using the physical unclonable function generation array based on the configuration bit information, The physical unclonable function generation array includes a memristor array, the configuration bit information includes information for controlling which computing units in the physical unclonable function generation array participate in key calculation, and the calculation includes multiplication and accumulation calculation.

2. The key sharing method according to claim 1, further comprising: A physical unclonable function value for sharing in the physical unclonable function generation array is received from the receiving end, wherein the physical unclonable function value includes a value for each physical unclonable function unit in the physical unclonable function generation array.

3. The key sharing method according to claim 1, wherein: The configuration bit information includes first configuration bit information and second configuration bit information; The method of using a physical unclonable function generation array that shares a physical unclonable function value with a receiving end to calculate and obtain at least part of the configuration bit information for the receiving end based on the key comprises: Randomly generate the first configuration bit information, wherein the first configuration bit information is configured to control which computing units in the physical unclonable function generation array participate in key calculation; The second configuration bit information is calculated based on the first configuration bit information and the key using the physical unclonable function generation array, wherein the second configuration bit information is configured to indicate a difference between a first result calculated based on the first configuration bit information using the physical unclonable function generation array and the key.

4. The key sharing method according to claim 3, wherein: The using the physical unclonable function to generate an array to obtain second configuration bit information based on the first configuration bit information and the key calculation includes: Using the physical unclonable function generation array to calculate a first result based on the first configuration bit information; The first result is compared with the key to obtain the second configuration bit information.

5. The key sharing method according to claim 4, wherein: The memristor array includes 2n columns, each two columns form a group, the source line ends of the two columns in each group are respectively connected to the first input end and the second input end of the comparator, the second configuration bit information includes n bits, the key includes n bits, and n is a positive integer; The using the physical unclonable function to generate an array to calculate and obtain the first result based on the first configuration bit information includes: Using the first configuration bit information as a row control signal input of the physical unclonable function generation array, applying a read voltage to a bit line terminal of the physical unclonable function generation array to perform calculation; and Each group of corresponding comparators compares the read current at the first input terminal and the read current at the second input terminal and outputs a comparison result, thereby obtaining an n-bit output result; and comparing the first result with the key to obtain the second configuration bit information, including: The n-bit output result is compared bit by bit with the key to obtain the second configuration bit information, wherein the bits with the first logic value in the second configuration bit information indicate that the values ​​of the key and the first result at the corresponding bits are different, the bits with the second logic value in the second configuration bit information indicate that the values ​​of the key and the first result at the corresponding bits are the same, and the first logic value is opposite to the second logic value.

6. A key sharing method, comprising: Acquire configuration bit information provided by a transmitting end, wherein at least part of the configuration bit information or a key is calculated based on a physical unclonable function generation array that shares a physical unclonable function value with the transmitting end; The physical unclonable function generation array is used to calculate the key based on the acquired configuration bit information, The physical unclonable function generation array includes a memristor array, the configuration bit information includes information for controlling which computing units in the physical unclonable function generation array participate in key calculation, and the calculation includes multiplication and accumulation calculation.

7. The key sharing method according to claim 6, further comprising: The physical unclonable function generation array is initialized to obtain a physical unclonable function value for sharing, and the physical unclonable function value is provided to the sending end.

8. The key sharing method according to claim 6, wherein: The configuration bit information includes first configuration bit information and second configuration bit information; The using the physical unclonable function to generate an array to calculate the key based on the acquired configuration bit information includes: Using the physical unclonable function generation array to calculate a first result based on the first configuration bit information; The first result is processed based on the second configuration bit information to obtain the key.

9. The key sharing method according to claim 8, wherein: The memristor array includes 2n columns, each two columns form a group, the source line ends of the two columns in each group are respectively connected to the first input end and the second input end of the comparator, the second configuration bit information includes n bits, the key includes n bits, and n is a positive integer; The bits of the second configuration bit information that are the first logic value indicate that the values ​​of the key and the first result at the corresponding bits are different, the bits of the second configuration bit information that are the second logic value indicate that the values ​​of the key and the first result at the corresponding bits are the same, and the first logic value is opposite to the second logic value; The using the physical unclonable function to generate an array to calculate a first result based on the first configuration bit information includes: Using the first configuration bit information as a row control signal input of the physical unclonable function generation array, applying a read voltage to a bit line terminal of the physical unclonable function generation array to perform calculation; and Each group of corresponding comparators compares the read current at the first input terminal and the read current at the second input terminal and outputs a comparison result, thereby obtaining an n-bit output result; and processing the first result based on the second configuration bit information to obtain the key, comprising: Based on the value of each bit in the second configuration bit information, determine whether to perform a negation operation on the n-bit output result bit by bit to obtain the key.

10. The key sharing method according to claim 9, wherein: The physical unclonable function generation array further includes a two-to-one switch connected to the output end of each group of corresponding comparators, and the first output end of the two-to-one switch directly outputs, and the second output end of the two-to-one switch includes an inverter to invert the input signal and then output; The determining whether to perform a negation operation on the n-bit output result bit by bit based on the value of each bit in the second configuration bit information includes: Based on the value of each bit in the second configuration bit information as the control signal of the two-choice switch of the corresponding bit, it is determined whether to output directly or after inversion.

11. A key sharing device, comprising: An initialization unit, configured to obtain a key by random initialization; Physical unclonable function generation arrays, including memristor arrays; The control device is configured to use the physical unclonable function generation array that shares the physical unclonable function value with the receiving end to calculate at least part of the configuration bit information for the receiving end based on the key, or randomly initialize to obtain the configuration bit information, and use the physical unclonable function generation array to calculate the key for the receiving end based on the configuration bit information, wherein the configuration bit information includes information for controlling which computing units in the physical unclonable function generation array participate in the key calculation, and the calculation includes a multiplication-addition calculation; as well as The output device is configured to provide the configuration bit information to the receiving end.

12. A key sharing device, comprising: A receiving unit is configured to obtain configuration bit information provided by a sending end, wherein at least part of the configuration bit information or a key is calculated based on a physical unclonable function generation array whose physical unclonable function value is shared between the receiving end and the sending end; Physical unclonable function generation arrays, including memristor arrays; and A control device is configured to use the physical unclonable function generation array to calculate the key based on the obtained configuration bit information, wherein the configuration bit information includes information for controlling which computing units in the physical unclonable function generation array participate in the key calculation, and the calculation includes a multiplication and addition calculation.

13. The key sharing device according to claim 11 or 12, wherein: The memristor array comprises a plurality of memristor units, the plurality of memristor units are arranged into a plurality of memristor unit rows and a plurality of memristor unit columns along a first direction and a second direction, and each two columns form a group, each of the memristor units comprises a memristor element and a switch element, and a first end of the memristor element is electrically connected to a first end of the switch element; The physical unclonable function generation array further includes: A plurality of comparators, wherein a first input terminal and a second input terminal of each of the plurality of comparators are respectively connected to source line terminals of two columns in each group of the memristor array; A plurality of two-to-one switches, each of the plurality of two-to-one switches is connected to the output end of each corresponding comparator of the memristor array, and the first output end of the two-to-one switch is directly output, and the second output end of the two-to-one switch includes an inverter to invert the input signal and then output it.

14. The key sharing device according to claim 13, wherein: The configuration bit information includes first configuration bit information and second configuration bit information; The control device is further configured to use the first configuration bit information to control which computing units in the physical unclonable function generation array participate in key calculation, and provide the second configuration bit information to the control ends of the multiple two-to-one switches to control whether the multiple two-to-one switches output directly or output after inversion.

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