Quantization-based pure simulation adaptive real time delay alignment device

Abstract

The invention discloses a pure simulation self-adaptive real time delay alignment device based on quantization, and belongs to the technical field of communication. The device comprises a first amplitude normalization quantization module, a second amplitude normalization quantization module, a time delay module, a time delay statistics module and a time delay control voltage generation module. The time delay statistics module is used for integrating the time delay difference of the two paths of input signals, and representing the time delay amount of the two paths of input signals by a voltage value; the time delay control voltage generation module generates a discrete time delay control voltage coding signal according to the time delay statistical voltage signal and feeds back the discrete time delay control voltage coding signal to a discrete adjustable delayer of the time delay module, so as to roughly adjust the time delay of the first signal; and meanwhile, a continuous time delay control voltage signal is generated and fed back to a continuous adjustable delayer of the time delay module to carry out time delay fine adjustment on the first signal so as to realize time delay alignment. The device is simple in structure and low in complexity, has adaptive capacity, and can be suitable for time delay alignment of various signals.

Description

Technical Field

[0001] The invention belongs to the field of communication technology, and in particular relates to a pure analog adaptive real delay alignment device based on quantization. Background Art

[0002] In wireless communication systems, there will be a time delay after the signal passes through the circuit system, resulting in a non-periodic integer multiple offset of the signal in the time domain. For example, in actual situations, when the power amplifier performs digital pre-distortion (DPD) processing, it is necessary to collect input and output signals for correlation analysis. However, the time delay difference of the signal will affect the performance and accuracy of DPD, and thus cannot achieve an excellent linearization effect. Therefore, when performing correlation analysis on the input and output signals, the time delay of the signal must be considered. The general solution is to reduce or offset the impact of signal delay through appropriate calibration technology, thereby reducing errors and improving system performance.

[0003] At present, most time delay alignment technologies are implemented through "digital delay alignment", which selects corresponding algorithms or technologies for different signals to adjust the timing of the signal, estimate, adjust or compensate for the time offset of the signal, so that the input and output signals are aligned in time. However, "digital delay alignment" currently has shortcomings such as being restricted by the algorithm, high requirements for overall system stability, and susceptibility to interference, which means that its alignment performance and stability are affected by the algorithm selection and the actual environment. In addition, digital delay alignment requires the use of analog-to-digital converters (ADCs) to down-convert and digitize the signal, which is complex and costly. For high-speed broadband data processing systems, in order to obtain better delay alignment effects, higher complexity and computational overhead will be required, occupying more system resources and processing power, increasing the cost, complexity and power consumption of the system.

[0004] At present, the academic community has carried out a series of research on analog delay alignment technology, and the main implementation methods include delay line, clock delay, signal processor delay, etc. However, these analog delay technologies have problems such as large area and difficulty in integration, high power consumption, and no adaptive delay alignment. Therefore, the current research hotspot is to meet the requirements of high precision, adjustability, high stability and consistency of analog delay alignment, and have adaptive delay alignment that meets a large delay range, low cost, and simple structure. Summary of the invention

[0005] In view of the problems existing in the digital delay alignment and the traditional analog delay alignment technology proposed in the background technology, the present invention provides a pure analog adaptive real delay alignment device based on quantization.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A pure analog adaptive real delay alignment device based on quantization, characterized in that the device is used to perform delay alignment on a first signal and a second signal with a delay; the device includes a first amplitude normalization quantization module, a second amplitude normalization quantization module, a delay module, a delay statistics module, and a delay control voltage generation module.

[0008] The delay module adaptively delays the input first signal according to the continuous delay control voltage signal and the discrete delay control voltage encoding signal generated by the delay control voltage generating module, and inputs the delayed first signal into the first amplitude normalization quantization module; at the same time, the delayed first signal is output as an output signal.

[0009] The first amplitude normalization and quantization module is used to normalize the delayed first signal to obtain a first signal with amplitude normalization and quantization and input it into the delay statistics module.

[0010] The second amplitude normalization and quantization module is used to normalize the second signal to obtain a second signal with amplitude normalization and quantization and input it into the delay statistics module.

[0011] The time delay statistics module is used to perform frequency and phase discrimination on the amplitude normalized and quantized first signal and the second signal to obtain a voltage signal with time delay information of the two signals; integrate the voltage signal to obtain a time delay statistics voltage signal, and input it into the time delay control voltage generation module.

[0012] The delay control voltage generating module is used to generate a continuous delay control voltage signal and a discrete delay control voltage encoding signal according to the delay statistical voltage signal, and input the signals into the delay module.

[0013] Preferably, the delay module includes a continuously adjustable delay device and a discrete adjustable delay device; wherein the discrete adjustable delay device selects delay devices with different delay multiples according to a discrete delay control voltage coding signal to coarsely adjust the delay of the first signal; and the continuously adjustable delay device finely adjusts the delay of the first signal after the coarse delay adjustment according to the continuous delay control voltage signal to achieve the effect of aligning the delay of the first signal with the second signal.

[0014] Preferably, the delay statistics module includes a frequency detector, a charge pump and a capacitor; wherein the frequency detector is used to perform frequency detection and phase detection on the first signal and the second signal with normalized and quantized amplitudes to obtain a voltage signal with delay information of the two signals; the charge pump and the capacitor work together to integrate the voltage signal to obtain a delay statistics voltage signal.

[0015] Preferably, the delay control voltage generating module comprises a continuous delay control voltage calculation circuit and a discrete delay control voltage generating circuit.

[0016] Preferably, the discrete delay control voltage generating circuit includes multiple comparators and logic operation circuits, one of the input signals of each comparator is a delay statistical voltage signal, and the other input signal is a preset delay reference voltage, and the voltage values ​​of the delay reference voltages of all comparators are different. The outputs of all comparators enter the logic operation circuit to obtain a discrete delay control voltage encoding signal.

[0017] Preferably, the first amplitude normalization and quantization module is implemented by a comparator; the delayed first signal and a preset first normalization reference signal are used as inputs of the comparator, and the first amplitude normalization and quantization signal is obtained through the comparator.

[0018] Preferably, the second amplitude normalization quantization module is implemented using a comparator and a follower; the second signal and a preset second normalized reference signal are used as inputs of the comparator, and the signal output by the comparator is buffered by the follower to obtain a second signal of amplitude normalization quantization.

[0019] Beneficial effects of the present invention:

[0020] The present invention utilizes a time delay statistics module to integrate the time delay difference between two input signals, and uses the voltage value of a time delay statistics voltage signal to characterize the time delay of the two input signals; then a time delay control voltage generation module generates a discrete time delay control voltage encoding signal and a continuous time delay control voltage signal according to the time delay statistics voltage signal; the discrete time delay control voltage encoding signal is fed back to a discrete adjustable delay device of the time delay module to perform a coarse adjustment on the time delay of a first signal; meanwhile, the continuous time delay control voltage signal is fed back to a continuously adjustable delay device of the time delay module to perform a fine adjustment on the time delay of the coarsely adjusted first signal, thereby achieving time delay alignment and obtaining a final output signal.

[0021] Compared with digital delay alignment, the present invention has a simple structure, low complexity, and adaptability, and can be applied to delay alignment of various signals, including but not limited to circuit delay alignment of radio frequency power amplifiers, antenna arrays, and radar signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the overall structure of the pure analog adaptive real delay alignment device based on quantization of the present invention.

[0023] Figure 2 It is an overall detailed block diagram of a pure analog delay alignment device according to an embodiment of the present invention.

[0024] Figure 3 These are two delayed radio frequency signals input in the embodiment of the present invention.

[0025] Figure 4 It is a time domain waveform and quantization timing diagram of the normal operation of the normalized quantization module in an embodiment of the present invention.

[0026] Figure 5 This is a waveform diagram generated when the frequency and phase detector in the delay statistics module in the embodiment of the present invention works normally.

[0027] Figure 6 It is a time domain waveform diagram generated by the normal operation of the delay statistics module in an embodiment of the present invention.

[0028] Figure 7 It is the response generated when the delay module in the embodiment of the present invention works normally.

[0029] Figure 8 FIG. 4 is an internal structure of a circuit for discrete delay control voltage in a delay control voltage generating module in an embodiment of the present invention.

[0030] Fig. 9 The figure shows the response of the discrete delay control voltage circuit in the delay control voltage generating module in the embodiment of the present invention to different voltages. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the implementation modes and the accompanying drawings.

[0032] The embodiment of the present invention is a pure analog adaptive real delay alignment device based on quantization, which is used for Figure 3 The first signal V1 and the second signal V2 with time delay are shown to be time-delay aligned.

[0033] like Figure 1 and Figure 2 As shown, the device includes a first amplitude normalization quantization module, a second amplitude normalization quantization module, a delay module, a delay statistics module, and a delay control voltage generation module.

[0034] The delay module includes a discrete adjustable delay device and a continuously adjustable delay device; the discrete adjustable delay device is used to select delay devices with different delay multiples according to a discrete delay control voltage coding signal to coarsely adjust the delay of the first signal; the continuously adjustable delay device finely adjusts the delay of the coarsely adjusted first signal according to the continuous delay control voltage, and inputs the delayed first signal into the first amplitude normalization quantization module; at the same time, the delayed first signal is output as an output signal.

[0035] Specifically, in a discrete adjustable delay device, the input first signal is divided into multiple paths and enters different delay branches. Each delay branch is composed of a different number of delay devices connected in series, that is, different delay branches have different multiples of delay amounts. A discrete delay control voltage coding signal is used to select a delay branch to control the delay amount, thereby completing the control of the discrete delay (integer delay). The continuously adjustable delay device is implemented using a voltage-controlled continuous delay device. Under the control of the continuous delay control voltage signal, the fractional delay is completed to make the delay amount continuous. The final relationship between the delay amount of the first signal and the delay statistical voltage signal is as follows: Figure 7 shown.

[0036] The first amplitude normalization quantization module is implemented by a comparator; the delayed first signal and the first normalized reference signal are used as inputs of the comparator, and the comparator is used to obtain Figure 4 The first signal V1′ shown has its amplitude normalized and quantized and is input into the delay statistics module.

[0037] The second amplitude normalization quantization module is implemented by a comparator and a follower; the second signal and the second normalized reference signal are used as inputs of the comparator, and the signal output by the comparator is buffered by the follower to obtain Figure 4 The second signal V2′ is shown as having normalized and quantized amplitude and is input into the delay statistics module.

[0038] The time delay statistics module is used to perform frequency and phase discrimination on the first signal and the second signal (V1′, V2′) with normalized amplitude and quantized amplitude, and obtain the following: Figure 5 The voltage signal with two signal delay information is shown; then the voltage signal is integrated to obtain a delay statistical voltage signal, and is input into the delay control voltage generation module.

[0039] Specifically, the delay statistics module in this embodiment is composed of a PFD (phase frequency detector), a charge pump and a capacitor; Figure 5 As shown, two normalized square wave signals (V1′, V2′) are input into the PFD. The phase difference will cause the PFD to output high and low levels. The high level controls the charge pump to charge the capacitor, increasing the voltage value on the capacitor and obtaining a time-delay statistical voltage signal, such as Figure 6 The higher the level on the capacitor, the greater the delay between the two normalized signals, which means that the statistics of the delay information are completed.

[0040] The delay control voltage generating module is used to generate a continuous delay control voltage signal and a discrete delay control voltage encoding signal according to the delay statistical voltage signal, and input the signals into the delay module.

[0041] Specifically, the delay control voltage generating module includes a continuous delay control voltage calculation circuit and a discrete delay control voltage generating circuit.

[0042] like Figure 8 As shown, the discrete delay control voltage generating circuit in this embodiment includes 8 comparators, 7 XOR gates and 1 inverter; one of the input signals of each comparator is a delay statistical voltage signal, and the other input signal is a preset delay reference voltage, and the voltage values ​​of the delay reference voltages of all comparators are different; the outputs of every two adjacent comparators are connected to an XOR gate, and at the same time, the output of the comparator corresponding to the lowest value of the delay reference voltage is additionally connected to the inverter as the first output, and the remaining 7 XOR gate outputs are the second to eighth outputs respectively, and the outputs of the inverter and the 7 XOR gates constitute a discrete delay control voltage encoding signal, as shown in FIG. Fig. 9 As shown in FIG. 8 , the 8-bit discrete delay control voltage encoding signal always outputs only a high level, that is, only one delay branch is selected.

[0043] For example, when the delay statistical voltage is between 270mV and 380mV, the output of the comparator is 0 0 0 0 0 01 1, and the corresponding discrete delay control voltage encoding signal is 0 0 0 0 0 1 0 0, which controls the opening of the delay branch with two delay devices.

[0044] The continuous delay control voltage generating circuit is used to subtract the preset threshold voltage from the delay statistical voltage signal to generate a continuous delay control voltage signal. There are multiple preset threshold voltages in the continuous delay control voltage generating circuit. When the voltage value of the delay statistical voltage signal is within the range of two threshold voltages, the lower threshold voltage will be subtracted accordingly; for example, when the delay statistical voltage is between 270mV and 380mV, the continuous delay control voltage is V 连续 =(V 量化 -270mV).

Claims

1. A pure analog adaptive real delay alignment device based on quantization, characterized in that: The device is used to perform time delay alignment on a first signal and a second signal with time delay; the device comprises a first amplitude normalization quantization module, a second amplitude normalization quantization module, a time delay module, a time delay statistics module, and a time delay control voltage generation module; The delay module adaptively delays the input first signal according to the continuous delay control voltage signal and the discrete delay control voltage encoding signal generated by the delay control voltage generating module, and inputs the delayed first signal to the first amplitude normalization quantization module; meanwhile, the delayed first signal is output as an output signal; The first amplitude normalization and quantization module is used to normalize the delayed first signal to obtain a first channel of amplitude normalized and quantized signals and input the signals into the delay statistics module; The second amplitude normalization and quantization module is used to normalize the second signal to obtain a second signal with amplitude normalization and quantization and input it into the delay statistics module; The time delay statistics module is used to perform frequency and phase discrimination on the first signal and the second signal with normalized and quantized amplitudes to obtain a voltage signal with time delay information of the two signals; Integrate the voltage signal to obtain a time-delay statistical voltage signal, and input it into a time-delay control voltage generation module; The delay control voltage generating module is used to generate a continuous delay control voltage signal and a discrete delay control voltage encoding signal according to the delay statistical voltage signal, and input the signals into the delay module.

2. A quantization-based pure analog adaptive real delay alignment device according to claim 1, characterized in that: The time delay statistics module includes a frequency detector, a charge pump and a capacitor; wherein the frequency detector is used to perform frequency detection and phase detection on the first signal and the second signal with normalized and quantized amplitudes to obtain a voltage signal with time delay information of the two signals; the charge pump and the capacitor work together to integrate the voltage signal to obtain a time delay statistics voltage signal.

3. A quantization-based pure analog adaptive real delay alignment device as claimed in claim 2, characterized in that: The delay control voltage generating module comprises a continuous delay control voltage calculation circuit and a discrete delay control voltage generating circuit.

4. A quantization-based pure analog adaptive real delay alignment device as claimed in claim 3, characterized in that: The discrete delay control voltage generating circuit includes multiple comparators and a logic operation circuit, one of the input signals of each comparator is a delay statistical voltage signal, and the other input signal is a preset delay reference voltage, and the voltage values ​​of the delay reference voltages of all comparators are different. After the outputs of all comparators enter the logic operation circuit, a discrete delay control voltage encoding signal is obtained.

5. A quantization-based pure analog adaptive real delay alignment device as claimed in claim 4, characterized in that: The delay module includes a continuously adjustable delay device and a discretely adjustable delay device; wherein the discretely adjustable delay device selects delay branches with different delay multiples according to a discrete delay control voltage coding signal to perform a coarse adjustment on the delay of the first signal; and the continuously adjustable delay device performs a fine adjustment on the delay of the first signal after the coarse adjustment of the delay according to a continuous delay control voltage signal to achieve the effect of aligning the delays of the first signal and the second signal.

6. A quantization-based pure analog adaptive real delay alignment device as claimed in claim 5, characterized in that: The first amplitude normalization and quantization module is implemented by a comparator; the delayed first signal and a preset first normalization reference signal are used as inputs of the comparator, and the first amplitude normalization and quantization signal is obtained through the comparator.

7. A quantization-based pure analog adaptive real delay alignment device according to claim 6, characterized in that: The second amplitude normalization quantization module is implemented using a comparator and a follower; the second signal and a preset second normalized reference signal are used as inputs of the comparator, and the signal output by the comparator is buffered by the follower to obtain a second signal with amplitude normalization quantization.

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