A high-speed Tx topology having a serialization stage embedded within an AN output stage and controlled in common mode

Abstract

Disclosed is a high-speed transmitter system that uses a serialization stage embedded in an output stage and controlled in a common mode. In some of the plurality of embodiments, the transmitter includes a serialization circuit configured to convert parallel data into serial data using one or more serialization stages, a logic circuit configured to connect each of the inputs of the final stage of one or more serialization stages of the serialization circuit to respective dedicated output stages of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal based on a received input using NMOS transistors. Additionally, the logic circuit is configured to achieve a desired voltage value (such as the common mode of the output circuit), thereby making it possible to reduce the switching point of the gm stage of the NMOS and activate the gm stage within the reduced time.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims priority based on U.S. Provisional Patent Application No. 63 / 340,370, entitled "High - Speed Tx Topology with a Serialization Stage Embedded in an Output Stage and Controlled in Common Mode", filed on May 10, 2022, the content of which is hereby incorporated by reference in its entirety.

[0002] [Technical Field] This disclosure relates to a transmitter system that uses a common mode controlled serialization stage embedded in an output stage that enables high - speed operation and high reliability.

Background Art

[0003] The transmitter (Tx) is an important component of a physical layer communication system. Converting the digital signal from the encoder into an analog signal is an electronic component, and the converted analog signal can travel through a transmission medium (such as a wired or wireless channel, etc.) and may be received by the receiver (Rx). The data transmitted by the transmitter (Tx) is often generated by a logic portion. Usually, the logic portion generates data at a much lower speed than the data rate that the Tx can process. Therefore, in the transmitter (Tx), parallel-in, serial-out (PISO) conversion is widely used to achieve the required data rate. Generally, serialization is implemented by a chain of multiplexers (mux) to output a single signal at a high frequency. However, this topology (especially the last mux) has significant speed limitations and thus can hardly or cannot meet the speed requirements of state-of-the-art Tx systems at all. Summary of the Invention

[0004] To address the above drawbacks, a high-speed transmitter system is disclosed that uses a common mode controlled serialization stage embedded in an output stage. In some of the various embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data using one or more serialization stages, a logic circuit configured to connect each of the inputs of a last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of the output circuit via a respective logic function, and an output circuit implementing a plurality of output stages and configured to generate signals based on received inputs using NMOS transistors. Additionally, the logic circuit is configured to result in a desired voltage value (such as the output circuit’s common mode), thereby enabling reduction of the switching point of the NMOS gm stage and activation of the gm stage within a reduced time.

[0005] The above features and other preferred features, including various novel details of implementation and combinations of elements, will be described more specifically with reference to the accompanying drawings and pointed out in the claims. It will be understood that those specific methods and apparatuses are shown by way of example only and not as limitations. As will be appreciated by those skilled in the art, the principles and features described herein may be used in a variety of numerous embodiments.

Brief Description of the Drawings

[0006] The disclosed embodiments have multiple advantages and features, and these multiple advantages and features will become more readily apparent from the detailed description, the appended claims, and the appended drawings (or, the figures). The following is a brief introduction to the figures.

[0007]

Figure 1

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Best Mode for Carrying Out the Invention

[0008] The plurality of drawings and the following description relate to a plurality of preferred embodiments for illustrative purposes only. It should be noted that from the following description, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the invention as recited in the claims.

[0009] Here, reference is made in detail to some of the embodiments illustrated in the accompanying drawings, where such examples are shown. It should be noted that whenever practical, the same or similar reference numerals may be used in the drawings and may indicate the same or similar functions. The drawings show, for illustrative purposes only, multiple embodiments of the disclosed system (or method). One of ordinary skill in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.

[0010] FIG. 1 illustrates one exemplary topology 100 of a DAC-based transmitter (Tx). Although one DAC-based transmitter (Tx) is presented, it should be noted that the systems and approaches described herein in this disclosure are not limited to only DAC-based transmitter (Tx) topologies, but rather are limited to all Tx topologies that use analog output drivers. The exemplary DAC-based transmitter (Tx) in FIG. 1 includes three parts (a), (b), and (c). In FIG. 1(a), the logical portion or data acquisition circuit generates the data that the transmitter (Tx) transmits. In this example, the data is generated in m parallel branches or links.

[0011] The data generated in the m parallel branches has a data rate that is significantly lower than the data rate of the transmitter (Tx) (such as 160 times slower as shown in, for example, FIG. 1). As described above, due to the generation of this low-speed data from the logical portion, the transmitter (Tx) often uses parallel-in, serial-out (PISO) to increase the data rate. PISO enables the conversion of its data from a parallel format to a serial format. The data is loaded into the transmitter (Tx) in parallel format, which means that data bits are generated and presented simultaneously in multiple low-speed branches (such as individual wires, etc.). The data is output after serialization, which means that the data bits are output sequentially in time on a single wire or branch. In other words, the PISO conversion may be able to store the data received in parallel, shift the data on a clock basis, and delay the data by a value equal to the number of stages times the clock period until a single sequence of data is obtained. FIG. 1(b) shows the PISO or serialization, in which the low-rate data is serialized to reach the higher data rate required for the transmitter (Tx).

[0012] As shown in FIG. 1(b), for example, the serialization process can be implemented by a chain of multiplexers such as mux102, mux104, and mux106. Each of these muxes is controlled by clock phases, whereby it is possible to route the correct data to the output at the appropriate time. The outcome of the serialization process is a single signal with a high frequency. Unfortunately, this topology (mainly the last mux) has a speed limitation, and this topology often cannot meet the speed requirements of the transmitter (Tx). The system described herein addresses the speed limitation problem and dramatically improves system performance.

[0013] In some of the multiple embodiments, when the data is serialized, the output stage 112 is driven to convert the input serialized data 108 into an analog signal 110, as shown in FIG. 1(c).

[0014] In a non-return-to-zero (NRZ) transmitter (Tx), each analog symbol is represented by a single logic bit. However, in a digital-to-analog converter (DAC)-based transmitter (Tx), when using equalization, each analog symbol may contain multiple digital bits, and the combination of digital bits generates a single analog symbol. As can be understood from FIG. 1, analog symbol 110 may be generated by m analog stages, where m is a positive integer. In this example, those m analog stages are trans-conductance (gm) stages. Analog stage or gm stage 112 is supplied with digital data 108. The output of that analog stage / gm stage is shorted to a common resistive load, and then the output of that analog stage / gm stage generates analog symbol 110 as shown in FIG. 1(c). In contrast, since each analog symbol is represented by a single bit, the NRZ transmitter (Tx) has only a single gm stage.

[0015] An approach for implementing serialization is shown, for example, in FIG. 1(b). Serialization is performed among multiple chained stages. The data rate increases when the amount of parallel data branches decreases in a subsequent stage (e.g., such that mux104 operates following mux102). The amount of parallel data branches continues to decrease until serialization proceeds to the last serialization stage, where the remaining parallel data branches are serialized into a single data branch with a high data rate (e.g., digital data 108). This last serialization stage is the most challenging because it operates at the highest speed.

[0016] In some of the embodiments, the load of the last PISO or the last serialization stage is the other "off" branches and the subsequent analog buffer. FIG. 2 illustrates the last serialization stage 200 of FIG. 1. This stage includes an "n-to-1" mux, i.e., an n:1 mux such as the 4:1 mux 106 shown in FIG. 1(b). The n:1 mux has n - 1 "off" passgates (such as n - 1 branches that are switched off, for example) and one gm stage. This load is usually too large to support the high data rates present in state-of-the-art transmitters (Tx). For example, a fin field-effect transistor (FinFET)-based transmitter (Tx) can process data at speeds exceeding 10 gigahertz (GHz). It should be noted that this speed problem exists similarly in both NRZ-based topologies and DAC-based topologies. Therefore, the solution to the speed problem is described here in the context of a DAC-based topology, but the solution to the above speed problem is also applicable to other topologies not only NRZ-based topologies.

[0017] One of the conventional methods for achieving the required bandwidth while reducing the load is to reduce the size of the transistor. However, this method results in signal attenuation. The attenuated signal needs to be compensated by a large amount of power consumption, and such a large amount of power consumption further causes significant reliability problems.

[0018] FIG. 3 illustrates one exemplary n:1 circuit configuration 300 (e.g., 4:1, etc.). This configuration is an improved configuration of the last PISO stage in FIG. 1. As shown in FIG. 3, in some of the plurality of embodiments, by connecting each input 302 of the last PISO stage to a dedicated analog stage 304 (e.g., gm stage, etc.) via a logic function or cell 306, it is possible to address the speed limitation problem of the last PISO stage. Input 302 is connected to analog stage 304 having a related clock phase (not shown), thereby enabling activation of analog stage 304 at an appropriate time. The logic function may be, for example, an "AND" function between inputs 302 having a related clock phase. As shown above in FIGS. 1(b) and 2, the last PISO stage is a 4:1 mux 106. Using this 4:1 mux as one example, in FIG. 3, it is possible to connect the four-bit input of the 4:1 mux 106 to four logic functions and four gm stages. This occurs m times for the exemplary DAC topology in FIG. 1. The configuration of FIG. 3 makes it possible to increase the processing speed while reducing the data load. Additionally, connecting each bit to a dedicated analog stage enables gain mismatch calibration for each bit.

[0019] As shown in FIG. 3, a transistor may be used to amplify or switch an electrical signal and power. A transistor typically includes at least three terminals (such as 308, 310, and 312, etc.) for connection to an electronic circuit. When a voltage is applied, the transistor can control the current flowing through a pair of terminals. For example, when a voltage is applied to the gate 308 of the transistor, the transistor generates an electric field, and the electric field controls the flow of charge carriers (such as electrons) between the source 310 (which is, for example, the terminal where current enters the transistor) and the drain 312 (which is, for example, the terminal where current exits the transistor). Since the output power may be higher than the control power or the input power, the transistor can amplify the signal to obtain an output signal 314.

[0020] When using a gm stage for the analog stage, the source voltage of one of the pair of inputs is the drain voltage of the current source, that is, the V of the current source ds This means that in order to operate the gm stage, the gate voltage needs to be higher than the sum of the current source voltage V ds and the V of the transistor t The logic function / cell 306 toggles between the ground voltage (V ss ) and the supply voltage (V dd ), so it takes a certain amount of time to charge the gate 308 from the voltage of V ss to the voltage of V dd + V ss to V ds + V t The voltage of V ds + V t turns on the analog stage. This gate charging time is not negligible in state-of-the-art transmitter (Tx) systems, thereby affecting the performance of the transmitter (Tx) regarding speed, gain, efficiency, etc.

[0021] The transmitter topology in this disclosure is further improved to address the above drawbacks, as will be described with reference to FIG. 4. Specifically, the ground of the logic circuit is controllable, and thus, it can easily be raised to approximate to the switching point of the NMOS gm stage. In the scenario of FIG. 4, the ground of the logic circuit / logic function 402 that drives the analog output circuit / cell is not V ss Rather, the ground of the logic circuit is derived from the common mode of the analog circuit, as shown at 404. This indicates that the output of the logic circuit 402 is toggled around the switching point of the analog circuit 406. The switching point is the point at which the circuit of the analog output stage 406 turns on (e.g., a certain voltage value, etc.). As a result, it is possible to more quickly activate the analog circuit and to lengthen the conduction period of the analog circuit.

[0022] In the system of the present invention, the analog stage or the analog output stage is implemented by NMOS devices / transistors, that is, the analog gm stage is an NMOS-based stage. NMOS transistor or NMOS refers to an n-channel metal oxide semiconductor (MOS) field effect transistor (MOSFET). The NMOS transistor may include three terminals such as a gate 408, a source 410, and a drain 412 as shown in FIG. 4. The NMOS transistor turns on (for example, becomes in an open state) when the gate voltage is above the source voltage plus a threshold voltage. When the ground of the logic circuit 402 is set to 0, the output of the logic circuit 402 toggles between zero and the supply voltage V dd . In such a case, in order to activate the analog gm stage 406, that is, to turn on the NMOS transistor, the gate voltage of gm needs to be increased from 0 to the sum of the V dd of the transistor and the voltage V t of the current source, that is, V d +V d +V t . This rising time may be too long for efficient transmitter operation. As shown in FIG. 4, this system derives the ground of the logic circuit 402 from the common mode of the analog circuit 406 by the analog function 414. That is, the ground of the logic function is configured to be close to a desired voltage such as V d . As a result, V tWhen only increasing the gate voltage, it is possible to activate the analog gm stage 406. This significantly shortens the stage activation time, enables the analog stage to operate even faster, and improves the operating efficiency.

[0023] Another feature of the topology shown in FIG. 4 is the use of an external reference voltage 416. This external reference voltage 416 may be used to set the input common mode of the analog stage 406 to any desired voltage. In addition, the external reference voltage 416 can ensure that the current source remains in the saturation mode. Furthermore, since the external reference voltage 416 controls the ground, the external reference voltage 416 may also be used to determine the output range of the digital circuit. Therefore, by using the external reference voltage, it is possible to increase the speed and gain of the transmitter, obtain the desired current, and improve the common-mode rejection ratio (CMRR).

[0024] System flowchart

[0025] The inventive system discloses a transmitter topology having a common mode controlled serialization stage embedded in an output stage, which not only increases the operating speed but also improves transmitter gain, stability, etc. To achieve these technological advances, the inventive system includes several distinct features. The inventive transmitter system uses a unique gm stage for each bit in the last serialization stage, thereby eliminating the speed limitations associated with the last stage. This unique connection feature alone can solve the speed problems present in various types of transmitters (e.g., DAC transmitters, NRZ transmitters, etc.). In addition, the inventive transmitter system uses an NMOS-based gm stage to generate the analog signal. In particular, the ground of the logic circuitry that drives the NMOS-based gm stage of the analog circuitry is derived from the common mode of the analog circuitry. Thus, to turn on the NMOS transistor to activate the analog gm stage, V d +V t Not V t 2. Increase the gate voltage of gm by 1 V. This reduces the activation time of the gm stage, which speeds up the operation of the gm stage and further improves the performance of the transmitter.

[0026] FIG. 5 illustrates one exemplary process 500 for constructing and implementing a transmitter having a serialization stage embedded within an output stage and controlled in common mode. In some of the plurality of embodiments, the transmitter includes a data acquisition circuit, a serialization circuit, a logic circuit, and an output circuit, and these circuits are electrically and communicatively connected to operate in a fast and reliable manner.

[0027] In some of the plurality of embodiments, the transmitter may be a DAC transmitter, an NRZ transmitter, etc. In the context of a DAC transmitter, the data acquisition circuit may generate or collect digital data associated with a plurality of data branches. The serialization circuit and the logic circuit receive the data in parallel from these data branches, and the output circuit can, for example, convert the received data into a single sequence of data to generate a signal such as an analog signal.

[0028] In step 505, the serialization circuit receives data from a plurality of data branches. The serialization circuit may include one or more serialization stages, as shown in FIG. 1(b). For example, the final stage of the serialization stage implemented by the 4:1 mux in FIG. 1(b) often lacks the ability to process high-load data at the required high data rate, thereby causing performance degradation.

[0029] In step 510, the logic circuit connects each of the inputs of the final stage to the respective dedicated output stage of the output circuit via their respective logic functions. For example, when the final stage is a 4:1 mux, 4-bit data is connected to 4 logic functions and 4 gm stages. This reduces the data load and increases the processing speed.

[0030] In step 515, the output circuit uses NMOS to implement the output stage to generate a signal based on the received input. In some of the multiple embodiments, the output stage is an NMOS-based gm stage. The ground of the logic circuit is configured to be a desired voltage value, such as the common mode of the output circuit. By deriving the ground of the logic circuit from the common mode of the output circuit, the switching point of the gm stage of the NMOS is reduced, thereby enabling the gm stage to be activated within the reduced time, thereby further accelerating the transmitter operation. In some of the multiple embodiments, digital data is supplied to each output stage and output to a common resistive load to generate an analog symbol.

[0031] Other Considerations

[0032] In some of the multiple implementations, at runtime, one or more processing devices can implement at least a portion of the multiple approaches described above by instructions that cause the processes and functions described above to be executed. Such instructions may include, for example, script instructions or executable code, or other interpreted instructions such as those stored in a non-transitory computer-readable medium. The storage device 830 may be implemented in a manner distributed across a network, such as as a server farm or as a set of servers widely distributed, or may be implemented within a single computing device.

[0033] Although one exemplary processing system has been described, the subject matter, functional operations, and process embodiments described herein can be implemented by other types of digital electronic circuitry, by computer software or firmware embodied in a tangible form, by computer hardware including the structures disclosed herein and their structurally equivalent ones, or by one or more combinations thereof. The subject matter described herein can be implemented as one or more computer programs, i.e., as one or more modules of computer program instructions encoded in a tangible, non-transitory program carrier for execution by, or to control the operation of, a data processing apparatus. Alternatively or additionally, the program instructions can be encoded so as to be an artificially generated propagated signal, such as an electrical, optical, or electromagnetic signal generated by a machine for encoding information to be transmitted to a suitable receiver device for execution by a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random access memory device, or a serial access memory device, or one or more combinations thereof.

[0034] The term "system" may include, for example, a programmable processor, a computer for processing data, or any kind of device, apparatus, and machine that includes a plurality of processors or computers. The processing system may include, for example, dedicated logic circuits such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The processing system may include code in addition to hardware, and the code creates an execution environment for a targeted computer program, such as, for example, constituting processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0035] (Also referred to as, or described as, a program, software, software application, module, software module, script, or code) A computer program may be described in any form of programming language, including a compiled or interpreted language, or a declarative or procedural language, and the computer program may be deployed in any form, as a stand-alone program, or as a module, component, subroutine, or other unit suitable for use in a computing environment. The computer program may correspond to a file in a file system, but does not necessarily have to. The program may be part of a file that holds other programs or data (such as one or more scripts stored in a markup language document), a single file dedicated to the program being targeted, or stored in multiple coordinated files (such as a file that stores one or more modules, subprograms, or multiple parts of code). The computer program may be deployed to be executed by one computer, or located at one site, or deployed to be executed by multiple computers located at multiple sites and interconnected by a communication network.

[0036] One or more programmable computers may execute one or more computer programs to perform functions by operating on input data and generating output, thereby executing the processes and logic flows described herein. The processes and logic flows may also be executed by, for example, a dedicated logic circuit such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and the apparatus may be implemented as a dedicated logic circuit.

[0037] A computer suitable for the execution of a computer program may include, for example, a general-purpose microprocessor or a dedicated microprocessor or both, or any other kind of central processing unit. Generally, the central processing device receives instructions and data from a read-only memory or a random access memory, or both. A computer generally includes a central processing unit for executing or performing instructions, and one or more memory devices for storing instructions and data. Generally, a computer also includes, or is operatively coupled to receive data from or transfer data to, one or more mass storage devices for storing data, such as, for example, magnetic disks, magneto-optical disks, or optical disks. In contrast, a computer need not have such devices. Further, a computer may be embedded in other devices, such as, for example, a cellular phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable memory device (such as, for example, a universal serial bus (USB) flash drive).

[0038] Computer-readable media suitable for storing computer program instructions and data include, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and all forms of non-volatile memory, media, and memory devices including CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in, dedicated logic circuitry.

[0039] To provide interaction with a user, embodiments of the subject matter described herein can be implemented by a computer, which can have, for example, a display device such as a cathode ray tube (CRT) monitor or a liquid crystal display (LCD) monitor for displaying information to the user, and a pointing device such as a mouse or a trackball and a keyboard that enable the user to provide input to the computer. Other types of devices can be used as well to provide interaction with the user. For example, the feedback provided to the user can be any form of sensory feedback such as visual feedback, auditory feedback, or tactile feedback, and the input received from the user can be received in any form including acoustic input, voice input, or tactile input. Additionally, the computer can interact with the user by sending and receiving documents to and from the devices used by the user, such as by sending a web page to a web browser displayed on the user's user device in response to a request received from the web browser.

[0040] Embodiments of the subject matter described herein can be implemented by a computing system, which can include, for example, backend components as a data server, or can include middleware components such as an application server, or can include frontend components such as a client computer having a graphical user interface or a web browser that enables a user to interact with an implementation of the subject matter described herein, or can include any combination of one or more such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication such as, for example, a communication network. Examples of communication networks include wide area networks ("WAN") such as the Internet and local area networks ("LAN").

[0041] A computing system may include clients and servers. The clients and servers are generally remote from each other and typically interact via a communication network. The relationship between a client and a server arises through computer programs that are executed by respective computers and have a client-server relationship with each other.

[0042] This specification includes many details of specific implementations, which should not be construed as limitations on the scope of the invention that may be described in the claims, but rather as descriptions of features that may be specific to particular embodiments. In this specification, specific features described in connection with multiple individual embodiments may also be implemented in combination within a single embodiment. Conversely, various features described in connection with a single embodiment may also be implemented separately, or in any suitable sub-combination, in multiple embodiments. Furthermore, multiple features may be described above as operating in a particular combination, and may even be initially described in the claims as being in such a particular combination, but one or more features of the combinations described in the claims may, in some cases, be deleted from that combination, and the combinations described in the claims may relate to sub-combinations or variations of sub-combinations.

[0043] Similarly, although the operations are shown in a particular order in the drawings, this should not be construed as requiring that such operations be performed in the particular order shown or in a series of orders, or that all of the illustrated operations be performed, to achieve a desirable result. In certain circumstances, multitasking and parallel processing may be advantageous. Further, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and the described program components and systems may generally be integrated together, either into a single software product, or packaged into multiple software products.

[0044] Multiple specific embodiments of the subject matter have been described. Other embodiments are within the scope of the invention as recited in the claims. For example, the operations recited in the claims may be performed in a different order and still achieve a desirable result. As one example, the processes shown in the accompanying drawings do not necessarily require the particular order or series of orders shown to achieve a desirable result. In certain implementations, multitasking and parallel processing may be advantageous. Other steps or stages may be provided, or steps or stages may be removed from the described processes. Accordingly, other implementations are within the scope of the invention as recited in the following claims.

[0045] The terminology and phraseology used herein are for the purpose of description and should not be considered limiting.

[0046] The terms "approximately", "approximately equal to", and other similar expressions (e.g., "X has a value approximately equal to Y" or "X is approximately equal to Y") used in the specification and claims are to be understood to mean that one value (X) exists within a predetermined range of another value (Y). The predetermined range may be 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1% unless otherwise specified.

[0047] The indefinite articles "a" and "an" used in the specification and claims are to be understood to mean "at least one" unless otherwise stated. The phrase "and / or" used in the specification and claims is to be understood to mean "either or both" of the elements so combined, i.e., in some cases existing conjunctively and in other cases disjunctively. Multiple elements listed with "and / or" are to be interpreted in the same way, i.e., as "one or more" of the elements so combined. Other elements than those specifically identified by the "and / or" clause may optionally exist, whether or not they are related to those specifically identified elements. Thus, by way of non-limiting example, a reference to "A and / or B", when used with open-ended language such as "comprising", may in one embodiment refer only to A (optionally including elements other than B), in another embodiment refer only to B (optionally including elements other than A), and in yet another embodiment refer to both A and B (optionally including other elements), etc.

[0048] As used in this specification and the claims, "or" shall be understood to have the same meaning as "and / or" as defined above. For example, when separating multiple items in a list, the word "or" or the phrase "and / or" shall be construed as inclusive, i.e., being one or more of the number of elements or items in the list, and including, optionally, additional unlisted items. Expressions such as "only one of", "exactly one of", or, when used in the claims, "consisting of", which clearly indicate a contrary meaning, shall refer to including exactly one element of the number of elements or items in the list. Generally, when used, the word "or" shall be construed as indicating an exclusive alternative (i.e., "one or the other, but not both") only when preceded by exclusive terms such as "either", "one of", "only one of", or "exactly one of". "Consisting essentially of" shall have its ordinary meaning as used in the field of patent law when used in the claims.

[0049] As used in this specification and the claims, the phrase "at least one" in reference to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, although those at least one elements need not necessarily include at least one of each and every element specifically listed in the list of elements and is not intended to exclude any combinations of elements in the list of elements. This definition also allows for the possibility that elements other than those specifically identified in the list of elements referred to by the phrase "at least one" may optionally be present, whether or not they are related to those specifically identified elements. Thus, by way of non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B", or, equivalently, "at least one of A and / or B") may, in one embodiment, refer to at least one that optionally includes more than one A (and, optionally, elements other than B) in the absence of B, in another embodiment, may refer to at least one that optionally includes more than one B (and, optionally, elements other than A) in the absence of A, and in yet another embodiment, may refer to at least one that optionally includes more than one A, and at least one that optionally includes more than one B (and, optionally, other elements), etc.

[0050] The use of "comprising", "including", "having", "containing", "involving", and variations thereof means including the items listed thereafter and additional items.

[0051] In the claims, the use of ordinal terms such as "first", "second", "third", etc. to modify elements of the claims does not by itself mean a priority, precedence or order of one claim element over another claim element, or the temporal order in which acts of a method are performed. The ordinal terms are used only to distinguish one claim element having that name from other claim elements having the same name (except for the use of the ordinal term) as a label for distinguishing claim elements.

[0052] Although some aspects of at least one embodiment of the invention have been described in this way, it should be understood by those skilled in the art that various changes, modifications and improvements can readily be devised. Such changes, modifications and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. A transmitter, the transmitter comprising: A serialization circuit configured to convert parallel data into serial data using one or more serialization stages; A logic circuit electrically coupled to the serialization circuit and an output circuit, the logic circuit configured to connect each of the inputs of the final stage of the one or more serialization stages of the serialization circuit to respective dedicated output stages of the output circuit via respective logic functions; The output circuit is configured to implement output stages to generate signals based on received inputs using n-channel metal-oxide-semiconductor (NMOS) field-effect transistors, and the ground of the logic circuit is configured to have a desired voltage value. A transmitter.

2. The transmitter according to claim 1, wherein the dedicated output stage is an NMOS-based transconductance (gm) stage.

3. By configuring the ground of the logic circuit to have the desired voltage value, reducing the switching point of the gm stage of the NMOS, thereby enabling the gm stage to be activated within a reduced time; The switching point is the value of the threshold voltage at which the NMOS transistor turns on; The transmitter according to claim 2, wherein the desired voltage value includes the common mode of the output circuit.

4. The serialization circuit includes a series of multiplexers among the one or more serialization stages; The final stage is an n:1 multiplexer; The transmitter according to claim 1, wherein the logic circuit is configured to connect an n-bit input from the final stage to n gm stages via n logic functions.

5. The transmitter according to claim 4, wherein the inputs of the final stage are connected to respective dedicated output stages having associated clock phases.

6. The transmitter according to claim 5, wherein the serialization circuit and the output circuit are connected by the logic circuit to reduce the data load of the final stage and increase the operating speed of the transmitter.

7. Each output stage is supplied with digital data and output to a common resistive load to generate an analog symbol, the transmitter according to claim 1.

8. further comprising a data acquisition circuit configured to generate the parallel data in a plurality of data branches The transmitter according to claim 1, wherein the serialization circuit and the logic circuit are configured to convert the parallel data received from the plurality of data branches into a single sequence of data.

9. The transmitter according to claim 1, which is one of a digital-to-analog converter (DAC)-based transmitter, a non-return-to-zero (NRZ) transmitter, or another type of transmitter.

10. The transmitter according to claim 1, wherein the logic circuit is connected to an external reference voltage and is adjusted to enable the current source to operate in a saturation state.

11. A method for constructing and implementing a transmitter, the method comprising: receiving data in parallel from a plurality of data branches by a serialization circuit, the serialization circuit including one or more serialization stages; connecting each of the inputs of the final stage of the one or more serialization stages to a respective dedicated output stage of the output circuit via respective logic functions of the logic circuit; implementing an output stage to generate a signal based on the received input using an n-channel metal-oxide-semiconductor (NMOS) field-effect transistor by the output circuit, wherein the ground of the logic circuit is configured to have a desired voltage value. Method.

12. The method according to claim 11, wherein the dedicated output stage is an NMOS-based transconductance (gm) stage.

13. By configuring the ground of the logic circuit to have the desired voltage value, reducing the switching point of the NMOS gm stage, thereby enabling the gm stage to be activated within the reduced time, wherein the switching point is the value of the threshold voltage at which the NMOS transistor turns on, The method according to claim 12, wherein the desired voltage value includes the common mode of the output circuit.

14. configuring a series of multiplexers in the one or more serialization stages of the serialization circuit, wherein the final stage is an n:1 multiplexer. connecting an n-bit input from the final stage to n gm stages via n logic functions by the logic circuit, the method according to claim 11

15. the method according to claim 14, wherein the input of the final stage is connected to respective dedicated output stages having associated clock phases

16. the method according to claim 15, wherein the serialization circuit and the output circuit are connected by the logic circuit so as to reduce the data load of the final stage and increase the operating speed of the transmitter

17. the method according to claim 11, wherein each output stage is supplied with digital data and output to a common resistive load to generate an analog symbol

18. generating the data in the plurality of data branches further comprising converting the data received in parallel from the plurality of data branches into a single sequence of data, the method according to claim 11

19. the method according to claim 11, wherein the transmitter is one of a digital-to-analog converter (DAC)-based transmitter, a non-return-to-zero (NRZ) transmitter, or another type of transmitter

20. connecting the logic circuit to an external reference voltage further comprising adjusting the logic circuit so that a current source can operate in a saturated state, the method according to claim 11

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