Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device comprises a plurality of semiconductor columns which are arranged in an array along a first direction and a second direction, and each semiconductor column extends along a third direction; the shielding structures are located between the adjacent semiconductor columns and extend in the first direction; the first connecting structure is positioned on one side of the shielding structure along the third direction and is connected with the shielding structure; the first contact structure extends along the third direction and is connected with the first connecting structure; wherein the first contact structure and the shielding structure are located on the same side of the first connection structure, and the first direction, the second direction and the third direction intersect with one another.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In the field of semiconductor manufacturing, as the feature size continues to shrink, the coupling effect between adjacent transistors intensifies. In order to improve the coupling effect, a shielding structure is often needed. However, the shielding structure and its related structures have a small process window and high process difficulty, which also affects product performance and yield. Summary of the invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, and each semiconductor pillar extends along a third direction; a shielding structure located between adjacent semiconductor pillars and extending along the first direction; a first connecting structure located on one side of the shielding structure along the third direction and connected to the shielding structure; and a first contact structure extending along the third direction and connected to the first connecting structure; wherein the first contact structure and the shielding structure are located on the same side of the first connecting structure, and the first direction, the second direction and the third direction intersect with each other.

[0005] In some embodiments, the semiconductor device further includes: a second connection structure located on a surface of the first connection structure away from the shielding structure, wherein the first contact structure extends to the second connection structure.

[0006] In some embodiments, the semiconductor device further includes: a capacitor connection structure connected to an end surface of the semiconductor column close to the first connection structure; wherein the end surface of the capacitor connection structure away from the semiconductor column is substantially flush with a surface of the second connection structure away from the first connection structure.

[0007] In some embodiments, the semiconductor device further includes: a capacitor connected to an end surface of the capacitor connection structure away from the semiconductor column.

[0008] In some embodiments, the first contact structure extends to the first connection structure.

[0009] In some embodiments, the first connecting structure extends along the second direction and directly contacts the plurality of shielding structures arranged along the second direction.

[0010] In some embodiments, on a plane perpendicular to the third direction, the semiconductor device includes a storage region and a connection region located at a periphery of the storage region, the first connection structure extends in the connection region, and the first contact structure is located in the connection region.

[0011] In some embodiments, the semiconductor column has a first side wall close to the shielding structure, and a second side wall opposite to the first side wall; the semiconductor device also includes: a gate dielectric layer located on the second side wall of the semiconductor column; a word line located on the surface of the gate dielectric layer and extending along a first direction; and a word line contact structure located on the same side of the first connection structure as the first contact structure and extending to the word line.

[0012] In some embodiments, the semiconductor device also includes: a bit line, located on a side of the semiconductor column away from the first connection structure and connected to a plurality of semiconductor columns arranged along the second direction; and a bit line contact structure, located on the same side of the first connection structure as the first contact structure and extending to the bit line.

[0013] In some embodiments, at least two of a surface of the first contact structure away from the first connection structure, a surface of the bit line contact structure away from the bit line, and a surface of the word line contact structure away from the word line are substantially flush.

[0014] In some embodiments, on a plane perpendicular to the third direction, the semiconductor device includes a storage area and a connection area located outside the storage area, and the first contact structure, the word line contact structure, and the bit line contact structure are located in the connection area and do not overlap with each other.

[0015] In a second aspect, some embodiments of the present application provide a memory system, which includes: a memory including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory and used to control the memory to store data.

[0016] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein each semiconductor pillar extends along a third direction; forming a shielding structure extending along the first direction between adjacent semiconductor pillars, and forming a first connection structure connected to the shielding structure on one side of the shielding structure along the third direction; and forming a first contact structure extending along the third direction from a first side of the semiconductor pillar away from the first connection structure, wherein the first contact structure is connected to the first connection structure; wherein the first direction, the second direction, and the third direction intersect with each other.

[0017] In some embodiments, the manufacturing method also includes: forming a second connection structure on a surface of the first connection structure away from the shielding structure; wherein, forming a first contact structure extending along a third direction from a first side of the semiconductor column away from the first connection structure includes: forming a first contact structure extending to the second connection structure.

[0018] In some embodiments, the manufacturing method further includes: forming a capacitor connection structure extending to the semiconductor column from a second side of the semiconductor column opposite to the first side; wherein the second connection structure and the capacitor connection structure are formed in the same process.

[0019] In some embodiments, forming a first contact structure extending along a third direction from a first side of the semiconductor pillar away from the first connection structure includes: forming a first contact structure extending to the first connection structure.

[0020] In some embodiments, the semiconductor column has a first side wall close to the shielding structure and a second side wall opposite to the first side wall; the manufacturing method also includes: forming a gate dielectric layer on the second side wall of the semiconductor column; forming a word line extending along a first direction on the surface of the gate dielectric layer; and forming a word line contact structure extending to the word line from the first side of the semiconductor column.

[0021] In some embodiments, the manufacturing method further includes: forming a bit line extending along the second direction on the first side of the semiconductor column, the bit line being connected to a plurality of semiconductor columns arranged along the second direction; and forming a bit line contact structure extending to the bit line on the first side of the semiconductor column.

[0022] In some embodiments, at least two of the first contact structure, the bit line contact structure, and the word line contact structure are formed in the same process step.

[0023] In some embodiments, forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction includes: etching a semiconductor layer to form a plurality of semiconductor walls arranged along the first direction, wherein the semiconductor walls extend along the second direction; filling an insulating material around the periphery of the plurality of semiconductor walls; and etching the plurality of semiconductor walls and the insulating material to form first grooves and second grooves alternately arranged along the second direction, thereby dividing the plurality of semiconductor walls into a plurality of semiconductor pillars, wherein both the first grooves and the second grooves extend along the first direction.

[0024] In some embodiments, a shielding structure extending along a first direction is formed between adjacent semiconductor pillars, and a first connection structure connected to the shielding structure is formed on one side of the shielding structure along a third direction, including: forming a shielding structure in a first groove; forming a conductive layer on a second side of a plurality of semiconductor pillars opposite to the first side; etching a portion of the conductive layer so that the retained conductive layer serves as the first connection structure and is in direct contact with the shielding structure.

[0025] In some embodiments, etching a portion of the conductive layer so that the remaining conductive layer serves as the first connecting structure and directly contacts the shielding structure further comprises: removing a portion of the shielding structure close to the second side of the semiconductor pillar.

[0026] According to at least one embodiment of the present application, the semiconductor device, memory system and semiconductor device manufacturing method provided by the present application, by arranging the first contact structure and the shielding structure on the same side of the first connection structure, can simplify the manufacturing process of the first connection structure and the first contact structure used to lead out the shielding structure, improve the process window, reduce the manufacturing difficulty, and help improve the yield and product performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0028] Figure 1A is a perspective schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0029] Figure 1B It is along Figure 1A A perspective schematic diagram of a semiconductor device taken along line AA' is shown;

[0030] Figure 1C is a partial perspective schematic diagram of a semiconductor device including a shielding structure, a first connecting structure and a first contact structure;

[0031] Figure 2 is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application;

[0032] Figure 3 is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application;

[0033] Figure 4 is a perspective schematic diagram of a semiconductor device provided by yet another embodiment of the present application;

[0034] Figure 5 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0035] Figure 6 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0036] FIG. 7A to FIG. 18 is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present application; and

[0037] FIG. 19A to FIG. 19CIt is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by another embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first connection structure discussed in this application may also be referred to as the second connection structure, and vice versa.

[0040] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0044] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0045] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0046] An embodiment of the present application provides a semiconductor device. Figures 1A to 1C is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. Figure 1A It is a perspective schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 1B It is along Figure 1A A schematic perspective view of a semiconductor device taken along line AA′ is shown. Figure 1C The semiconductor device 100 is a partial perspective diagram of a semiconductor device including a shielding structure, a first connecting structure and a first contact structure. For example, the semiconductor device 100 may be a part of a dynamic random access memory (DRAM).

[0047] It should be noted that, hereinafter, the D1 direction, the D2 direction, and the D3 direction in each figure show the spatial relationship of the components in the semiconductor device. For example, the D3 direction is the extension direction of the semiconductor column, and the D1 direction and the D2 direction are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the extension direction. For example, the D1 direction is the word line direction, and the D2 direction is the bit line direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0048] like Figure 1A and Figure 1B As shown, the semiconductor device 100 includes a plurality of semiconductor pillars (e.g., 111a, 111b) arranged in an array along the D1 direction and the D2 direction. For example, each semiconductor pillar (e.g., 111a, 111b) extends along the D3 direction. As will be described in detail below, the semiconductor pillars (e.g., 111a, 111b) can be formed using a semiconductor substrate, and the extension direction (e.g., D3 direction) of the semiconductor pillars (e.g., 111a, 111b) can be perpendicular to the horizontal extension direction of the semiconductor substrate.

[0049] In the case where the semiconductor device 100 is a part of a DRAM memory, the DRAM memory may include a plurality of memory cells, and each memory cell may include a transistor and a capacitor. The following first describes the transistors and related components constituting the memory cells.

[0050] In some embodiments, Figure 1A As shown, on a plane perpendicular to the D3 direction, the semiconductor device 100 may include a storage area 101 (in a dotted frame) and a connection area 102 (outside the dotted frame) located at the periphery of the storage area 101. For example, a memory cell may be disposed in the storage area 101, and a contact structure (e.g., a first contact structure 118, a word line contact structure 121, and a bit line contact structure 122) may be disposed in the connection area 102.

[0051] In some embodiments, Figure 1B As shown, the semiconductor column (e.g., 111a) has a first side wall 112 and a second side wall 113 opposite to each other in the D1 direction. The first side wall 112 is close to the shielding structure 116. The shielding structure 116 will be described in detail below. The semiconductor device 100 may include a gate dielectric layer 114 located on the second side wall 113. For example, the gate dielectric layer 114 is in direct contact with the second side wall 113 and extends (e.g., continuously) along the D1 direction. The gate dielectric layer 114 may be in direct contact with the second side wall 113 of each of a column of semiconductor columns (e.g., 111a) arranged along the D1 direction. Exemplarily, the material of the gate dielectric layer 114 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), high dielectric constant material or any other suitable insulating material. For example, the gate dielectric layer 114 may be made of silicon oxide (SiO2).

[0052] In some embodiments, the semiconductor device 100 may further include a word line 115 located on the surface of the gate dielectric layer 114. The word line 115 may extend in the D1 direction (e.g., continuously). In some examples, the word line 115 may include an adhesive layer and a metal layer (not shown) attached to each other. The adhesive layer may be located on the surface of the gate dielectric layer 114 and extend in the D1 direction (e.g., continuously). The metal layer may be located on the surface of the adhesive layer and extend in the D1 direction (e.g., continuously). In other words, the adhesive layer may be located between the metal layer and the gate dielectric layer 114. The adhesive layer helps to improve the bonding performance between the metal layer and the gate dielectric layer 114. For example, the material of the adhesive layer may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the metal layer may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. In some other examples, the word line 115 may not have a composite structure, but may be made of a conductive material, which is not specifically limited in the present application.

[0053] According to the above description, in some embodiments, a semiconductor column (e.g., 111a), and a gate dielectric layer 114 and a word line 115 covering a portion of the second side wall 113 of the semiconductor column (e.g., 111a) can constitute a transistor. In the transistor, the semiconductor column (e.g., 111a) serves as a channel, the word line 115 corresponding to the portion of the second side wall 113 of the semiconductor column (e.g., 111a) serves as a gate, and the two ends of the semiconductor column (e.g., 111a) in the extension direction serve as one of the source and drain electrodes, respectively. Since the extension direction (e.g., D3 direction) of the semiconductor column (e.g., 111a) is perpendicular to the horizontal extension direction of the semiconductor substrate, the transistor can also be called a vertical channel transistor. A vertical channel transistor can effectively reduce the plane occupied area and improve the storage density. In this case, the word line 115 extending in the D1 direction can be used to control a column of transistors arranged along the D1 direction. Each transistor can be part of a memory cell.

[0054] In some embodiments, Figure 1A As shown, from the D3 direction, the word line 115 and the gate dielectric layer 114 may be a hollow rectangle and extend in the storage area 101 and the connection area 102. The semiconductor device 100 may further include a cutout 123. For example, two cutouts 123 are respectively located in the connection area 102 on both sides of the storage area 101 in the D1 direction, and penetrate the word line 115 and the gate dielectric layer 114 along the D3 direction to divide the word line 115 into a first part and a second part, so that the first part and the second part are electrically isolated in the storage area 101. For example, the cutout 123 may be filled with silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOx N y ) or any other suitable insulating material or materials. Optionally, the number of word lines 115 can be multiple, and they are spaced between adjacent semiconductor pillars (eg, 111a).

[0055] As the characteristic size of transistors and related components is miniaturized, the coupling effect between adjacent transistors is aggravated. In order to improve the coupling effect, the shielding structure 116 comes into being. The shielding structure 116 and its related structures are exemplarily described below.

[0056] Continue to refer Figure 1A and Figure 1B , the semiconductor device 100 further includes a shielding structure 116, a first connection structure 117, and a first contact structure 118. The shielding structure 116 is located between adjacent semiconductor pillars (e.g., 111a, 111b) and extends along the D1 direction (e.g., continuously extends). For example, the shielding structure 116 extends within the storage area 101 and within the connection area 102. In some examples, the shielding structure 116 may be located on the first sidewall 112 of the semiconductor pillar (e.g., 111a) and directly contact the semiconductor pillar (e.g., 111a). In other examples, a dielectric layer (not shown) may be provided between the shielding structure 116 and the semiconductor pillar (e.g., 111a). Exemplarily, the material of the shielding structure 116 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. Optionally, the number of the shielding structures 116 may be plural, and the plurality of shielding structures 116 may be arranged alternately with the word lines 115 in the direction D2 .

[0057] like Figure 1A and 1CAs shown, the first connection structure 117 is located on one side of the shielding structure 116 along the D3 direction and is connected to the shielding structure 116. In some embodiments, the first connection structure 117 may be located in the connection area 102, which may include a first portion 1171 and a second portion 1172. From the D3 direction, the first portion 1171 may be rectangular and connected to a plurality of shielding structures 116. The second portion 1172 may be connected to a side of the first portion 1171 away from the storage area 101. It should be noted that the first connection structure 117 may be an integral structure, the first portion 1171 and the second portion 1172 do not have a clear boundary, and the two surfaces of the first portion 1171 and the second portion 1172 in the D3 direction may be substantially flush (for example, the error is less than ±10%). Exemplarily, the material of the first connection structure 117 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material.

[0058] In some embodiments, the shielding structure 116 may have different sizes in the D3 direction. For example, in the D3 direction, the size of the portion of the shielding structure 116 located in the storage area 101 is smaller than the size of the portion thereof located in the partial connection area 102 (for example, the first connection structure 117 is disposed in the partial connection area 102). In the D3 direction, the size of the portion of the shielding structure 116 located in the storage area 101 has a smaller value to match the size of the word line 115 in the D3 direction, thereby optimizing the control effect. In the D3 direction, the size of the portion of the shielding structure 116 located in the partial connection area 102 has a larger value to directly contact the first connection structure 117. Exemplarily, the material of the first connection structure 117 may be the same as that of the shielding structure 116, in which case the two may be an integral structure and have no obvious boundaries.

[0059] Reference again Figure 1A and Figure 1C , the first contact structure 118 extends along the direction D3 and is connected to the first connection structure 117. The first contact structure 118 and the shielding structure 116 are located on the same side of the first connection structure 117. In some embodiments, the first contact structure 118 may be substantially columnar, one end surface of which is in direct contact with the second portion 1172 of the first connection structure 117, and the other end surface of which is located on the side of the shielding structure 116 away from the first connection structure 117. In other words, the first contact structure 118 may extend to the second portion 1172 of the first connection structure 117.

[0060] According to the above description, the shielding structure 116 is located on the back side of the channel of the transistor (the side where the gate is not set), and a voltage (for example, a ground voltage) is applied to the shielding structure 116, for example, through the first contact structure 118 and the first connection structure 117, so as to improve the coupling effect between a column of transistors and another column of transistors arranged along the D1 direction.

[0061] In some exemplary embodiments, the first contact structure and the shielding structure are arranged non-overlappingly in the D3 direction, and the shielding structure is led out by additionally arranging a metal connection layer and a through contact. Compared with this exemplary embodiment, according to the semiconductor device provided by the above-mentioned embodiment of the present application, the first contact structure and the shielding structure are arranged on the same side of the first connection structure, which can simplify the manufacturing process of the first connection structure and the first contact structure for leading out the shielding structure, improve the process window, reduce the manufacturing difficulty, and help improve the yield and product performance of the semiconductor device.

[0062] In some embodiments, Figure 1A and 1B As shown, the semiconductor device 100 may further include a capacitor connection structure 119 and a capacitor. As described above, in addition to the transistor, the memory cell may also include a capacitor (not shown). For example, one transistor and one capacitor constitute a memory cell. The capacitor connection structure 119 may be connected to the end face of the semiconductor column (e.g., 111a) close to the first connection structure 117. For example, the capacitor connection structure 119 may be roughly columnar, one end face of which is in direct contact with the end face of the semiconductor column (e.g., 111a) close to the first connection structure 117, and the other end face of which may be connected to the capacitor so that the capacitor is connected to one of the source or drain of the transistor. For example, the size of the capacitor connection structure 119 in the D3 direction may be greater than the size of the first connection structure 117 in the D3 direction. Exemplarily, the material of the capacitor connection structure 119 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material.

[0063] In some embodiments, the capacitor may include a first electrode, an insulating layer, and a second electrode. The insulating layer may be located between the first electrode and the second electrode. The first electrode may be in direct contact with the capacitor connection structure 119. In some examples, the capacitor may be roughly columnar. The first electrode may be barrel-shaped with one end open, the second electrode may be columnar and located inside the first electrode, and the insulating layer is located between the first electrode and the second electrode. The closed end of the first electrode is in direct contact with the capacitor contact structure 119. In other examples, the first electrode, the insulating layer, and the second electrode may be stacked in sequence along the D3 direction. It should be noted that the present application does not limit the specific structure of the capacitor. In addition, the capacitor connection structure 119 and the capacitor may be the same as the number of semiconductor pillars (e.g., 111a) located in the storage area 101.

[0064] In some embodiments, the semiconductor device 100 may further include a bit line 120. The bit line 120 may be located on a side of the semiconductor column (e.g., 111a) away from the first connection structure 117, and connected to a row of semiconductor columns (e.g., 111a, 111b) arranged along D2. For example, the bit line 120 extends along the D2 direction in the storage area 101 and the connection area 102, and the ends of the row of semiconductor columns (e.g., 111a) arranged along D2 away from the first connection structure 117 may be connected to each other and directly contact the bit line 120. Thus, one of the source or drain of a row of transistors arranged along the D2 direction is connected to the same bit line 120. The number of the bit lines 120 may be multiple, and the multiple bit lines 120 may be arranged along the D1 direction. Exemplarily, the material of the bit line 120 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicide (e.g., silicide of one or more of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt)), or any other suitable conductive material.

[0065] In some embodiments, the semiconductor device 100 may further include a bit line contact structure 122. The bit line contact structure 122 and the first contact structure 118 are located on the same side of the first connection structure 117 and extend to the bit line 120. For example, the bit line contact structure 122 may be substantially columnar, one end surface of which is in direct contact with the bit line 120, and the other end surface of which is located on the side of the bit line 120 away from the first connection structure 117. For example, the bit line contact structure 122 may be located in the connection region 102, and each bit line 120 may be connected to one bit line contact structure 122. Exemplarily, the material of the bit line contact structure 122 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicide (e.g., silicide of one or more of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt)), or any other appropriate conductive material.

[0066] In some embodiments, the semiconductor device 100 may further include a word line contact structure 121. The word line contact structure 121 and the first contact structure 118 are located on the same side of the first connection structure 117 and extend to the word line 115. For example, the word line contact structure 121 may be substantially columnar, one end surface of which is in direct contact with the word line 115, and the other end surface of which is located on a side of the word line 115 away from the first connection structure 117. For example, the word line contact structure 121 may be located in the connection region 102, and each word line 115 may be connected to two word line contact structures 121, so that the first portion and the second portion of the word line 115 are respectively connected to one word line contact structure 121. Exemplarily, the material of the word line contact structure 121 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicide (e.g., silicide of one or more of titanium (Ti), cobalt (Co), nickel (Ni) and platinum (Pt)) or any other suitable conductive material. For example, the first contact structure 118 and the plurality of word line contact structures 121 are arranged approximately collinearly along the D2 direction.

[0067] In some embodiments, at least two of the surfaces of the first contact structure 118 away from the first connection structure 117, the surface of the bit line contact structure 122 away from the bit line 120, and the surface of the word line contact structure 121 away from the word line 115 are substantially flush (for example, with an error of less than ±10%). Thus, the first contact structure 118, the bit line contact structure 122, and the word line contact structure 121 can be formed in the same process from the side of the shielding structure 116 away from the first connection structure 117, thereby simplifying the manufacturing process, improving production efficiency, and reducing manufacturing costs.

[0068] In some embodiments, from the direction D3, the first contact structure 118, the bit line contact structure 122, and the word line contact structure 121 are all located in the connection region 102, and respectively serve as the lead-out structures of the shielding structure 116, the bit line 120, and the word line 115. The first contact structure 118, the bit line contact structure 122, and the word line contact structure 121 do not overlap with each other to avoid structural interference.

[0069] Figure 2 1 is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application. For the purpose of concise description, the same contents as the previous embodiment will not be repeated in the following embodiments.

[0070] like Figure 2 As shown, in the semiconductor device 200, the first connection structure 217 is located on one side of the shielding structure 216 along the D3 direction and is connected to the shielding structure 216. For example, the first connection structure 217 may be located in the connection area 202 (outside the dotted line frame). From the D3 direction, the first connection structure 217 may be rectangular and connected to multiple shielding structures 216. One end surface of the first contact structure 218 is in direct contact with the end of the first connection structure 217 in the D2 direction, and the other end surface is located on the side of the shielding structure 216 away from the first connection structure 217. In other words, the first contact structure 218 may extend to the end of the first connection structure 217 in the D2 direction. For example, the first contact structure 218 and the multiple bit line contact structures 222 are arranged approximately collinearly along the D1 direction.

[0071] Figure 3 FIG. 1 is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application. Figure 3As shown, in the semiconductor device 300, it may also include a second connection structure 324. The second connection structure 324 may be located on the surface of the first connection structure 317 away from the shielding structure 316. For example, the first connection structure 317 and the second connection structure 324 are both located in the connection area 302 (outside the dotted box). From the D3 direction, the first connection structure 317 may be rectangular and connected to a plurality of shielding structures 316. The second connection structure 324 is in direct contact with the first connection structure 317, and in the D1 direction, the second connection structure 324 extends in a direction away from the storage area 301. Optionally, the surface of the second connection structure 324 away from the first connection structure 317 is substantially flush with the end surface of the capacitor connection structure 319 away from the semiconductor column (e.g., 311a) (e.g., the error is less than ±10%), so that the second connection structure 324 and the capacitor connection structure 319 can be formed in the same process, thereby simplifying the manufacturing process. One end surface of the first contact structure 318 is in direct contact with the second connection structure 324, and the other end surface is located on the side of the shielding structure 316 away from the first connection structure 317. In other words, the first contact structure 318 extends to the second connection structure 324. For example, the first contact structure 318 and the plurality of word line contact structures 321 are arranged substantially collinearly along the D2 direction.

[0072] Figure 4 FIG. 1 is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application. Figure 4 As shown, in the semiconductor device 400, the second connection structure 424 may be located on the surface of the first connection structure 417 away from the shielding structure 416. For example, in the D2 direction, the end surface of the second connection structure 424 is substantially flush with the end surface of the first connection structure 417 (for example, the error is less than ±10%). One end surface of the first contact structure 418 is in direct contact with the first connection structure 417, and the other end surface is located on the side of the shielding structure 416 away from the first connection structure 417. In other words, the first contact structure 418 extends to the first connection structure 417. For example, the first contact structure 418 and the plurality of bit line contact structures 422 are arranged approximately collinearly along the D1 direction.

[0073] In some embodiments, in the direction D2, the end surface of the second connection structure 424 may protrude from the end surface of the first connection structure 417, and the first contact structure 418 extends to the second connection structure 424 (not shown).

[0074] An embodiment of the present application also provides a memory system. Figure 5 is a block diagram of a system with a memory system provided in an embodiment of the present application.

[0075] like Figure 5As shown, the system 500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has a memory system 510 located therein). Figure 5 As shown, system 500 may include a host 520 and a memory system 510. Memory system 510 has one or more memories 511 and a controller 512. Host 520 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 520 may be configured to send or receive data to and from memory 511.

[0076] In some embodiments, the controller 512 is coupled to the memory 511 and the host 520, and is configured to control the memory 511. For example, the controller 512 may be configured to control the memory 511 to perform operations such as reading, erasing, and programming. The controller 512 may also manage data stored in the memory 511 and communicate with the host 520. For example, the controller 512 may communicate with an external device (e.g., the host 520) according to a specific communication protocol.

[0077] An embodiment of the present application also provides a method for manufacturing a semiconductor device. Figure 6 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figure 6 As shown, a method 600 for manufacturing a semiconductor device (hereinafter referred to as manufacturing method 600 ) may include the following steps.

[0078] S610 , forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein each semiconductor pillar extends along a third direction.

[0079] S620 , forming a shielding structure extending along a first direction between adjacent semiconductor pillars, and forming a first connecting structure connected to the shielding structure on one side of the shielding structure along a third direction.

[0080] S630 , forming a first contact structure extending along a third direction from a first side of the semiconductor column away from the first connection structure, wherein the first contact structure is connected to the first connection structure.

[0081] According to the manufacturing method of the semiconductor device provided by this embodiment, by forming a first connection structure connected to the shielding structure on one side of the shielding structure along the third direction, and forming a first contact structure extending along the third direction from the first side of the semiconductor column away from the first connection structure and connected to the first connection structure, the manufacturing process of the first connection structure and the first contact structure for leading out the shielding structure can be simplified, the process window can be improved, the manufacturing difficulty can be reduced, and it is beneficial to improve the yield and product performance of the semiconductor device.

[0082] FIG. 7A to FIG. 18 is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present application. For example, FIG. 7A to FIG. 18 Can be used to form Figure 3 The semiconductor device 300 is shown. FIG. 7A to FIG. 18 as well as Figure 3 The above steps S610 to S630 are explained by way of example.

[0083] S610

[0084] Fig. 7A and Figure 7B An intermediate structure 700a including a semiconductor layer 731, a first dielectric layer 732 and a second dielectric layer 733 is shown. Fig. 7A is a schematic top view of the intermediate structure 700a. Figure 7B It is along Fig. 7A A schematic cross-sectional view taken along line BB' is shown.

[0085] In some embodiments, Fig. 7A and Figure 7B As shown, the semiconductor layer 731 may be a semiconductor substrate. For example, the material of the semiconductor substrate may be silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). For another example, the semiconductor substrate may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc.

[0086] In some embodiments, the material of the first dielectric layer 732 may include silicon oxide (SiO2), and the material of the second dielectric layer 733 may include silicon nitride (Si3N4). In some examples, the first dielectric layer 732 and the second dielectric layer 733 may be sequentially formed on the semiconductor layer 731 using a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other examples, the first dielectric layer 732 may be formed on the semiconductor layer 731 using a dry oxidation method or a wet oxidation method.

[0087] Fig. 8A and Figure 8B The intermediate structure 700b is shown after forming a plurality of semiconductor walls 734 and filling the insulating material 735. Fig. 8A is a schematic top view of the intermediate structure 700b. Figure 8B It is along Fig. 8A It should be noted that in order to more clearly show the spatial relationship between the components in the intermediate structure 700b, Fig. 8A The first dielectric layer 732 and the second dielectric layer 733 are omitted in the figure, and the same illustration method is used for similar top view schematic diagrams below.

[0088] In some embodiments, Fig. 8A and Figure 8B As shown, the semiconductor layer 731 may be patterned by photolithography and etching (e.g., dry etching and / or wet etching) processes to form a plurality of semiconductor walls 734 extending in the D2 direction and arranged in the D1 direction. For example, the second dielectric layer 733 may be used as a hard mask for etching the semiconductor layer 731. The semiconductor walls 734 and the unetched semiconductor layer 731 are arranged vertically in the D3 direction. Since the semiconductor walls 734 are formed by etching the semiconductor layer 731, the semiconductor walls 734 are made of the same material as the semiconductor layer 731. For example, from the D3 direction, the plurality of semiconductor walls 734 have the same size in the D2 direction, but their ends are not flush. Specifically, the ends of the odd-numbered semiconductor walls 734 are flush, and the ends of the even-numbered semiconductor walls 734 are flush. Further, a thin film deposition process of CVD, PVD, ALD, or any combination thereof may be used to fill the outer periphery of the plurality of semiconductor walls 734 with an insulating material 735 to electrically isolate adjacent semiconductor walls 734.

[0089] Fig.9A and Fig. 9B The intermediate structure 700c is shown after forming the first trench 736 and the initial second trench 737'. Fig.9A is a schematic top view of the intermediate structure 700c. Fig. 9B It is along Fig.9A A schematic cross-sectional view taken along line CC' is shown. Fig. 10A and Fig. 10B The intermediate structure 700d is shown after the first sacrificial material 738 is filled in the first trench 736 and the initial second trench 737'. Fig. 10A is a schematic top view of the intermediate structure 700d.

[0090] Fig. 10B It is along Fig. 10A A schematic cross-sectional view taken along line CC' is shown. Fig.11A and Fig. 11B The intermediate structure 700e is shown after removing the first sacrificial material 738 in the initial second trench 737'. Fig.11A is a schematic top view of the intermediate structure 700e. Fig. 11B It is along Fig.11A A schematic cross-sectional view taken along line CC' is shown. Fig. 12A and Fig. 12B The intermediate structure 700f after forming the second trench 737 is shown. Fig. 12A 700f is a top view of the intermediate structure. Fig. 12B It is along Fig. 12A A schematic cross-sectional view taken along line CC' is shown.

[0091] In some embodiments, Fig.9A and Fig. 9B As shown, the semiconductor wall 734 and the insulating material 735 formed on the semiconductor layer 731 can be patterned by photolithography and etching (for example, dry etching and / or wet etching) processes to form a first trench 736 and an initial second trench 737' both extending along the D1 direction, and the plurality of semiconductor walls 734 (refer to Fig. 8A ) is divided into a plurality of initial semiconductor pillars 711'. The first trenches 736 and the initial second trenches 737' are alternately arranged in the D2 direction. For example, the size of the first trench 736 in the D2 direction may be equal to the size of the initial second trench 737' in the D2 direction. For another example, the size of the first trench 736 in the D1 direction may be smaller than the size of the initial second trench 737' in the D1 direction, and the two ends of the plurality of first trenches 736 in the D1 direction are substantially flush (for example, the error is less than ±10%), and the two ends of the plurality of initial second trenches 737' in the D1 direction are substantially flush (for example, the error is less than ±10%). The end of the first trench 736 in the D1 direction is indented relative to the end of the initial second trench 737' in the D1 direction.

[0092] Next, in some embodiments, as Fig. 10A and Fig. 10B As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the first trench 736 and the initial second trench 737' with a first sacrificial material 738. For example, the first sacrificial material 738 may include polysilicon (Poly), carbon (Carbon), spin-on-carbon (SOC), spin-on-dielectric material (Spin-on-Dielectric) or any other appropriate sacrificial material.

[0093] Then, in some embodiments, a mask material layer (e.g., a photoresist layer and / or a hard mask layer) may be covered on the top surface of the intermediate structure 700d, and the initial second trench 737' may be exposed by patterning. Further, an etching process (e.g., dry etching and / or wet etching) may be used to remove the first sacrificial material 738 in the initial second trench 737', and the first sacrificial material layer 738 in the first trench 736 may be retained, such as Fig.11A and Fig. 11B shown.

[0094] Next, in some embodiments, Fig. 12A and Fig. 12B As shown, an etching (e.g., wet etching) process may be used to increase the size of the initial second trench 737' in the D2 direction to form a second trench 737 having a larger size in the D2 direction. Optionally, in the process of increasing the size of the initial second trench 737' in the D2 direction, the size of the initial second trench 737' in the D3 direction may also increase. For example, the depths of the first trench 736 and the second trench 737 are both less than the semiconductor wall 734 (refer to Fig. 8A ) in the direction D3. Thus, the ends of the semiconductor pillars 711 arranged along the direction D2 can be connected to each other through the semiconductor walls 734 that are not etched.

[0095] According to the above, if Fig. 12A and Fig. 12B As shown, the first trench 736 and the second trench 737 separate the plurality of semiconductor walls 734 (refer to Fig. 8A ) is divided into a plurality of semiconductor pillars 711. The semiconductor pillars 711 and the unetched semiconductor layer 731 are arranged vertically in the D3 direction. Since the semiconductor pillars 711 are formed by etching the semiconductor layer 731, the semiconductor pillars 711 and the semiconductor layer 731 are made of the same material. For example, on a plane perpendicular to the D3 direction, the intermediate structure 700f may include a storage area 701 (in a dotted box) and a connection area 702 (outside a dotted box) located at the periphery of the storage area 701. Among them, the first trench 736 and the second trench 737 extend (for example, continuously extend) in the storage area 701 and the storage area 701.

[0096] It should be noted that, although the method of forming the second groove 737 by increasing the size of the initial second groove 737' in the D2 direction is described in detail above, the present application does not specifically limit the method of forming the second groove 737. For example, the second groove 737 may be directly formed by patterning. Fig. 12A and Fig. 12B The first groove 736 and the second groove 737 are shown. In addition, the size relationship between the first groove 736 and the second groove 737 in the direction D2 is not specifically limited in this application.

[0097] Fig.13A and Fig. 13B The intermediate structure 700g is shown after the initial gate dielectric layer 714' and the initial word line 715' are formed. Fig.13A It is a schematic cross-sectional view of the intermediate structure 700g taken in a direction perpendicular to D1. Fig. 13B It is along Fig.13A A schematic cross-sectional view taken along line DD' is shown.

[0098] In some embodiments, FIG. 12A to FIG. 13B As shown, when the second trench 737 is in an unfilled state, a thin film deposition process such as CVD, PVD, ALD or any combination thereof, or an oxidation method (for example, a dry oxidation method or a wet oxidation method) may be used to form an initial gate dielectric layer 714' on the inner wall of the second trench 737. Since the second trench 737 may expose the second sidewall of the semiconductor pillar 711 perpendicular to the direction D2, the initial gate dielectric layer 714' may be formed on the second sidewall of the semiconductor pillar 711.

[0099] Then, continue to refer to Fig.13A and Fig. 13B , an initial adhesion layer 7151' and an initial metal layer 7152' may be sequentially formed on the surface of the initial gate dielectric layer 714' by a thin film deposition process of CVD, PVD, ALD or any combination thereof. The initial adhesion layer 7151' and the initial metal layer 7152' may serve as an initial word line 715'. Optionally, an etching process (e.g., dry etching and / or wet etching) may be used to remove a portion of the initial word line 715' away from the semiconductor layer 731, so that the surface of the initial word line 715' away from the semiconductor layer 731 is lower than the surface of the semiconductor pillar 711 away from the semiconductor layer 731. Next, an insulating material may be filled on the top of the initial word line 715' by a thin film deposition process of CVD, PVD, ALD or any combination thereof.

[0100] In some embodiments, Fig. 13B As shown, an etching (e.g., dry etching and / or wet etching) process may be used to form a cutout 723 that penetrates the initial word line 715' and the initial gate dielectric layer 714'. Optionally, the cutout 723 may only penetrate the initial word line 715' without etching the initial gate dielectric layer 714'. For example, the cutout 723 may be filled with a material such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the cutout 723 is used to divide the annular (from the direction D3) initial word line 715' into a first part and a second part, and to electrically isolate the first part and the second part in the storage area 701.

[0101] S620

[0102] Fig.14A and Fig. 14B The intermediate structure 700h after forming the conductive layer 739 and the photoresist layer 740 is shown. Fig.14A 700h is a top view schematic diagram of the intermediate structure. Fig. 14B It is along Fig.14A A schematic cross-sectional view taken along line EE' is shown. FIG. 15A to FIG. 15C The intermediate structure 700i is shown after the shielding structure 716 and the first connecting structure 717 are formed. Fig.15A It is a top view schematic diagram of the intermediate structure 700i. Fig. 15B It is along Fig.15A A schematic cross-sectional view taken along line CC' is shown. Fig. 15C It is along Fig.15A A schematic cross-sectional view taken along line EE' is shown.

[0103] In some embodiments, FIG. 13A to FIG. 14B As shown in FIG. 1 , after forming the initial gate dielectric layer 714' and the initial word line 715', the first sacrificial material 738 in the first trench 736 can be removed. Further, a thin film deposition process of CVD, PVD, ALD or any combination thereof can be used to form a conductive layer 739 in the first trench 736 and on one side (hereinafter referred to as the second side) of the plurality of semiconductor pillars 711. The conductive layer 739 in the first trench 736 can serve as a shielding structure 716. Further, a photoresist can be spin-coated on the top surface of the conductive layer 739, and the photoresist can be patterned using a photolithography process to form a conductive layer 739 as shown in FIG. Fig.14A The photoresist layer 740 is shown. Subsequently, the photoresist layer 740 is used as a masking layer, and an etching (e.g., dry etching and / or wet etching) process is used to remove a portion of the conductive layer 739 formed on the second side of the plurality of semiconductor pillars 711 (e.g., a portion not covered by the photoresist layer 740). The retained conductive layer 739 can be used as the first connection structure 717, such as Fig.15A As shown. The first connection structure 717 may be connected to (eg, directly contacted with) the plurality of shielding structures 716 in the direction D3. Optionally, during the formation of the first connection structure 717, a portion of the shielding structure 716 close to the second side of the semiconductor pillar 711 may be removed to align with the word line 715 to be formed (see FIG. Figure 3 ) in the D3 direction.

[0104] Fig.16A and Fig. 16B The intermediate structure 700j after forming the insulating layer 741 is shown. Fig.16A It is a top view schematic diagram of the intermediate structure 700j. Fig. 16B It is along Fig.16A A schematic cross-sectional view taken along line EE' is shown. 17A to 17C The intermediate structure 700k is shown after forming the capacitor connection structure 719 and the second connection structure 724. Fig. 17B It is along Fig.17A A schematic cross-sectional view taken along line CC' is shown. Fig. 17C It is along Fig.17A A schematic cross-sectional view taken along line EE' is shown.

[0105] In some embodiments, Fig.16A and Fig. 16B As shown, the insulating layer 741 may be formed on the second side of the plurality of semiconductor pillars 711 by a thin film deposition process of CVD, PVD, ALD or any combination thereof. For example, the surface of the insulating layer 741 away from the semiconductor layer 731 is substantially flush (for example, with an error of less than ±10%). For example, the material of the insulating layer 741 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. 17A to 17C As shown, an etching (e.g., dry etching and / or wet etching) process and a thin film deposition process can be used to form a capacitor connection structure 719 extending to the semiconductor pillar 711. Optionally, in the process of forming the capacitor connection structure 719, a second connection structure 724 can be formed on the surface of the first connection structure 717 away from the shielding structure 716. In other words, the second connection structure 724 and the capacitor connection structure 719 can be formed in the same process to simplify the process and save manufacturing costs. In this embodiment, from the D3 direction, the second connection structure 724 can extend along the D1 direction.

[0106] Fig.18 is a cross-sectional view of the intermediate structure 7001 after forming the capacitor 742. In some embodiments, as Fig.18 As shown, capacitor 742 can be formed at the end of capacitor connection structure 719 away from semiconductor pillar 711 by any process known in the art. For example, capacitor 742 is formed in storage area 701. As described above, capacitor 742 can be implemented in various structural forms, not limited to Fig.18 Columnar shape shown.

[0107] S630

[0108] In some embodiments, Fig.18 The intermediate structure 7001 is shown flipped 180° to move away from the semiconductor pillar 711 and away from the first connection structure 717 (see FIG. Fig. 17B ) is subjected to subsequent processing on one side (hereinafter referred to as the first side).

[0109] like Fig.18 As shown, in some embodiments, the semiconductor layer 731 may be planarized by a CMP process. Then, an etching process (e.g., dry etching and / or wet etching) may be used to remove a portion of the initial gate dielectric layer 714' and the initial word line 715' away from the capacitor 742, so that the initial word line 715' is disconnected in the direction D2, thereby forming a gate dielectric layer 314 and a word line 315, as shown in FIG. Figure 3 Optionally, Figure 3 As shown, during the formation of the word line 315, an etching (eg, dry etching and / or wet etching) process may be used to remove a portion of the shielding structure 316 away from the capacitor (not shown) to match the dimensions of the shielding structure 316 and the word line 315 in the direction D3.

[0110] In some embodiments, continue to refer to Figure 3 , the bit line 320 can be formed by photolithography and etching processes and thin film deposition processes. For example, the bit line 320 extends along the direction D2 and is connected to the semiconductor wall 734 (refer to Fig. 8A ) are directly in contact with the unetched portion, thereby connecting the bit line 320 to a plurality of semiconductor pillars (eg, 311a) arranged along the direction D2.

[0111] In some embodiments, a photolithography and etching process and a thin film deposition process may be used to form a bit line contact structure 322 extending to the bit line 320, a word line contact structure 321 extending to the word line 315, and a first contact structure 318 extending to the second connection structure 324 from the first side of the semiconductor pillar (e.g., 311a). The first contact structure 318 is in direct contact with the second connection structure 324, and is connected to the first connection structure 317 through the second connection structure 324. Optionally, at least two of the first contact structure 318, the bit line contact structure 322, and the word line contact structure 321 may be formed in the same process.

[0112] FIG. 19A to FIG. 19C FIG. 8 shows an intermediate structure 800k after forming a capacitor connection structure 819 and a second connection structure 824 in another embodiment. Fig.19B It is along Fig.19A A schematic cross-sectional view taken along line CC' is shown. Fig.19C It is along Fig.19A A schematic cross-sectional view taken along line EE' is shown.

[0113] like FIG. 19A to FIG. 19CAs shown, an etching (e.g., dry etching and / or wet etching) process and a thin film deposition process can be used to form a capacitor connection structure 819 extending to the semiconductor pillar 811. Optionally, in the process of forming the capacitor connection structure 819, a second connection structure 824 can be formed on the surface of the first connection structure 817 away from the shielding structure 816. In other words, the second connection structure 824 and the capacitor connection structure 819 can be formed in the same process to simplify the process and save manufacturing costs. In this embodiment, from the D3 direction, the second connection structure 824 can extend along the D2 direction.

[0114] It should be noted that in the method described above, the step of forming the second connection structure can be omitted, so that the first contact structure extends to the first connection structure so as to connect the two by directly contacting the first connection structure. This application does not impose any specific restrictions on this.

[0115] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that: include: A plurality of semiconductor pillars are arranged in an array along a first direction and a second direction, and each of the semiconductor pillars extends along a third direction; A shielding structure, located between adjacent semiconductor pillars and extending along the first direction; A first connecting structure, located at one side of the shielding structure along the third direction and connected to the shielding structure; as well as a first contact structure extending along the third direction and connected to the first connecting structure; The first contact structure and the shielding structure are located on the same side of the first connecting structure, and the first direction, the second direction and the third direction intersect with each other.

2. The semiconductor device according to claim 1, wherein Also includes: The second connection structure is located on a surface of the first connection structure away from the shielding structure, wherein the first contact structure extends to the second connection structure.

3. The semiconductor device according to claim 2, wherein: Also includes: A capacitor connection structure connected to an end surface of the semiconductor column close to the first connection structure; The end surface of the capacitor connection structure away from the semiconductor column is substantially flush with the surface of the second connection structure away from the first connection structure.

4. The semiconductor device according to claim 3, wherein: Also includes: The capacitor is connected to the end surface of the capacitor connection structure away from the semiconductor column.

5. The semiconductor device according to claim 1, wherein The first contact structure extends to the first connecting structure.

6. The semiconductor device according to claim 1, wherein The first connecting structure extends along the second direction and directly contacts the plurality of shielding structures arranged along the second direction.

7. The semiconductor device according to claim 6, wherein: On a plane perpendicular to the third direction, the semiconductor device includes a storage area and a connection area located at the periphery of the storage area, the first connection structure extends in the connection area, and the first contact structure is located in the connection area.

8. The semiconductor device according to claim 1, wherein The semiconductor pillar has a first sidewall close to the shielding structure, and a second sidewall opposite to the first sidewall; The semiconductor device further comprises: a gate dielectric layer, located on the second side wall of the semiconductor column; a word line, located on a surface of the gate dielectric layer and extending along the first direction; and The word line contact structure is located on the same side of the first connection structure as the first contact structure and extends to the word line.

9. The semiconductor device according to claim 8, wherein: Also includes: A bit line, located at a side of the semiconductor column away from the first connection structure and connected to a plurality of the semiconductor columns arranged along the second direction; as well as The bit line contact structure is located on the same side of the first connection structure as the first contact structure and extends to the bit line.

10. The semiconductor device according to claim 9, wherein At least two of a surface of the first contact structure away from the first connection structure, a surface of the bit line contact structure away from the bit line, and a surface of the word line contact structure away from the word line are substantially flush.

11. The semiconductor device according to claim 10, wherein: On a plane perpendicular to the third direction, the semiconductor device includes a storage area and a connection area located outside the storage area, and the first contact structure, the word line contact structure and the bit line contact structure are located in the connection area and do not overlap with each other.

12. A memory system, characterized in that: include: A memory comprising a semiconductor device according to any one of claims 1 to 11; as well as The controller is coupled to the memory and is used to control the memory to store data.

13. A method for manufacturing a semiconductor device, characterized in that: include: Forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein each of the semiconductor pillars extends along a third direction; forming a shielding structure extending along a first direction between adjacent semiconductor pillars, and forming a first connecting structure connected to the shielding structure on one side of the shielding structure along the third direction; and forming a first contact structure extending along the third direction from a first side of the semiconductor column away from the first connection structure, wherein the first contact structure is connected to the first connection structure; The first direction, the second direction and the third direction intersect with each other.

14. The manufacturing method according to claim 13, wherein: Also includes: forming a second connection structure on a surface of the first connection structure away from the shielding structure; Wherein, forming a first contact structure extending along the third direction from a first side of the semiconductor column away from the first connection structure comprises: The first contact structure is formed to extend to the second connection structure.

15. The manufacturing method according to claim 14, wherein: Also includes: forming a capacitor connection structure extending to the semiconductor column from a second side of the semiconductor column opposite to the first side; Wherein, the second connection structure and the capacitor connection structure are formed in the same process.

16. The manufacturing method according to claim 13, wherein: Forming a first contact structure extending along the third direction from a first side of the semiconductor column away from the first connection structure comprises: The first contact structure is formed to extend to the first connection structure.

17. The manufacturing method according to claim 13, wherein: The semiconductor pillar has a first sidewall close to the shielding structure and a second sidewall opposite to the first sidewall; The manufacturing method further comprises: forming a gate dielectric layer on the second sidewall of the semiconductor column; forming a word line extending along the first direction on a surface of the gate dielectric layer; and A word line contact structure extending to the word line is formed from the first side of the semiconductor pillar.

18. The manufacturing method according to claim 17, wherein: Also includes: forming a bit line extending along the second direction on the first side of the semiconductor pillar, wherein the bit line is connected to a plurality of the semiconductor pillars arranged along the second direction; A bit line contact structure extending to the bit line is formed on the first side of the semiconductor pillar.

19. The manufacturing method according to claim 18, wherein: At least two of the first contact structure, the bit line contact structure and the word line contact structure are formed in the same process.

20. The manufacturing method according to claim 13, wherein: Forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction comprises: Etching the semiconductor layer to form a plurality of semiconductor walls arranged along the first direction, wherein the semiconductor walls extend along the second direction; Filling an insulating material around the plurality of semiconductor walls; and The plurality of semiconductor walls and the insulating material are etched to form first trenches and second trenches alternately arranged along the second direction, thereby dividing the plurality of semiconductor walls into the plurality of semiconductor pillars, wherein the first trenches and the second trenches both extend along the first direction.

21. The manufacturing method according to claim 20, wherein: Forming a shielding structure extending along a first direction between adjacent semiconductor pillars, and forming a first connecting structure connected to the shielding structure on one side of the shielding structure along the third direction comprises: forming the shielding structure in the first trench; forming a conductive layer on a second side of the plurality of semiconductor pillars opposite to the first side; A portion of the conductive layer is etched so that the remaining conductive layer serves as the first connecting structure and directly contacts the shielding structure.

22. The manufacturing method according to claim 21, wherein: Etching a portion of the conductive layer so that the remaining conductive layer serves as the first connecting structure and directly contacts the shielding structure further comprises: A portion of the shielding structure adjacent to the second side of the semiconductor pillar is removed.

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