Semiconductor structure, preparation method of semiconductor structure and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method of the semiconductor structure and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; a first circuit is formed on the substrate, a conductive interconnection structure is formed on the first circuit, and the conductive interconnection structure is electrically connected with the first circuit; a stacking layer is formed on the conductive interconnection structure, the stacking layer comprises an isolation layer and a conductive layer which are alternately stacked, and a device through hole penetrating through the isolation layer and the conductive layer is formed in the stacking layer; sequentially forming a channel material layer, a gate dielectric material layer and a first word line material layer on the hole wall of the device through hole; forming a through hole which penetrates through the first word line material layer, the gate dielectric material layer and the channel material layer at the bottom of the device through hole and extends to the conductive interconnection structure; and forming a second word line layer in the through hole and the device through hole above the through hole. According to the invention, the integration level can be improved, and the device performance can be ensured.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor structure, a method for preparing the semiconductor structure, and an electronic device that can both improve integration and ensure device performance.

[0005] A method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a first circuit on the substrate, and forming a conductive interconnection structure on the first circuit, wherein the conductive interconnection structure is electrically connected to the first circuit;

[0008] Forming a stacking layer on the conductive interconnect structure, the stacking layer comprising an isolation layer and a conductive layer stacked alternately, and forming a device through hole penetrating the isolation layer and the conductive layer in the stacking layer, wherein the device through hole overlaps with the orthographic projection of the conductive interconnect structure on the substrate;

[0009] Sequentially forming a channel material layer, a gate dielectric material layer and a first word line material layer on the hole wall of the device through hole;

[0010] Forming a through hole that penetrates the first word line material layer, the gate dielectric material layer and the channel material layer at the bottom of the device through hole and extends to the conductive interconnect structure, the remaining first word line material layer forms a first word line layer, the remaining gate dielectric material layer forms a gate dielectric layer, and the remaining channel material layer forms a channel layer;

[0011] A second word line layer is formed in the remaining space in the through hole and the device through hole.

[0012] In the method for preparing the semiconductor structure, the first circuit (such as a peripheral logic circuit) is fabricated below the storage array, which can effectively save the area of ​​the chip and is conducive to improving the integration density of the device. At the same time, before etching the channel material layer to form a through hole extending to the conductive interconnect structure, a channel material layer, a gate dielectric material layer and a first word line material layer are sequentially formed on the hole wall of the device through hole. Then, the first word line material layer, the gate dielectric material layer and the channel material layer are sequentially etched. At this time, in the process of forming the through hole, the first word line layer formed by the remaining first word line material layer after etching can be used as a protective layer to protect the channel material layer from damage during the dry etching process. And the first word line layer does not need to be removed, so the channel layer will not be damaged when the protective layer is removed, so the channel layer and the gate dielectric layer can be effectively protected, thereby ensuring the performance of the device.

[0013] In one of the embodiments, before forming the first word line material layer, the gate dielectric material layer and the channel material layer penetrating the bottom of the device through hole and extending to the through hole of the conductive interconnect structure, the method further includes:

[0014] The first word line material layer located at a top of the device through hole is at least partially etched.

[0015] In one embodiment, forming a stacked layer on the conductive interconnect structure includes:

[0016] forming a stacking initial layer on the conductive interconnect structure, wherein the stacking initial layer comprises alternately stacked isolation material layers and sacrificial material layers;

[0017] forming a dummy word line hole penetrating the stacked initial layer, and forming a dummy word line in the dummy word line hole;

[0018] Performing a patterning process on the stacked initial layer after forming the dummy word line to form an isolation trench, the remaining isolation material layer forms the isolation layer, and the remaining sacrificial material layer forms a sacrificial layer;

[0019] Removing the sacrificial layer by etching the self-isolation trench;

[0020] forming the conductive material layer in the sacrificial layer removal area, and forming a filling dielectric layer in the isolation trench;

[0021] The dummy word line is removed, and the conductive material layer is laterally etched from the dummy word line hole to form a lateral hole, wherein the lateral hole and the dummy word line hole form the device through hole, and the remaining conductive material layer forms the conductive layer.

[0022] In one of the embodiments, after a channel material layer, a gate dielectric material layer and a first word line material layer are sequentially formed on the hole wall of the device through hole, the lateral hole is filled.

[0023] In one embodiment,

[0024] Before forming the stacking initial layer on the conductive interconnect structure, the method further includes:

[0025] forming an insulating dielectric layer on the conductive interconnect structure;

[0026] The forming of a dummy word line hole penetrating the stacked initial layer and forming a dummy word line in the dummy word line hole comprises:

[0027] Using the insulating dielectric layer as an etching barrier layer, etching the stacked initial layer to form a pseudo word line hole;

[0028] The dummy word line is formed in the dummy word line hole.

[0029] In one embodiment, the stacked initial layer is patterned after forming the pseudo word line, and after forming the isolation trench, the stacked initial layer has a first main stem extending along a first direction and a first branch located on at least one side of the first main stem along a second direction, the pseudo word line runs through the first branch, and the first direction intersects with the second direction and is parallel to the substrate.

[0030] In one embodiment, the patterning of the stacked initial layer after forming the dummy word line and before forming the isolation trench further comprises:

[0031] A support layer is formed which penetrates the stacking initial layer and extends along the first direction, and the support layer is located on a side of the first branch portion away from the first trunk portion.

[0032] In one embodiment, the side of the pseudo word line away from the first trunk portion has a capacitor region, and the capacitor region is spaced apart from the pseudo word line.

[0033] Before removing the dummy word line and laterally etching the conductive material layer from the dummy word line hole to form the lateral hole, the method further includes:

[0034] removing the isolation layer located in the capacitor region to expose the conductive material layer;

[0035] A capacitor dielectric layer and a capacitor external electrode layer are sequentially formed around the outer peripheral surface of the conductive material layer located in the capacitor region.

[0036] A semiconductor structure comprising:

[0037] substrate;

[0038] A first circuit, located on the substrate;

[0039] A stacking layer, located on a side of the first circuit away from the substrate, comprising alternately stacked isolation layers and conductive layers;

[0040] A transistor structure, comprising a channel layer, a gate dielectric layer, a first word line layer and a second word line layer, wherein the second word line layer penetrates the stacked layer and is electrically connected to the first circuit, the first word line layer is located in the stacked layer and at least partially covers the side wall of the second word line layer, the gate dielectric layer and the channel layer are located in the stacked layer, and the gate dielectric layer is located on a side of the first word line layer away from the second word line layer, and the channel layer is located on a side of the gate dielectric layer away from the first word line layer, and is located between the gate dielectric layer and the conductive layer.

[0041] The semiconductor structure has a first word line layer in the stacked layer, and the first word line layer is located between the second word line layer 5 and the gate dielectric layer. Therefore, in the process of forming the second word line layer electrically connected to the first circuit, the first word line layer can well protect the channel layer and the gate dielectric layer, thereby improving device performance.

[0042] In one embodiment, an orthographic projection of the bottom of the second word line layer on the substrate is surrounded by an orthographic projection of the bottom of the first word line layer on the substrate.

[0043] In one embodiment, the semiconductor structure further includes a conductive interconnect structure, wherein the conductive interconnect structure is located between the first circuit and the stacked layer and electrically connects the first circuit and the second word line layer.

[0044] In one of the embodiments, an orthographic projection of a bottom portion of the second word line layer on the substrate is located within an orthographic projection of a top portion of the second word line layer on the substrate.

[0045] In one embodiment, the first word line layer has a protruding portion protruding in a direction away from the second word line layer, the protruding portion is located between adjacent isolation layers and overlaps with the conductive layer in a direction perpendicular to the substrate.

[0046] In one embodiment, the semiconductor structure further includes an insulating dielectric layer located on a side of the conductive interconnect structure away from the substrate, the stacked layer is located on a side of the insulating dielectric layer away from the substrate, and the second word line layer penetrates the stacked layer and the insulating dielectric layer.

[0047] In one embodiment, the stacked layer has a second main body extending along a first direction and a second branch located on at least one side of the second main body along a second direction, the transistor structure runs through the second branch, and the first direction intersects with the second direction and is parallel to the substrate.

[0048] In one embodiment, the semiconductor structure further comprises:

[0049] The support layer is located on a side of the second branch portion away from the second main portion, penetrates the stacking layer and extends along the first direction.

[0050] In one embodiment, the transistor structure has a capacitor region on a side away from the second main body, the capacitor region is spaced apart from the transistor structure, the capacitor region is provided with a capacitor dielectric layer and a capacitor external electrode layer, the capacitor dielectric layer is located on the outer peripheral surface of the conductive layer, and the capacitor external electrode layer is located on the outer peripheral surface of the capacitor dielectric layer.

[0051] An electronic device comprises the semiconductor structure mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0054] Figures 2 to 14 Schematic diagram of the structure obtained in each step of the method for preparing a semiconductor structure provided in an embodiment, wherein: Fig.11 for Fig.10 The enlarged view of the dotted box A, where Fig.13 for Fig.12 An enlarged view of the portion B in the dashed box;

[0055] Fig.15 is a schematic structural diagram of a semiconductor structure provided in an embodiment;

[0056] Fig.16 for Fig.15 An enlarged view of the portion C in the dashed box;

[0057] Fig.17 for Fig.15 Enlarged view of the dashed box D.

[0058] Description of the accompanying drawings: 100-substrate, 200-first circuit, 300-conductive interconnection structure, 310-first interconnection structure, 320-rewiring layer, 330-second interconnection structure, 400-stacked layer, 400a-second main stem, 400b-second branch, 410-isolation layer, 4101-isolation material layer, 420-conductive layer, 4201-conductive material layer, 4001-stacked initial layer, 4001a-first main stem, 4001b-first branch, 430-sacrificial layer, 4301-sacrificial material layer, 500-transistor structure, 510-channel layer, 5101-channel material layer, 520 -gate dielectric layer, 5201-gate dielectric material layer, 530-first word line layer, 5301-first word line material layer, 531-protrusion, 540-second word line layer, 550-pseudo word line, 610-first dielectric layer, 620-second dielectric layer, 630-third dielectric layer, 640-filling dielectric layer, 700-insulating dielectric layer, 800-support layer, 900-capacitor, 910-capacitor dielectric layer, 920-capacitor external electrode layer, 10-device through hole, 11-pseudo word line hole, 12-lateral hole, 13-through hole, 20-isolation trench, 30-first photoresist, 40-hard mask layer, 50-third patterned photoresist. DETAILED DESCRIPTION

[0059] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0061] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0062] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0063] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] In some embodiments, see Figure 1 , a method for preparing a semiconductor structure is provided, comprising the following steps:

[0065] Step S10, providing a substrate 100;

[0066] Step S20, forming a first circuit 200 on the substrate 100, and forming a conductive interconnection structure 300 on the first circuit 200, wherein the conductive interconnection structure 300 is electrically connected to the first circuit 200;

[0067] Step S30, forming a stacking layer 400 on the conductive interconnect structure 300, wherein the stacking layer 400 includes an isolation layer 410 and a conductive layer 420 that are alternately stacked, and forming a device through hole 10 that penetrates the isolation layer 410 and the conductive layer 420 in the stacking layer 400, wherein the device through hole 10 and the conductive interconnect structure 300 have an overlapped orthographic projection on the substrate;

[0068] Step S40, forming a channel material layer 5101, a gate dielectric material layer 5201 and a first word line material layer 5301 in sequence on the hole wall of the device through hole 10;

[0069] Step S60, forming a first word line material layer 5301, a gate dielectric material layer 5201 and a channel material layer 5101 penetrating the bottom of the device through hole 10 and extending to the through hole 13 of the conductive interconnect structure 300, the remaining first word line material layer 5301 forms a first word line layer 530, the remaining gate dielectric material layer 5201 forms a gate dielectric layer 520, and the remaining channel material layer 5101 forms a channel layer 510;

[0070] In step S70 , a second word line layer 540 is formed in the remaining space in the through hole 13 and the device via 10 .

[0071] In step S10, refer to Figure 2 The substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 is a multi-layer structure, it may include a semiconductor substrate and other structures or film layers formed on the semiconductor substrate.

[0072] In step S20, please continue to refer to Figure 2 The first circuit 200 may be, for example, a peripheral logic circuit. The peripheral logic circuit may include a complementary metal oxide semiconductor (CMOS) circuit.

[0073] The conductive interconnect structure 300 may be formed in one or more dielectric layers covering the first circuit 200, and is used to electrically connect the first circuit 200 with the subsequently formed second word line layer 540. At the same time, while forming the conductive interconnect structure 300 electrically connecting the first circuit 200 with the subsequently formed second word line layer 540, other conductive connection structures connecting the first circuit 200 with the bit lines of the memory array above it and the capacitor external electrode layer 920 may also be formed.

[0074] For example, see Figures 2 to 3 , step S20 may include:

[0075] Step S21, forming a first circuit 200 on the substrate 100;

[0076] Step S22, forming a first interconnect structure 310 on the first circuit 200;

[0077] Step S23, forming a redistribution layer 320 on the first interconnect structure 310;

[0078] In step S24 , a second interconnect structure 330 is formed on the redistribution layer 320 . The second interconnect structure 330 , the redistribution layer 320 , and the first interconnect structure 310 form a conductive interconnect structure 300 .

[0079] In step S21, the substrate 100 may include, for example, a semiconductor substrate and a shallow trench isolation structure. At this time, when forming the first circuit 200 (such as a peripheral logic circuit), the semiconductor substrate may be doped to form a P-well region 110 and an N-well region 120. And a shallow trench isolation structure 130 may be formed in the semiconductor substrate. The shallow trench isolation structure may separate the semiconductor substrate into a plurality of active regions. The transistors in the first circuit 200 (such as transistors in a CMOS circuit) may be formed based on the active region processing.

[0080] In step S22, a first dielectric layer 610 may be formed to cover the first circuit 200 and the substrate 100. Then, a first interconnect structure 310 connected to the first circuit 200 is formed through the first dielectric layer 610. The first interconnect structure 310 may be connected to one of the drain or source of a transistor in a CMOS circuit, for example.

[0081] In step S23, a second dielectric layer 620 may be first formed on the first dielectric layer 610 and the first interconnect structure 310. Then, a trench penetrating the second dielectric layer may be formed, and a conductive material may be filled in the trench, thereby forming a redistribution layer 320 connected to the first interconnect structure 310 through a Damascene process.

[0082] In step S24, a third dielectric layer 630 may be first formed on the second dielectric layer 620 and the redistribution layer 320. Then, a second interconnect structure 330 connected to the redistribution layer 320 is formed through the third dielectric layer 630. The second interconnect structure 330, the redistribution layer 320, and the first interconnect structure 310 form a conductive interconnect structure 300, so that the conductive interconnect structure 300 is electrically connected to the first circuit 200.

[0083] Of course, the form of the conductive interconnect structure 300 is not limited here. For example, the conductive interconnect structure 300 may also include only the first interconnect structure 310. Alternatively, when forming the redistribution layer 320, the second dielectric layer 620 may not be formed. In this case, a redistribution material layer may be formed first. Then, a process such as photolithography is performed on it to achieve patterning, thereby forming the redistribution layer 320.

[0084] In step S30, refer to Fig. 9 , a stacked layer 400 may be formed on the conductive interconnect structure 300 and the dielectric layer where it is located. As an example, the top film layer and the bottom film layer of the stacked layer 400 may both be isolation layers 410 , and the conductive layer 420 is located between the isolation layers 410 .

[0085] The material of the isolation layer 410 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0086] The material of the conductive layer 420 may include but is not limited to tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0087] The device via 10 formed in the stacked layer 400 may be used to form a transistor structure 500 .

[0088] In step S40, refer to Figure 10 to Figure 11 , a channel material layer 5101 may be first formed on the hole wall of the device through hole 10 and the upper surface of the structure obtained by the previous process steps. Then, a gate dielectric material layer 5201 is formed on the surface of the channel material layer 5101. Then, a first word line material layer 5301 is formed on the surface of the gate dielectric material layer 5201.

[0089] Furthermore, the channel material layer 5101, the gate dielectric material layer 5201 and the first word line material layer 5301 may be formed by, but not limited to, a deposition process. The deposition process may include, but is not limited to, a chemical vapor deposition process (CVD) and an atomic layer deposition process (ALD).

[0090] Meanwhile, the material of the channel material layer 5101 may include but is not limited to indium gallium zinc oxide (IGZO) and the like. The material of the gate dielectric material layer 5201 may include but is not limited to high dielectric constant layers such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The material of the first word line material layer 5301 may include but is not limited to indium tin oxide (ITO) and the like.

[0091] In step S60, refer to Fig.14 , the first word line material layer 5301, the gate dielectric material layer 5201 and the channel material layer 5101 at the bottom of the device trench can be etched away in sequence by dry etching, and a through hole 13 exposing the conductive interconnect structure 300 is formed. The through hole 13 is connected to the device through hole 10.

[0092] The first word line layer 530 formed by the remaining first word line material layer 5301 after etching can serve as a protective layer to protect the channel material layer 5101 from damage during the dry etching process. The first word line layer 530 does not need to be removed, so the channel layer 510 will not be damaged when removing the protective layer.

[0093] In step S70, refer to Fig.15 First, a second word line material layer may be formed in the through hole 13, the remaining space in the device through hole 10, and the upper surface of the structure outside the device through hole 10. Then, the second word line material layer formed outside the device through hole 10 may be removed by chemical mechanical polishing (CMP) to form a second word line layer 540.

[0094] As an example, see Fig.16 as well as Fig.17 Before forming the second word line material layer in the through hole 13, the remaining space in the device through hole 10, and the upper surface of the structure outside the device through hole 10, the channel layer 510 and the gate dielectric layer 520 opposite to the isolation layer 410 can be removed, or the channel layer 510 opposite to the isolation layer 410 can be removed to prevent the formation of parasitic transistors between adjacent conductive layers 420.

[0095] When removing the channel layer 510 and the gate dielectric layer 520 located on the side wall of the isolation layer 410, a side-excavated groove may be first formed in the stacked layer 400. Then, the isolation layer 410 is etched sideways from the side-excavated groove to expose the channel layer 510 opposite to the isolation layer. Afterwards, the channel layer 510 may be etched sideways to remove the channel layer 510 opposite to the isolation layer 410. Optionally, the gate dielectric layer 520 may be further etched sideways to remove the gate dielectric layer 520 opposite to the isolation layer 410. Afterwards, the isolation layer material may be refilled in the etched side-excavated area of ​​the isolation layer 400, the etched side-excavated area of ​​the channel layer 510, and the etched side-excavated area of ​​the gate dielectric layer 520 to form a new isolation layer 410. Afterwards, the second word line layer 540 is formed in the remaining space in the through hole 13 and the device through hole 10.

[0096] At this time, the second word line layer 540 and the first word line layer 530 together form the word line of the transistor, please refer to Fig.17 , the width of the word line of the transistor above the bottom isolation layer 410 is L2, which is the sum of the widths of the second word line layer 540 and the first word line layer 530. The width of the word line of the transistor below the bottom isolation layer 410 and the width of the part of the word line of the transistor below the stacked layer 400 (such as the part located in the insulating dielectric layer 700) is L1, which is the width of the second word line layer 540. Therefore, L2 is greater than L1.

[0097] The material of the second word line layer 540 and the material of the first word line layer 530 may be the same (for example, both are ITO), or may be different.

[0098] As an example, the material of the second word line layer 540 is the same as that of the first word line layer 530. At this time, while removing the second word line material layer formed outside the device through hole 10 by chemical mechanical polishing (CMP), the first word line layer 530 outside the device through hole 10 can be removed simultaneously.

[0099] The second word line layer 540, the first word line layer 530, the gate dielectric layer 520 and the channel layer 510 may together form a transistor structure 500. When the stacked layer 400 includes n layers of conductive layers 420, the same transistor structure 500 may include n stacked switch transistors in a memory array, where n is a positive integer. The conductive layers 420 on both sides of the transistor structure 500 are connected to the channel layer 510 of the transistor structure 500, thereby forming the source and drain of each switch transistor.

[0100] In this embodiment, the first circuit 200 (such as a peripheral logic circuit) is fabricated below the memory array, which can effectively save the chip area and is conducive to improving the integration density of the device. At the same time, before etching the channel material layer 5101 to form a through hole 13 extending to the conductive interconnect structure 300, a channel material layer 5101, a gate dielectric material layer 5201 and a first word line material layer 5301 are sequentially formed on the hole wall of the device through hole 10. Then, the first word line material layer 5301, the gate dielectric material layer 5201 and the channel material layer 5101 are sequentially etched. At this time, in the process of forming the through hole 13, the first word line layer 530 formed by the first word line material layer 5301 remaining after etching can be used as a protective layer to protect the channel material layer 5101 from damage during the dry etching process. And the first word line layer 530 does not need to be removed, so the channel layer 510 will not be damaged when the protective layer is removed. Therefore, in this embodiment, the channel layer 510 and the gate dielectric layer 520 can be effectively protected, thereby ensuring the device performance.

[0101] In some embodiments, see Figure 12 to Figure 13 , before step S60, further comprising:

[0102] Step S50 , at least partially etching the first word line material layer 5301 located on the top of the device through hole 10 .

[0103] At this time, after the second word line layer 540 is formed in the through hole 13 in a subsequent step, the orthographic projection of the bottom of the second word line layer 540 on the substrate 100 is located within the orthographic projection of the top of the second word line layer 540 on the substrate 100 .

[0104] As an example, after the first word line material layer 5301 is formed, the first photoresist 30 may be coated on the remaining space of the device through hole 10 and the upper surface of the first word line material layer 5301. Then, the first photoresist 30 is exposed and developed to remove the first photoresist 30 at the top of the device through hole 10, thereby exposing the first word line material layer 5301 at the top of the device through hole 10. Afterwards, the first word line material layer 5301 at the top of the device through hole 10 may be etched by steam etching. During etching, the first word line material layer 5301 at the top may be partially etched away, or the first word line material layer 5301 may be completely etched away, as long as the space at the top of the device through hole is enlarged. At this time, the remaining space of the device through hole 10 is enlarged at the top, so that it is convenient to etch the through hole 13 in step S60.

[0105] In some embodiments, step S30 includes:

[0106] Step S302, see Figure 3, forming a stacking initial layer 4001 on the conductive interconnect structure 300 , wherein the stacking initial layer 4001 includes alternately stacked isolation material layers 4101 and sacrificial material layers 4301 ;

[0107] Step S304, see Figure 3 , forming a pseudo word line hole 11 penetrating the stacked initial layer 4001, and forming a pseudo word line 550 in the pseudo word line hole 11;

[0108] Step S306, see Figure 6 , the stacked initial layer 4001 after forming the dummy word line 550 is patterned to form an isolation trench 20, the remaining isolation material layer 4101 forms an isolation layer 410, and the remaining sacrificial material layer 4301 forms a sacrificial layer 430;

[0109] Step S308 , etching and removing the sacrificial layer 430 from the isolation trench 20 ;

[0110] Step S310, see Figure 7 , forming a conductive material layer 4201 in the removed area of ​​the sacrificial layer 430 , and forming a filling dielectric layer 640 in the isolation trench 20 ;

[0111] Step S312, see Fig. 9 , remove the dummy word line 550 , and laterally etch the conductive material layer 4201 from the dummy word line hole 11 to form a lateral hole 12 , the lateral hole 12 and the dummy word line hole 11 form a device through hole 10 , and the remaining conductive material layer 4201 forms a conductive layer 420 .

[0112] In step S302, refer to Figure 3 When forming the stack initial layer 4001, the isolation material layer 4101 and the sacrificial material layer 4301 can be repeatedly and alternately formed through a deposition process.

[0113] The material of the isolation material layer 4101 may include but is not limited to silicon oxide (SiO 2 ), and the material of the sacrificial material layer 4301 may include but is not limited to silicon nitride (Si 3 N 4 ).

[0114] In step S304, refer to Figure 3 , a dummy word line hole 11 may be first formed in the stacked initial layer 4001 by a photolithography process, and then a dummy word line 550 may be filled in the dummy word line hole 11 .

[0115] Specifically, a second patterned photoresist may be first formed on the stacked initial layer 4001. The second patterned photoresist has a second opening. The second opening may define the size and position of the dummy word line hole 11. Then, based on the second patterned photoresist, the stacked initial layer 4001 is dry-etched, etc., to form the dummy word line hole 11. Afterwards, the second patterned photoresist may be removed.

[0116] Then, a dummy word line 550 material (such as polysilicon) may be formed on the upper surface of the stacked initial layer 4001 and in the dummy word line hole 11 through a deposition process. Then, the dummy word line 550 material on the upper surface of the stacked initial layer 4001 may be removed through a chemical mechanical polishing (CMP) process, and the dummy word line 550 material remaining in the dummy word line hole 11 may be formed.

[0117] In step S306, refer to Figure 6 The stacked initial layer 4001 after forming the dummy word line 550 can be patterned by a photolithography process to form an isolation trench 20 penetrating the stacked initial layer 4001. The isolation trench 20 exposes the sidewalls of each isolation layer 410 and each sacrificial layer 430 formed after etching.

[0118] In step S308, the wet etching solution can flow to the sacrificial layer 430 through the isolation trench 20 to remove it. At this time, the dummy word line 550 can support the structure of each isolation layer 410 during the process of removing the sacrificial layer 430.

[0119] In step S310, refer to Figure 7 First, a conductive material layer 4201 may be formed on the surface of the structure obtained after removing the sacrificial layer 430 by a process such as atomic layer deposition. Then, a surface planarization process may be performed by chemical mechanical polishing (CMP) to remove the conductive material layer 4201 located on the upper surface of the top isolation layer 410. Thereafter, the conductive material layer 4201 located in the isolation trench 20 may be removed by dry etching. Thereafter, a filling material layer may be formed to fill the isolation trench 20, and a surface planarization process may be performed by chemical mechanical polishing (CMP) to remove the filling material layer located outside the top isolation trench 20, thereby forming a filling dielectric layer 640 located in the isolation trench 20.

[0120] The material filling the dielectric layer 640 may include, but is not limited to, silicon oxide (SiO 2 ). For example, the material filling the dielectric layer 640 may also be silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0121] It is understandable that the drawings in the specification are drawn by taking the material of the filling dielectric layer 640 as the same as the material of the isolation layer 410 as an example. However, the material of the filling dielectric layer 640 and the material of the isolation layer 410 are not limited to be the same, and the two can also be different.

[0122] In step S312, refer to Fig. 9, the pseudo word line 550 can be removed by dry etching. At this time, the conductive material layer 4201 located on the side wall of the pseudo word line hole 11 is exposed. Then, the conductive material layer 4201 can be wet-etched laterally from the pseudo word line hole 11 to form a lateral hole 12. The lateral hole 12 is connected to the pseudo word line hole 11, and the two form a device through hole 10. In addition, the conductive material layer 4201 remaining after etching forms a conductive layer 420.

[0123] In this embodiment, a stacked initial layer 4001 including alternately stacked isolation material layers 4101 and sacrificial material layers 4301 is first formed. Then the sacrificial layer 430 is removed through the isolation trench 20. Then the conductive layer 420 is formed in the area where the sacrificial layer 430 is removed. Before the isolation trench 20 is formed to remove the sacrificial layer 430, a pseudo word line 550 is formed to penetrate the stacked initial layer 4001, so that the structure of each layer of the isolation layer 410 can be supported during the process of removing the sacrificial layer 430. After the conductive layer 420 is formed, the pseudo word line 550 is removed, that is, the device through hole 10 can be formed based on the pseudo word line hole 11, which facilitates the formation of the device through hole 10.

[0124] In other embodiments, the stacked layer 400 may be formed in a different manner. For example, the alternately stacked isolation layer 410 and the conductive layer 420 may be directly formed, and after the alternately stacked isolation layer 410 and the conductive layer 420 are formed, etching is performed to form the device through hole 10 penetrating the isolation layer 410 and the conductive layer 420.

[0125] In some embodiments, see Figure 10 to Figure 11 After step S40, the lateral hole 12 is filled. At this time, the first word line layer 530 has a protruding portion 531 away from the second word line portion, so that the first word line layer 530 (especially the first word line layer 530 at a position opposite to the conductive layer 420) can be ensured to have a sufficient thickness.

[0126] At this time, in the process of etching the gate dielectric material layer 5201 and the channel material layer 5101, the first word line layer 530 located on the side wall of the gate dielectric material layer 5201 will not be etched through, thereby providing good protection for the gate dielectric layer 520 and the channel layer 510, and preventing the gate dielectric layer 520 and the channel layer 510 from being damaged in the process of forming the through hole 13.

[0127] Of course, in other embodiments, after forming the first word line material layer 5301, the lateral hole 12 may not be filled. In this case, the first word line material layer 5301 may be formed with a preset thickness to ensure that it will not be etched through during the process of forming the through hole 13, thereby providing good protection for the gate dielectric layer 520 and the channel layer 510. The preset thickness may be greater than 30 nm, for example.

[0128] In some embodiments, see Figure 3 , before step S302, further comprising:

[0129] Step S301 , forming an insulating dielectric layer 700 on the conductive interconnect structure 300 .

[0130] At this time, in step S302 , a stacking initial layer 4001 is formed on the insulating dielectric layer 700 .

[0131] Meanwhile, step S304 includes:

[0132] Step S3041, using the insulating dielectric layer 700 as an etching barrier layer, etching the stacked initial layer 4001 to form a dummy word line hole 11;

[0133] In step S3042 , a dummy word line 550 is formed in the dummy word line hole 11 .

[0134] The material of the insulating dielectric layer 700 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). At the same time, the material of the insulating dielectric layer 700 is different from the material of the isolation layer 410, so that it can be used as an etching barrier when etching the stacked initial layer 4001. For example, when the material of the isolation layer 410 includes silicon oxide (SiO2), the material of the insulating dielectric layer 700 may include silicon carbon nitride (SiCN).

[0135] The provision of the insulating dielectric layer 700 can effectively prevent the underlying structure (such as the conductive interconnect structure 300 ) from being damaged when etching the stacked initial layer 4001 .

[0136] It can be understood that at this time, when the through hole 13 is formed in step S60, a through hole 13 can be formed that penetrates the first word line material layer 5301, the gate dielectric material layer 5201, the channel material layer 5101 and the insulating dielectric layer 700 at the bottom of the device through hole 10, so that the through hole 13 extends to the conductive interconnect structure 300.

[0137] In some embodiments, see Figure 6After the isolation trench 20 is formed after step S306, the stacked initial layer 4001 may have a first main body 4001a and a first branch 4001b. The first main body 4001a extends along the first direction. The first branch 4001b is located on at least one side of the first main body 4001a along the second direction. The first direction intersects with the second direction and is parallel to the substrate. As an example, the first branch 4001b may be located on opposite sides of the first main body 4001a along the second direction. There may be a plurality of first branch 4001b on the same side of the first main body 4001a along the second direction. And the first branch 4001b located on opposite sides of the first main body 4001a along the second direction are symmetrically arranged.

[0138] Meanwhile, the dummy word line 550 formed in step S304 runs through the first branch portion 4001 b , and each first branch portion 4001 b may have a dummy word line 550 therein.

[0139] At this time, see Figure 7 , after the sacrificial layer 430 is removed in a subsequent step and the stacked layer 400 is formed by replacing the sacrificial layer 430 with the conductive layer 420, the first main body 4001a can be converted into the second main body 400a, and the first branch 4001b can be converted into the second branch 400b. That is, the stacked layer 400 has a second main body 400a and a second branch 400b. The second main body 400a extends along the first direction. The second branch 400b is located on at least one side of the second main body 400a along the second direction. As an example, the second branch 400b can be located on opposite sides of the second main body 400a along the second direction. On the same side of the second main body 400a along the second direction, there can be a plurality of second branches 400b. And the second branches 400b located on opposite sides of the second main body 400a along the second direction are symmetrically arranged.

[0140] Meanwhile, after the dummy word line 550 is removed in a subsequent step and the transistor structure 500 is formed in the device through hole 10 , each second branch 400 b has a transistor structure 500 including a multi-layer switch transistor.

[0141] The conductive layer 420 in the second trunk 400a can be used as a bit line, and the conductive layer 420 in the second branch 400b located on both sides of the switch transistor can be used as the source and drain of the switch transistor, so that the bit line is connected to the switch transistor. When the second branch 400b is located on two opposite sides of the second trunk 400a along the second direction, the same bit line can supply power to the switch transistors of the memory cells located on both sides thereof.

[0142] In some embodiments, see Figure 5 , before step S306, it also includes:

[0143] Step S305 , forming a support layer 800 that penetrates the stacked initial layer 4001 and extends along the first direction, wherein the support layer 800 is located on a side of the first branch portion 4001 b away from the first trunk portion 4001 a .

[0144] Specifically, see Figure 4 After forming the dummy word line 550 in the stack initial layer 4001 in step S304, a hard mask layer 40 may be deposited on the stack initial layer 4001. The hard mask layer 40 may include one or more film layers. Then, a third patterned photoresist 50 may be formed on the hard mask layer 40. The third patterned photoresist 50 has a third opening. The third opening may define the size and position of the support layer 800, etc.

[0145] Then, based on the third patterned photoresist 50, the stacked initial layer 4001 is dry-etched, etc., so as to form a supporting hole. When the stacked initial layer 4001 is formed on the insulating dielectric layer 700, the insulating dielectric layer 700 can be used as an etching barrier. Afterwards, the third patterned photoresist 50 can be removed.

[0146] As an example, see Figure 5 After forming the supporting hole, the isolation material layer 4101 in the stacked initial layer 4001 can be laterally etched back from the supporting hole to form a supporting side hole. Then, a supporting layer 800 can be formed in the supporting hole and the supporting side hole.

[0147] The support layer 800 can play a supporting role together with the dummy word line 550 in the process of removing the sacrificial layer 430 and replacing the sacrificial layer 430 with the conductive layer 420 in the subsequent step.

[0148] The material of the support layer 800 may include, but is not limited to, silicon oxynitride (SiON), for example, silicon oxide (SiO2) or silicon nitride (Si3N4).

[0149] In some embodiments, a side of the dummy word line 550 away from the first trunk portion 4001 a has a capacitor region, and the capacitor region is spaced apart from the dummy word line 550 .

[0150] Before step S312, please refer to Figure 8 , also includes:

[0151] Step S3111, removing the isolation layer 410 located in the capacitor region to expose the conductive material layer 4201;

[0152] In step S3112, a capacitor dielectric layer 910 and a capacitor external electrode layer 920 are sequentially formed around the outer peripheral surface of the conductive material layer 4201 located in the capacitor region.

[0153] In step S3111, a fourth patterned photoresist may be formed on the surface of the structure obtained after forming the filling dielectric layer. The fourth patterned photoresist has a fourth opening. The fourth opening may define the size and position of the capacitor region.

[0154] Then, based on the fourth patterned photoresist, the isolation layer 410 located in the capacitor region is dry-etched to remove the isolation layer 410 between the conductive material layers 4201 adjacent along the first direction. Afterwards, the isolation layer 410 between the conductive material layers 4201 adjacent along the stacking direction is wet-etched laterally, thereby completely removing the isolation layer 410 in the capacitor region. At this point, the conductive material layer 4201 in the capacitor region is exposed. The exposed conductive material layer 4201 can be used as an inner electrode layer of the capacitor. Therefore, the inner electrode layer of the capacitor and the bit line can be connected to both sides of the switch transistor respectively.

[0155] In step S3112, a capacitor dielectric layer 910 may be formed on the outer peripheral surface of the exposed conductive material layer 4201 located in the capacitor region. Then, a capacitor outer electrode layer 920 is formed on the outer peripheral surface of the capacitor dielectric layer 910. The capacitor outer electrode layer 920, the capacitor dielectric layer 910, and the capacitor inner electrode layer (the conductive material layer 4201 located in the capacitor region) together form a capacitor 900. The capacitor 900 and the switch transistor together form a storage unit.

[0156] As an example, the material of the capacitor dielectric layer 910 may include, but is not limited to, a high dielectric constant layer such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The material of the capacitor external electrode layer 920 may include, but is not limited to, polycrystalline silicon, etc.

[0157] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0158] In some embodiments, see Fig.15 as well as Fig.16, a semiconductor structure is also provided, which includes a substrate 100, a first circuit 200, a conductive interconnect structure 300, a stacked layer 400 and a transistor structure 500.

[0159] The substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 is a multi-layer structure, it may include a semiconductor substrate and other structures or film layers formed on the semiconductor substrate.

[0160] The first circuit 200 is located on the substrate 100 . The first circuit 200 may be, for example, a peripheral logic circuit. The peripheral logic circuit may include a complementary metal oxide semiconductor (CMOS) circuit, and may be formed based on the substrate 100 .

[0161] As an example, the base 100 may include a semiconductor substrate. The semiconductor substrate may include a P-well region and an N-well region. A shallow trench isolation structure (STI) may be provided in the semiconductor substrate. The shallow trench isolation structure may separate the semiconductor substrate into a plurality of active regions. The transistors in the first circuit 200 (such as transistors in a CMOS circuit) may be formed based on the active region processing.

[0162] The conductive interconnect structure 300 is located on a side of the first circuit 200 away from the substrate 100 and is electrically connected to the first circuit 200 .

[0163] As an example, the conductive interconnect structure 300 may include a first interconnect structure 310 , a redistribution layer 320 , and a second interconnect structure 330 . Meanwhile, the semiconductor structure may also include a first dielectric layer 610 , a second dielectric layer 620 , and a third dielectric layer 630 .

[0164] The first dielectric layer 610 may cover the first circuit 200 and the substrate 100. The first interconnect structure 310 may penetrate the first dielectric layer 610 and be connected to the first circuit 200. For example, the first interconnect structure 310 may be connected to one of the drain or source of a transistor in a CMOS circuit.

[0165] The second dielectric layer 620 may cover the first dielectric layer 610 and the first interconnect structure 310. The redistribution layer 320 is located in the second dielectric layer 620 and connected to the first interconnect structure 310.

[0166] The third dielectric layer 630 may cover the second dielectric layer 620 and the redistribution layer 320. The second interconnect structure 330 may penetrate the third dielectric layer 630 and be connected to the redistribution layer 320. The second interconnect structure 330, the redistribution layer 320, and the first interconnect structure 310 form a conductive interconnect structure 300, so that the conductive interconnect structure 300 is electrically connected to the first circuit 200.

[0167] The stacked layer 400 is located on a side of the conductive interconnect structure 300 away from the substrate.

[0168] Meanwhile, the stacked layer 400 includes alternately stacked isolation layers 410 and conductive layers 420. As an example, the top film layer and the bottom film layer of the stacked layer 400 may both be isolation layers 410, and the conductive layers 420 are located between the isolation layers 410.

[0169] The material of the isolation layer 410 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0170] The material of the conductive layer 420 may include, but is not limited to, tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0171] The transistor structure 500 includes a channel layer 510 , a gate dielectric layer 520 , a first word line layer 530 and a second word line layer 540 .

[0172] The second word line layer 540 penetrates the stacked layer 400 and extends to the conductive interconnect structure 300 , so that the conductive interconnect structure 300 electrically connects the second word line layer 540 and the first circuit 200 .

[0173] Of course, in other embodiments, the conductive interconnect structure 300 may not be provided, and the second word line layer 540 may be provided to directly connect the first circuit 200, and the stacked layer 400 may be located on the side of the first circuit 200 away from the substrate 100. At this time, in the preparation process of the semiconductor structure, in step S20, after the first circuit is formed on the substrate 100, an isolation dielectric layer covering the first circuit may be directly formed. In step S30, a stacked layer is formed on the isolation dielectric layer, and a device through hole penetrating the isolation layer and the conductive layer 420 is formed in the stacked layer. Then, in step S60, a first word line material layer 5301, a gate dielectric material layer 5201, and a channel material layer 5101 are formed to penetrate the bottom of the device through hole 10 and extend to the through hole 13 of the first circuit 200.

[0174] The first word line layer 530 is located in the stacked layer 400 and at least partially covers a sidewall of the second word line layer 540 .

[0175] The gate dielectric layer 520 and the channel layer 510 are located in the stacked layer 400 . The gate dielectric layer 520 is located on the side of the first word line layer 530 away from the second word line layer 540 , and the channel layer 510 is located on the side of the gate dielectric layer 520 away from the first word line layer 530 and between the gate dielectric layer 520 and the conductive layer 420 .

[0176] As an example, the first word line layer 530 may completely surround the second word line layer 540. At this time, the gate dielectric layer 520 completely surrounds the first word line layer 530, and the channel layer 510 completely surrounds the gate dielectric layer 520.

[0177] As another example, the first word line layer 530 may also partially surround the second word line layer 540 . In this case, the gate dielectric layer 520 partially surrounds the first word line layer 530 , and the channel layer 510 partially surrounds the gate dielectric layer 520 .

[0178] Alternatively, the first word line layer 530 may also be in other forms.

[0179] As another example, the second word line layer 540 is a cubic columnar structure, and the first word line layer 530 is a columnar structure located between the gate dielectric layer 520 and one side of the second word line layer 540. Correspondingly, the gate dielectric layer 520 is a columnar structure between the channel layer 510 and the first word line layer 530, and the channel layer 510 is a columnar structure located between the stacked layer 400 and the gate dielectric layer 520.

[0180] At this time, in the preparation process of the semiconductor structure, for example, it can be set that: the device through hole 10 can be a square hole; at the same time, when the through hole is formed in step 60, the first word line material layer 5301, the gate dielectric material layer 5201 and the channel material layer 5101 on one of the side walls of the device through hole 10 are retained, and the first word line material layer 5301, the gate dielectric material layer 5201 and the channel material layer 5101 on the remaining side walls of the device through hole and the bottom of the device through hole 10 are removed.

[0181] The material of the second word line layer 540 may be the same as that of the first word line layer 530 (for example, both are ITO). Of course, the two may also be different. For example, the material of the second word line layer 540 includes tungsten or copper, and the material of the first word line layer includes ITO or IZO.

[0182] The material of the channel layer 510 may include but is not limited to indium gallium zinc oxide (IGZO), etc. The material of the gate dielectric layer 520 may include but is not limited to high dielectric constant layers such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0183] The second word line layer 540, the first word line layer 530, the gate dielectric layer 520 and the channel layer 510 may together form a transistor structure 500. When the stacked layer 400 includes n layers of conductive layers 420, the same transistor structure 500 may include n stacked switch transistors in a memory array, where n is a positive integer. The conductive layers 420 on both sides of the transistor structure 500 are connected to the channel layer 510 of the transistor structure 500, thereby forming the source and drain of each switch transistor.

[0184] In this embodiment, a first word line layer 530 is provided in the stacked layer 400, and the first word line layer 530 is located between the second word line layer 540 and the gate dielectric layer 520. Therefore, in the process of forming the second word line layer 540 electrically connected to the first circuit, such as the process of forming the second word line layer 540 connected to the conductive interconnect structure 300, the first word line layer 530 can well protect the channel layer 510 and the gate dielectric layer 520, thereby improving the device performance.

[0185] In some embodiments, an orthographic projection of a bottom portion of the second word line layer 540 on the substrate 100 is surrounded by an orthographic projection of a bottom portion of the first word line layer 530 on the substrate 100 .

[0186] At this time, the first word line layer 530 formed earlier is used to protect the channel layer 510, and the second word line layer 540 is formed inside the first word line layer 530, so it has the above structural features and can improve the stability of the channel layer.

[0187] In some embodiments, an orthographic projection of a bottom portion of the second word line layer 540 on the substrate 100 is located within an orthographic projection of a top portion of the second word line layer 540 on the substrate 100 .

[0188] At this time, the top size of the second word line layer 540 is large, so that the second word line layer 540 is easily formed.

[0189] As an example, at this time, the top of the second word line layer 540 may directly contact the sidewall of the gate dielectric layer 520 .

[0190] In some embodiments, the first word line layer 530 has a protrusion 531 protruding in a direction away from the second word line layer. The protrusion 531 is located between adjacent isolation layers 410 and overlaps with the conductive layer in a direction perpendicular to the substrate.

[0191] At this time, the first word line layer 530 can better protect the channel layer 510 and the gate dielectric layer 520 during the process of forming the second word line layer 540, thereby improving device performance.

[0192] In some embodiments, the semiconductor structure further includes an insulating dielectric layer 700 located on a side of the conductive interconnect structure 300 away from the substrate 100. The stacking layer 400 is located on a side of the insulating dielectric layer 700 away from the substrate 100. The second word line layer 540 penetrates the stacking layer 400 and the insulating dielectric layer 700.

[0193] As an example, the insulating dielectric layer 700 may be located on the upper surface of the second interconnect structure 330 and the upper surface of the third dielectric layer 630 . At this time, the stacked layer 400 may be located on the upper surface of the insulating dielectric layer 700 .

[0194] The material of the insulating dielectric layer 700 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). At the same time, the material of the insulating dielectric layer 700 is different from the material of the isolation layer 410. For example, when the material of the isolation layer 410 includes silicon oxide (SiO2), the material of the insulating dielectric layer 700 may include silicon carbonitride (SiCN). At this time, during the preparation of the semiconductor structure, the insulating dielectric layer 700 may serve as an etching stop layer during the etching of the stacked layer 400.

[0195] In some embodiments, the stacked layer 400 has a second main body 400a extending along a first direction and a second branch portion 400b located on at least one side of the second main body 400a along a second direction, and the transistor structure 500 passes through the second branch portion 400b. The first direction intersects with the second direction and is parallel to the substrate.

[0196] As an example, the second branch portions 400b may be located on two opposite sides of the second trunk portion 400a along the second direction. A plurality of second branch portions 400b may be provided on the same side of the second trunk portion 400a along the second direction. The second branch portions 400b located on two opposite sides of the second trunk portion 400a along the second direction are symmetrically arranged.

[0197] Each second branch 400 b has a transistor structure 500 including a multi-layer switch transistor.

[0198] The conductive layer 420 in the second trunk 400a can be used as a bit line. The conductive layer 420 located on both sides of the switch transistor in the second branch 400b can be used as the source and drain of the switch transistor, so that the bit line is connected to the switch transistor. When the second branch 400b is located on two opposite sides of the second trunk 400a along the second direction, the same bit line can supply power to the switch transistors of the memory cells located on both sides thereof.

[0199] In some embodiments, the semiconductor structure further includes a support layer 800. The support layer 800 is located on a side of the second branch portion 400b away from the second trunk portion 400a. Meanwhile, the support layer 800 penetrates the stacked layer 400 and extends along the first direction.

[0200] The material of the support layer 800 may include, but is not limited to, silicon oxynitride (SiON), for example, silicon oxide (SiO2) or silicon nitride (Si3N4).

[0201] In some embodiments, a side of the transistor structure 500 away from the second main body 400a has a capacitor region, and the capacitor region is spaced apart from the transistor structure 500. The capacitor region is provided with a capacitor dielectric layer 910 and a capacitor external electrode layer 920. The capacitor dielectric layer 910 is located on the outer peripheral surface of the conductive layer 420, and the capacitor external electrode layer 920 is located on the outer peripheral surface of the capacitor dielectric layer 910.

[0202] As an example, the material of the capacitor dielectric layer 910 may include, but is not limited to, a high dielectric constant layer such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The material of the capacitor external electrode layer 920 may include, but is not limited to, polycrystalline silicon, etc.

[0203] At this time, the conductive layer 420 located in the capacitor region can be used as the capacitor internal electrode layer. Therefore, the capacitor internal electrode layer and the bit line can be connected to the two sides of the switch transistor respectively.

[0204] The capacitor outer electrode layer 920, the capacitor dielectric layer 910 and the capacitor inner electrode layer (the conductive layer 420 located in the capacitor region) together form a capacitor 900. The capacitor 900 and the switch transistor together form a storage unit.

[0205] In some embodiments, an electronic device is also provided, which includes the semiconductor structure in the above embodiments, and the electronic device includes but is not limited to a storage device, a computer, a mobile phone, a television, a display, a notebook, and the like.

[0206] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0207] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0208] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first circuit on the substrate, and forming a conductive interconnection structure on the first circuit, wherein the conductive interconnection structure is electrically connected to the first circuit; Forming a stacking layer on the conductive interconnect structure, the stacking layer comprising an isolation layer and a conductive layer stacked alternately, and forming a device through hole penetrating the isolation layer and the conductive layer in the stacking layer, wherein the device through hole overlaps with the orthographic projection of the conductive interconnect structure on the substrate; Sequentially forming a channel material layer, a gate dielectric material layer and a first word line material layer on the hole wall of the device through hole; Forming a through hole that penetrates the first word line material layer, the gate dielectric material layer and the channel material layer at the bottom of the device through hole and extends to the conductive interconnect structure, the remaining first word line material layer forms a first word line layer, the remaining gate dielectric material layer forms a gate dielectric layer, and the remaining channel material layer forms a channel layer; A second word line layer is formed in the remaining space in the through hole and the device through hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the first word line material layer, the gate dielectric material layer and the channel material layer penetrating the bottom of the device through hole and extending to the through hole of the conductive interconnect structure, the method further includes: The first word line material layer located at a top of the device through hole is at least partially etched.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of a stacking layer on the conductive interconnect structure comprises: forming a stacking initial layer on the conductive interconnect structure, wherein the stacking initial layer comprises alternately stacked isolation material layers and sacrificial material layers; forming a dummy word line hole penetrating the stacked initial layer, and forming a dummy word line in the dummy word line hole; Performing a patterning process on the stacked initial layer after forming the dummy word line to form an isolation trench, the remaining isolation material layer forms the isolation layer, and the remaining sacrificial material layer forms a sacrificial layer; Etching the self-isolation trench to remove the sacrificial layer; forming the conductive material layer in the sacrificial layer removal area, and forming a filling dielectric layer in the isolation trench; The dummy word line is removed, and the conductive material layer is laterally etched from the dummy word line hole to form a lateral hole, wherein the lateral hole and the dummy word line hole form the device through hole, and the remaining conductive material layer forms the conductive layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: After the channel material layer, the gate dielectric material layer and the first word line material layer are sequentially formed on the hole wall of the device through hole, the lateral hole is filled.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: Before forming the stacking initial layer on the conductive interconnect structure, the method further includes: forming an insulating dielectric layer on the conductive interconnect structure; The forming of a dummy word line hole penetrating the stacked initial layer and forming a dummy word line in the dummy word line hole comprises: Using the insulating dielectric layer as an etching barrier layer, etching the stacked initial layer to form a pseudo word line hole; The dummy word line is formed in the dummy word line hole.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that: The stacked initial layer is subjected to a graphical processing after the pseudo word line is formed. After the isolation groove is formed, the stacked initial layer has a first main body extending along a first direction and a first branch portion located on at least one side of the first main body portion along a second direction. The pseudo word line runs through the first branch portion. The first direction intersects with the second direction and is parallel to the substrate.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The patterning of the stacked initial layer after forming the dummy word line and before forming the isolation trench further comprises: A support layer is formed which penetrates the stacking initial layer and extends along the first direction, and the support layer is located on a side of the first branch portion away from the first trunk portion.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that: The side of the pseudo word line away from the first trunk portion has a capacitor region, and the capacitor region is spaced apart from the pseudo word line. Before removing the dummy word line and laterally etching the conductive material layer from the dummy word line hole to form the lateral hole, the method further includes: removing the isolation layer located in the capacitor region to expose the conductive material layer; A capacitor dielectric layer and a capacitor external electrode layer are sequentially formed around the outer peripheral surface of the conductive material layer located in the capacitor region.

9. A semiconductor structure, characterized in that: include: substrate; A first circuit, located on the substrate; A stacking layer, located on a side of the first circuit away from the substrate, comprising alternately stacked isolation layers and conductive layers; A transistor structure includes a channel layer, a gate dielectric layer, a first word line layer and a second word line layer, wherein the second word line layer runs through the stacked layers and is electrically connected to the first circuit, the first word line layer is located in the stacked layers and at least partially covers the sidewall of the second word line layer, the gate dielectric layer and the channel layer are located in the stacked layers, and the gate dielectric layer is located on a side of the first word line layer away from the second word line layer, and the channel layer is located on a side of the gate dielectric layer away from the first word line layer, and is located between the gate dielectric layer and the conductive layer.

10. The semiconductor structure according to claim 9, characterized in that: An orthographic projection of the bottom of the second word line layer on the substrate is surrounded by an orthographic projection of the bottom of the first word line layer on the substrate.

11. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further includes a conductive interconnect structure, which is located between the first circuit and the stacked layer and electrically connects the first circuit and the second word line layer.

12. The semiconductor structure according to claim 9, characterized in that: An orthographic projection of a bottom portion of the second word line layer on the substrate is located within an orthographic projection of a top portion of the second word line layer on the substrate.

13. The semiconductor structure according to claim 9, characterized in that: The first word line layer has a protruding portion protruding in a direction away from the second word line layer, the protruding portion is located between adjacent isolation layers and overlaps with the conductive layer in a direction perpendicular to the substrate.

14. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further includes an insulating dielectric layer located on a side of the conductive interconnect structure away from the substrate, the stacked layer is located on a side of the insulating dielectric layer away from the substrate, and the second word line layer penetrates the stacked layer and the insulating dielectric layer.

15. The semiconductor structure according to claim 9, characterized in that The stacked layer has a second main body extending along a first direction and a second branch located at at least one side of the second main body along a second direction. The transistor structure runs through the second branch. The first direction intersects with the second direction and is parallel to the substrate.

16. The semiconductor structure according to claim 15, characterized in that The semiconductor structure further comprises: The support layer is located on a side of the second branch portion away from the second main portion, penetrates the stacking layer and extends along the first direction.

17. The semiconductor structure according to claim 15, characterized in that The transistor structure has a capacitor region on one side away from the second main body, the capacitor region is spaced apart from the transistor structure, the capacitor region is provided with a capacitor dielectric layer and a capacitor external electrode layer, the capacitor dielectric layer is located on the outer peripheral surface of the conductive layer, and the capacitor external electrode layer is located on the outer peripheral surface of the capacitor dielectric layer.

18. An electronic device, characterized in that: A semiconductor structure comprising any one of claims 9 to 17.

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