Anti-fuse OTP memory and its manufacturing method

Abstract

This invention discloses an antifuse OTP memory, comprising: a first gate structure of a control transistor and a second gate structure of an antifuse transistor, with a first spacing between the two gate structures; the first spacing is less than the minimum spacing of the layout design rules and greater than or equal to the minimum spacing that can be manufactured by the gate process. First and second sidewalls are formed on each side of each gate structure. First to third lightly doped drain regions are formed on the surface region of the well region at the side of each gate structure; no source / drain injection region is formed between the two gate structures; the first and second source / drain regions are respectively self-aligned and formed on the surface region of the well region at the second sidewall outside the two gate structures. The second lightly doped drain region serves as a series node of the control transistor and the antifuse transistor. This invention also discloses a method for manufacturing the antifuse OTP memory. This invention can reduce cell size, increase storage density, reduce manufacturing costs, reduce leakage current and thus improve programming success rate and reduce read power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an antifuse one-time-programmable (OTP) memory. This invention also relates to a method for manufacturing an antifuse OTP memory. Background Technology

[0002] One-time programmable memory (IPM) is a commonly used embedded memory. Its storage principle is to break down the gate dielectric layer of the MOSFET by high voltage and form a current path between the gate and the lightly doped drain (LDD). The capacitor becomes a small resistive device to realize the writing of data, hence it is called an antifuse device.

[0003] To ensure compatibility with existing traditional CMOS logic processes and achieve higher storage density, CMOS logic processes include core devices and input / output (I / O) devices. The antifuse devices used in memory cells often utilize the core devices of this process platform. Patents CN104347637B and CN106981313B both describe methods for manufacturing antifuse memory cells using core MOS transistors.

[0004] like Figure 1 The diagram shown is a cross-sectional view of the antifuse memory cell in an existing antifuse OTP memory. Taking an N-type device as an example, the existing antifuse OTP memory includes an antifuse memory cell formed in the active region.

[0005] The antifuse memory cell includes: a P-type well region 102 formed in a semiconductor substrate 101, a first gate structure of a control transistor formed on the surface of the well region 102, and a second gate structure of an antifuse transistor. The active region is defined by surrounding a field oxide layer 203.

[0006] The first gate structure includes a first gate dielectric layer 106 and a first gate conductive material layer 107 stacked sequentially.

[0007] The second gate structure includes a second gate dielectric layer 108 and a second gate conductive material layer 109 stacked sequentially.

[0008] Lightly doped drain regions 105, which are side-aligned with the corresponding first sidewalls, are formed on the surface regions of the well regions 102 on each side of the first gate structure and the second gate structure.

[0009] Source / drain regions 104 that are side-aligned with the corresponding second sidewalls are formed on the surface regions of the well region 102 on each side of the first gate structure and the second gate structure.

[0010] The lightly doped drain region 105 and source / drain region 104 between the first gate structure and the second gate structure are shared by the control transistor and the antifuse transistor and form a series node between the control transistor and the antifuse transistor.

[0011] When a higher programming voltage is applied to the second gate conductive material layer 109, the second gate dielectric layer 108 will be broken down to achieve programming, as shown by the lightning bolt.

[0012] In existing antifuse OTP memory, although the gate pitch of the core MOS transistor is often the minimum pitch allowed by the layout design rules of the process platform, the process can actually manufacture gates with smaller pitches. Considering processes such as source vias (CTs) between gates and ion implantation in the source and drain regions, the minimum gate pitch is limited to a larger value, otherwise it would violate the layout design rules and manufacturing process rules.

[0013] For a continuous active region, the photomask for source-drain ion implantation is also a single piece, and the implantation area between gates is determined by the spacing between adjacent gate sidewalls. However, for the series intermediate nodes of antifuse memory cells, ion implantation in the source-drain regions reduces the equivalent series resistance, leading to an increase in gate-induced leakage current (GIDL) of unselected memory cells. This increases the programming suppression current, which may cause a voltage drop in the programming power supply for large-capacity memories, resulting in partial antifuse programming failure. Long-term exposure of unselected cells to programming suppression current can also lead to device degradation or even failure. Summary of the Invention

[0014] The technical problem to be solved by this invention is to provide an antifuse OTP memory that can reduce cell size, increase storage density, reduce manufacturing costs, reduce leakage current thereby improving programming success rate and reducing read power consumption. To this end, this invention also provides a method for manufacturing the antifuse OTP memory.

[0015] To solve the above-mentioned technical problems, the antifuse OTP memory provided by the present invention includes: an antifuse memory cell formed in the active region.

[0016] The antifuse memory cell includes: a well region of a second conductivity type formed in a semiconductor substrate, and a first gate structure and a second gate structure formed on the surface of the well region.

[0017] There is a first spacing between the second side of the first gate structure and the first side of the second gate structure; the first spacing is less than the minimum spacing of the layout design rules and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process.

[0018] A first sidewall and a second sidewall are sequentially self-aligned on the first sidewall and the second sidewall of the first gate structure and the first sidewall and the second sidewall of the second gate structure.

[0019] A first lightly doped drain region of a first conductivity type is self-aligned and formed on the surface region of the well region at the first sidewall on the first side of the first side of the first gate structure.

[0020] The first source / drain region, heavily doped with a first conductivity type, is self-aligned and formed on the surface region of the well region at the second sidewall of the first sidewall of the first sidewall of the first gate structure.

[0021] The thickness of the first sidewall is less than twice the first spacing, and there is a first spacing region between the first sidewall at the second side of the first gate structure and the first sidewall at the first side of the second gate structure. The second lightly doped drain region is self-aligned to form the surface region of the well region at the bottom of the first spacing region.

[0022] The second sidewall completely fills the first spacer region and forms a source / drain injection barrier structure, with no heavily doped source / drain injection regions of the first conductivity type in the surface region of the well region at the bottom of the first spacer region.

[0023] A third lightly doped drain region of a first conductivity type is self-aligned and formed on the surface region of the well region at the first sidewall on the second side of the second gate structure.

[0024] The second source / drain region, heavily doped with a first conductivity type, is self-aligned and formed on the surface region of the well region at the second sidewall on the second side of the second gate structure.

[0025] The first gate structure serves as the gate structure of the control transistor, the second gate structure serves as the gate structure of the antifuse transistor, and the second lightly doped drain region serves as the series node of the control transistor and the antifuse transistor.

[0026] A further improvement is that the first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked sequentially.

[0027] The second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked sequentially.

[0028] A further improvement is that the first gate dielectric layer and the second gate dielectric layer are made of the same material and are formed simultaneously.

[0029] The first gate conductive material layer and the second gate conductive material layer are made of the same material and are formed simultaneously.

[0030] A further improvement is that it includes a storage array formed by arranging a plurality of the aforementioned antifuse storage cells.

[0031] In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row.

[0032] Each of the first source-drain regions in the same column is connected to the bit line in the same column.

[0033] The second source-drain region of each of the aforementioned antifuse memory cells is floating.

[0034] The second gate conductive material layer of each of the antifuse memory cells is connected to the first voltage source.

[0035] The trap region of each of the aforementioned antifuse storage cells is connected to a fixed point.

[0036] A further improvement is that both the control transistor and the antifuse are NMOS, with the first conductivity type being N-type and the second conductivity type being P-type; or, both the control transistor and the antifuse are PMOS, with the first conductivity type being P-type and the second conductivity type being N-type.

[0037] A further improvement is that both the control transistor and the antifuse transistor are NMOS.

[0038] The well region of each of the aforementioned antifuse storage cells is grounded.

[0039] During programming, the voltage of the first voltage source is a programming voltage greater than the breakdown voltage of the second gate dielectric layer; the bit line connected to the selected antifuse memory cell is connected to a low voltage and the word line connected to it is connected to a first positive voltage, which turns on the control transistor; the bit lines not connected to the selected antifuse memory cell are all connected to a second positive voltage and the word lines not connected to the selected antifuse memory cell are all connected to a low voltage.

[0040] During a read operation, the voltage of the first voltage source is reduced to a third positive voltage. The bit line connected to the selected antifuse memory cell is connected to a sensitive discharge device, and the word line connected to it is connected to a first positive voltage. The bit lines not connected to the selected antifuse memory cell are disconnected from the connection to the sensitive discharge device, and the word lines not connected to the selected antifuse memory cell are all connected to a low voltage. The first positive voltage, the second positive voltage, and the third positive voltage are all greater than or equal to the operating voltage of the NMOS transistor, and the minimum value of the low voltage is 0V.

[0041] A further improvement is that, in the storage array, every two antifuse storage cells in the same column form an antifuse storage cell combination.

[0042] In the antifuse memory cell assembly, the active regions of two antifuse memory cells are connected to form an integral structure and share the same first source / drain region and are connected to the corresponding bit lines in the same column through the same contact hole; the active regions of each antifuse memory cell assembly are isolated from each other by a field oxide layer.

[0043] A further improvement is that the first voltage source powers the entire memory array through a power mesh.

[0044] Alternatively, the first voltage source is divided into multiple first voltage source sub-blocks, each of which corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source sub-block is selected for power supply.

[0045] To solve the above-mentioned technical problems, the manufacturing method of the antifuse OTP memory provided by the present invention includes the following steps in forming the antifuse memory cell:

[0046] Step 1: Provide a semiconductor substrate, form a well region doped with a second conductivity type in the semiconductor substrate, form a field oxide layer in the well region, and define the active region of the antifuse memory cell.

[0047] Step 2: Forming the gate structure, including:

[0048] A first dielectric layer and a second conductive material layer are formed sequentially.

[0049] The formation regions of the first gate structure and the second gate structure are defined using a first photomask.

[0050] The second conductive material layer and the first dielectric layer are sequentially etched on the surface of the well region to form a first gate structure and a second gate structure.

[0051] The first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked sequentially; the second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked sequentially; both the first gate dielectric layer and the second gate dielectric layer are composed of the first dielectric layer after etching; both the first gate conductive material layer and the second gate conductive material layer are composed of the second conductive material layer after etching; a first spacing is provided between the second side of the first gate structure and the first side of the second gate structure; the first spacing is less than the minimum spacing of the layout design rules and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process.

[0052] Step 3: Form a first sidewall by self-alignment on the first and second sides of the first gate structure and the first and second sides of the second gate structure.

[0053] The thickness of the first sidewall is less than twice the first spacing, and there is a first gap between the first sidewall at the second side of the first gate structure and the first sidewall at the first side of the second gate structure.

[0054] Step 4: Perform lightly doped drain implantation of the first conductivity type to form the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region.

[0055] The first lightly doped drain region is self-aligned and formed in the surface region of the well region at the first sidewall on the first side of the first gate structure; the second lightly doped drain region is self-aligned and formed in the surface region of the well region at the bottom of the first spacer region; the third lightly doped drain region is self-aligned and formed in the surface region of the well region at the first sidewall on the second side of the second gate structure.

[0056] Step 5: Form a second sidewall by self-aligning the first sidewall of the first sidewall of the first gate structure and the second sidewall of the second gate structure.

[0057] The second sidewall completely fills the first interval area and forms a source-drain injection barrier structure.

[0058] Step 6: Perform source / drain implantation with heavy doping of the first conductivity type to form the first source / drain region and the second source / drain region.

[0059] The first source / drain region is self-aligned and formed on the surface region of the well region at the second sidewall of the first side of the first gate structure.

[0060] The second source / drain region is self-aligned and formed on the surface region of the well region at the second sidewall on the second side of the second gate structure.

[0061] The source / drain injection blocking structure ensures that there are no heavily doped source / drain injection regions of the first conductivity type in the surface region of the well region at the bottom of the first spacer region.

[0062] The first gate structure serves as the gate structure of the control transistor, the second gate structure serves as the gate structure of the antifuse transistor, and the second lightly doped drain region serves as the series node of the control transistor and the antifuse transistor.

[0063] A further improvement includes the following steps:

[0064] An interlayer film, contact holes, and a front metal layer are formed, and the front metal layer is patterned to form word lines, bit lines, and first voltage source connections.

[0065] A storage array formed by arranging multiple antifuse storage cells.

[0066] In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row.

[0067] Each of the first source / drain regions in the same column is connected to the bit line in the same column through the corresponding contact hole.

[0068] The second source-drain region of each of the aforementioned antifuse memory cells is floating.

[0069] The second gate conductive material layer of each of the antifuse memory cells is connected to the first voltage source line through the corresponding contact hole and connected to the first voltage source line through the first voltage source line.

[0070] The trap region of each of the aforementioned antifuse storage cells is connected to a fixed point.

[0071] A further improvement is that both the control transistor and the antifuse are NMOS, with the first conductivity type being N-type and the second conductivity type being P-type; or, both the control transistor and the antifuse are PMOS, with the first conductivity type being P-type and the second conductivity type being N-type.

[0072] A further improvement is that, in the storage array, every two antifuse storage cells in the same column form an antifuse storage cell combination.

[0073] In the antifuse memory cell assembly, the active regions of two antifuse memory cells are connected to form an integral structure and share the same first source / drain region and are connected to the corresponding bit lines in the same column through the same contact hole; the active regions of each antifuse memory cell assembly are isolated from each other by the field oxide layer.

[0074] A further improvement is that the first voltage source powers the entire memory array through a power mesh.

[0075] Alternatively, the first voltage source is divided into multiple first voltage source sub-blocks, each of which corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source sub-block is selected for power supply.

[0076] A further improvement is that a first identification layer is used in the layout design of the first photomask. The coverage area of ​​the first identification layer is larger than the formation areas of the first gate structure and the second gate structure, in order to avoid design rule violations of the first spacing.

[0077] The present invention makes a special setting for the first spacing between the first gate structure and the second gate structure of the antifuse memory cell, so that the first spacing is less than the minimum spacing of the layout design rules and greater than or equal to the minimum spacing that can be manufactured by the gate process. In this way, the first spacing can be reduced as much as possible while ensuring the realization of the gate structure manufacturing, breaking through the limitation of the minimum spacing of the layout design rules on the first spacing. Therefore, the cell size can be reduced and the storage density can be increased. The increase in storage density can reduce the manufacturing cost.

[0078] In addition, the present invention sets the first spacing to be less than the minimum spacing of the layout design rules. During the layout design process, the violation detection of the design rules for the first spacing can be avoided by setting an identification layer, and photomask calculation is not required. Therefore, the present invention sets the first spacing to be less than the minimum spacing of the layout design rules, which itself does not require the addition of an extra photomask, and thus does not lead to an increase in manufacturing costs.

[0079] By setting a first spacing and combining it with the setting of a first sidewall and a second sidewall, this invention ensures that only a lightly doped drain region, i.e. a second lightly doped drain region, is formed on the surface of the well region between the first gate structure and the second gate structure, which is self-aligned with the first sidewall. The source-drain injection blocking structure is realized by utilizing the characteristic that the second sidewall completely fills the first spacing region between the first gate structure and the second gate structure, and prevents the formation of a source-drain injection region on the surface of the well region between the first gate structure and the second gate structure. First of all, this process of forming only a second lightly doped drain region and not forming a source-drain injection region in the region between the gate structures is completely achieved by self-alignment, which has the advantages of simple process and low cost.

[0080] Secondly, the structure where only a second lightly doped drain region and no source / drain injection region are formed between the gate structures allows the series connection between the control transistor and the antifuse transistor to be achieved through the second lightly doped drain region. Compared to existing structures where the series connection between the control transistor and the antifuse transistor uses a heavily doped source / drain injection region, the resistance of the series connection is increased. This reduces leakage current, such as GIDL leakage current. During programming, reduced leakage current reduces the drop in programming voltage, thereby improving programming success rate. Reduced leakage current also reduces read power consumption. Therefore, this invention can further reduce leakage current, thereby improving programming success rate and reducing read power consumption. Attached Figure Description

[0081] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0082] Figure 1 This is a cross-sectional schematic diagram of the antifuse memory cell in an existing antifuse OTP memory.

[0083] Figure 2 This is a cross-sectional structural schematic diagram of the antifuse storage cell of the antifuse OTP memory according to an embodiment of the present invention;

[0084] Figure 3 This is a layout of the antifuse memory cell of the antifuse OTP memory according to an embodiment of the present invention;

[0085] Figure 4A This is a layout of a storage array of an antifuse OTP memory according to an embodiment of the present invention;

[0086] Figure 4B yes Figure 4A The circuit diagram of the storage array;

[0087] Figure 5 This is a structural diagram of another storage array of the antifuse OTP memory according to an embodiment of the present invention;

[0088] Figure 6 This is a structural diagram of another storage array of the antifuse OTP memory according to an embodiment of the present invention;

[0089] Figures 7A-7F This is a cross-sectional structural schematic diagram of the antifuse memory cell in each step of the manufacturing method of the antifuse OTP memory according to an embodiment of the present invention. Detailed Implementation

[0090] In this embodiment of the invention, the antifuse OTP memory includes a memory array formed by arranging a plurality of said antifuse memory cells 301. For example... Figure 4A The diagram shown is a layout of a storage array for an antifuse OTP memory according to an embodiment of the present invention. Figure 4B yes Figure 4A The circuit diagram of the storage array; Figure 4A The 501a storage array is a 4x4 array, which will be discussed below. Figure 4A and Figure 4B The storage array is described in detail below:

[0091] In the memory array, the first gate conductive material layers 205a in the same row are all connected to the word lines WL in the same row. Figure 4A The vertical direction is the row direction, and the horizontal direction is the column direction. Figure 4A The image shows four rows, with the word lines labeled WL0, WL1, WL2, and WL3, respectively. The number following WL indicates the row number. Typically, the first gate conductive material layers 205a in the same row are connected to form a row, and the end of the row of the first gate conductive material layers 205a is connected to the corresponding word line WL through contact holes 306.

[0092] Each of the first source / drain regions 209a in the same column is connected to the bit line BL in the same column. Figure 4A The image shows four columns, labeled BL0, BL1, BL2, and BL3, with the numbers following BL indicating the column number.

[0093] The second source-drain region 209b of each of the antifuse storage units 301 is floating.

[0094] The second gate conductive material layer 205b of each of the antifuse memory cells 301 is connected to the first voltage source VPP. Typically, the second gate conductive material layers 205b in the same row are connected to form a row, and the end of the row of second gate conductive material layers 205b is connected to the corresponding first voltage source connection line 308 through the contact hole 306 and then connected to the first voltage source VPP through the first voltage source connection line 308.

[0095] The trap region 202 of each of the antifuse storage units 301 is connected to a fixed point.

[0096] In this embodiment of the invention, both the control transistor 304 and the antifuse 305 are NMOS transistors, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, both the control transistor 304 and the antifuse 305 can be PMOS transistors, with P-type as the first conductivity type and N-type as the second conductivity type.

[0097] In this embodiment of the invention, both the control transistor 304 and the antifuse transistor 305 are NMOS, such as a core NMOS. The voltage applied to the antifuse memory cell 301 during operation includes:

[0098] The well region 202 of each of the antifuse storage cells 301 is grounded.

[0099] During programming, the voltage of the first voltage source VPP is a programming voltage greater than the breakdown voltage of the second gate dielectric layer 204b; the bit line BL connected to the selected antifuse memory cell 301 is connected to a low voltage and the word line WL connected to it is connected to a first positive voltage, which turns on the control transistor 304; the bit lines BL not connected to the selected antifuse memory cell 301 are all connected to a second positive voltage and the word lines WL not connected to the selected antifuse memory cell 301 are all connected to a low voltage.

[0100] The following is combined with Figure 4B The bit line BL and the word line WL connected to the unselected antifuse memory cell 301 are further explained as follows:

[0101] like Figure 4BAs shown, the four rows are represented by A, B, C, and D, and the four columns are represented by 0, 1, 2, and 4. If the selected antifuse memory cell 301 is A0, that is, the cell with row number A and column number 0, which is also the cell where word line WL0 and bit line BL0 intersect. The bit line connected to cell A0 is bit line BL0, which will be connected to a low voltage. The bit lines not connected to cell A0 are bit lines BL1, BL2, and BL3, which will be connected to a second positive voltage. The word line connected to cell A0 is word line WL0, which will be connected to a first positive voltage. The word lines not connected to cell A0 are word lines WL1, WL2, and WL3, which will all be connected to a low voltage.

[0102] During a read operation, the voltage of the first voltage source VPP is reduced to a third positive voltage. The bit line BL connected to the selected antifuse memory cell 301 is connected to a sensitive discharge device, and the word line WL connected to it is connected to a first positive voltage. The bit line BL not connected to the selected antifuse memory cell 301 is disconnected from the connection to the sensitive discharge device, and the word lines WL not connected to the selected antifuse memory cell 301 are all connected to a low voltage. The first positive voltage, the second positive voltage, and the third positive voltage are all greater than or equal to the operating voltage of the NMOS transistor, and the minimum value of the low voltage is 0V. In this embodiment of the invention, the first positive voltage, the second positive voltage, and the third positive voltage are all equal to or slightly greater than the operating voltage of the core NMOS transistor.

[0103] like Figure 4A As shown, in the storage array, in the antifuse storage cells 301 in the same column, every two antifuse storage cells 301 form an antifuse storage cell 301 combination.

[0104] In the antifuse memory unit 301 assembly, the active regions 401 of two antifuse memory units 301 are connected to form an integral structure and share the same first source-drain region 209a. They are connected to the corresponding bit line BL in the same column through the same contact hole 306. The structure in which two adjacent active regions 401 are connected together at the first source-drain region 209a end is a "head-to-head" arrangement.

[0105] The active regions 401 of each of the antifuse memory cells 301 are isolated from each other by a field oxide layer 203. The structure in which two adjacent active regions 401 are isolated from each other at the second source-drain region 209b end is connected to each other, which is a "back-to-back" arrangement.

[0106] In this embodiment of the invention, the number of antifuse storage cells 301 in the storage array can be set as needed, and the specific arrangement structure is as follows: Figure 4AThe structure can be expanded upon, and will not be described in detail here.

[0107] like Figure 5 The diagram shown is a structural diagram of another type of storage array for the antifuse OTP memory according to an embodiment of the present invention; storage array 501b is an m*n array. Figure 5 In this context, an m*n array is also represented as array m*n, where m and n are both positive integers greater than 1.

[0108] The first voltage source VPP supplies power to the entire memory array through the power mesh 502. That is, the same first voltage source VPP supplies power to all the antifuse memory cells 301 simultaneously, which is more suitable for medium-capacity memory arrays.

[0109] Depend on Figure 5 As shown, the antifuse memory cell 301 in memory array 501b is selected via bit line BL and word line WL. Bit line BL is selected via column address signal and bit line multiplexer 503 (BL MUX). Word line WL is selected via row address signal after decoding by word line decoder 504 (WL decoder).

[0110] like Figure 6 The diagram shown is a structural diagram of another type of storage array for the antifuse OTP memory according to an embodiment of the present invention; and Figure 5 The difference is that the storage array 501b has a larger capacity, meaning the values ​​of m and n are larger. In this case, if the same first voltage source VPP is used to power all the antifuse storage cells 301 simultaneously, the combined leakage current of the larger-capacity antifuse storage cells 301 will be relatively large, easily causing a significant drop in the voltage of the first voltage source VPP and increasing power consumption.

[0111] The first voltage source VPP is divided into multiple first voltage source VPP sub-blocks, and each first voltage source VPP sub-block corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source VPP sub-block is selected for power supply. Figure 6 In the diagram, VPP[0], VPP[1] to VPP[i] are the voltages output by i first voltage source VPP sub-blocks, and each voltage is selected by the first voltage source multiplexer 505 (VPP MUX). During operation, the corresponding first voltage source VPP is applied only to the selected memory array sub-blocks, while the corresponding first voltage source VPP is not applied to the unselected memory array sub-blocks. Therefore, the voltage drop of the first voltage source VPP and the power consumption can be reduced.

[0112] In this embodiment of the invention, a special setting is made for the first spacing between the first gate structure 302 and the second gate structure 303 of the antifuse memory cell 301, so that the first spacing is less than the minimum spacing of the layout design rules and greater than or equal to the minimum spacing that can be manufactured by the gate process. In this way, the first spacing can be reduced as much as possible while ensuring the realization of the gate structure manufacturing, breaking through the limitation of the minimum spacing of the layout design rules on the first spacing. Therefore, the cell size can be reduced and the storage density can be increased. The increase in storage density can reduce the manufacturing cost.

[0113] In addition, in this embodiment of the invention, the first spacing is set to be less than the minimum spacing of the layout design rule. During the layout design process, the violation detection of the design rule for the first spacing can be avoided by setting an identification layer, and photomask calculation is not required. Therefore, setting the first spacing to be less than the minimum spacing of the layout design rule in this embodiment of the invention does not require adding an additional photomask, thereby not leading to an increase in manufacturing costs.

[0114] By setting a first spacing and combining it with the setting of a first sidewall 206 and a second sidewall 207, this embodiment of the invention ensures that only a lightly doped drain region, namely a second lightly doped drain region 208b, is formed on the surface of the well region 202 between the first gate structure 302 and the second gate structure 303, which is self-aligned with the first sidewall 206. The source-drain injection blocking structure is realized by utilizing the characteristic that the second sidewall 207 completely fills the first spacing region between the first gate structure 302 and the second gate structure 303, and prevents the formation of a source-drain injection region on the surface of the well region 202 between the first gate structure 302 and the second gate structure 303. First of all, this process of forming only the second lightly doped drain region 208b and not forming a source-drain injection region in the region between the gate structures is completely self-aligned, which has the advantages of simple process and low cost.

[0115] Secondly, the region between the gate structures only forms a second lightly doped drain region 208b and no source / drain injection region. This means that the series connection between the control transistor 304 and the antifuse transistor 305 is achieved by the second lightly doped drain region 208b. Compared to the existing structure where the series connection between the control transistor 304 and the antifuse transistor 305 uses a heavily doped source / drain injection region, the resistance of the series connection is increased. This reduces leakage current, such as GIDL leakage current. During programming, reduced leakage current reduces the decrease in programming voltage, thereby improving programming success rate. Reduced leakage current also reduces read power consumption. Therefore, this embodiment of the invention can further reduce leakage current, thereby improving programming success rate and reducing read power consumption.

[0116] like Figures 7A to 7F The diagram shown is a cross-sectional view of the antifuse memory cell in each step of the manufacturing method of the antifuse OTP memory according to an embodiment of the present invention. The step of forming the antifuse memory cell 301 in the manufacturing method of the antifuse OTP memory according to an embodiment of the present invention includes:

[0117] Step 1, such as Figure 7A As shown, a semiconductor substrate 201 is provided, in which a well region 202 doped with a second conductivity type is formed, a field oxide layer 203 is formed in the well region 202 and the active region 401 of the antifuse memory cell 301 is defined.

[0118] Step 2: Forming the gate structure, including:

[0119] like Figure 7A As shown, a first dielectric layer 204 and a second conductive material layer 205 are formed sequentially.

[0120] like Figure 7B As shown, the formation regions of the first gate structure 302 and the second gate structure 303 are defined by the first photomask.

[0121] The second conductive material layer 205 and the first dielectric layer 204 are etched sequentially to form a first gate structure 302 and a second gate structure 303 on the surface of the well region 202.

[0122] The first gate structure 302 includes a first gate dielectric layer 204a and a first gate conductive material layer 205a stacked sequentially; the second gate structure 303 includes a second gate dielectric layer 204b and a second gate conductive material layer 205b stacked sequentially; both the first gate dielectric layer 204a and the second gate dielectric layer 204b are composed of etched first dielectric layers 204; both the first gate conductive material layer 205a and the second gate conductive material layer 205b are composed of etched second conductive material layers 205; a first spacing is provided between the second side surface of the first gate structure 302 and the first side surface of the second gate structure 303; the first spacing is less than the minimum spacing of the layout design rules and greater than or equal to the minimum spacing that can be manufactured by the gate process.

[0123] In some embodiments, the first dielectric layer 204 is a silicon dioxide layer, and the second conductive material layer 205 is polysilicon. In other embodiments, the first dielectric layer 204 may be a high dielectric constant (HK) gate oxide layer, and the second conductive material layer 205 may be a metal gate.

[0124] Please refer to the map corresponding to the first light shield. Figure 3 As shown, Figure 3 A first gate conductive material layer 205a and a second gate conductive material layer 205b are respectively formed in the forming regions of the first gate structure 302 and the second gate structure 303.

[0125] like Figure 3As shown, the first spacing is less than the minimum spacing of the layout design rules, therefore it cannot pass the layout design rule check in the layout design of the first photomask defining the gate structure. The method in this embodiment of the invention also requires an identification layer 402 to avoid design rule violations related to the first spacing. This identification layer 402 is not used for special calculations of the photomask and will not add additional photomasks, thus avoiding increased manufacturing costs.

[0126] Step 3, as follows Figure 7C As shown, a first sidewall 206 is formed by self-alignment on the first and second sides of the first gate structure 302 and the first and second sides of the second gate structure 303.

[0127] The thickness of the first sidewall 206 is less than twice the first spacing, and there is a first gap between the first sidewall 206 at the second side of the first gate structure 302 and the first sidewall 206 at the first side of the second gate structure 303.

[0128] Step 4, as follows Figure 7D As shown, a first lightly doped drain region 208a, a second lightly doped drain region 208b, and a third lightly doped drain region 208c are formed by lightly doped drain implantation of a first conductivity type.

[0129] The first lightly doped drain region 208a is self-aligned and formed on the surface region of the well region 202 at the first sidewall 206 on the first side of the first gate structure 302; the second lightly doped drain region 208b is self-aligned and formed on the surface region of the well region 202 at the bottom of the first spacer region; the third lightly doped drain region 208c is self-aligned and formed on the surface region of the well region 202 at the first sidewall 206 on the second side of the second gate structure 303.

[0130] Step 5, as follows Figure 7E As shown, a second sidewall 207 is formed by self-alignment of the sidewall 206 on the first sidewall and the second sidewall of the first gate structure 302 and the first sidewall and the second sidewall of the second gate structure 303.

[0131] The second sidewall 207 completely fills the first interval area and forms a source-drain injection barrier structure.

[0132] Step Six, as Figure 7F As shown, source-drain implantation with heavy doping of the first conductivity type is performed to form the first source-drain region 209a and the second source-drain region 209b.

[0133] The first source / drain region 209a is self-aligned and formed on the surface region of the well region 202 at the second sidewall 207 on the first side of the first gate structure 302.

[0134] The second source / drain region 209b is self-aligned and formed on the surface region of the well region 202 at the second sidewall 207 on the second side of the second gate structure 303.

[0135] The source / drain injection blocking structure ensures that there are no heavily doped source / drain injection regions of the first conductivity type in the surface region of the well region 202 at the bottom of the first spacer region.

[0136] The first gate structure 302 serves as the gate structure of the control transistor 304, the second gate structure 303 serves as the gate structure of the antifuse transistor 305, and the second lightly doped drain region 208b serves as the series node of the control transistor 304 and the antifuse transistor 305.

[0137] It also includes the following steps:

[0138] An interlayer film, contact hole 306, and a front metal layer are formed. The front metal layer is patterned to form word line WL, bit line BL, and the first voltage source VPP connection. (Please refer to the image for contact hole 306.) Figure 4A As shown.

[0139] like Figure 4A As shown, a storage array is formed by arranging multiple antifuse storage units 301.

[0140] In the memory array, the first gate conductive material layers 205a in the same row are all connected to the word lines WL in the same row.

[0141] Each of the first source / drain regions 209a in the same column is connected to the bit line BL in the same column through the corresponding contact hole 306.

[0142] The second source-drain region 209b of each of the antifuse storage units 301 is floating.

[0143] The second gate conductive material layer 205b of each antifuse memory cell 301 is connected to the first voltage source VPP line through the corresponding contact hole 306 and to the first voltage source VPP through the first voltage source VPP line.

[0144] The trap region 202 of each of the antifuse storage units 301 is connected to a fixed point.

[0145] In the method of this embodiment, both the control transistor 304 and the antifuse 305 are NMOS, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the control transistor 304 and the antifuse 305 can also be PMOS, with the first conductivity type being P-type and the second conductivity type being N-type.

[0146] In the storage array, in the same column of the antifuse storage units 301, every two antifuse storage units 301 form an antifuse storage unit 301 combination.

[0147] In the antifuse memory cell 301 assembly, the active regions 401 of two antifuse memory cells 301 are connected to form an integral structure and share the same first source / drain region 209a and are connected to the corresponding bit line BL in the same column through the same contact hole 306; the active regions 401 of each antifuse memory cell 301 assembly are isolated from each other by the field oxide layer 203.

[0148] In some examples, such as Figure 5 As shown, the first voltage source VPP supplies power to the entire memory array through power mesh 502.

[0149] In some examples, such as Figure 6 As shown, the first voltage source VPP is divided into multiple first voltage source VPP sub-blocks, and each first voltage source VPP sub-block corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source VPP sub-block is selected for power supply.

[0150] The antifuse OTP memory of this invention, based on the existing device structure, can further reduce the distance between the gate of the gate control transistor 302 and the gate of the antifuse transistor 303. The second sidewalls of the two gates are superimposed and interconnected, and the source / drain ion implantation between the two gates is removed, leaving only the lightly doped drain region (LDD). Figure 3 In the layout shown, the embodiment of the present invention requires an additional identification layer 402 for the antifuse memory cell 301 to avoid design rule violations and manufacturing rule violations of the minimum gate pitch. This identification layer 402 will not be used for special calculations of the photomask, and will not add an additional photomask, thus increasing manufacturing costs.

[0151] In this embodiment of the invention, because the distance between the selection control transistor 302 and the antifuse device, i.e., the antifuse tube 303, is significantly reduced, the area of ​​a single antifuse memory cell 301 is also significantly reduced. Depending on the manufacturing process, this reduction can be achieved by 15% to 35%, thus lowering the chip manufacturing cost. Furthermore, because the source-drain injection between the selection control transistor 302 and the antifuse device is removed, and only the LDD provides the series path, its series resistance is significantly increased. For unselected memory cells, the drain current (GIDL) induced by the high-voltage gate of the adjacent antifuse device in the selection control transistor 302 is significantly suppressed. For large-capacity memory arrays, a large number of unselected memory cells may occur during a single programming process; a smaller GIDL can prevent local programming failures caused by the high-voltage programming power supply voltage being pulled down.

[0152] Because the gate pitch of the antifuse memory cell 301 in this embodiment of the invention is smaller than that of the existing antifuse memory cell, the storage density of this embodiment of the invention is greater, the manufacturing cost is lower, the leakage current is smaller, the programming success rate is higher, and the read power consumption is lower.

[0153] In embodiments of the present invention, such as Figure 4B As shown, in programming operations:

[0154] The voltage of VPP is the voltage that can break down the antifuse dielectric layer, i.e., the second gate dielectric layer 204b. The high voltage of WL / BL is the core MOS voltage or slightly higher. VPP is the first voltage source VPP, WL is the word line, and BL is the bit line.

[0155] The storage unit has four different states, for example:

[0156] When memory cell A0 is selected for programming, its WL0 is high and BL0 is low, allowing programming operations to proceed. A0 represents row number A and column number 0, corresponding to row number 0 in WL0. The numbers following A in subsequent A1, A2, and A3 also correspond to the corresponding column numbers; similarly, B, C, and D in B0, C0, and D0 correspond to row numbers 1, 2, and 3 in WL1, WL2, and WL3, respectively.

[0157] At this time, in the A1, A2, and A3 cells in the same row, WL0 is high, BL1, BL2, and BL3 are high, and the LDD potential below the antifuse is also high. The gate dielectric layer voltage difference is insufficient to break down the circuit, so programming is not possible.

[0158] At this point, in cells B0, C0, and D0 of the same column, WL1, WL2, and WL3 are low, and BL0 is low. After the LDD below the antifuse is charged high by the gate leakage current, the gate dielectric layer voltage difference is insufficient to break down, and programming is impossible. Similarly, in cells of different rows and columns, WL1, WL2, and WL3 are low, and BL1, BL2, and BL3 are high; the antifuse gate dielectric layer also cannot be broken down. Therefore, this array can achieve programming operations at specific addresses.

[0159] During the reading process:

[0160] The VPP voltage is reduced to a voltage slightly higher than the core MOS voltage but sufficient to ensure the reliability of the gate dielectric layer, i.e., the second gate dielectric layer 204b. The high voltage of WL is the core MOS voltage or slightly higher. BL transmits the voltage to the sensitive amplifier and sampling module through the column gating module to achieve data readout.

[0161] For example, when performing a data reading operation on cell A0, if this cell is programmed, the VPP voltage of the antifuse gate, i.e., the second gate conductive material layer 205b, is connected in series to the selection control transistor 302 through a small equivalent resistance. At this time, BL0 will generate a large read current. Since the voltage division of BL0 to ground in the sampling module is high, the programmed data is read out.

[0162] If this cell is not programmed, the VPP voltage of the antifuse gate has negligible effect on the leakage current of the LDD, i.e., the second lightly doped drain region 208b. There is almost no read current on BL0, and the voltage division of the sampling module is about 0, so the unprogrammed data is read.

[0163] For the same-line storage cells, although VPP and WL0 are both enabled, BL1, BL2, and BL3 are not selected to the sampling module and can be approximately in a floating state. Therefore, BL1, BL2, and BL3 will not generate read current.

[0164] For different row storage units, WL1, WL2, and WL3 are low, and VPP will not supply power to BL through these units, so it will not affect the data reading of the selected unit.

[0165] In this embodiment of the invention, in order to increase the storage array density, the gate control transistors 302 of adjacent rows are arranged in a "head-to-head" manner, sharing the source-drain region, namely the first source-drain region 209a, and are connected to the BL potential through a hole. The antifuse devices of adjacent rows are arranged in a "back-to-back" manner. However, since the gates of the antifuse devices in the same column are connected to the same high voltage, the active regions of the "back-to-back" antifuse devices need to be isolated to avoid mutual conduction leading to programming and reading failures.

[0166] The storage array of this invention can Figure 4A It is expanded to a larger capacity by copying from the 2*2, and WL and BL are selected by row and column decoding.

[0167] In some examples, such as Figure 5 As shown, the VPP can interconnect the entire array via a power grid.

[0168] In some examples, such as Figure 6 As shown, depending on the actual leakage current of the memory cells, the VPPs of some columns can be connected together, and the entire array can be divided into multiple blocks of VPPs, namely the first voltage source VPP sub-blocks. By using the column decoding address strobe for certain bits, only the VPP of the selected block is powered on, thereby reducing the leakage current of the entire array. Similarly, when the word line gate WL load is too large, or the long metal resistance of the bit line BL causes a voltage drop, which affects the overall speed or read / write characteristics of the memory, more array blocks can be divided for design.

[0169] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An antifuse OTP memory, characterized in that, include: Antifuse memory cells formed in the active region; The antifuse memory cell includes: a well region of a second conductivity type formed in a semiconductor substrate, and a first gate structure and a second gate structure formed on the surface of the well region; There is a first spacing between the second side of the first gate structure and the first side of the second gate structure; the first spacing is less than the minimum spacing of the layout design rules and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process; A first sidewall and a second sidewall are sequentially self-aligned and formed on the first side and the second side of the first gate structure and the first side and the second side of the second gate structure. A first lightly doped drain region of a first conductivity type is self-aligned and formed on the surface region of the well region at the first sidewall on the first side of the first side of the first gate structure. The first source / drain region, heavily doped with a first conductivity type, is self-aligned and formed on the surface region of the well region at the second sidewall of the first side of the first gate structure. The thickness of the first sidewall is less than twice the first spacing, and there is a first gap region between the first sidewall at the second side of the first gate structure and the first sidewall at the first side of the second gate structure. The second lightly doped drain region is self-aligned to form the surface region of the well region at the bottom of the first gap region. The second sidewall completely fills the first spacer region and forms a source / drain injection barrier structure, with no heavily doped source / drain injection regions of the first conductivity type in the surface region of the well region at the bottom of the first spacer region; A third lightly doped drain region of a first conductivity type is self-aligned and formed on the surface region of the well region at the first sidewall on the second side of the second gate structure. The second source / drain region, heavily doped with a first conductivity type, is self-aligned and formed on the surface region of the well region at the second sidewall on the second side of the second gate structure. The first gate structure serves as the gate structure of the control transistor, the second gate structure serves as the gate structure of the antifuse transistor, and the second lightly doped drain region serves as the series node of the control transistor and the antifuse transistor.

2. The antifuse OTP memory as described in claim 1, characterized in that: The first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked sequentially; The second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked sequentially.

3. The antifuse OTP memory as described in claim 2, characterized in that: The first gate dielectric layer and the second gate dielectric layer are made of the same material and are formed simultaneously. The first gate conductive material layer and the second gate conductive material layer are made of the same material and are formed simultaneously.

4. The antifuse OTP memory as described in claim 2, characterized in that, This includes a storage array formed by arranging multiple of the aforementioned antifuse storage cells; In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row; Each of the first source / drain regions in the same column is connected to the bit line in the same column; The second source-drain region of each of the aforementioned antifuse memory cells is floating. The second gate conductive material layer of each of the aforementioned antifuse memory cells is connected to the first voltage source; The trap region of each of the aforementioned antifuse storage cells is connected to a fixed point.

5. The antifuse OTP memory as described in claim 4, characterized in that: Both the control transistor and the antifuse are NMOS, with N-type as the first conductivity type and P-type as the second conductivity type; or, both the control transistor and the antifuse are PMOS, with P-type as the first conductivity type and N-type as the second conductivity type.

6. The antifuse OTP memory as described in claim 5, characterized in that: Both the control transistor and the antifuse are NMOS; The well region of each of the aforementioned antifuse memory cells is grounded; During programming, the voltage of the first voltage source is a programming voltage that is greater than the breakdown voltage of the second gate dielectric layer; The bit lines connected to the selected antifuse memory cell are connected to a low voltage, and the word lines connected to it are connected to a first positive voltage, which turns on the control transistor; the bit lines not connected to the selected antifuse memory cell are all connected to a second positive voltage, and the word lines not connected to the selected antifuse memory cell are all connected to a low voltage. During a read operation, the voltage of the first voltage source is reduced to a third positive voltage. The bit line connected to the selected antifuse memory cell is connected to a sensitive discharge device, and the word line connected to it is connected to a first positive voltage. The bit lines not connected to the selected antifuse memory cell are disconnected from the connection to the sensitive discharge device, and the word lines not connected to the selected antifuse memory cell are all connected to a low voltage. The first positive voltage, the second positive voltage, and the third positive voltage are all greater than or equal to the operating voltage of the NMOS transistor, and the minimum value of the low voltage is 0V.

7. The antifuse OTP memory as described in claim 4, characterized in that: In the storage array, in the same column of the antifuse storage cells, every two antifuse storage cells form an antifuse storage cell combination; In the antifuse memory cell assembly, the active regions of two antifuse memory cells are connected to form an integral structure and share the same first source-drain region and are connected to the corresponding bit lines in the same column through the same contact holes; The active regions of each of the aforementioned antifuse memory cell combinations are isolated from each other by a field oxide layer.

8. The antifuse OTP memory as described in claim 4, characterized in that: The first voltage source supplies power to the entire memory array through a power mesh. Alternatively, the first voltage source is divided into multiple first voltage source sub-blocks, each of which corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source sub-block is selected for power supply.

9. A method for manufacturing an antifuse OTP memory, characterized in that, The steps for forming an antifuse memory cell include: Step 1: Provide a semiconductor substrate, form a well region doped with a second conductivity type in the semiconductor substrate, form a field oxide layer in the well region and define the active region of the antifuse memory cell; Step 2: Forming the gate structure, including: A first dielectric layer and a second conductive material layer are formed sequentially; The formation regions of the first gate structure and the second gate structure are defined using a first photomask; The second conductive material layer and the first dielectric layer are sequentially etched onto the surface of the well region to form a first gate structure and a second gate structure. The first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked sequentially; the second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked sequentially; both the first gate dielectric layer and the second gate dielectric layer are composed of the first dielectric layer after etching; both the first gate conductive material layer and the second gate conductive material layer are composed of the second conductive material layer after etching; a first spacing is provided between the second side of the first gate structure and the first side of the second gate structure; the first spacing is less than the minimum spacing of the layout design rules and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process; Step 3: Form a first sidewall by self-alignment on the first and second sides of the first gate structure and the first and second sides of the second gate structure; The thickness of the first sidewall is less than twice the first spacing, and there is a first gap between the first sidewall at the second side of the first gate structure and the first sidewall at the first side of the second gate structure. Step 4: Perform lightly doped drain implantation of the first conductivity type to form the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region; The first lightly doped drain region is self-aligned and formed in the surface region of the well region at the first sidewall on the first side of the first gate structure; the second lightly doped drain region is self-aligned and formed in the surface region of the well region at the bottom of the first spacer region; the third lightly doped drain region is self-aligned and formed in the surface region of the well region at the first sidewall on the second side of the second gate structure. Step 5: Form a second sidewall by self-aligning the first sidewall of the first sidewall of the first gate structure and the second sidewall of the second gate structure. The second sidewall completely fills the first gap area and forms a source-drain injection barrier structure; Step 6: Perform source / drain implantation with heavy doping of the first conductivity type to form the first source / drain region and the second source / drain region; The first source / drain region is self-aligned and formed on the surface region of the well region at the second sidewall of the first side of the first gate structure; The second source / drain region is self-aligned and formed on the surface region of the well region at the second sidewall on the second side of the second gate structure; The source / drain injection blocking structure ensures that there are no heavily doped source / drain injection regions of the first conductivity type in the surface region of the well region at the bottom of the first spacer region. The first gate structure serves as the gate structure of the control transistor, the second gate structure serves as the gate structure of the antifuse transistor, and the second lightly doped drain region serves as the series node of the control transistor and the antifuse transistor.

10. The method for manufacturing the antifuse OTP memory as described in claim 9, characterized in that: It also includes the following steps: An interlayer film, contact holes, and a front metal layer are formed, and the front metal layer is patterned to form word lines, bit lines, and first voltage source connections. A storage array formed by arranging multiple antifuse storage cells; In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row; Each of the first source / drain regions in the same column is connected to the bit line in the same column through the corresponding contact hole; The second source-drain region of each of the aforementioned antifuse memory cells is floating. The second gate conductive material layer of each antifuse memory cell is connected to the first voltage source line through the corresponding contact hole and connected to the first voltage source through the first voltage source line. The trap region of each of the aforementioned antifuse storage cells is connected to a fixed point.

11. The method for manufacturing the antifuse OTP memory as described in claim 10, characterized in that: Both the control transistor and the antifuse are NMOS, with N-type as the first conductivity type and P-type as the second conductivity type; or, both the control transistor and the antifuse are PMOS, with P-type as the first conductivity type and N-type as the second conductivity type.

12. The method for manufacturing the antifuse OTP memory as described in claim 10, characterized in that: In the storage array, in the same column of the antifuse storage cells, every two antifuse storage cells form an antifuse storage cell combination; In the antifuse memory cell assembly, the active regions of two antifuse memory cells are connected to form an integral structure and share the same first source-drain region and are connected to the corresponding bit lines in the same column through the same contact holes; The active regions of each of the aforementioned antifuse memory cell combinations are isolated from each other by the field oxide layer.

13. The method for manufacturing the antifuse OTP memory as described in claim 10, characterized in that: The first voltage source supplies power to the entire memory array through a power mesh. Alternatively, the first voltage source is divided into multiple first voltage source sub-blocks, each of which corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source sub-block is selected for power supply.

14. The method for manufacturing the antifuse OTP memory as described in claim 9, characterized in that: A first identification layer is used in the layout design of the first photomask. The coverage area of ​​the first identification layer is larger than the formation areas of the first gate structure and the second gate structure, in order to avoid design rule violations of the first spacing.

Images