Semiconductor devices, three-dimensional memory devices, and methods of forming same

Abstract

Semiconductor devices, three-dimensional memory devices, and methods of forming the same are disclosed herein. The semiconductor device includes a semiconductor layer, a stacked structure over the semiconductor layer, a first contact structure, and a second contact structure. The stacked structure includes alternating first layers and first dielectric layers. The stacked structure includes a first portion and a second portion adjacent to the first portion, the first layer of the first portion including a second dielectric layer, and the first layer of the second portion including a conductive layer. A first contact structure extends through the first portion and the semiconductor layer. A second contact structure extends through a portion of the first portion and is connected with one of the conductive layers.

Description

Background Art

[0001] The present disclosure relates to a semiconductor device having multiple contact structures, a three-dimensional (3D) memory device, and a method of manufacturing the same.

[0002] Planar memory cells have been scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] 3D memory architecture can address density limitations in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the invention

[0004] In one aspect, a semiconductor device includes a semiconductor layer, a stacked structure located on the semiconductor layer, a first contact structure, and a second contact structure. The stacked structure includes alternating first layers and first dielectric layers. The stacked structure includes a first portion and a second portion adjacent to the first portion, the first layer of the first portion includes a second dielectric layer, and the first layer of the second portion includes a conductive layer. The first contact structure extends through the first portion and the semiconductor layer. The second contact structure extends through a portion of the first portion and is connected to one of the conductive layers.

[0005] In some embodiments, the first contact structure includes a first segment and a second segment connected to the first segment in a first direction, the first segment includes a first end contacting the second segment, and the second segment includes a second end contacting the first segment. In a second direction perpendicular to the first direction, a size of the first end is greater than a size of the second end.

[0006] In some embodiments, the first section further includes a third end away from the first end, and the second section further includes a fourth end away from the second end. In the second direction, the size of the third end is greater than the size of the first end, and in the second direction, the size of the second end is greater than the size of the fourth end.

[0007] In some embodiments, the first segment is located on a side of the second segment away from the semiconductor layer.

[0008] In some embodiments, the second contact structure includes a vertical contact structure and a horizontal contact structure connected to the vertical contact structure. The vertical contact structure extends in the same direction as the first contact structure. The horizontal contact structure is connected to one of the conductive layers.

[0009] In some embodiments, the first contact structure includes a first joint located in a first stacking pair, and the vertical contact structure extends to the first stacking pair. The first stacking pair is a pair including one of the first dielectric layers and one of the first layers in contact with one of the first dielectric layers.

[0010] In some embodiments, the semiconductor device further includes a third contact structure extending through a portion of the first portion, the third contact structure is connected to the second stack pair, and the first contact structure includes a second bonding portion located in the second stack pair.

[0011] In some embodiments, the first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer. The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The first spacer and the second spacer include the same material, and the first conductor layer and the second conductor layer include the same material.

[0012] In some embodiments, the first contact structure further includes a first filler body surrounded by the first conductor layer.

[0013] In some embodiments, the second contact structure further includes a second filler body surrounded by the second conductor layer, and the first filler body and the second filler body include the same material.

[0014] In some embodiments, the semiconductor device further includes a channel structure extending through the second portion into the semiconductor layer.

[0015] In some embodiments, in the vertical direction, a length of the first contact structure is greater than a length of the channel structure.

[0016] In some embodiments, the second portion includes a first portion and a second portion spaced apart from the first portion. The first portion connects the first portion and the second portion.

[0017] In some embodiments, the semiconductor device further includes a peripheral circuit connected to the first contact structure.

[0018] In some embodiments, the semiconductor device further comprises a first connection layer and a second connection layer, wherein the first connection layer is connected to the first contact structure, and the second connection layer is connected to the peripheral circuit. The first connection layer is bonded to the second connection layer.

[0019] In some embodiments, the peripheral circuit is disposed under the stack structure, and the first contact structure extends through the semiconductor layer to connect with the peripheral circuit.

[0020] In another aspect, a memory device includes a first semiconductor structure, a second semiconductor structure, and a first peripheral circuit. The first semiconductor structure includes: a first stacked structure, the first stacked structure includes alternating first and second dielectric layers; and a first contact structure, the first contact structure extending through the first stacked structure. The second semiconductor structure includes: a second stacked structure, the second stacked structure includes alternating third and fourth dielectric layers; and a second contact structure, the second contact structure extending through the second stacked structure. The first peripheral circuit is connected to the first contact structure and the second contact structure.

[0021] In some embodiments, the first peripheral circuit is bonded to the first semiconductor structure, and the first peripheral circuit includes a first connection structure located between the first semiconductor structure and the second semiconductor structure.

[0022] In some embodiments, the memory device further includes a second peripheral circuit bonded to the second semiconductor structure. The second peripheral circuit includes a second connection structure connected to the second contact structure.

[0023] In some embodiments, the second semiconductor structure is located between the first peripheral circuit and the second peripheral circuit.

[0024] In some embodiments, the first peripheral circuit further includes a semiconductor layer and an interconnect structure extending through the semiconductor layer.

[0025] In some embodiments, the first contact structure includes an insulating filler and a conductor layer surrounding the insulating filler, the interconnect structure includes a conductive filler and a spacer surrounding the conductive filler, and the conductor layer is connected to the conductive filler.

[0026] In some embodiments, the first contact structure includes a first segment and a second segment connected to the first segment in a first direction, the first segment includes a first end contacting the second segment, the second segment includes a second end contacting the first segment, and in a second direction perpendicular to the first direction, a size of the first end is greater than a size of the second end.

[0027] In some embodiments, the first segment further includes a third end away from the first end, and the second segment further includes a fourth end away from the second end, and in the second direction, the size of the third end is larger than the size of the first end, and in the second direction, the size of the second end is larger than the size of the fourth end.

[0028] In some embodiments, the first stacked structure is disposed on the semiconductor layer, and the first segment is located on a side of the second segment away from the semiconductor layer.

[0029] In some embodiments, the first semiconductor structure further includes a third contact structure extending through a portion of the first stacked structure. The third contact structure includes a vertical contact structure and a lateral contact structure connected to the vertical contact structure, and the vertical contact structure extends in the same direction as the first contact structure.

[0030] In some embodiments, the first contact structure includes a first joint located in a first stacking pair, and the vertical contact structure extends to the first stacking pair. The first stacking pair is a pair including one of the first dielectric layers and one of the second dielectric layers that contacts the one of the first dielectric layers.

[0031] In some embodiments, the memory device further includes a fourth contact structure extending through a portion of the first stack structure, the fourth contact structure is connected to the second stack pair, and the first contact structure includes a second joint portion located in the second stack pair.

[0032] In some embodiments, the first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer. The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The third contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The first spacer and the second spacer include the same material, and the first conductor layer and the second conductor layer include the same material.

[0033] In some embodiments, the first contact structure further includes a first filler body surrounded by the first conductor layer.

[0034] In yet another aspect, a method of forming a semiconductor device is disclosed. The method includes forming a stacked structure including alternating first and second dielectric layers. The method also includes forming a first contact hole extending through the stacked structure. The method also includes forming a second contact hole extending through a portion of the stacked structure during the forming of the first contact hole.

[0035] In some embodiments, forming a first contact hole and forming a second contact hole during the formation of the first contact hole includes: etching the stacked structure using a first mask to form a first opening extending into the stacked structure and one or more second openings, wherein the second contact hole includes one or more second openings, and etching the first opening using a second mask to form a third opening further extending through the stacked structure, wherein the first contact hole includes the first opening and the third opening.

[0036] In some embodiments, forming the second contact hole further comprises: etching the stack structure using a third mask to form one or more fourth openings extending into the stack structure. The second contact hole further comprises one or more fourth openings.

[0037] In some embodiments, the method further includes: forming a first contact structure in the first contact hole, and forming a second contact structure in each of the second contact holes during the forming of the first contact structure.

[0038] In some embodiments, the first contact structure includes a first spacer, a first conductor layer surrounded by the first spacer, and a first filler body surrounded by the first conductor layer. The second contact structure includes a second spacer, a second conductor layer surrounded by the second spacer, a lateral contact structure connected to the second conductor layer, and a second filler body surrounded by the second conductor layer.

[0039] In some embodiments, forming a first contact structure and forming a second contact structure include: respectively forming a first spacer on the sidewall of the first contact hole and forming a second spacer on the sidewall of the second contact hole; forming a lateral contact structure of the second contact structure below the bottom of the second contact hole; respectively forming a first conductor layer above the first spacer and the bottom of the first contact hole, and forming a second conductor layer above the second spacer and the lateral contact structure; and respectively filling the remaining portion of the first contact hole with a first filler body and filling the remaining portion of the second contact hole with a second filler body.

[0040] In some embodiments, forming a lateral contact structure of the second contact structure below the bottom of the second contact hole includes: removing portions of the corresponding second dielectric layer exposed at the bottom of the second contact hole to form lateral recesses; and filling the lateral recesses respectively by depositing a conductive material through the second contact hole to form the lateral contact structure.

[0041] In some embodiments, forming the first contact structure and forming the second contact structure further include: forming a first contact pad on the first conductor layer and the first filler body, and forming a second contact pad on the second conductor layer and the second filler body, respectively.

[0042] In yet another aspect, a semiconductor device includes a stacked structure, a first contact structure, and a second contact structure. The stacked structure includes alternating first and second dielectric layers. The first contact structure extends through the stacked structure and includes a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer. The second contact structure extends through a portion of the stacked structure and includes a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer. The first spacer and the second spacer include a first material, and the first and second conductor layers include a second material different from the first material.

[0043] In some embodiments, the first contact structure includes a first segment and a second segment connected to the first segment in a first direction, the first segment includes a first end contacting the second segment, and the second segment includes a second end contacting the first segment. In a second direction perpendicular to the first direction, a size of the first end is greater than a size of the second end.

[0044] In some embodiments, the first section further includes a third end away from the first end, and the second section further includes a fourth end away from the second end. In the second direction, the size of the third end is greater than the size of the first end, and in the second direction, the size of the second end is greater than the size of the fourth end.

[0045] In some embodiments, the first stacked structure is disposed on the semiconductor layer, and the first segment is located on a side of the second segment away from the semiconductor layer.

[0046] In some embodiments, the second contact structure includes a vertical contact structure and a lateral contact structure connected to the vertical contact structure, and the vertical contact structure extends in the same direction as the first contact structure.

[0047] In some embodiments, the first contact structure includes a first joint located in a first stacking pair, and the vertical contact structure extends to the first stacking pair. The first stacking pair is a pair including one of the first dielectric layers and one of the second dielectric layers that contacts the one of the first dielectric layers.

[0048] In some embodiments, the semiconductor device further includes a third contact structure extending through the stack structure, the third contact structure is connected to the second stack pair, and the first contact structure includes a second bonding portion located in the second stack pair.

[0049] In some embodiments, the semiconductor device further includes a peripheral circuit connected to the first contact structure and the second contact structure.

[0050] In another aspect, a memory device includes a first contact structure and a second contact structure. The first contact structure includes an insulating filler and a conductor layer surrounding the insulating filler and extending in a first direction. The second contact structure includes a conductive filler and a spacer surrounding a sidewall of the conductive filler and extending in the first direction. The conductor layer is connected to the conductive filler.

[0051] In yet another aspect, a semiconductor device includes: a semiconductor layer; a stacked structure located above the semiconductor layer and including alternating conductive layers and dielectric layers; a first contact structure extending through the stacked structure and including a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer; and a second contact structure extending through a portion of the stacked structure and including a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer. The second conductor layer is connected to one of the conductive layers, and the first conductor layer is separated from the conductive layer by the first spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable those skilled in the relevant art to make and use the disclosure.

[0053] Figure 1A A plan view of a semiconductor structure having multiple contact structures according to some aspects of the present disclosure is shown.

[0054] Figure 1B Another plan view of a semiconductor structure having multiple contact structures according to aspects of the present disclosure is shown.

[0055] Figure 2A A cross-sectional side view of a first exemplary embodiment of a contact structure according to aspects of the present disclosure is shown.

[0056] Figure 2B According to some aspects of the present disclosure Figure 2A Cross-sectional side view of a first contact structure in FIG.

[0057] Figure 2C A cross-sectional side view of a second exemplary embodiment of a contact structure according to aspects of the present disclosure is shown.

[0058] Figure 3A A cross-sectional side view of a semiconductor device according to some examples is shown.

[0059] Figure 3B A cross-sectional side view of a semiconductor device having multiple contact structures according to some aspects of the present disclosure is shown.

[0060] Figure 4A A cross-sectional side view of a 3D memory device is shown according to some examples.

[0061] Figure 4B A cross-sectional side view of a 3D memory device with multiple contact structures according to some aspects of the present disclosure is shown.

[0062] Figure 4C A cross-sectional side view of another 3D memory device having multiple contact structures according to aspects of the present disclosure is shown.

[0063] Figure 5 A cross-sectional side view of yet another semiconductor device having multiple contact structures according to aspects of the present disclosure is shown.

[0064] Figure 6 A cross-sectional side view of yet another semiconductor device having multiple contact structures according to aspects of the present disclosure is shown.

[0065] Figure 7 is a flow chart of a method for forming a semiconductor device having multiple contact structures according to some aspects of the present disclosure.

[0066] Figure 8A-8F A fabrication process for forming a semiconductor device having multiple contact structures according to some aspects of the present disclosure is shown.

[0067] Fig. 9 is a flow chart of a method for forming a plurality of contact structures in a semiconductor structure according to some aspects of the present disclosure.

[0068] Figures 10A-10G A fabrication process for forming a plurality of contact structures in a semiconductor structure according to some aspects of the present disclosure is shown.

[0069] Fig.11 A block diagram of an exemplary system having a 3D memory device according to some aspects of the present disclosure is shown.

[0070] Fig. 12A A schematic diagram of an exemplary memory card having a 3D memory device according to some aspects of the present disclosure is shown.

[0071] Fig. 12B A schematic diagram of an exemplary solid-state drive (SSD) having a 3D memory device according to some aspects of the present disclosure is shown.

[0072] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0073] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may also be used in various other applications. The functions and structural features described in the present disclosure may be combined, adjusted, and modified with each other and in a manner not explicitly depicted in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0074] In general, a term may be understood, at least in part, from usage in context. For example, depending, at least in part, on the context, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending, at least in part, on the context, terms such as "one" or "the" may also be understood to convey singular usage or to convey plural usage. In addition, also depending, at least in part, on the context, the term "based on" may be understood to not necessarily be intended to convey a set of exclusive factors, but may allow for the presence of additional factors that are not necessarily explicitly described.

[0075] It should be readily understood that the meanings of “on,” “over,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” not only means “over something” or “on something,” but also can include the meaning of “over something” or “on something” with no intervening features or layers therebetween (i.e., directly on something).

[0076] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0077] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0078] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire underlying layer or overlying structure, or may have a range less than the range of the underlying layer or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0079] In some 3D memory devices (e.g., 3D NAND memory devices), a channel structure is formed in a core array region. Memory cells for storing data are stacked vertically by a stacked structure (e.g., a memory stack) in a vertical channel structure. For purposes such as word line pick-up / fan-out using word line contacts that land on different steps / levels of the step structure, the 3D memory device typically includes a step structure formed in a step region (e.g., on one or more sides (edges) or at the center of the stacked memory structure). Through-substrate vias (TSVs) may also be formed on the edge of the step region or outside the step region to provide interconnections across the entire stack structure.

[0080] Initially, the stacked structure may include an interlaced first dielectric layer (e.g., a silicon oxide layer) and a second dielectric layer (e.g., a silicon nitride layer). During the formation of the channel structure, all of the second dielectric layers in the core array region and part of the second dielectric layers in the step region are replaced by a conductive layer, leaving the remaining second dielectric layer in the step region. In some applications, it is necessary to remove the remaining second dielectric layer in the step region and then replace it with silicon oxide. The area where the TSV is located is also filled with silicon oxide. Then, word line contacts and TSVs can be formed by first etching the silicon oxide to form contact holes in the silicon oxide region, and then filling the contact holes with a conductive material. However, with the removal of the remaining second dielectric layer in the step region, the manufacturing process may be complex and costly.

[0081] In order to solve one or more of the aforementioned problems, the present disclosure introduces a solution that can form multiple contact structures in a connection area (an area located outside the core array area) without removing the remaining second dielectric layer in the connection area. The multiple contact structures formed thereby may include a contact structure that extends through only a portion of the stacked structure, a contact structure that extends through the entire stacked structure and only penetrates the semiconductor layer on which a portion of the stacked structure is arranged, a contact structure that extends through both the stacked structure and the semiconductor layer, or any combination thereof. The contact structure that extends through both the stacked structure and the semiconductor layer can be used as an interconnect structure between stacked dies. Since the contact structure disclosed herein can be formed by etching the first dielectric layer and the remaining second dielectric layer, the manufacturing process can be simplified and has low cost.

[0082] Figure 1A A plan view of a semiconductor structure 100 having multiple contact structures according to some aspects of the present disclosure is shown. In some embodiments, the semiconductor structure 100 may be part of a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Note that in Figure 1A 100 includes an x-axis and a y-axis to illustrate two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the word line direction of the semiconductor structure 100 , and the y-direction is the bit line direction of the semiconductor structure 100 .

[0083] like Figure 1A As shown, the semiconductor structure 100 may include one or more blocks 102 arranged in the y direction (bit line direction) and separated by parallel slit structures 108 (e.g., gate line slits (GLS)). In some embodiments where the semiconductor structure 100 is a NAND flash memory device, each block 102 is the minimum erasable unit of the NAND flash memory device. Each block 102 may also include a plurality of fingers 104 separated by some of the slit structures 108 having an "H" cut 109 in the y direction.

[0084] like Figure 1A As shown, the semiconductor structure 100 can be divided into at least a core array region 101 and a connection region 103, an array of channel structures 110 is formed in the core array region 101, and a plurality of contact structures 106, 116 are formed in the connection region 103. According to some embodiments, the core array region 101 and the connection region 103 are arranged in the x direction (word line direction). It should be understood that although Figure 1A1 shows one core array region 101 and one connection region 103, but the semiconductor structure 100 may include multiple core array regions 101 and / or multiple connection regions 103, for example, one connection region 103 located between two core array regions 101 in the x direction, or one core array region 101 located between two connection regions 103. It should also be understood that Figure 1A Only the portion of the core array region 101 adjacent to the connection region 103 is shown.

[0085] As described in detail below, the connection region 103 may include a conductive portion 105 and a dielectric portion 107 arranged in the y-direction. Figure 1A As shown, according to some embodiments, the contact structures 106, 116 are disposed in the dielectric portion 107, while the dummy channel structure 112 is disposed in the conductive portion 105 of the connection region 103 to provide mechanical support and / or load balancing. Figure 1A As shown in FIG. 1 , the dummy channel structure 112 is also disposed in the dielectric portion 107 of the connection region 103, for example, between the contact structures 106 and 116 in the x-direction. In some embodiments, the dummy channel structure 112 is not disposed in the dielectric portion 107 of the connection region 103, that is, it is disposed only in the conductive portion 105 of the connection region 103. Figure 1A As shown, each finger 104 of semiconductor structure 100 may include a row of contact structures 106, 116 disposed in dielectric portion 107 of connection region 103. It should be appreciated that the layout and arrangement of contact structures 106, 116 and the shape of each contact structure 106, 116 may vary in different examples.

[0086] Figure 1B Another plan view of a semiconductor structure 100 having multiple contact structures according to some aspects of the present disclosure is shown. Figure 1B Can include Figure 1A The components in FIG. 1 are similar to the components in FIG. 1 , and similar descriptions will not be repeated herein. Figure 1B In the embodiment, the core array region 101 may include a first portion 101A and a second portion 101B separated from the first portion 101A. The connection region 103 may connect the first portion 101A and the second portion 101B of the core array region 101. For example, the connection region 103 may be located between the first portion 101A and the second portion 101B of the core array region 101.

[0087] Figure 2A A cross-sectional side view of a first exemplary embodiment of a contact structure 106 , 116 according to aspects of the present disclosure is shown. Figure 2B According to some aspects of the present disclosure Figure 2A The following describes in more detail the first contact structure 116 in the cross-sectional side view. Figure 2A and Figure 2B The cross section can be along Figure 1A or Figure 1B AA direction in the dielectric portion 107 of the connection region 103 in the embodiment.

[0088] like Figure 2A As shown in , a stacked structure 203 can be formed on a semiconductor layer 201. In some embodiments, the semiconductor layer 201 can be a substrate, which can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. In some embodiments, the substrate includes single crystal silicon, which is a portion of a wafer on which the semiconductor structure 100 is manufactured, and the substrate is in its original thickness or is thinned. In some embodiments, for example, the substrate includes polycrystalline silicon, which is a semiconductor layer that replaces the portion of the wafer on which the semiconductor structure 100 is manufactured. It should be noted that the x and z axes are included in Figure 2A , to further illustrate the spatial relationship of the components in the semiconductor structure 100. The semiconductor layer 201 of the semiconductor structure 100 includes two lateral surfaces extending laterally in the xy plane: a top surface located on the front side of the wafer on which the stacked structure 203 can be formed, and a bottom surface located on the back side of the wafer opposite to the front side. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether one component (e.g., a layer or a device) of the semiconductor structure 100 is "on," "above," or "below" another component (e.g., a layer or a device) is determined by the position relative to the semiconductor layer 201 of the semiconductor structure 100 in the z-direction (the vertical direction perpendicular to the xy plane). The same concept used to describe spatial relationships applies throughout the present disclosure.

[0089] The stacked structure 203 may include alternating first layers and first dielectric layers 224. The first layers and first dielectric layers 224 may alternate in a vertical direction (z direction). In some embodiments, the stacked structure 203 may include a plurality of stack pairs stacked vertically in the z direction, and each stack pair in the stack pairs includes one first layer in the first layers and one first dielectric layer in the first dielectric layers 224.

[0090] The stacked structure 203 may include a first portion and a second portion adjacent to the first portion. The first portion may be located in the connection region 103. For example, referring to Figure 3B, the first and second portions of the stacked structure 203 may be labeled with a first feature 362 and a second feature 364, respectively. The second portion 364 may include the core array region 101 and a portion of the connection region 103, and the first portion 362 may include the remaining portion of the connection region 103. In another example, the second portion may include the core array region 101 and the conductive portion 105 of the connection region 103. The first portion may include the dielectric portion 107 of the connection region 103. By way of example, Figure 2A Only a first portion of the stacked structure 203 is shown.

[0091] In some embodiments, semiconductor structure 100 may be part of a NAND flash memory device, and stack structure 203 may be a stacked memory structure by which NAND memory strings are formed. Figure 3B and Figure 8B-Figure 8F As shown, the first layer of the stacked structure 203 may have different materials in different regions / portions of the semiconductor structure 100. For example, the first layer in the first portion of the stacked structure 203 may include the second dielectric layer 222. The first layer in the second portion of the stacked structure may include the conductive layer 302. Figure 2A 2 shows a first portion of a stacked structure 203, which may include alternating first dielectric layers 224 and second dielectric layers 222. Figure 3B and Figure 8B-Figure 8F As shown, the second portion of the stack structure 203 may include alternating first dielectric layers 224 and conductive layers 302 .

[0092] As follows about Figure 8A-8F As described in detail in the manufacturing process of FIG. 1 , by controlling the different degrees and ranges of the gate replacement process in different regions / portions, it is possible to form a stacked structure 203 having first layers of different materials in different regions / portions. For example, the stacked structure 203 may have undergone a complete gate replacement process in the core array region 101, thereby replacing all the second dielectric layers 222 with the conductive layer 302, and may have undergone a partial gate replacement process in the connection region 103, thereby replacing some of the second dielectric layers 222 with the conductive layer 302 in a portion of the connection region 103, leaving the remaining second dielectric layers 222 in the remaining portion of the connection region 103.

[0093] In some embodiments, each conductive layer in the second portion of the stacked structure 203 (within the core array region 101 and the conductive portion 105 of the connection region 103) serves as a gate line (in the form of a channel structure 110) for the NAND memory string in the core array region 101, and a word line extending laterally from the gate line and terminating in the conductive portion 105 of the connection region 103 for word line pickup / fan-out via a word line pickup structure (e.g., contact structure 106). According to some embodiments, each word line (i.e., conductive layer) located at a different depth / level in the second portion of the stacked structure 203 extends laterally in the core array region 101 and the conductive portion 105 of the connection region 103, but is discontinuous (e.g., replaced by a second dielectric layer 222) in the dielectric portion 107 of the connection region 103.

[0094] Conductive layer 302 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. First dielectric layer 224 or second dielectric layer 222 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. First dielectric layer 224 and second dielectric layer 222 may have different dielectric materials, such as silicon oxide and silicon nitride, respectively. In some embodiments, conductive layer 302 includes a metal (e.g., tungsten), first dielectric layer 224 includes silicon oxide, and second dielectric layer 222 includes silicon nitride.

[0095] By way of example, Figure 2A A first contact structure 116, a second contact structure 106A, and a third contact structure 106B are shown. The second contact structure 106A and the third contact structure 106B (individually or collectively 106) may be examples of word line pickup structures. According to some embodiments, the second contact structure 106A and the third contact structure 106B extend vertically into the stacked structure 203 (the dielectric portion 107 of the connection region 103) at different depths in the z-direction. The top surfaces of the second contact structure 106A and the third contact structure 106B may be flush with each other, while the bottom surfaces of the second contact structure 106A and the third contact structure 106B may extend to different horizontal planes, for example, different second dielectric layers 222 of the stacked structure 203.

[0096] In some embodiments, each of the second contact structure 106A and the third contact structure 106B includes a vertical contact structure (e.g., a conductor layer 202) and a lateral contact structure 206 connected to the vertical contact structure. The vertical contact structure extends in the same direction as the first contact structure 116. The lateral contact structure 206 is connected to one of the conductive layers 302. For example, each of the second contact structure 106A and the third contact structure 106B includes a conductor layer 202, a spacer 204 surrounding the conductor layer 202, and a lateral contact structure 206 located below the conductor layer 202 and in contact with the conductor layer 202. The conductor layer 202 and the lateral contact structure 206 may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof. The spacer 204 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer 202 and the lateral contact structure 206 include TiN / W, and the spacer 204 includes silicon oxide.

[0097] In some embodiments, each of the second contact structure 106A and the third contact structure 106B may further include a filler body 208 surrounded by the conductor layer 202. The filler body 208 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Each of the second contact structure 106A and the third contact structure 106B may further include a contact pad 210 located on top of and in contact with the filler body 208 and the conductor layer 202. The contact pad 210 may be electrically connected to the conductor layer 202. The contact pad 210 may include a conductive material including, but not limited to, W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof.

[0098] The first contact structure 116 may be a contact structure that may extend through the stacked structure 203 and a portion of the semiconductor layer 201 or the entire semiconductor layer 201. For example, the first contact structure 116 may penetrate the stacked structure 203 and a portion of the semiconductor layer 201. In another example, Figure 2A As shown, the first contact structure 116 may penetrate both the stack structure 203 and the semiconductor layer 201 .

[0099] refer to Figure 2B, the first contact structure 116 may include a first segment 250 and a second segment 252 connected to the first segment 250 in the z-direction. The first segment 250 may be located on a side of the second segment 252 away from the semiconductor layer 201. The first segment 250 may include a first end 256 contacting the second segment 252, and the second segment 252 may include a second end 258 contacting the first segment 250. In the x-direction perpendicular to the z-direction, the size of the first end 256 may be greater than the size of the second end 258. The first segment 250 may further include a third end 254 away from the first end 256, and the second segment 252 may further include a fourth end 260 away from the second end 258. In the x-direction, the size of the third end 254 may be greater than the size of the first end 256, and in the x-direction, the size of the second end 258 may be greater than the size of the fourth end 260.

[0100] Return to reference Figure 2A , the first contact structure 116 may include a conductor layer 212 and a spacer 214 surrounding the conductor layer 212. The first contact structure 116 may also include a filler 218 surrounded by the conductor layer 212, and a contact pad 220 located on top of the filler 218 and the conductor layer 212 and in contact with the filler 218 and the conductor layer 212. The contact pad 220 may be electrically connected to the conductor layer 212. In some embodiments, the spacers 204 and 214 may include the same material or different materials, which is not limited herein. The conductor layers 202 and 212 may include the same material or different materials, which is not limited herein. The fillers 208 and 218 may include the same material or different materials, which is not limited herein.

[0101] In some embodiments, the vertical contact structure (e.g., conductor layer 202) of the second contact structure 106A can extend to the first stacking pair. The first stacking pair can be a pair including (a) one of the first dielectric layers 224 and (b) one of the first layers that contacts one of the first dielectric layers 224. For example, Figure 2A As shown, the first stack pair may include a first dielectric layer 224A and a second dielectric layer 222A adjacent to the first dielectric layer 224A. The lateral contact structure 206 of the second contact structure 106A may be located in the second dielectric layer 222A of the first stack pair. The first contact structure 116 may include a first joint 216 located in the first stack pair. Figure 2B As shown, the first section 250 and the second section 252 of the first contact structure 116 may be connected to each other at the first joint 216 .

[0102] In some embodiments, Figure 2AAs shown, the vertical contact structure (e.g., conductor layer 202) of the third contact structure 106B can extend to the second stack pair. The second stack pair can include a first dielectric layer 224B and a second dielectric layer 222B adjacent to the first dielectric layer 224B. The lateral contact structure 206 of the third contact structure 106B can be located in the second dielectric layer 222B of the second stack pair.

[0103] Figure 2C A cross-sectional side view of a second exemplary embodiment of a contact structure 106, 116 according to some aspects of the present disclosure is shown. The cross section may be along Figure 1A or Figure 1B AA direction in the dielectric portion 107 of the connection region 103 in the embodiment. Figure 2C Can include Figure 2A-2B and similar descriptions will not be repeated herein. Figure 2A-2B compared to, Figure 2C The first contact structure 116 in the embodiment may include three sections, for example, a first section, a second section, and a third section from top to bottom. The first section and the second section are connected to each other at the first joint portion 216. The second section and the third section are connected to each other at the second joint portion 217. Figure 2A In contrast, the third contact structure 106B may include two segments, for example, a first segment on the top of the third contact structure 106B and a second segment at the bottom of the third contact structure 106B. The first segment and the second segment of the third contact structure 106B may be connected to each other at the third joint 219 .

[0104] The vertical contact structure (e.g., conductor layer 202) of the second contact structure 106A may extend to the first stack pair (first dielectric layer 224A and second dielectric layer 222A). The lateral contact structure 206 of the second contact structure 106A may be located in the second dielectric layer 222A of the first stack pair. The first joint 216 of the first contact structure 116 and the third joint 219 of the third contact structure 106B may be located in the first stack pair.

[0105] The vertical contact structure (e.g., conductor layer 202) of the third contact structure 106B may extend to the second stack pair (first dielectric layer 224B and second dielectric layer 222B). The lateral contact structure 206 of the third contact structure 106B may be located in the second dielectric layer 222B of the second stack pair. The second joint 217 of the first contact structure 116 may be located in the second stack pair.

[0106] Figure 3AA cross-sectional side view of a semiconductor device 300 according to some examples is shown. The semiconductor device 300 may include a semiconductor structure 329 and a peripheral circuit 330 stacked on and connected to the semiconductor structure 329. The peripheral circuit 330 may include a semiconductor layer 331 and a device layer 332 disposed on and in contact with the semiconductor layer 331. In some embodiments, the device layer 332 includes one or more circuits, such as a drive circuit, a page buffer circuit, and a logic circuit. In some embodiments, the device layer 332 includes a plurality of transistors 333 in contact with the semiconductor layer 331. The transistor 333 may include any transistor, such as a metal oxide semiconductor (MOS) transistor, a complementary metal oxide semiconductor (CMOS) transistor, or other type of transistor.

[0107] In some embodiments, the peripheral circuit 330 may further include a connection layer 334 and a bonding layer 335. The connection layer 334 may be connected to the device layer 332 to transmit electrical signals to and from the device layer 332. Figure 3A As shown, the connection layer 334 can be vertically located between the bonding layer 335 and the device layer 332. The connection layer 334 may include a plurality of interconnects (also referred to herein as "contacts") including lateral lines and vias. As used herein, the term "interconnect" may broadly include any appropriate type of interconnect, such as middle-end process (MEOL) interconnects and back-end process (BEOL) interconnects. The interconnects in the connection layer 334 may be coupled to transistors 333 located in the device layer 332. The connection layer 334 may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers") in which lateral lines and vias may be formed. That is, the connection layer 334 may include lateral lines and vias located in multiple ILD layers. In some embodiments, the devices located in the device layer 332 are coupled to each other via interconnects located in the connection layer 334. For example, different transistors 333 may be coupled to each other via the connection layer 334. The interconnects in the connection layer 334 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the connection layer 334 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. In some embodiments, the interconnects in the connection layer 334 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (fewer defects, e.g., voids) among conductive metal materials.

[0108] The semiconductor structure 329 may be divided into at least a core array region 311 and a connection region 315. The connection region 315 may also be divided into a step region 316 and a region 313 located outside the step region 316. In the core array region 311, the semiconductor structure 329 may include a semiconductor layer 301 and a stacked structure formed on the semiconductor layer 301. The stacked structure may include an interlaced conductive layer 302 and a first dielectric layer 304. The semiconductor structure 329 may also include a channel structure 310 extending through the stacked structure. Memory cells for storing data are vertically stacked by the stacked structure (e.g., a memory stack) in a vertical channel structure.

[0109] like Figure 3A As shown, the semiconductor structure 329 may also include a connection layer 308 formed on the channel structure 310 and electrically connected to the channel structure 310 to transmit electrical signals to and from the memory cells formed in the channel structure 310. In some embodiments, the connection layer 308 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects located in the connection layer 308 also include local interconnects, such as bit line contacts and word line contacts. The connection layer 308 may also include one or more ILD layers in which lateral lines and vias may be formed. The interconnects located in the connection layer 308 may include a conductive material, including but not limited to: W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer located in the connection layer 308 may include a dielectric material, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0110] In the step region 316, the semiconductor structure 329 may include a step structure. The semiconductor structure 329 may also include a word line contact 312, which extends through the dielectric material (e.g., oxynitride) filled above the step structure and lands on different steps / levels of the step structure. In a region 313 located on the edge of the step region 316 or outside the step region 316, the semiconductor structure 329 may also include a TSV 314 extending through both (a) the dielectric material (e.g., oxynitride) filled in the region 313 and (b) the semiconductor layer 301.

[0111] like Figure 3AAs shown, the semiconductor structure 329 may include a bonding layer 325 located above the connection layer 308 and in contact with the connection layer 308. In some embodiments, the semiconductor structure 329 and the peripheral circuit 330 may be coupled to each other by hybrid bonding. Hybrid bonding (also referred to as "metal / dielectric hybrid bonding") is a direct bonding technology (e.g., bonding is formed without using an intermediate layer such as solder or adhesive between surfaces), and metal-metal bonding and dielectric-dielectric bonding can be obtained simultaneously. Hybrid bonding in a face-to-face manner can achieve millions of parallel short interconnections between bonded semiconductor structures, thereby increasing the throughput and input / output (I / O) speed of the semiconductor packaging structure. Each of the bonding layers 325 and 335 may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, such as Cu. The remaining area of ​​each of the bonding layers 325 and 335 may be formed by a dielectric material (e.g., silicon oxide). The bonding contacts and surrounding dielectric in each of the bonding layers 325 , 335 may be used for hybrid bonding.

[0112] The manufacturing process of semiconductor structure 329 is briefly described herein. Initially, a stack structure including an interlaced first dielectric layer 304 (e.g., a silicon oxide layer) and a second dielectric layer (e.g., a silicon nitride layer) may be formed on semiconductor layer 301. A channel structure 310 may be formed to extend through the stack structure and into semiconductor layer 301. Then, all of the second dielectric layers in core array region 311 and a portion of the second dielectric layers in the step structure are replaced by conductive layer 302, leaving the remaining second dielectric layers in step region 316. The remaining second dielectric layers in step region 316 may be removed and then replaced by silicon oxide. Region 313 is also filled with silicon oxide. As a result, silicon oxide region 328 may be formed. Then, word line contacts 312 in step region 316 and TSV 314 in region 313 may be formed by first forming contact holes in silicon oxide region 328 and then filling the contact holes with a conductive material. The manufacturing process requires removal of the remaining second dielectric layer in step region 316, which may be complicated.

[0113] Figure 3B 1 shows a cross-sectional side view of a semiconductor device 350 having a plurality of contact structures 106, 116 according to some aspects of the present disclosure. As described in more detail below, Figure 3A In contrast, a plurality of contact structures 106, 116 may be formed in the connection region 103 without removing the remaining second dielectric layer 222 in the connection region 103. Therefore, the manufacturing process of the semiconductor device 350 may be simplified. Figure 3B Can include Figure 1A-1B , Figure 2A-2C and Figure 3A The components are similar to those in , and similar descriptions will not be repeated in this article.

[0114] The semiconductor device 350 may include a semiconductor structure 360 ​​and a peripheral circuit 330 stacked on and connected to the semiconductor structure 360. The semiconductor structure 360 ​​may be divided into at least a core array region 101 and a connection region 103. In some embodiments, the semiconductor structure 360 ​​may include a semiconductor layer 201 and a stacked structure 203 located above the semiconductor layer 201. The stacked structure 203 may include alternating first layers and first dielectric layers 224. The stacked structure 203 may include a first portion 362 and a second portion 364 adjacent to the first portion 362. In some examples, the second portion 364 of the stacked structure 203 may include a first portion located in the core array region 101A and a second portion (such as a first portion) located in the core array region 101B and separated from the first portion. Figure 1B As shown), wherein the first portion 362 of the stacked structure 203 connects the first portion and the second portion.

[0115] The first layer of the first portion 362 may include the second dielectric layer 222, and the first layer of the second portion 364 may include the conductive layer 302. For example, the first portion 362 of the stacked structure 203 may include the staggered second dielectric layer 222 and the first dielectric layer 224. The second portion 364 of the stacked structure 203 may include the staggered conductive layer 302 and the first dielectric layer 224.

[0116] In some embodiments, the semiconductor structure 360 ​​may further include (a) a first contact structure 116 extending through the first portion 362 and the semiconductor layer 201 and (b) a second contact structure 106 extending through a portion of the first portion 362 and connected to one of the conductive layers 302. For example, a vertical contact structure (e.g., a conductor layer 202) of the second contact structure 106 may extend to the first stacking pair (e.g., a stacking pair including the first dielectric layer 224A and the second dielectric layer 222A). A lateral contact structure 206 of the second contact structure 106 may be located in the second dielectric layer 222A and connected to the conductive layer 302A located in the same layer (e.g., the second dielectric layer 222A and the conductive layer 302A are different parts of the same first layer).

[0117] The semiconductor structure 360 ​​may further include a channel structure 110 extending through the second portion 364 into the semiconductor layer 201. The length of the first contact structure 116 may be greater than the length of the channel structure 110 in the vertical direction (eg, z-direction).

[0118] like Figure 3BAs shown, the semiconductor structure 360 ​​may further include a connection layer 308 formed on the channel structure 110 and electrically connected to the channel structure 110 to transmit electrical signals to and from the memory cells formed in the channel structure 110. The connection layer 308 may also be connected to the first contact structure 116 and the second contact structure 106. Figure 3B As shown, the semiconductor structure 360 ​​may include a bonding layer 325 located above and in contact with the connection layer 308. In some embodiments, the semiconductor structure 360 ​​and the peripheral circuit 330 may be coupled to each other via hybrid bonding. For example, the connection layer 334 of the peripheral circuit 330 may be bonded to the connection layer 308 of the semiconductor structure 360 ​​using bonding layers 335 and 325. The bonding contacts and surrounding dielectrics in each of the bonding layers 325 and 335 may be used for hybrid bonding.

[0119] In some embodiments, the peripheral circuit 330 may be connected to the first contact structure 116. In some embodiments, the peripheral circuit 330 may be disposed below the stack structure 203, and the first contact structure 116 may extend through the semiconductor layer 301 to connect to the peripheral circuit 330.

[0120] Consistent with some aspects of the present disclosure, the semiconductor structure 360 ​​may include a stacked structure 203 having a uniform height (e.g., without steps) and a second contact structure 106 for word line pick-up / fan-out located in the dielectric portion 107 of the connection region 103, rather than having a stepped structure and word line contacts landing on different levels / steps of the stepped structure. Figure 3B As shown, the lateral contact structure 206 of each second contact structure 106 in the dielectric portion 107 can extend laterally in a plane defined by the x-direction and the y-direction to contact the corresponding conductive layer 302 (word line) in the conductive portion 105 located at the same level of the stacked structure 203. According to some embodiments, since the lateral contact structure 206 contacts the conductor layer 202 of the second contact structure 106, each second contact structure 106 is electrically connected to the corresponding conductive layer 302 (word line) across the conductive portion 105 in the connection region 103 and the core array region 101. In other words, the second contact structure 106 can vertically extend through the stacked structure 203 at different depths to be electrically connected to the word lines located at different levels, respectively, so as to achieve word line pick-up / fan-out.

[0121] Consistent with some aspects of the present disclosure, the first contact structure 116 and the second contact structure 106 may be formed in the same region or in different regions, which is not limited herein. For example, the first contact structure 116 may be formed near the seal ring, and the second contact structure 106 may be formed in a region near the core array region 101. The semiconductor device disclosed herein may include: (a) a stacked structure including alternating first and second dielectric layers; (b) a first contact structure 116 extending through the stacked structure and including a first conductor layer and a first spacer surrounding the sidewalls of the first conductor layer; and (c) a second contact structure extending through a portion of the stacked structure and including a second conductor layer and a second spacer surrounding the sidewalls of the second conductor layer. The first spacer and the second spacer may include a first material (e.g., a dielectric material), and the first and second conductor layers may include a second material (e.g., a conductive material) different from the first material.

[0122] Figure 4A 1 shows a cross-sectional side view of a 3D memory device 400 according to some examples. The memory device 400 may include a first semiconductor device 300A and a second semiconductor device 300B. The first semiconductor device 300A and the second semiconductor device 300B may have Figure 3A The first semiconductor device 300A and the second semiconductor device 300B may be bonded together to form the memory device 400.

[0123] For example, the first semiconductor device 300A may include a first semiconductor structure 329A and a first peripheral circuit 330A. The first semiconductor structure 329A may include a word line contact 312A and a TSV 314A. The second semiconductor device 300B may include a second semiconductor structure 329B and a second peripheral circuit 330B. The second semiconductor structure 329B may include a word line contact 312B and a TSV 314B. It is contemplated that the first semiconductor structure 329A and the second semiconductor structure 329B may have the same Figure 3A The first peripheral circuit 330A and the second peripheral circuit 330B may have a structure similar to that of the semiconductor structure 329 in FIG. Figure 3A The word line contacts 312A and 312B may have a structure similar to that of the peripheral circuit 330 in FIG. Figure 3A The TSVs 314A and 314B may have a structure similar to that of the word line contact 312 in FIG. Figure 3A The structure of the TSV 314 is similar to that of the TSV 314. Similar descriptions will not be repeated herein.

[0124] like Figure 4A As shown, the memory device 400 may further include a through-die contact structure 402 extending through both the first semiconductor device 300A and the second semiconductor device 300B. In addition to the TSVs 314A, 314B and the word line contacts 312A, 312B, the through-die contact structure 402 is additionally formed in the memory device 400, which may require additional manufacturing operations, such as forming a via extending through both the first semiconductor device 300A and the second semiconductor device 300B, forming a spacer on the sidewall of the via, and then filling the via with a conductive material to form a filler. Forming the through-die contact structure 402 may make the manufacturing process more complicated.

[0125] Figure 4B 4 shows a cross-sectional side view of a 3D memory device 450 having multiple contact structures 106, 116 according to some aspects of the present disclosure. Figure 4A Differently, memory device 450 can utilize contact structure 116 to form a through-die contact structure and thus does not need to form a through-die contact structure. Figure 4A The additional through-die contact structure 402 is similar to the through-die contact structure in FIG. Therefore, the manufacturing process can be simplified.

[0126] The memory device 450 may include a first semiconductor device 350A and a second semiconductor device 350B. The first semiconductor device 350A and the second semiconductor device 350B may have Figure 3B 350B and 350B may be similar to the structure of the semiconductor device 350 in the embodiment, and similar descriptions will not be repeated herein. For example, the first semiconductor device 350A may include a first semiconductor structure 360A and a first peripheral circuit 330A. The first semiconductor structure 360A may include a first stacked structure 203A and a channel structure 110A extending through the first stacked structure 203A. The first semiconductor structure 360A may also include a first contact structure 116A, and the first contact structure 116A may include a spacer 214A, a conductor layer 212A, and a filler 218A. The second semiconductor device 350B may include a second semiconductor structure 360B and a second peripheral circuit 330B. The second semiconductor structure 360B may include a second stacked structure 203B and a channel structure 110B extending through the second stacked structure 203B. The second semiconductor structure 360B may also include a first contact structure 116B, and the first contact structure 116B may include a spacer 214B, a conductor layer 212B, and a filler 218B. It is contemplated that the first semiconductor structure 360A and the second semiconductor structure 360B may have Figure 3B The stacked structures 203A and 203B may have a structure similar to that of the semiconductor structure 360 ​​in FIG. Figure 2A-2B and Figure 3BThe first contact structures 116A and 116B may have a structure similar to that of the stacked structure 203 in FIG. Figure 2A-2B and Figure 3B The structure of the first contact structure 116 in FIG. 1 is similar to that of the first contact structure 116 in FIG. Similar description will not be repeated herein.

[0127] The first semiconductor device 350A and the second semiconductor device 350B can be bonded together to form a memory device 450. For example, a bonding layer 454 can be formed between the first semiconductor device 350A and the second semiconductor device 350B to bond the two devices together. Any suitable bonding technology can be applied to the bonding layer 454, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc. An interconnect structure 458 can be formed in the bonding layer 454, so that the interconnect structure 452A of the first peripheral circuit 330A can be connected to the first contact structure 116B of the semiconductor structure 360B through the interconnect structure 458.

[0128] Consistent with some aspects of the present disclosure, the memory device 450 may include: (a) a first semiconductor structure 360A, the first semiconductor structure 360A including a first stacking structure and a contact structure 116A extending through the first stacking structure 203A; (b) a second semiconductor structure 360B, the second semiconductor structure 360B including a second stacking structure 203B and a contact structure 116B extending through the second stacking structure 203B; and (c) a first peripheral circuit 330A, the first peripheral circuit 330A being connected to the contact structures 116A and 116B.

[0129] In some embodiments, the first stacked structure 203A may include alternating first and second dielectric layers. The second stacked structure 203B may include alternating third and fourth dielectric layers. The third and fourth dielectric layers may include the same material as the first and second dielectric layers, respectively.

[0130] In some embodiments, the first peripheral circuit 330A may be bonded to the first semiconductor structure 360A, and the first peripheral circuit 330A may include a first connection structure 455A between the first semiconductor structure 360A and the second semiconductor structure 360B. The first connection structure 455A may be filled with a filler 456A.

[0131] In some embodiments, the memory device 450 may further include a second peripheral circuit 330B bonded to the second semiconductor structure 360B. The second semiconductor structure 360B may be located between the first peripheral circuit 330A and the second peripheral circuit 330B. The second peripheral circuit 330B may include a second connection structure 455B connected to the contact structure 116B. The second connection structure 455B may be filled with a filler 456B.

[0132] In some embodiments, the first peripheral circuit 330A may further include a semiconductor layer 331A and an interconnect structure 452A extending through the semiconductor layer 331A. The interconnect structure 452A may include a conductive filler 454A and a spacer 453A surrounding the conductive filler 454A. Similarly, the second peripheral circuit 330B may further include a semiconductor layer 331B and an interconnect structure 452B extending through the semiconductor layer 331B. The interconnect structure 452B may include a conductive filler 454B and a spacer 453B surrounding the conductive filler 454B.

[0133] In some embodiments, the first contact structure 116A may include an insulating filler (e.g., filler body 218A) and a conductor layer 212A surrounding the insulating filler, and the interconnect structure 452A may include a conductive filler 454A and a spacer 453A surrounding the conductive filler 454A. The conductor layer 212A of the first contact structure 116A may be connected to the conductive filler 454A of the interconnect structure 452A. Similarly, the second contact structure 116B may include an insulating filler (e.g., filler body 218B) and a conductor layer 212B surrounding the insulating filler, and the interconnect structure 452B may include a conductive filler 454B and a spacer 453B surrounding the conductive filler 454B. The conductor layer 212B of the second contact structure 116B may be connected to the conductive filler 454B of the interconnect structure 452B.

[0134] Consistent with some aspects of the present disclosure, a memory device disclosed herein may include: (a) a first contact structure (e.g., 116A) including an insulating filler and a conductor layer surrounding the insulating filler and extending in a first direction (e.g., z-direction); and (b) a second contact structure (e.g., 452A) including a conductive filler and a spacer surrounding a sidewall of the conductive filler and extending in the first direction. The conductor layer is connected to the conductive filler.

[0135] Figure 4C 4 shows a cross-sectional side view of another 3D memory device 480 having multiple contact structures according to some aspects of the present disclosure. The memory device 480 may have Figure 4B The components of the memory device 450 are similar to those of the components in FIG. 4 , and similar descriptions will not be repeated herein. Figure 4C The first contact structure 116 in may have Figure 4B Specifically, in Figure 4C In the embodiment, each first contact structure 116 may include a conductive filler body and a spacer surrounding the conductive filler body. The conductive filler body may include any conductive material disclosed herein. For example, Figure 4C As shown, the first contact structure 116A of the first semiconductor device 350A may include a conductive filler body 484 and a spacer 214 surrounding the conductive filler body 484 .

[0136] Figure 5 A cross-sectional side view of another semiconductor device 500 with multiple contact structures according to some aspects of the present disclosure is shown. The semiconductor device 500 may include a semiconductor structure 550 and a peripheral circuit 330. The semiconductor structure 550 may include a semiconductor layer 501, a stack structure located on the semiconductor layer 501 and including alternating conductive layers 502 and dielectric layers 504, a channel structure 110 extending through the stack structure, a first contact structure 516 extending through the stack structure, and a second contact structure 506 extending through a portion of the stack structure. The first contact structure 516 may include a first conductor layer 522 and a first spacer 524 surrounding a sidewall of the first conductor layer 522. The second contact structure 506 may include a second conductor layer 512 and a second spacer 514 surrounding a sidewall of the second conductor layer 512. The second conductor layer 512 is connected to one of the conductive layers 502 (e.g., conductive layer 502A), and the first conductor layer 522 and the conductive layer 302 are separated by the first spacer 524.

[0137] It is contemplated that the first contact structure 516 may have Figure 2A-2C , Figure 3B and Figure 4B The second contact structure 506 may have a structure similar to the structure of the first contact structure 116 in FIG. Figure 2A-2C , Figure 3B and Figure 4B The structure of the second contact structure 106 is similar to that of the second contact structure 106. However, Figure 5 The first contact structure 516 and the second contact structure 506 extend through the alternating conductive layers 502 and dielectric layers 504, and Figure 2A-2C , Figure 3B and Figure 4B The first contact structures 116 and the second contact structures 106 in FIG. 1 extend through alternating first dielectric layers 224 and second dielectric layers 222 . Figure 5The second contact structure 506 in the embodiment has no lateral contact structure. The second contact structure 506 may extend to a stacking pair including the conductive layer 502A and the dielectric layer 504A, and the first contact structure 516 may have a joint located in the stacking pair.

[0138] Figure 6 A cross-sectional side view of another semiconductor device 600 with multiple contact structures according to some aspects of the present disclosure is shown. The semiconductor device 600 may include a semiconductor structure 650 and a peripheral circuit 330. The semiconductor structure 650 may include a semiconductor layer 601, a stack structure located above the semiconductor layer 601 and including alternating conductive layers and dielectric layers, a channel structure 110 extending through the stack structure, and contact structures 616A, 616B extending through the stack structure and the semiconductor layer 601. The contact structures 616A and 616B are located in the connection regions 103A and 103B, respectively. In some embodiments, the peripheral circuit 330 may be disposed below the stack structure, and the contact structures 616A, 616B may extend through the semiconductor layer 601 to connect to the peripheral circuit 330.

[0139] It is contemplated that the contact structures 616A, 616B may have Figure 2A-2C , Figure 3B and Figure 4B However, the contact structures 616A, 616B extend through alternating conductive and dielectric layers, while Figure 2A-2C , Figure 3B and Figure 4B The first contact structure 116 in FIG. 1 extends through the alternating first dielectric layers 224 and second dielectric layers 222 .

[0140] Figure 7 is a flow chart of a method 700 for forming a semiconductor device having multiple contact structures according to some aspects of the present disclosure. Figure 8A-8F A fabrication process for forming a semiconductor device having multiple contact structures according to some aspects of the present disclosure is shown. Figure 7 and Figure 8A-8F Examples of semiconductor devices depicted in the drawings include Figure 3B The semiconductor device 350 depicted in FIG. Figure 7 and Figure 8A-8F It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Figure 7 The order shown in the figure is different from the order in which it is executed.

[0141] refer to Figure 7, method 700 begins at operation 702, in which a stack structure including an alternating first dielectric layer and a second dielectric layer is formed on a semiconductor layer. The first dielectric layer may include silicon oxide, and the second dielectric layer may include silicon nitride. The stack structure may be formed by one or more thin film deposition processes, including but not limited to ALD, CVD, PVD, or any combination thereof.

[0142] Method 700 proceeds to operation 704, such as Figure 7 As shown in , in operation 704, a channel structure extending through the first dielectric layer and the second dielectric layer is formed in the core array region of the stacked structure. Fig. 8A A stack structure 203 including staggered first and second dielectric layers 224 and 222 may be formed over the semiconductor layer 201 . A channel structure 110 may be formed to extend through the stack structure 203 into the semiconductor layer 201 .

[0143] In some embodiments, to form a channel structure, a channel hole extending vertically through the stacked structure is formed, and a memory layer and a channel layer are sequentially formed on the sidewalls of the channel hole. In some embodiments, to form a channel structure, a channel hole extending vertically through the stacked structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed on the sidewalls of the channel hole. In some embodiments, in the same process of forming the channel structure, a dummy channel structure (e.g., a dummy channel structure extending through the first dielectric layer and the second dielectric layer) is formed in a second region of the stacked structure. Figure 1A That is, the channel structure and the dummy channel structure may be simultaneously formed through the first dielectric layer and the second dielectric layer in the first portion and the second portion of the stacked structure, respectively.

[0144] In some embodiments, in order to form a channel structure, a plurality of channel holes are opened so that each channel hole becomes a position for growing a single channel structure in a subsequent process. In some embodiments, the manufacturing process of the channel hole for forming the channel structure includes wet etching and / or dry etching, such as deep reactive ion etching (DRIE). Subsequently, a memory layer (including a barrier layer, a storage layer, and a tunneling layer) and a channel layer are sequentially formed along the sidewalls and bottom surfaces of the channel hole in this order. In some embodiments, the memory layer is first deposited along the sidewalls and bottom surfaces of the channel hole, and then a semiconductor channel is deposited on the memory layer. Subsequently, the barrier layer, the storage layer, and the tunneling layer can be sequentially deposited in this order using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other appropriate process, or any combination thereof) to form a memory layer. Then, a channel layer can be formed by depositing a semiconductor material (e.g., polysilicon) on the tunneling layer of the memory layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other appropriate process, or any combination thereof). In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are subsequently deposited to form a memory layer and a channel layer of the channel structure.

[0145] In some embodiments, a high-k gate dielectric layer is formed before forming the memory layer. That is, the high-k gate dielectric layer, the memory layer (including the barrier layer, the storage layer, and the tunneling layer), and the channel layer can be sequentially formed in this order along the sidewalls and bottom surfaces of the channel hole. In some embodiments, the high-k gate dielectric layer is first deposited along the sidewalls and bottom surfaces of the channel hole, and then the memory layer is deposited on the high-k gate dielectric layer, and then the semiconductor channel is deposited on the memory layer. The high-k gate dielectric layer can be formed by depositing a high-k dielectric material (e.g., aluminum oxide) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). Subsequently, a barrier layer, a storage layer, and a tunneling layer can be sequentially deposited on the high-k gate dielectric layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) in this order to form a memory layer. A channel layer may then be formed by depositing a semiconductor material (e.g., polysilicon) over the tunneling layer of the memory layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are subsequently deposited to form a high-k gate dielectric layer, a memory layer, and a channel layer of the channel structure.

[0146] In some embodiments, in the same process of forming the channel structure, in the stacked structure (eg, Figure 2A , Figure 2C and Figure 3B The connection area of ​​the stacked structure 203) (for example, Figure 1A-1B and Figure 3B A dummy channel structure (eg, Figure 1A-1B dummy channel structure 112 in the stack). To form each dummy channel structure, a dummy channel hole can be formed in the connection area simultaneously with the channel hole by the same wet etching and / or dry etching (e.g., DRIE), and the dummy channel hole is another opening extending vertically through the stacked structure. Then, the dummy channel structure can be formed simultaneously with the channel structure by depositing the memory layer (including the barrier layer, the storage layer, and the tunneling layer) and the channel layer, or the same thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) of the high-k gate dielectric layer, the memory layer (including the barrier layer, the storage layer, and the tunneling layer) and the channel layer. It should be understood that in some examples, the dummy channel structure can be formed in a process separate from the channel structure.

[0147] Method 700 proceeds to operation 706, such as Figure 7 As shown, in operation 706, all the second dielectric layers in the second portion of the stacked structure and part of the second dielectric layers in the first portion are replaced with a conductive layer, for example, by a gate replacement process. The conductive layer may include metal. For example, referring to Figure 8B The stacked structure 203 may include a first portion 362 and a second portion 364. For example, the conductive layer 302 is used to replace all the second dielectric layers 222 in the second portion 364 (including the core array region 101 and a portion of the connection region 103) through a gate replacement process.

[0148] At the beginning of the gate replacement process, a gap is formed that extends through the first dielectric layer 224 and the second dielectric layer 222 and across the first portion 362 and the second portion 364 of the stacked structure 203. In some embodiments, the gap also extends vertically through the local contact layer. The gap can also extend laterally across the core array region 101 and the connection region 103 in the x-direction (word line direction). In some embodiments, the manufacturing process for forming the gap includes wet etching and / or dry etching of the first dielectric layer and the second dielectric layer, such as DRIE. The etching process through the stacked structure may not stop at the top surface of the silicon substrate, and portions of the silicon substrate may continue to be etched to ensure that the gap extends vertically through all of the first dielectric layer and the second dielectric layer of the stacked structure 203.

[0149] Thereafter, the portion of the gap located in the core array region is covered by the sacrificial layer. In some embodiments, a sacrificial layer (e.g., a polysilicon layer or a carbon layer) different from the first dielectric layer and the second dielectric layer is deposited into the gap using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the gap (cover the exposed first dielectric layer and second dielectric layer in the gap). The sacrificial layer can then be patterned using photolithography and wet etching and / or dry etching to remove the portion of the sacrificial layer located in the connection region, thereby leaving only the portion of the sacrificial layer located in the core array region, thereby covering only the portion of the gap located in the core array region.

[0150] Subsequently, a portion of the second dielectric layer 222 in the connection region 103 of the stacked structure 203 is removed through the gap in the connection region 103 of the stacked structure 203. The removal can be performed by wet etching to form a lateral recess, thereby leaving the remaining second dielectric layer 222 in the dielectric portion of the connection region 103 intact. In some embodiments, a portion of the second dielectric layer is wet etched by applying a wet etchant through the portion of the gap in the connection region that is not covered by the sacrificial layer, thereby generating lateral recesses staggered between the first dielectric layers 224. The wet etchant may include phosphoric acid for etching the second dielectric layer including silicon nitride. In some embodiments, one or both of the etching rate and the etching time are controlled to remove only the conductive portion (e.g., Figure 1A-1B The conductive portion 105 in the second dielectric layer 222 is formed so that the dielectric portion (eg, Figure 1A-1B The remaining second dielectric layer 222 in the dielectric portion 107 in the core array region 107 is intact. By controlling the etching time, the wet etchant does not proceed all the way to completely remove the second dielectric layer in the connection region 103, thereby defining two portions in the connection region: a dielectric portion in which the second dielectric layer is removed, and a dielectric portion in which the second dielectric layer is retained. Since the portion of the gap located in the core array region 101 is covered by a sacrificial layer (which is resistant to the etchant used to remove the second dielectric layer), all of the second dielectric layer remains intact in the core array region 101.

[0151] Then, the gap in the core array region 101 of the stacked structure is opened. Specifically, the portion of the gap located in the core array region 101 is reopened by removing the sacrificial layer to expose the first dielectric layer and the second dielectric layer. In some embodiments, for example, potassium hydroxide (KOH) for etching a sacrificial layer having polysilicon is used to selectively etch away the sacrificial layer from the portion of the gap located in the core array region to open the portion of the gap located in the core array region.

[0152] Thereafter, the gap in the connection region 103 of the stacked structure is covered. Specifically, the lateral recess and the portion of the gap located in the connection region are covered by another sacrificial layer. In some embodiments, a sacrificial layer (e.g., a polysilicon layer or a carbon layer) different from the first dielectric layer and the second dielectric layer is deposited into the lateral recess and the gap using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof) to at least partially fill the gap (covering the exposed first dielectric layer and the second dielectric layer). The sacrificial layer can then be patterned using photolithography and wet etching and / or dry etching to remove the portion of the sacrificial layer located in the core array region, leaving only the portion of the sacrificial layer located in the connection region to cover only the lateral recess and the portion of the gap located in the core array region rather than in the core array region. It should be understood that the lateral recess can be considered as the portion of the gap located in the connection region. Therefore, even if only the lateral recess is completely or partially filled by the sacrificial layer, the portion of the gap located in the connection region can still be considered to be covered.

[0153] Then, all the second dielectric layers in the core array region 101 of the stacked structure are removed through the gaps in the core array region 101 of the stacked structure. Specifically, all the second dielectric layers in the core array region 101 are completely removed by wet etching to form lateral recesses. In some embodiments, the second dielectric layer is wet-etched by applying a wet etchant through the portion of the gap in the core array region that is not covered by the sacrificial layer, thereby generating lateral recesses staggered between the first dielectric layers. The wet etchant may include phosphoric acid for etching the second dielectric layer including silicon nitride. In some embodiments, one or both of the etching rate and the etching time are controlled to ensure that all the second dielectric layers in the core array region are completely etched away. Since the portion of the gap located in the connection region 103 is covered by the sacrificial layer (which can resist the etchant used to remove the second dielectric layer), the remaining second dielectric layer in the dielectric portion 107 of the connection region 103 remains intact.

[0154] Thereafter, the slit in the connection region 103 of the stacked structure is opened. Specifically, the portion of the slit located in the connection region is reopened by removing the sacrificial layer to expose the first dielectric layer and the remaining second dielectric layer in the connection region. In some embodiments, for example, the sacrificial layer is selectively etched away from the portion of the slit located in the connection region using KOH for etching the sacrificial layer having polysilicon to open the portion of the slit (and the lateral recess) located in the connection region.

[0155] Finally, a conductive layer is deposited into the lateral recesses in the conductive portions 105 of the core array region 101 and the connection region 103 through the gap. In some embodiments where a high-k gate dielectric layer is not formed in the channel structure, the high-k gate dielectric layer is deposited into the lateral recesses before the conductive layer, so that the conductive layer is deposited on the high-k gate dielectric layer and surrounded by the high-k gate dielectric layer. In some embodiments where a high-k gate dielectric layer is formed in the channel structure, the high-k gate dielectric layer is not deposited into the lateral recesses before the conductive layer, so that the conductive layer is deposited on the first dielectric layer and surrounded by the first dielectric layer. The conductive layer (e.g., metal layer) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0156] As described above, by partially covering the gap in the core array region or the connection region, the removal of the second dielectric layer (e.g., a stacked sacrificial layer having silicon nitride) can be performed in the core array region and the connection region, respectively, to allow the second dielectric layer to be removed in different ranges (e.g., complete removal in the core array region and partial removal in the connection region). It should be understood that in another gate replacement process, the removal of the second dielectric layer can be performed first in the core array region and then in the connection region.

[0157] Return to reference Figure 7 , method 700 proceeds to operation 708, such as Figure 7 As shown, in operation 708, contact structures extending through the first dielectric layer and the remaining second dielectric layer in the first portion of the stacked structure are formed at different depths. Figure 8C A first contact structure 116 extending through the first dielectric layer 224 and the remaining second dielectric layer 222 and a second contact structure 106 extending through a portion of the first dielectric layer 224 and the remaining second dielectric layer 222 may be formed in the connection region 103. Fig. 9 and Figures 10A-10G An exemplary method of forming a contact structure and an exemplary manufacturing process are respectively shown.

[0158] Return to reference Figure 7 , method 700 proceeds to operation 710, such as Figure 7 As shown, in operation 710, a connection layer is formed over the contact structure and the channel structure. Fig.8D , a connection layer 308 may be formed over the contact structures 116, 106 and the channel structure 110. As a result, a semiconductor structure 360 ​​may be formed.

[0159] Return to reference Figure 7, method 700 proceeds to operation 712, such as Figure 7 As shown, in operation 712, a peripheral circuit is formed. Fig. 8E , the peripheral circuit 330 may be formed by forming a device layer 332 over the semiconductor layer 331 and forming a connection layer 334 over the device layer 332 .

[0160] Return to reference Figure 7 , method 700 proceeds to operation 714, such as Figure 7 As shown, in operation 714, a semiconductor device is formed by bonding the connection layer to the peripheral circuit. Figure 8F , you can Figure 8C The peripheral circuit 330 in the embodiment is flipped and bonded to the connection layer 308 of the semiconductor structure 360 ​​to form Figure 3B A semiconductor device 350 is provided in the embodiment of the present invention.

[0161] Fig. 9 is a flow chart of a method 900 for forming a plurality of contact structures in a semiconductor structure according to some aspects of the present disclosure. Figures 10A-10G A fabrication process for forming a plurality of contact structures in a semiconductor structure according to some aspects of the present disclosure is shown. Fig. 9 and Figures 10A-10G Examples of semiconductor structures depicted in include Figure 3B The semiconductor structure 360 ​​depicted in FIG. Fig. 9 and Figures 10A-10G It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Fig. 9 The order shown in the figure is different from the order in which it is executed.

[0162] refer to Fig. 9 , method 900 begins at operation 902, in which a stack structure including a staggered (alternating) first dielectric layer and a second dielectric layer is formed on a semiconductor layer. The first dielectric layer may include silicon oxide, and the second dielectric layer may include silicon nitride. The stack structure may be formed by one or more thin film deposition processes, including but not limited to ALD, CVD, PVD, or any combination thereof.

[0163] Method 900 proceeds to operation 904, such as Fig. 9 As shown, in operation 904, a first contact hole extending through the stacked structure is formed. The method 900 proceeds to operation 906, as shown in FIG. Fig. 9 As shown, in operation 906, a second contact hole extending through a portion of the stack structure is formed during the formation of the first contact hole.

[0164] For example, refer to Fig. 10A , a stack structure including staggered first dielectric layers 224 and second dielectric layers 222 is formed on the semiconductor layer 201. The stack structure can be etched using a first mask to form a first opening 1002 and a second opening 1004 extending into the stack structure. In some embodiments, the second opening 1004 can form at least one of the second contact holes. The first opening 1002 and the second opening 1004 can have the same depth and extend into the first stack pair including the first dielectric layer 224A and the second dielectric layer 222A to expose the second dielectric layer 222A. Although Fig. 10A Only one second opening 1004 is shown in the figure, but a plurality of second openings 1004 may be formed, which is not limited herein.

[0165] refer to Fig. 10B , the first opening 1002 may be etched out using a second mask to form a third opening 1006 that further extends through the stacked structure and the semiconductor layer 201. Thus, a first contact hole including the first opening 1002 and the third opening 1006 is formed. It should be noted that when forming the third opening 1006, the smaller remaining portion of the semiconductor layer 201 may not be etched away, so that the material of the first contact structure formed in the first contact hole may be deposited above the remaining portion of the semiconductor layer 201. As described below, Figure 10G As shown in , this remaining portion of the semiconductor layer 201 may be removed after forming the first contact structure.

[0166] In some embodiments, the stacked structure may be further etched using a third mask to form a fourth opening (not shown) extending into the stacked structure at a depth different from the depth of the opening 1004. The second contact hole may further include a fourth opening. For example, the fourth opening may be formed for Figure 2A By performing similar operations, a plurality of second contact holes extending into the stack structure and having the same or different depths can be formed by etching the stack structure using the same or different masks.

[0167] The method of forming openings with different depths is referred to as a cutting process. As used herein, a "cutting" process is a process of increasing the depth of one or more openings extending through a stacked structure including a staggered first dielectric layer and a second dielectric layer through multiple etching cycles. Each etching cycle may include one or more dry etching and / or wet etching processes for etching a pair of first dielectric layers and a second dielectric layer (i.e., reducing the depth by one dielectric layer pair). The purpose of the cutting process is to form multiple openings at different depths. Therefore, depending on the number of openings, a specific number of cutting processes and a certain number of cutting masks may be required. It should be understood that the number of cutting masks, the order of the cutting masks, the design of each cutting mask (e.g., the number and pattern of openings) and / or the depth reduced by each cutting process (e.g., the number of etching cycles) may affect the specific depth of each opening after the cutting process. A detailed description of the cutting process can be referred to U.S. Patent Application No. 16 / 881,168 filed on May 22, 2022 and U.S. Patent Application No. 16 / 881,339 filed on May 22, 2022, both of which are incorporated herein by reference in their entirety.

[0168] Method 900 proceeds to operation 908, such as Fig. 9 As shown, in operation 908, a first contact structure is formed in the first contact hole. The method 900 proceeds to operation 910, as shown in FIG. Fig. 9 As shown, in operation 910, during the formation of the first contact structure, second contact structures are formed in the second contact holes, respectively.

[0169] For example, refer to Fig. 10C A first spacer 214 may be formed on the sidewall of the first contact hole, and a first spacer 214 may be formed on the sidewall of the first contact hole. Fig. 10C . Specifically, the first spacer 214 may be formed on the sidewalls and bottom of the first contact hole, and the second spacer 204 may be formed on the sidewalls and bottom of the second contact hole, thereby covering the first dielectric layer 224 and the second dielectric layer 222 exposed from the sidewalls and bottom of the first and second contact holes. In some embodiments, the first spacer 214 and the second spacer 204 may be formed by depositing a dielectric material (e.g., silicon oxide) over the sidewalls and bottom surfaces of the first and second contact holes using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0170] Then, the portion of the first spacer 214 located on the bottom of the first contact hole is removed to expose the remaining portion of the semiconductor layer 201. The portion of the second spacer 204 located on the bottom of the second contact hole is also removed to expose the second dielectric layer 222A. In some embodiments, dry etching can be applied to remove the portion of the first spacer 214 located on the bottom of the first contact hole and the portion of the second spacer 204 located on the bottom of the second contact hole. For example, the etching rate, direction and / or duration of the RIE is controlled to etch only the portion of the first spacer 214 and the second spacer 204 located on the bottom surface, without etching the portion located on the sidewall, that is, "punching" through the first spacer 214 and the second spacer 204 in the z direction to expose the remaining portion of the semiconductor layer 201 and the second dielectric layer 222A, respectively.

[0171] Then, refer to Fig. 10D and Fig. 10E , a lateral contact structure 206 may be formed below the bottom of the second contact hole. Fig. 10D As shown in , the portion of the second dielectric layer 222A exposed at the bottom of the second contact hole is removed by wet etching to form a lateral recess 1008. In some embodiments, a portion of the second dielectric layer 222A is wet etched by applying a wet etchant through the second contact hole, thereby creating a lateral recess 1008 sandwiched between the two first dielectric layers 224. The wet etchant may include phosphoric acid for etching the second dielectric layer 222A including silicon nitride. In some embodiments, the etching rate and / or etching time is controlled to remove only enough of the second dielectric layer 222A to expose the corresponding conductive layer 302A located at the same level ( Figure 3B Then, the lateral recess 1008 may be filled by depositing a conductive material through the second contact hole to form Fig. 10E The lateral contact structure 206 in the second contact hole can be partially replaced by the corresponding lateral contact structure 206 in the dielectric portion 107 of the connection region 103. The conductive material (e.g., metal layer) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The deposition rate and / or duration can be controlled to ensure that the lateral contact structure 206 can contact the exposed corresponding conductive layer 302A at the same level as the lateral recess 1008. In other words, the second dielectric layer 222A exposed from the bottom of the second contact hole can be partially replaced by the corresponding lateral contact structure 206 in the dielectric portion 107 of the connection region 103, while other second dielectric layers 222 located at other levels in the dielectric portion 107 remain intact.

[0172] Reference again Fig. 10E, the first conductor layer 212 can be formed on the first spacer 214 and the bottom of the first contact hole. The second conductor layer 202 can be formed on the second spacer 204 and the lateral contact structure 206. In some embodiments, the first conductor layer 212 and the second conductor layer 202 can be formed in the same process of forming the lateral contact structure 206 by depositing conductive material not only into the lateral recess 1008 but also on the sidewalls and bottom surfaces of the first contact hole and the second contact hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0173] refer to Fig.10F , the remaining portion of the first contact hole may be filled with the first filler body 218. The remaining portion of the second contact hole may be filled with the second filler body 208. The first filler body 218 and the second filler body 208 (e.g., dielectric layers) may be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). Excess portions of the conductor layer and the dielectric layer may be removed using chemical mechanical polishing (CMP).

[0174] refer to Figure 10G , the first contact pad 220 may be formed on the first conductor layer 212 and the first filler body 218. The second contact pad 210 may be formed on the second conductor layer 202 and the second filler body 208. In some embodiments, the remaining portion of the semiconductor layer 201 under the first contact hole may be removed, and the contact pad 1050 may be formed to fill the space of the remaining portion of the semiconductor layer 201.

[0175] Fig.11 A block diagram of an exemplary system 1100 having a 3D memory device according to some aspects of the present disclosure is shown. System 1100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Fig.11 As shown, the system 1100 may include a host 1108 and a memory system 1102 having one or more 3D memory devices 1104 and a memory controller 1106. The host 1108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1108 may be configured to send data to the 3D memory device 1104 or receive data from the 3D memory device 1104.

[0176] The memory device 1104 can be any 3D memory device disclosed herein. In some implementations, the memory device 1104 includes NAND flash memory.

[0177] According to some embodiments, the memory controller 1106 (also referred to as a controller circuit) is coupled to the memory device 1104 and the host 1108 and is configured to control the memory device 1104. For example, the memory controller 1106 may be configured to operate a plurality of channel structures via word lines. The memory controller 1106 may manage data stored in the memory device 1104 and communicate with the host 1108. In some embodiments, the memory controller 1106 is designed to operate in a low duty cycle environment, for example, a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1106 is designed to operate in a high duty cycle environment, for example, an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptops, etc. and an enterprise storage array. The memory controller 1106 may be configured to control the operation of the memory device 1104 (e.g., a read operation, an erase operation, and a program operation). The memory controller 1106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 1104, including but not limited to: bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 1106 is also configured to process error correction code (ECC) regarding data read from or written to the memory device 1104. The memory controller 1106 may also perform any other appropriate functions, such as formatting the memory device 1104. The memory controller 1106 may communicate with an external device (e.g., a host 1108) according to a specific communication protocol. For example, the memory controller 1106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0178] The memory controller 1106 and one or more 3D memory devices 1104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage device (UFS) package or an eMMC package). That is, the memory system 1102 may be implemented and packaged into different types of terminal electronic products. Fig. 12A In one example shown in FIG. 1 , the memory controller 1106 and the single memory device 1104 may be integrated into a memory card 1202. The memory card 1202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1202 may also include a processor that connects the memory card 1202 to a host (e.g., Fig.11 The host 1108 in the memory card connector 1204 is electrically coupled. Fig. 12B In another example shown in FIG. 1 , the memory controller 1106 and the plurality of 3D memory devices 1104 may be integrated into an SSD 1206. The SSD 1206 may also include a processor that interfaces the SSD 1206 with a host (e.g., Fig.11 In some implementations, the storage capacity and / or operating speed of the SSD 1206 is greater than the storage capacity and / or operating speed of the memory card 1202.

[0179] The above description of specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance given herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0180] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: Semiconductor layer; a stacked structure located above the semiconductor layer and comprising alternating first layers and first dielectric layers, wherein the stacked structure comprises a first portion and a second portion adjacent to the first portion, the first layer of the first portion comprises a second dielectric layer, and the first layer of the second portion comprises a conductive layer; a first contact structure extending through the first portion and the semiconductor layer; as well as A second contact structure extends through a portion of the first portion and is connected to one of the conductive layers.

2. The semiconductor device according to claim 1, wherein: The first contact structure includes a first segment and a second segment connected to the first segment in a first direction, the first segment includes a first end contacting the second segment, and the second segment includes a second end contacting the first segment, wherein in a second direction perpendicular to the first direction, a size of the first end is larger than a size of the second end.

3. The semiconductor device according to claim 2, wherein: The first section further includes a third end away from the first end, and the second section further includes a fourth end away from the second end, wherein in the second direction, the size of the third end is larger than the size of the first end, and in the second direction, the size of the second end is larger than the size of the fourth end.

4. The semiconductor device according to claim 2, wherein: The first section is located on a side of the second section away from the semiconductor layer.

5. The semiconductor device according to claim 1, wherein: The second contact structure includes a vertical contact structure and a lateral contact structure connected to the vertical contact structure, and the vertical contact structure extends in the same direction as the first contact structure, wherein the lateral contact structure is connected to the one of the conductive layers.

6. The semiconductor device according to claim 5, wherein: The first contact structure includes a first joint portion located in a first stacking pair, and the vertical contact structure extends to the first stacking pair, wherein the first stacking pair is a pair including a first dielectric layer in the first dielectric layers and a first layer in the first layer that contacts the first dielectric layer in the first dielectric layer.

7. The semiconductor device according to claim 6, further comprising a third contact structure extending through a portion of the first portion, wherein: The third contact structure is connected to a second stack pair, and the first contact structure includes a second joint portion located in the second stack pair.

8. The semiconductor device according to claim 1, wherein: The first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer; and The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer, wherein the first spacer and the second spacer include a same material, and the first conductor layer and the second conductor layer include a same material.

9. The semiconductor device according to claim 8, wherein: The first contact structure further includes a first filler body surrounded by the first conductor layer.

10. The semiconductor device according to claim 9, wherein: The second contact structure further includes a second filler body surrounded by the second conductor layer, and the first filler body and the second filler body include a same material. 11 . The semiconductor device of claim 1 , further comprising a channel structure extending through the second portion into the semiconductor layer.

12. The semiconductor device according to claim 11, wherein: In the vertical direction, the length of the first contact structure is greater than the length of the channel structure.

13. The semiconductor device according to claim 11, wherein: The second portion includes a first portion and a second portion spaced apart from the first portion, wherein the first portion connects the first portion and the second portion. 14 . The semiconductor device according to claim 1 , further comprising a peripheral circuit connected to the first contact structure.

15. The semiconductor device according to claim 14, further comprising a first connection layer and a second connection layer, wherein the first connection layer is connected to the first contact structure, and the second connection layer is connected to the peripheral circuit. in, The first connection layer is bonded to the second connection layer.

16. The semiconductor device according to claim 14, wherein: The peripheral circuit is disposed below the stack structure, and the first contact structure extends through the semiconductor layer to be connected to the peripheral circuit.

17. A memory device comprising: A first semiconductor structure, the first semiconductor structure comprising: a first stacked structure comprising alternating first and second dielectric layers; and a first contact structure extending through the first stack structure; A second semiconductor structure, the second semiconductor structure comprising: a second stacked structure comprising alternating third and fourth dielectric layers; and a second contact structure extending through the second stack structure; and A first peripheral circuit is connected to the first contact structure and the second contact structure.

18. The memory device of claim 17, wherein: The first peripheral circuit is bonded to the first semiconductor structure, and the first peripheral circuit includes a first connection structure located between the first semiconductor structure and the second semiconductor structure.

19. The memory device according to claim 17, further comprising a second peripheral circuit, the second peripheral circuit being bonded to the second semiconductor structure, wherein: The second peripheral circuit includes a second connection structure connected to the second contact structure.

20. The memory device of claim 19, wherein: The second semiconductor structure is located between the first peripheral circuit and the second peripheral circuit.

21. The memory device of claim 17, wherein: The first peripheral circuit also includes a semiconductor layer and an interconnect structure extending through the semiconductor layer.

22. The memory device of claim 21, wherein: The first contact structure includes an insulating filler and a conductor layer surrounding the insulating filler, the interconnection structure includes a conductive filler and a spacer surrounding the conductive filler, and the conductor layer is connected to the conductive filler.

23. The memory device of claim 17, wherein: The first contact structure includes a first segment and a second segment connected to the first segment in a first direction, the first segment includes a first end contacting the second segment, the second segment includes a second end contacting the first segment, and in a second direction perpendicular to the first direction, a size of the first end is larger than a size of the second end.

24. The memory device of claim 23, wherein: The first section further includes a third end away from the first end, and the second section further includes a fourth end away from the second end. In the second direction, the size of the third end is larger than the size of the first end, and in the second direction, the size of the second end is larger than the size of the fourth end.

25. The memory device of claim 23, wherein: The first stacked structure is disposed on a semiconductor layer, and the first section is located on a side of the second section away from the semiconductor layer.

26. The memory device of claim 17, wherein: The first semiconductor structure further comprises: A third contact structure extends through a portion of the first stacking structure, wherein the third contact structure includes a vertical contact structure and a lateral contact structure connected to the vertical contact structure, and the vertical contact structure extends in the same direction as the first contact structure.

27. The memory device of claim 26, wherein: The first contact structure includes a first joint portion located in a first stacking pair, and the vertical contact structure extends to the first stacking pair, wherein the first stacking pair is a pair including a first dielectric layer in the first dielectric layers and a second dielectric layer in the second dielectric layer that contacts the first dielectric layer in the first dielectric layer.

28. The memory device of claim 27, further comprising a fourth contact structure extending through a portion of the first stack structure, wherein The fourth contact structure is connected to a second stack pair, and the first contact structure includes a second joint portion located in the second stack pair.

29. The memory device of claim 26, wherein: The first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer; The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer; and The third contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer, wherein the first spacer and the second spacer include a same material, and the first conductor layer and the second conductor layer include a same material.

30. The memory device of claim 29, wherein: The first contact structure further includes a first filler body surrounded by the first conductor layer.

31. A method of forming a semiconductor device, comprising: forming a stack structure comprising alternating first and second dielectric layers; forming a first contact hole extending through the stacked structure; as well as During the forming of the first contact hole, a second contact hole extending through a portion of the stack structure is formed.

32. The method according to claim 31, wherein: Forming the first contact hole and forming the second contact hole during the forming of the first contact hole comprises: Etching the stack structure using a first mask to form a first opening and one or more second openings extending into the stack structure, wherein the second contact hole includes the one or more second openings; and The first opening is etched using a second mask to form a third opening further extending through the stack structure, wherein the first contact hole includes the first opening and the third opening.

33. The method of claim 32, wherein: Forming the second contact hole further includes: The stack structure is etched using a third mask to form one or more fourth openings extending into the stack structure, wherein the second contact hole further includes the one or more fourth openings.

34. The method of claim 31 , further comprising: forming a first contact structure in the first contact hole; as well as During the forming of the first contact structures, second contact structures are respectively formed in the second contact holes.

35. The method of claim 34, wherein: The first contact structure includes a first spacer, a first conductor layer surrounded by the first spacer, and a first filler body surrounded by the first conductor layer; and The second contact structures respectively include a second spacer, a second conductor layer surrounded by the second spacer, a lateral contact structure connected to the second conductor layer, and a second filler body surrounded by the second conductor layer.

36. The method of claim 35, wherein: Forming the first contact structure and forming the second contact structure includes: Respectively, forming the first spacer on the sidewall of the first contact hole, and forming the second spacer on the sidewall of the second contact hole; forming the lateral contact structure of the second contact structure below the bottom of the second contact hole; forming the first conductor layer over the first spacer and the bottom of the first contact hole, and forming the second conductor layer over the second spacer and the lateral contact structure, respectively; and Respectively, the remaining portion of the first contact hole is filled with the first filler body, and the remaining portion of the second contact hole is filled with the second filler body.

37. The method of claim 36, wherein: The lateral contact structure forming the second contact structure below the bottom of the second contact hole comprises: removing portions of the corresponding second dielectric layers exposed at the bottoms of the second contact holes, respectively, to form lateral recesses; and The lateral recesses are respectively filled by depositing a conductive material through the second contact holes to form the lateral contact structures.

38. The method of claim 36, wherein: Forming the first contact structure and forming the second contact structure further includes: A first contact pad is formed on the first conductor layer and the first filler body, and a second contact pad is formed on the second conductor layer and the second filler body, respectively.

39. A semiconductor device comprising: A stacked structure comprising alternating first and second dielectric layers; a first contact structure extending through the stack structure and comprising a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer; as well as a second contact structure extending through a portion of the stack structure and comprising a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer, The first spacer and the second spacer include a first material, and the first conductor layer and the second conductor layer include a second material different from the first material.

40. The semiconductor device according to claim 39, wherein: The first contact structure includes a first segment and a second segment connected to the first segment in a first direction, the first segment includes a first end contacting the second segment, and the second segment includes a second end contacting the first segment, wherein in a second direction perpendicular to the first direction, a size of the first end is larger than a size of the second end.

41. The semiconductor device according to claim 40, wherein The first section further includes a third end away from the first end, and the second section further includes a fourth end away from the second end, wherein in the second direction, the size of the third end is larger than the size of the first end, and in the second direction, the size of the second end is larger than the size of the fourth end.

42. The semiconductor device according to claim 40, wherein: The stacked structure is disposed on a semiconductor layer, and the first section is located on a side of the second section away from the semiconductor layer.

43. The semiconductor device according to claim 39, wherein: The second contact structure includes a vertical contact structure and a lateral contact structure connected to the vertical contact structure, and the vertical contact structure extends in the same direction as the first contact structure.

44. The semiconductor device according to claim 43, wherein: The first contact structure includes a first joint portion located in a first stacking pair, and the vertical contact structure extends to the first stacking pair, wherein the first stacking pair is a pair including a first dielectric layer in the first dielectric layers and a second dielectric layer in the second dielectric layer that contacts the first dielectric layer in the first dielectric layer.

45. The semiconductor device according to claim 44, further comprising a third contact structure extending through the stack structure, wherein: The third contact structure is connected to a second stack pair, and the first contact structure includes a second joint portion located in the second stack pair.

46. ​​The semiconductor device according to claim 40, further comprising a peripheral circuit connected to the first contact structure and the second contact structure.

47. A memory device comprising: a first contact structure, the first contact structure comprising an insulating filler and a conductor layer surrounding the insulating filler and extending in a first direction; as well as a second contact structure including a conductive filler and a spacer surrounding a sidewall of the conductive filler and extending in the first direction, Wherein, the conductor layer is connected to the conductive filler.

48. A semiconductor device comprising: Semiconductor layer; a stacked structure located above the semiconductor layer and comprising alternating conductive layers and dielectric layers; a first contact structure extending through the stack structure and comprising a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer; as well as a second contact structure extending through a portion of the stack structure and comprising a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer, The second conductor layer is connected to one of the conductive layers, and the first conductor layer is separated from the conductive layer by the first spacer.

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