Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include a stacked first gate line, a stacked second gate line, a channel structure extending through the first gate line and the second gate line, first contact plugs extending through the first gate lines and connected to front surfaces of the first gate lines, respectively, and second contact plugs extending through the second gate lines and connected to rear surfaces of the second gate lines, respectively.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a two-dimensional semiconductor device in which a memory cell is formed as a single layer on a substrate has reached a limit, a three-dimensional (3-D) semiconductor device in which memory cells are stacked at multiple heights above a substrate has been proposed. In addition, extensive research has been invested in developing a 3D semiconductor device with improved operational reliability and improving a method of manufacturing a 3D semiconductor device. Summary of the invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a first group of stacked first gate lines and a second group of stacked second gate lines overlapping the first group of stacked first gate lines, the first group of stacked first gate lines and the second group of stacked second gate lines being spaced apart from each other, wherein the first gate lines and the second gate lines alternate with insulating layers; a channel structure extending through the first gate lines and the second gate lines; a first contact plug extending through the first gate lines and connected to front surfaces of the first gate lines, respectively; and a second contact plug extending through the second gate lines and connected to rear surfaces of the second gate lines, respectively.

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a peripheral circuit; a gate structure including a front surface facing the peripheral circuit; a first contact plug extending into the gate structure through the front surface; a second contact plug extending into the gate structure through the rear surface; and an interconnect structure connecting the first contact plug and the second contact plug to the peripheral circuit.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a gate structure including a stacked first gate line and a stacked second gate line; forming a first contact plug, the first contact plug extending into the gate structure through a front surface and being respectively connected to the first gate lines; and forming a second contact plug, the second contact plug extending into the gate structure through a rear surface and being respectively connected to the second gate lines.

[0006] These and other features and advantages of the present invention will become apparent from the following detailed description of example embodiments and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a simplified diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A and Figure 2B is a simplified diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] FIG. 3A to FIG. 3J is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] Embodiments of the present disclosure provide a semiconductor device having a stable structure, improved characteristics, and improved integration, and a method of manufacturing the semiconductor device.

[0011] The integration degree of a semiconductor device can be improved by three-dimensionally stacking memory cells. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0012] Hereinafter, embodiments of the present disclosure are described with reference to the accompanying drawings.

[0013] Figure 1 is a simplified diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Reference Figure 1 , the semiconductor device may include a gate structure GST, a first contact plug CT1 and a second contact plug CT2. The semiconductor device may also include a substrate 10, a transistor TR, a dummy stack DST, a third contact plug CT3, a first insulating spacer SPC1, a second insulating spacer SPC2, a third insulating spacer SPC3, a channel structure CH, a slit structure SLS, a support SP, a source structure S, a first interconnection structure IC1, a second interconnection structure IC2, a third interconnection structure IC3, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and at least one of a third interlayer insulating layer IL3.

[0015] The gate structure GST may include a stacked first gate line 21G1 and a stacked second gate line 21G2. In some embodiments, the gate structure GST may include alternately stacked first gate lines 21G1 and insulating layers 22. The gate structure GST may also include alternately stacked second gate lines 21G2 and insulating layers 22. The first gate line 21G1 and the second gate line 21G2 may be a word line, a source selection line, a drain selection line, etc. The first gate line 21G1 and the second gate line 21G2 may include a conductive material such as polysilicon, tungsten, or molybdenum.

[0016] The gate structure GST may include a front surface FS and a rear surface RS. The front surface FS of the gate structure GST and the peripheral circuit PC may be positioned to face each other. The source structure S may be located on or above the rear surface RS of the gate structure GST. Figure 1In the illustrated embodiment, the source structure S is located on the rear surface RS of the gate structure GST and is in direct contact with the rear surface RS of the gate structure GST. The first gate line 21G1 may be positioned closer to the front surface FS of the gate structure GST, and the second gate line 21G2 may be positioned closer to the rear surface RS of the gate structure GST. The first gate line 21G1 may be grouped together to form a first group positioned closer to the front surface FS of the gate structure GST. The second gate line 21G2 may be grouped together to form a second group positioned closer to the rear surface RS of the gate structure GST. The number of the first gate lines 21G1 and the number of the second gate lines 21G2 may be equal to or different from each other. The number of the first gate lines 21G1 and the number of the second gate lines 21G2 may be changed based on design considerations. In addition, the sum of the number of the first gate lines 21G1 and the second gate lines 21G2 may be changed according to the integration of the semiconductor device. The term integration used here means integration density, that is, the number of components that can be integrated into the semiconductor device. Higher integration (or integration density) is desirable because it leads to a more powerful and compact device.

[0017] The gate structure GST may include a cell region CR where memory cells are stacked and a contact region CTR where an interconnection structure is located. The interconnection structure may provide a path for transmitting a bias signal (e.g., voltage or current) for driving the stacked memory cells. The interconnection structure may include one or more contact plugs, one or more conductive lines, etc.

[0018] The source structure S may be located on or above the gate structure GST. Figure 1 In the illustrated embodiment, the source structure S is located on the gate structure GST and is in direct contact with the gate structure GST.

[0019] The source structure S may cover the cell region CR of the gate structure and expose the contact region CTR. The source structure S may include a conductive material such as polysilicon or metal. In some embodiments, the source structure S may cover at least a portion of the contact region CTR, or may cover at least a portion of the dummy stack DST.

[0020] The channel structure CH may extend through the gate structure GST. In the cell region CR, the channel structure CH may pass through the gate structure GST and extend from the front surface FS into the source structure S. The channel structure CH may include at least one of a channel layer 1, a memory layer 2, and an insulating core 3. The memory layer 2 may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc.

[0021] The slit structure SLS may extend through the gate structure GST. In the cell region CR, the slit structure SLS may pass through the gate structure GST and may extend from the front surface FS into the source structure S. The slit structure SLS may extend from the cell region CR to the contact region CTR. The slit structure SLS may include at least one of an insulating material, a semiconductor material, and a conductive material. In some embodiments, the slit structure SLS may include a gap filling material such as an oxide layer, a nitride layer, or amorphous silicon. The slit structure SLS may include a source contact structure electrically connected to the source structure S and an insulating spacer surrounding the sidewall of the source contact structure.

[0022] The support SP may extend through the contact region CTR of the gate structure GST. The support SP may have a structure similar to the channel structure CH and may be a dummy channel structure. In some embodiments, the support SP may include at least one of a dummy channel layer 1D, a dummy memory layer 2D, and a dummy insulating core 3D.

[0023] The first contact plug CT1 may extend through the contact region CTR of the gate structure GST. The first contact plug CT1 may extend from the front surface FS of the gate structure GST into the gate structure GST. The first contact plug CT1 may extend through the first gate line 21G1 and may be respectively connected to the front surface of the first gate line 21G1. The first contact plug CT1 may extend to different depths and may be respectively electrically connected to the first gate line 21G1. The first insulating spacer SPC1 may respectively surround the sidewalls of the first contact plug CT1. The first contact plug CT1 may have a tapered cross section. In some embodiments, the width of a portion of the first contact plug CT1 closer to the front surface FS may be greater than the width of a portion closer to the rear surface RS.

[0024] Among the first contact plugs CT1, the height of the first contact plugs CT1 located farther from the cell region CR may be greater than the height of the first contact plugs CT1 located closer to the cell region CR. In some embodiments, the first contact plugs CT1 may be arranged such that the height increases as the distance from the cell region CR increases. However, the present invention is not limited to this configuration, and in some embodiments, the first contact plugs CT1 may be arranged according to other configurations.

[0025] The second contact plug CT2 may extend through the contact region CTR of the gate structure GST. The second contact plug CT2 may extend from the rear surface RS of the gate structure GST into the gate structure GST. The second contact plug CT2 may extend through the second gate line 21G2 and may be respectively connected to the rear surface of the second gate line 21G2. The second contact plug CT2 may extend to different depths and may be respectively electrically connected to the second gate line 21G2. The second insulating spacer SPC2 may respectively surround the sidewalls of the second contact plug CT2. The second contact plug CT2 may have a tapered cross section. In some embodiments, the width of a portion of the second contact plug CT2 closer to the rear surface RS may be greater than the width of a portion closer to the front surface FS. In some embodiments, the first contact plug CT1 may have a tapered cross section, and the second contact plug CT2 may have an inverted tapered cross section.

[0026] Among the second contact plugs CT2, the height of the second contact plugs CT2 located closer to the cell region CR may be greater than the height of the second contact plugs CT2 located farther from the cell region CR. In some embodiments, the second contact plugs CT2 may be arranged so that the height increases as the distance from the cell region CR decreases. However, the present invention is not limited to this configuration, and in some embodiments, the second contact plugs CT2 may be arranged according to other configurations.

[0027] The first contact plugs CT1 and the first gate lines 21G1 may be connected in one-to-one correspondence, respectively, meaning that the number of the first gate lines 21G1 and the number of the first contact plugs CT1 may be the same. The second contact plugs CT2 and the second gate lines 21G2 may be connected in one-to-one correspondence, respectively, meaning that the number of the second gate lines 21G2 and the number of the second contact plugs CT2 may be the same. The number of the first contact plugs CT1 and the number of the second contact plugs CT2 may be equal to or different from each other. The sum of the numbers of the first gate lines 21G1 and the second gate lines 21G2 may be equal to the sum of the numbers of the first contact plugs CT1 and the second contact plugs CT2.

[0028] The first contact plug CT1 and the second contact plug CT2 may be positioned to correspond to each other. In some embodiments, the first contact plug CT1 may be positioned below the second contact plug CT2, respectively. For example, the first contact plug CT1 having a relatively larger height may be arranged to correspond to or align with the second contact plug CT2 having a relatively smaller height. Therefore, the first contact plug CT1 and the second contact plug CT2 may be arranged symmetrically. However, the present invention is not limited to this configuration, and in some embodiments, the first contact plug CT1 and the second contact plug CT2 may be arranged asymmetrically.

[0029] The dummy stack DST may include a sacrificial layer 21S and an insulating layer 22 alternately stacked. The sacrificial layer 21S may be retained during the manufacturing process without being replaced by a gate line. In some embodiments, the sacrificial layer 21S may include a nitride, and the insulating layer 22 may include an oxide. The gate structure GST and the dummy stack DST may be connected to each other and may share the insulating layer 22.

[0030] The third contact plug CT3 may extend through the dummy stack DST. The third insulating spacer SPC3 may surround the sidewall of the third contact plug CT3. The third contact plug CT3 may pass through the dummy stack DST and may be connected to the second contact plug CT2 via the third interconnect structure IC3. In some embodiments, the third contact plug CT3 may pass through the contact region CTR instead of the dummy stack DST.

[0031] The peripheral circuit PC may be located on or above the substrate 10. The peripheral circuit PC may include, for example, a page buffer, a row decoder, a logic circuit, an input / output circuit, etc. The row decoder may include a pass transistor that controls the connection of a global line and a local line. The peripheral circuit PC may include a transistor TR, and the transistor TR may include a gate insulating layer 11 and a gate electrode 12.

[0032] The first interconnection structure IC1 may be located in the first interlayer insulating layer IL1 and may include at least one via 23 and at least one conductive line 24. The first interconnection structure IC1 may be located under the gate structure GST and may be connected to at least one of the channel structure CH, the first contact plug CT1, and the third contact plug CT3. The first interconnection structure IC1 may include a first bonding pad BP1.

[0033] The second interconnect structure IC2 may be located in the second interlayer insulating layer IL2 and may be electrically connected to the peripheral circuit PC. The second interconnect structure IC2 may include at least one via 13 and at least one conductive line 14. The second interconnect structure IC2 may include a second bonding pad BP2.

[0034] The third interconnection structure IC3 may be located in the third interlayer insulating layer IL3 and may include at least one via 25 and at least one conductive line 26. The third interconnection structure IC3 may be located on the gate structure GST and may be connected to at least one of the source structure S, the second contact plug CT2, and the third contact plug CT3.

[0035] The cell array and the peripheral circuit PC may be electrically connected through the first interconnection structure IC1, the second interconnection structure IC2, and the third interconnection structure IC3. The second contact plug CT2 and the first interconnection structure IC1 may be connected through the third contact plug CT3. The first interconnection structure IC1 and the second interconnection structure IC2 may be connected through the first bonding pad BP1 and the second bonding pad BP2, and the third contact plug CT3 and the peripheral circuit PC may be connected through the first interconnection structure IC1 and the second interconnection structure IC2. Thus, the second contact plug CT2 may be electrically connected to the peripheral circuit PC. The channel structure CH may be connected to the peripheral circuit PC through the first interconnection structure IC1 and the second interconnection structure IC2.

[0036] According to the above structure, the first contact plug CT1 and the second contact plug CT2 may be disposed on the front surface FS and the rear surface RS of the gate structure GST in a dispersed manner. Therefore, the height of the first contact plug CT1 and the second contact plug CT2 may be reduced compared to the case where the first contact plug CT1 and the second contact plug CT2 are disposed only on the front surface FS. In addition, the area of ​​the contact region CTR may be reduced.

[0037] Figure 2A and Figure 2B 1 is a simplified diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0038] Reference Figure 2A and Figure 2B The semiconductor device may include a gate structure GST, a first contact plug CT1, and a second contact plug CT2. The gate structure GST may include first gate lines 21G1 and insulating layers 22 alternately stacked, and may include second gate lines 21G2 and insulating layers 22 alternately stacked.

[0039] The first contact plug CT1 may extend into the gate structure GST through the front surface FS of the gate structure GST and may be connected to the first gate lines 21G1, respectively. The first contact plug CT1 may be connected to the front surface G1FS of the first gate line 21G1. In some embodiments, the first contact plug CT1 may be in contact with the front surface G1FS, or may be connected to the first gate line 21G1 through the front surface G1FS. The second contact plug CT2 may extend into the gate structure GST through the rear surface RS of the gate structure GST and may be connected to the second gate line 21G2, respectively. The second contact plug CT2 may be connected to the rear surface G2RS of the second gate line 21G2. In some embodiments, the second contact plug CT2 may be in contact with the rear surface G2RS, or may be connected to the second gate line 21G2 through the rear surface G2RS.

[0040] Among the first contact plugs CT1, the height of the first contact plug CT1 located farther away from the cell region edge CRE may be less than the height of the first contact plug CT1 located closer to the cell region edge CRE. In some embodiments, the first contact plugs CT1 may be arranged so that the height decreases as the distance from the cell region edge CRE increases. However, the present disclosure is not limited thereto, and the height may decrease as the distance from the cell region edge CRE decreases, or the first contact plugs CT1 may be randomly arranged regardless of the distance from the cell region edge CRE.

[0041] Among the second contact plugs CT2, the height of the second contact plug CT2 located closer to the cell region edge CRE may be less than the height of the second contact plug CT2 located farther from the cell region edge CRE. In some embodiments, the second contact plugs CT2 may be arranged so that the height decreases as the distance from the cell region edge CRE decreases. However, the present disclosure is not limited thereto, and the height may increase as the distance from the cell region edge CRE decreases, or the second contact plugs CT2 may be randomly arranged regardless of the distance from the cell region edge CRE.

[0042] In some embodiments, the first contact plug CT1 may be arranged so that the height decreases as the distance from the cell region edge CRE increases, and the second contact plug CT2 may be arranged so that the height decreases as the distance from the cell region edge CRE decreases. In other embodiments, the first contact plug CT1 may be arranged so that the height increases as the distance from the cell region edge CRE increases, and the second contact plug CT2 may be arranged so that the height increases as the distance from the cell region edge CRE decreases. The first contact plug CT1 and the second contact plug CT2 may be randomly arranged regardless of the distance from the cell region edge CRE.

[0043] Reference Figure 2A , the region where the second contact plug CT2 is located and the region where the first contact plug CT1 is located may overlap. The first contact plug CT1 and the second contact plug CT2 may be positioned to correspond to each other. The first contact plug CT1 may be located below the second contact plug CT2, respectively. The first contact plug CT1 and the second contact plug CT2 may be arranged to be aligned in a one-to-one correspondence (1:1), or may be arranged in a staggered (or offset) manner.

[0044] Reference Figure 2B, the first contact plug CT1 and the second contact plug CT2 may be formed in different regions so as not to overlap. In some embodiments, the first contact plug CT1 may be positioned closer to the cell region edge CRE than the second contact plug CT2. In other embodiments, the second contact plug CT2 may be positioned closer to the cell region edge CRE than the first contact plug CT1.

[0045] According to the above structure, the first and second contact plugs CT1 and CT2 may be disposed on the front and rear surfaces FS and RS of the gate structure GST in a dispersed manner, respectively. Therefore, the heights of the first and second contact plugs CT1 and CT2 may be reduced, and the areas of the contact regions may be reduced.

[0046] FIG. 3A to FIG. 3J 1 is a simplified diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0047] Reference Figure 3A , a stack ST may be formed on or over the substrate 30. The stack ST may include a cell region CR, a contact region CTR, and a dummy region DR. The dummy region DR may be a region where a dummy stack is to be formed in a subsequent process. The stack ST may include a stacked first material layer 31A and a stacked second material layer 31B. In some embodiments, after forming a first group of second material layers 31B and insulating layers 32 alternately stacked on the substrate 30, a second group of first material layers 31A and insulating layers 32 alternately stacked may be formed overlapping with the first group.

[0048] The first material layer 31A and the second material layer 31B may include a material having a high etching selectivity with respect to the insulating layer 32. The first material layer 31A and the second material layer 31B may be sacrificial layers including nitrides, or may be conductive layers including a conductive material such as polysilicon, tungsten, or molybdenum. The insulating layer 32 may include an insulating material such as oxide or nitride.

[0049] Subsequently, at least one of the channel hole CHH, the slit SL, the support hole SPH, and the contact hole CTH may be formed. The channel hole CHH, the slit SL, the support hole SPH, and the contact hole CTH may extend into the substrate 30 through the stack ST. Subsequently, a sacrificial layer 33 may be formed in the channel hole CHH, the slit SL, the support hole SPH, and the contact hole CTH. The sacrificial layer 33 may include a material having a high etching selectivity with respect to the first material layer 31A, the second material layer 31B, and the insulating layer 32.

[0050] Reference Figure 3B, at least one of the channel hole CHH and the support hole SPH may be reopened. In some embodiments, the insulating layer 32 may be formed on the stack ST to cover the sacrificial layer 33. Subsequently, a mask pattern covering the slit SL and the contact hole CTH and exposing the channel hole CHH and the support hole SPH may be formed on the insulating layer 32, and the sacrificial layer 33 may be selectively removed. Thus, the channel hole CHH and the support hole SPH may be selectively reopened.

[0051] Subsequently, a channel structure CH may be formed in the channel hole CHH. The channel structure CH may include at least one of a channel layer 34, a memory layer 35, and an insulating core 36. When the channel structure CH is formed, a support SP may be formed in the support hole SPH. The support SP may include at least one of a dummy channel layer 34D, a dummy memory layer 35D, and a dummy insulating core 36D. Thus, a support SP and a channel structure CH extending through the stack ST may be formed.

[0052] Reference Figure 3C , a sacrificial contact structure 39 may be formed. In some embodiments, first openings OP1 respectively exposing the first material layers 31A may be formed in the stack ST. The front surfaces of the first material layers 31A may be exposed through the first openings OP1.

[0053] Subsequently, a sacrificial contact structure 39 may be formed in each of the first openings OP1. The sacrificial contact structure 39 may include a sacrificial contact layer 38 and an insulating liner 37 surrounding the sacrificial contact layer 38. In some embodiments, the insulating liner 37 may be conformally formed on the wall of the first opening OP1, and the sacrificial contact layer 38 may be formed in the remaining central space inside the first opening OP1 that is not covered by the insulating liner 37. Subsequently, a planarization process may be performed on the stack ST until a front surface FS of the stack ST is formed to expose the sacrificial contact layer 38 and the insulating liner 37 located in the first opening OP1.

[0054] Reference Figure 3D , after exposing the sacrificial layer 33 formed in the slit SL, the sacrificial layer 33 may be removed to reopen the slit SL. Subsequently, the first material layer 31A and the second material layer 31B may be replaced with a conductive layer through the slit SL. The first material layer 31A may be replaced with a first gate line 31G1, and the second material layer 31B may be replaced with a second gate line 31G2. Thus, a gate structure GST including a stacked first gate line 31G1 and a stacked second gate line 31G2 may be formed. During the replacement process, the first material layer 31A and the second material layer 31B may be retained in a partial area without being replaced. The portion of the first material layer 31A and the second material layer 31B retained may be defined as a dummy stack DST.

[0055] When the first material layer 31A and the second material layer 31B are conductive layers, the replacement process may not be performed. In this case, the first material layer 31A may be used as the first gate line 31G1, the second material layer 31B may be used as the second gate line 31G2, and the stack ST may be used as the gate structure GST.

[0056] Subsequently, a slit structure SLS may be formed in the slit SL. The slit structure SLS may include at least one of an insulating material, a conductive material, and a semiconductor material. In some embodiments, the slit structure SLS may include a gap filling material such as oxide, nitride, or amorphous silicon. The slit structure SLS may include a source contact structure and an insulating spacer surrounding the sidewall of the source contact structure.

[0057] Reference Figure 3E , the sacrificial contact layer 38 may be removed to reopen the first opening OP1. Subsequently, the insulating liner 37 may be etched to form a first insulating spacer 37A. Subsequently, a first contact plug CT1 may be formed in the first opening OP1. The first contact plug CT1 may extend to different depths through the front surface FS of the gate structure GST and may be connected to the front surfaces of the first gate lines 31G1, respectively.

[0058] Reference Figure 3F , in the exposed contact hole CTH (see Figure 3E ), the sacrificial layer 33 may be removed to reopen the contact hole CTH, and then a third contact plug CT3 may be formed in the contact hole CTH. Figure 3F As shown, the third contact plug CT3 may be formed after forming the third insulating spacer 40 on the inner wall of the contact hole CTH. Through these operations, the third contact plug CT3 extending through the dummy stack DST may be formed.

[0059] Subsequently, a first interconnect structure IC1 and a first interlayer insulating layer 43 may be formed. The first interconnect structure IC1 may be located in the first interlayer insulating layer 43. The first interlayer insulating layer 43 may be a single layer or a multilayer. The first interconnect structure IC1 may be connected to at least one of the channel structure CH, the first contact plug CT1, and the third contact plug CT3. The first interconnect structure IC1 may include at least one via 41 and at least one conductive line 42. The first interconnect structure IC1 may include a first bonding pad BP1. Thus, a first wafer WF1 including a substrate 30, a gate structure GST, and a first contact plug CT1 may be manufactured. The first wafer WF1 may include a cell array CA.

[0060] Reference Figure 3G, a peripheral circuit PC may be formed on or over the substrate 50. The peripheral circuit PC may include, for example, a row decoder, a page buffer, an input / output circuit, etc. The transistor TR may include a gate insulating layer 51 and a gate electrode 52. Subsequently, a second interconnect structure IC2 and a second interlayer insulating layer 55 may be formed. The second interconnect structure IC2 may be located in the second interlayer insulating layer 55. The second interlayer insulating layer 55 may be a single layer or multiple layers. The second interconnect structure IC2 may be connected to the peripheral circuit PC. The second interconnect structure IC2 may include at least one via 53 and at least one conductive line 54. The second interconnect structure IC2 may include a second bonding pad BP2. Thus, a second wafer WF2 including the peripheral circuit PC may be manufactured.

[0061] Subsequently, the first wafer WF1 and the second wafer WF2 may be bonded to each other. The first wafer WF1 and the second wafer WF2 may be bonded so that the front surface FS of the gate structure GST and the peripheral circuit PC face each other. The first bonding pad BP1 and the second bonding pad BP2 may be bonded, and the first interlayer insulating layer 43 and the second interlayer insulating layer 55 may be bonded to form a bonding interface IF.

[0062] Subsequently, the substrate 30 may be removed. Thus, the rear surface RS of the gate structure GST may be exposed. Subsequently, the memory layer 35 of the channel structure CH exposed through the rear surface of the gate structure GST may be etched to expose the channel layer 34 .

[0063] Subsequently, a source layer 56 may be formed on or over the rear surface of the gate structure GST. The source layer 56 may include a conductive material such as polysilicon or a metal. For reference, impurities may be doped into the channel layer 34 before the source layer 56 is formed.

[0064] Reference Figure 3H , the source layer 56 may be etched to form a source structure 56A. In some embodiments, the source layer 56 may be etched to expose a region where the first contact plug CT1 is formed. Thus, the source structure 56A may be formed on the rear surface of the gate structure GST. The source structure 56A may cover or expose the dummy stack DST. Subsequently, an insulating layer 57 may be formed in the region where the source layer 56 is etched.

[0065] Subsequently, second openings OP2 respectively exposing the second material layers 31B may be formed. The second openings OP2 may pass through the insulating layer 57 and extend into the gate structure GST through the rear surface RS of the gate structure GST. Rear surfaces of the second gate lines 31G2 may be exposed through the second openings OP2, respectively.

[0066] Reference Fig. 3I, a second insulating spacer 58 may be conformally formed inside the second opening OP2. A second contact plug CT2 may be formed in a space inside the second opening OP2 that is not filled by the second insulating spacer 58. Thus, a second contact plug CT2 located on the first contact plug CT1 may be formed.

[0067] Reference Figure 3J , a third interconnect structure IC3 and a third interlayer insulating layer 63 may be formed. The third interconnect structure IC3 may be located in the third interlayer insulating layer 63. The third interlayer insulating layer 63 may be a single layer or multiple layers. The third interconnect structure IC3 may be connected to at least one of the second contact plug CT2 and the third contact plug CT3. The third interconnect structure IC3 may include at least one via 61 and at least one conductive line 62.

[0068] According to the above-mentioned manufacturing method, the first contact plug CT1 and the second contact plug CT2 can be formed on the front surface FS and the rear surface RS of the gate structure GST in a dispersed manner. Therefore, the aspect ratio of the first opening OP1 and the second opening OP2 can be reduced, and the process difficulty can be reduced. By separately forming the first contact plug CT1 and the second contact plug CT2 before and after wafer bonding, the first contact plug CT1 and the second contact plug CT2 can be vertically stacked. Therefore, the area of ​​the contact region can be reduced.

[0069] Although the embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings, this is only for describing the embodiments according to the technical concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Within the scope of the technical concept of the present disclosure, technicians in the field of the present disclosure can perform various forms of replacement, modification and change to the embodiments, which also belong to the scope of the present disclosure.

[0070] CROSS-REFERENCE TO RELATED APPLICATIONS

[0071] This application claims priority to Korean Patent Application No. 10-2023-0149968, filed on November 2, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first set of stacked first gate lines and a second set of stacked second gate lines overlapping the first set of stacked first gate lines, the first set of stacked first gate lines and the second set of stacked second gate lines being spaced apart from each other, wherein the first gate lines and the second gate lines are alternated with an insulating layer; a channel structure extending through the first gate line and the second gate line; first contact plugs extending through the first gate lines and connected to front surfaces of the first gate lines, respectively; and Second contact plugs extend through the second gate lines and are connected to rear surfaces of the second gate lines, respectively.

2. The semiconductor device according to claim 1, wherein The first contact plugs extend through the first gate lines to different depths.

3. The semiconductor device according to claim 1, wherein The second contact plugs extend through the second gate lines to different depths.

4. The semiconductor device according to claim 1, further comprising: Virtual stacking objects; Peripheral circuits; as well as A third contact plug extends through the dummy stack and connects the second contact plug and the peripheral circuit.

5. The semiconductor device according to claim 1, further comprising: Peripheral circuits; as well as An interconnect structure connects the peripheral circuit to the first contact plug and the second contact plug.

6. The semiconductor device according to claim 5, wherein: The interconnect structure includes a bonding pad.

7. The semiconductor device according to claim 1, further comprising: Insulating spacers surround sidewalls of the first contact plug and sidewalls of the second contact plug, respectively.

8. The semiconductor device according to claim 1, wherein The first contact plugs are respectively located under the second contact plugs.

9. The semiconductor device according to claim 1, wherein: The first contact plug has a tapered cross section, and the second contact plug has an inversely tapered cross section.

10. A semiconductor device, comprising: Peripheral circuits; a gate structure, the gate structure comprising a front surface facing the peripheral circuit; a first contact plug extending through the front surface into the gate structure; a second contact plug extending into the gate structure through the rear surface; as well as An interconnect structure connects the first contact plug and the second contact plug to the peripheral circuit.

11. The semiconductor device according to claim 10, further comprising: a dummy stack connected to the gate structure; as well as a third contact plug extending through the dummy stack and connected to the second contact plug, Wherein, the interconnection structure connects the third contact plug and the peripheral circuit.

12. The semiconductor device according to claim 10, wherein: The interconnect structure includes a bonding pad.

13. The semiconductor device according to claim 10, further comprising: A channel structure extends through the gate structure.

14. The semiconductor device according to claim 10, further comprising: Insulating spacers surround sidewalls of the first contact plug and sidewalls of the second contact plug, respectively.

15. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a gate structure including a stacked first gate line and a stacked second gate line; forming first contact plugs extending into the gate structure through the front surface and connected to the first gate lines respectively; as well as Second contact plugs are formed, the second contact plugs extending into the gate structure through the rear surface and connected to the second gate lines, respectively.

16. The method according to claim 15, wherein: The steps of forming the gate structure include: forming a stack including a first set of alternately stacked first material layers and insulating layers and a second set of alternately stacked second material layers and insulating layers; replacing the first material layer with the first gate line; and The second material layer is replaced by the second gate line.

17. The method according to claim 16, wherein: The step of forming the first contact plug includes: forming first openings extending through the stack and respectively exposing the first material layers; forming a sacrificial contact layer in the first opening; After replacing the first material layer with the first gate line, removing the sacrificial contact layer; and The first contact plug is formed in the first opening.

18. The method according to claim 17, wherein: The step of forming the first contact plug includes: forming an insulating liner in the first opening; and A first insulating spacer is formed by etching the insulating liner.

19. The method according to claim 16, further comprising the steps of: A channel structure is formed extending through the stack.

20. The method according to claim 16, further comprising the steps of: A third contact plug is formed extending through the stack.

21. The method according to claim 20, further comprising the steps of: An interconnection structure connecting the second contact plug and the third contact plug is formed.

22. The method according to claim 15, further comprising the steps of: bonding a first wafer including a substrate, the gate structure and the first contact plug and a second wafer including a peripheral circuit; as well as The rear surface of the gate structure is exposed by removing the substrate.

23. The method according to claim 22, further comprising the steps of: A source structure is formed on the rear surface of the gate structure.

24. The method according to claim 23, wherein: The steps of forming the source structure include: forming a source layer on the rear surface of the gate structure; and The source layer is etched to expose a region where the first contact plug is formed.

25. The method of claim 15, wherein: The step of forming the second contact plug includes: forming second openings extending through the rear surface and respectively exposing the second gate lines; forming a second insulating spacer in the second opening; and The second contact plug is formed in the second opening.

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