Semiconductor devices and their manufacturing methods, memory

Abstract

This application provides a semiconductor device and its manufacturing method, as well as a memory. In the semiconductor device manufacturing method provided in this application, the number of stacked units covering the (i-1)th transition step structure formed by the i-th deposition is half the number of stacked units formed by the (i-1)th deposition. Therefore, after the i-th deposition of the stacked units is patterned for the i-th time, the number of steps in the i-th transition step structure is twice the number of steps in the (i-1)-th transition step structure. This significantly reduces the number of patterning processes required to form the desired step structure, helping to reduce the manufacturing difficulty and cost of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and a memory. Background Technology

[0002] Currently, semiconductor devices, such as memory, typically include a core region and a peripheral region outside the core region. The core region contains components for implementing core functions, while the peripheral region usually contains peripheral circuits. Components often need to be connected to the peripheral circuits through connecting electrodes.

[0003] With the development of semiconductor technology, the number of stacked memory cells in memory is increasing, as is the number of electrode structures. Consequently, the number of step structures used to connect the electrode structures and memory cells is also increasing. Currently, memory manufacturing processes typically form one step structure per photolithography step.

[0004] For memory that includes multiple layers of storage cells, the number of photolithography processes required in the manufacturing process is significantly greater, which greatly increases the manufacturing complexity and cost of the memory. Summary of the Invention

[0005] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and a memory, thereby improving upon the deficiencies in the prior art.

[0006] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising:

[0007] A first deposition is performed to form at least two stacked units on one side of the substrate; each stacked unit comprises at least two layers.

[0008] The first patterning is performed, exposing part of the substrate surface and forming the first transition step structure;

[0009] The i-th deposition is performed to form a stacked unit covering the (i-1)-th transition step structure and part of the substrate; the number of stacked units formed by the i-th deposition is half the number of stacked units formed by the (i-1)-th deposition; the stacked unit formed by the i-th deposition is patterned for the i-th time to expose part of the substrate surface and form the i-th transition step structure; wherein, the number of steps in the i-th transition step structure is twice the number of steps in the (i-1)-th transition step structure.

[0010] Determine whether the number of steps in the i-th transition step structure meets the set number; if yes, a step structure that meets the expectations is obtained; if no, continue to manufacture the (i+1)-th transition step structure; i is a positive integer greater than 1.

[0011] Secondly, embodiments of this application provide a semiconductor device, obtained based on the manufacturing method of the semiconductor device provided in the first aspect above. The semiconductor device includes:

[0012] At least two stepped structures are disposed on one side of the substrate, and the stepped structures are electrically connected to the peripheral circuit.

[0013] Thirdly, embodiments of this application provide a memory obtained based on the semiconductor device manufacturing method provided in the first aspect above. The memory includes:

[0014] At least one memory array structure is disposed on one side of a substrate; the memory array structure includes at least two stacked memory cell arrays;

[0015] At least two stepped structures are set on one side of the storage array structure, and each layer of storage cell array is electrically connected to the external circuit through the corresponding stepped structure.

[0016] The beneficial technical effects of the technical solutions provided in this application include:

[0017] In the semiconductor device manufacturing method provided in this application embodiment, the number of stacked units covering the (i-1)th transition step structure formed by the i-th deposition is half the number of stacked units formed by the (i-1)th deposition. Thus, after the i-th deposition of the stacked units is patterned for the i-th time, the number of steps in the i-th transition step structure is twice the number of steps in the (i-1)th transition step structure. This significantly reduces the number of patterning processes required to form the desired step structure, which helps to reduce the manufacturing difficulty and cost of semiconductor devices.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the structure after forming the first mask structure in a method for manufacturing a semiconductor device according to an embodiment of this application;

[0022] Figure 3This is a schematic diagram of the structure after forming the first stacked structure in a method for manufacturing a semiconductor device according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the structure after a sub-dielectric layer is formed on a first mask structure in a method for manufacturing a semiconductor device according to an embodiment of this application.

[0024] Figure 5 This is a schematic diagram of the structure after etching the sub-dielectric layer in a semiconductor device manufacturing method provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure after forming the second mask structure in a method for manufacturing a semiconductor device according to an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure after forming the third stacked structure in a semiconductor device manufacturing method provided in this application embodiment;

[0027] Figure 8 This is a schematic diagram of the structure after forming the third mask structure in a semiconductor device manufacturing method provided in this application embodiment;

[0028] Figure 9 This is a schematic diagram of the structure after a step structure is formed in a semiconductor device manufacturing method provided in this application embodiment;

[0029] Figure 10 This is a schematic diagram of the structure after forming a via in the first dielectric layer in a method for manufacturing a semiconductor device according to an embodiment of this application.

[0030] Figure 11 This is a schematic diagram of the structure after the electrode structure is formed in a semiconductor device manufacturing method provided in this application embodiment.

[0031] Explanation of reference numerals in the attached figures:

[0032] 100-substrate;

[0033] 101 - Stacked unit;

[0034] 1011 - Sub-dielectric layer; 1012 - Sub-conductive layer;

[0035] 102 - Surrounding area; 103 - First mask structure;

[0036] 104 - First stacked structure;

[0037] 1041 - Sub-dielectric structure; 1042 - Sub-conductive structure;

[0038] 105 - First transition structure; 106 - Second initial stacked structure; 107 - Second initial transition structure;

[0039] 108 - Second mask structure; 109 - Second stacked structure; 110 - Second transition structure;

[0040] 111 - Third initial transition structure; 112 - Third mask structure; 113 - Third transition structure;

[0041] 114 - Second dielectric layer; 115 - Via; 116 - Electrode structure;

[0042] 201 - First dielectric layer;

[0043] 2011 - First dielectric structure;

[0044] 202 - First conductive layer;

[0045] 2021 - First conductive structure. Detailed Implementation

[0046] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0047] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is “connected” to another element, the element may be directly connected to the other element, or it may mean that the element and the other element are connected through an intermediate element. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0049] As the number of integrated components in semiconductor devices, such as memory, increases, the number of electrode structures that need to be formed in their surrounding areas also increases. Since the components to be electrically connected to each electrode structure are located in different film layers, the lengths of the electrode structures are not the same. In related technologies, each electrode structure requires a photolithography process to form a contact hole that matches the length of the electrode structure.

[0050] As the number of lithography processes required increases, the manufacturing complexity and cost of semiconductor devices will increase significantly.

[0051] Meanwhile, in related technologies, in order to avoid the electrode structure from being connected to the wires of other film layers, it is necessary to deposit insulating material on the peripheral wall of the contact hole before forming the electrode structure, which will further increase the manufacturing complexity and cost of semiconductor devices.

[0052] The semiconductor device, its manufacturing method, and memory provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0053] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0054] This application provides a method for manufacturing a semiconductor device, the process flow of which is shown in the figure below. Figure 1 As shown, the method includes steps S101 to S105.

[0055] S101, Perform the first deposition to form at least two stacked units on one side of the substrate; the stacked unit includes at least two stacked layers.

[0056] S102, the first patterning is performed, exposing part of the substrate surface and forming the first transition step structure.

[0057] S103, perform the i-th deposition to form a stacked unit covering the (i-1)-th transition step structure and part of the substrate; the number of stacked units formed in the i-th deposition is half the number of stacked units formed in the (i-1)-th deposition; perform the i-th patterning on the stacked units formed in the i-th deposition to expose part of the substrate surface and form the i-th transition step structure; wherein, the number of steps in the i-th transition step structure is twice the number of steps in the (i-1)-th transition step structure.

[0058] S104, determine whether the number of steps in the i-th transition step structure meets the set number; if yes, a step structure that meets the expectations is obtained; if no, execute S105 to continue manufacturing the (i+1)-th transition step structure; i is a positive integer greater than 1.

[0059] In the semiconductor device manufacturing method provided in this application embodiment, the number of stacked units covering the (i-1)th transition step structure formed by the i-th deposition is half the number of stacked units formed by the (i-1)th deposition. Thus, after the i-th deposition of the stacked units is patterned for the i-th time, the number of steps in the i-th transition step structure is twice the number of steps in the (i-1)th transition step structure. This significantly reduces the number of patterning processes required to form the desired step structure, which helps to reduce the manufacturing difficulty and cost of semiconductor devices.

[0060] To facilitate readers' intuitive understanding of the semiconductor device manufacturing method provided in the embodiments of this application and the advantages of the semiconductor device obtained based on this manufacturing method, the following will combine... Figures 2-11 Taking an example where the final number of stepped structures that meet the expected requirements is eight, the manufacturing method of the semiconductor device provided in this application embodiment will be described in detail.

[0061] Optionally, in one embodiment of this application, the first deposition is performed in step S101 above to form at least two stacked units on one side of the substrate 100, including: forming a first predetermined number of stacked units 101 in the peripheral region 102 of the substrate 100.

[0062] In this embodiment of the application, the stacking unit 101 includes at least two stacked layers. Optionally, the stacking unit 101 includes at least one sub-dielectric layer 1011 and at least one sub-conductive layer 1012.

[0063] Optionally, the above steps form a first predetermined number of stacked units 101 in the peripheral region 102 of the substrate 100, including: sequentially and alternately forming a sub-dielectric layer 1011 and a sub-conductive layer 1012 on the peripheral region 102 of the substrate 100 based on a deposition process until the first predetermined number of stacked units 101 are obtained.

[0064] Optionally, the deposition process includes CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition).

[0065] It should be noted that, in order to facilitate readers' intuitive understanding of the structure on the surrounding area 102 of the substrate 100, such as Figure 2 As shown, the structure of the core region of the substrate 100 is omitted, and only the peripheral region 102 of the substrate 100 is shown.

[0066] Optionally, in this embodiment, the first predetermined quantity is equal to half the number of the final, expected stepped structure. That is, the first predetermined quantity is four, such as... Figure 2 As shown, four stacked units 101 are formed in the peripheral region 102 of the substrate 100. Each stacked unit 101 includes a sub-dielectric layer 1011 and a sub-conductive layer 1012, as shown. Figure 2 As shown, there are a total of four sub-dielectric layers 1011 and four sub-conductive layers 1012 on the peripheral region 102 of the substrate 100.

[0067] Optionally, in one embodiment of this application, the first patterning in step S102, which exposes a portion of the surface of the substrate 100 and forms a first transition step structure, includes: forming a first mask structure 103 covering the stacked unit 101; and etching the stacked unit 101 based on the first mask structure 103 to form the first transition step structure.

[0068] Optionally, such as Figure 2 As shown, a first mask structure 103 is formed on the side of the stacked unit 101 away from the substrate 100.

[0069] Optionally, the above steps to form a first mask structure 103 covering the stacked unit 101 include: coating photoresist on the stacked unit 101 furthest from the substrate 100, and forming the first mask structure 103 after exposure and development by the first photomask.

[0070] Optionally, a first mask structure 103, which is a hard mask, can be formed on the stacked unit 101 based on deposition and patterning processes. Optionally, the material of the first mask structure 103 can be silicon nitride, which helps to ensure the subsequent etching operation.

[0071] Optionally, in this embodiment of the application, after the first deposition and the first patterning, a first transition step structure is formed. The first transition step structure includes a first transition structure 105 and a portion of the substrate 100 not covered by the first transition structure 105. For example... Figure 2 As shown, the portion of the first transition structure 105 and the substrate 100 not covered by the first transition structure 105 is respectively considered as a unit transition step, that is, the number of unit transition steps in the first transition step structure is two.

[0072] Optionally, in this embodiment of the application, the above steps are based on etching the stacked unit 101 using the first mask structure 103 to form a first transition step structure, including: using the first mask structure 103 as a mask, removing the portion of the stacked unit 101 not covered by the first mask structure 103 based on a dry or wet etching process, until a portion of the peripheral area 102 of the substrate 100 is exposed, the portion of the stacked unit 101 covered by the first mask structure 103 forms a first stacked structure 104, and all the stacked first stacked structures 104 form a first transition structure 105.

[0073] Optionally, such as Figure 2 As shown, the first direction is parallel to the substrate 100. The first dimension d1 of the first mask structure 103 along the first direction is equal to half the dimension of the peripheral region 102 along the first direction. This ensures that the dimension of the first transition structure 105 formed after etching the stacked units 101 based on the first mask structure 103 along the first direction is equal to half the dimension of the peripheral region 102 along the first direction. That is, along the first direction, the lengths of the two unit transition steps in the first transition step structure are equal, which helps to ensure that the lengths of the final step structures are all equal.

[0074] Optionally, in one embodiment of this application, after forming the first transition structure 105, the method further includes removing the first mask structure 103.

[0075] Optionally, such as Figure 3 As shown, a first transition structure 105 is formed in the peripheral region 102 of the substrate 100. The first transition structure 105 includes four stacked first stacked structures 104. Each first stacked structure 104 includes stacked sub-dielectric structures 1041 and sub-conductive structures 1042, combined with... Figure 2 and Figure 3 It can be seen that after the sub-dielectric layer 1011 is etched, a sub-dielectric structure 1041 is formed, and after the sub-conductive layer 1012 is etched, a sub-conductive structure 1042 is formed.

[0076] Optionally, in one embodiment of this application, the i-th deposition is performed in step S103 above to form a stacked unit covering the (i-1)-th transition step structure, including: forming a first dielectric layer 201 covering the (i-1)-th transition step structure and a portion of the substrate based on the deposition process; etching the first dielectric layer 201 to form a first dielectric structure 2011 located on the (i-1)-th transition step structure and a portion of the substrate; forming a first conductive layer 202 covering the first dielectric structure 2011 and the sidewalls of the (i-1)-th transition step structure; etching the first conductive layer 202 to form a first conductive structure 2021 located on the first dielectric structure 2011, and all the stacked first dielectric structures 2011 and first conductive structures 2021 form a stacked unit 101.

[0077] Optionally, in this embodiment of the application, forming a first dielectric layer 201 covering the i-1th transition step structure based on a deposition process includes: forming a first dielectric layer 201 on the peripheral region 102 of the substrate 100 based on a deposition process, such that the first dielectric layer 201 covers the first transition structure 105 and the exposed portion of the peripheral region 102 of the substrate 100.

[0078] Optionally, such as Figure 4 As shown, the first dielectric layer 201 covers the surface and side surfaces of the first transition structure 105 and the portion of the peripheral region 102 of the substrate 100 that is not covered by the first transition structure 105.

[0079] Optionally, in this embodiment of the application, etching the first dielectric layer 201 to form a first dielectric structure 2011 located on the (i-1)th transition step structure includes: etching the first dielectric layer 201 based on a wet etching process until the portion of the first dielectric layer 201 located on the sidewall of the first transition structure 105 is removed, so that the continuous first dielectric layer 201 forms two discontinuous first dielectric structures 2011.

[0080] Optionally, such as Figure 5 As shown, after etching the first dielectric layer 201, a first dielectric structure 2011 is provided on the first transition structure 105 and the substrate 100, and the two first dielectric structures 2011 form the sub-dielectric layer 1011 of the stacked unit 101.

[0081] Optionally, in this embodiment of the application, forming a first conductive layer 202 covering the sidewalls of the first dielectric structure 2011 and the (i-1)th transition step structure includes: forming a first conductive layer 202 covering each of the first dielectric structures 2011 based on a deposition process.

[0082] Optionally, the formation process of the first conductive layer 202 can refer to the formation process of the first dielectric layer 201 described above, and will not be repeated here.

[0083] Optionally, in this embodiment, etching the first conductive layer 202 to form a first conductive structure 2021 located on the first dielectric structure 2011 includes: etching the first conductive layer 202 using a wet etching process until the portion of the first conductive layer 202 located on the sidewall of the first transition structure 105 is removed, so that the continuous first conductive layer 202 forms two discontinuous first conductive structures 2021, thereby forming one first conductive structure 2021 on the first transition structure 105 and one on the substrate 100. The two first conductive structures 2021 form the sub-conductive layer 1012 of the stacked unit 101.

[0084] Optionally, the steps of forming the first dielectric structure 2011 and the first conductive structure 2021 described above are repeated until a second predetermined number of stacked units 101 are formed. Optionally, the second predetermined number is equal to two.

[0085] Optionally, such as Figure 6 As shown, a first dielectric structure 2011 and a first conductive structure 2021 are stacked to form a second initial stacked structure 106, and two second initial stacked structures 106 are stacked to form a second initial transition structure 107.

[0086] Optionally, such as Figure 6 As shown, a second initial transition structure 107 is provided on one side of the portion of the first transition structure 105 and the substrate 100 not covered by the first transition structure 105, that is, a second initial transition structure 107 is formed on each unit transition step in the first transition step structure.

[0087] like Figure 6 As shown, the number of stacked units formed by the second deposition is half the number of stacked units formed by the first deposition, and the number of second initial stacked structures 106 in the second initial transition structure 107 is half the number of first stacked structures in the first transition structure 105.

[0088] Optionally, in this embodiment, the thickness of each stacked unit is the same along the direction perpendicular to the substrate 100, so the thickness of the second initial transition structure 107 is half the thickness of the first transition structure 105, so that there is a height difference between the first transition structure 105 and the second initial transition structure 107 adjacent along the first direction.

[0089] Optionally, in one embodiment of this application, the i-th patterning of the stacked unit formed by the i-th deposition to expose a portion of the substrate surface and form the i-th transition step structure in step S103 includes: forming an i-th mask structure covering half of the area of ​​each step structure in the stacked unit formed by the i-th deposition; etching the stacked unit formed by the i-th deposition based on the i-th mask structure to expose a portion of the substrate surface and form the i-th transition step structure.

[0090] Optionally, in the embodiments of this application, such as Figure 3 The diagram shown is a schematic of the first transition step structure formed after the first patterning. For example, from... Figures 3-7 The structural diagram shown illustrates a second transition step structure formed based on a first transition step structure. Optionally, the following explanation uses an example where i equals 2.

[0091] Optionally, in this embodiment of the application, forming an i-th mask structure on one side of each unit transition step in the i-1-th transition step structure includes: coating photoresist on the second initial transition structure 107, and forming a second mask structure 108 after exposure and development by the second photomask.

[0092] Alternatively, a second mask structure 108, which is a hard mask, can be formed on the second initial transition structure 107 based on deposition and patterning processes. Optionally, the material of the second mask structure 108 can be silicon nitride, which helps to ensure the subsequent etching operation.

[0093] Optionally, such as Figure 6 As shown, the second dimension d2 of the second mask structure 108 along the first direction is equal to half of the first dimension d1. That is, the size of the second mask structure 108 is half the size of the first mask structure 103, and the size of the second mask structure 108 is one-quarter of the size of the peripheral region 102 along the first direction. Therefore, based on the second mask structure 108 as a mask, the size of the second transition structure 110 obtained after etching the second initial transition structure 107 along the first direction is equal to half the size of the unit transition step in the first transition step structure along the first direction. This ensures that the lengths of the four unit transition steps in the second transition step structure are equal, which helps to ensure that the lengths of the final formed step structure are all equal.

[0094] Optionally, in this embodiment of the application, based on dry or wet etching processes, using the second mask structure 108 as a mask, the second initial stacked structure 106 of each second initial transition structure 107 is etched, thereby exposing a portion of the first transition structure 105 and a portion of the substrate 100, such as... Figure 7 As shown, a second transition step structure is formed.

[0095] Optionally, such as Figure 7 As shown, each second transition structure 110 includes two stacked second stacked structures 109.

[0096] Optionally, such as Figure 7 As shown, the second transition step structure includes four unit transition steps, namely the exposed portion of the substrate 100, the second transition structure 110 located on one side of the substrate 100, the exposed portion of the first transition structure 105, and the second transition structure 110 located on one side of the first transition structure 105.

[0097] Optionally, such as Figure 7As shown, along the first direction, after the second patterning, each of the second initial transition structures 107 obtained by the second deposition forms even-numbered unit transition steps of the second transition step structure, such as the second transition structure 110 located on one side of the substrate 100 and the second transition structure 110 located on one side of the first transition structure 105; the part of the first transition step structure not covered by the unit transition steps obtained by this patterning forms odd-numbered unit transition steps, such as the part exposed by the substrate 100 and the part exposed by the first transition structure 105.

[0098] Optionally, in one embodiment of this application, after forming the second transition structure 110, the method further includes removing the second mask structure 108.

[0099] Optionally, in one embodiment of this application, a third deposition is performed to form a stacked unit covering the second transition step structure.

[0100] Optionally, the process steps for the third deposition can refer to the description of the process steps for the second deposition described above, and will not be repeated here. For example... Figure 8 As shown, after the third deposition, a third initial transition structure 111 is formed on one side of each unit transition step in the second transition step structure, and all the third initial transition structures 111 form a stacked unit covering the second transition step structure.

[0101] It should be noted that, as Figure 8 As shown, the second transition structure 110 is represented by a dashed box for easy understanding by the reader; it does not exist in the actual product. Figure 8 The dotted line shown.

[0102] Optionally, in one embodiment of this application, the stacked units formed by the third deposition are patterned a third time, including forming a third mask structure 112 on each of the third initial transition structures 111.

[0103] Optionally, the formation process of the third mask structure 112 can refer to the process descriptions of the first mask structure 103 and the second mask structure 108 described above, and will not be repeated here.

[0104] Optionally, such as Figure 8 As shown, the third dimension d3 of the third mask structure 112 along the first direction is equal to one-eighth of the dimension of the peripheral region 102 along the first direction, that is, the third dimension d3 is equal to one-quarter of the first dimension d1.

[0105] Optionally, in this embodiment, the portions of each third initial transition structure 111 not covered by the third mask structure 112 are etched using the third mask structure 112 as a mask to form a plurality of third transition structures 113, thereby exposing a portion of the second transition structure 110, a portion of the first transition structure 105, and a portion of the substrate 100, such as... Figure 9 As shown.

[0106] Optionally, after forming the third transition structure 113, the method further includes removing the third mask structure 112.

[0107] Optionally, such as Figure 9 As shown, the third transition step structure formed after the third patterning includes eight unit transition steps, namely the exposed portion of the substrate 100, the third transition structure 113 located on one side of the substrate 100, the exposed portion of a second transition structure 110, the third transition structure 113 located on one side of a second transition structure 110, the exposed portion of the first transition structure 105, the third transition structure 113 located on one side of the first transition structure 105, the exposed portion of another second transition structure 110, and the third transition structure 113 located on one side of another second transition structure 110.

[0108] Optionally, combined Figure 8 and Figure 9 As can be seen, along the first direction, after the third patterning, each of the third initial transition structures 111 obtained by the third deposition forms even-numbered unit transition steps in the third transition step structure, such as the third transition structure 113 located on one side of the substrate 100, the third transition structure 113 located on one side of a second transition structure 110, the third transition structure 113 located on one side of the first transition structure 105, and the third transition structure 113 located on one side of another second transition structure 110. The portion of the second transition step structure not covered by the unit transition steps obtained by this patterning forms odd-numbered unit transition steps, such as the exposed portion of the substrate 100, the exposed portion of a second transition structure 110, the exposed portion of the first transition structure 105, and the exposed portion of another second transition structure 110.

[0109] Optionally, in one embodiment of this application, the i-th patterning of the stacked unit formed by the i-th deposition in step S103, exposing part of the substrate surface and forming the i-th transition step structure, includes: in the i-th transition step structure formed by the i-th patterning, the number of steps is equal to the power of 2i.

[0110] Optionally, in the embodiments of this application, such as Figure 3 As shown, the first transition step structure formed after the first patterning includes two unit transition steps; as Figure 7As shown, the second transition step structure formed after the second patterning includes four unit transition steps; as Figure 9 As shown, the third transition step structure formed after the third patterning includes eight unit transition steps. That is, in two adjacent patterning processes, the number of unit transition steps formed in the next patterning is twice the number of unit transition steps formed in the previous patterning. Compared with the related technology that requires eight patterning to form an eight-step structure, the semiconductor device manufacturing method provided in this application only requires three patterning processes, which can greatly reduce the number of patterning processes in the manufacturing process and greatly reduce the manufacturing difficulty and cost of semiconductor devices.

[0111] Optionally, combined Figure 3 , Figure 7 as well as Figure 9 It can be seen that the number of unit transition steps in the i-th transition step structure formed by the i-th patterning is equal to 2 to the power of i, that is, 2 can be obtained after i patterning processes. i The stepped structure can greatly reduce the number of patterning steps in the manufacturing process, thereby significantly reducing the manufacturing difficulty and cost of semiconductor devices.

[0112] Optionally, in one embodiment of this application, the number of stacked units formed in the first deposition is equal to the number of the final stepped structures formed.

[0113] Optionally, in one embodiment of this application, after obtaining the desired step structure in the above steps, the method further includes: forming an electrode structure 116 on the side of each step structure away from the substrate, such that each electrode structure 116 is electrically connected to the step surface of each step structure in a one-to-one correspondence.

[0114] Optionally, an electrode structure 116 electrically connected to the step surface of each step structure is formed on one side of each step structure.

[0115] Optionally, in the embodiments of this application, such as Figure 11 As shown, since there is no need to electrically connect to the substrate 100, there is no need to form the electrode structure 116 on the stepped structure formed on the substrate 100.

[0116] Optionally, in one embodiment of this application, the above steps form an electrode structure 116 on the side of each step structure away from the substrate, such that each electrode structure 116 is electrically connected to the step surface of each step structure in a one-to-one correspondence, including: forming a second dielectric layer 114 covering all step structures; forming a plurality of vias 115 in the second dielectric layer 114 based on a patterning process, so that the step surface of a portion of the step structure is exposed; and forming an electrode structure 116 within the vias 115.

[0117] Optionally, in this embodiment of the application, forming a second dielectric layer 114 covering all the step structures includes: forming a second dielectric layer 114 covering all the step structures based on a deposition process.

[0118] Optionally, the second dielectric layer 114 can be treated with CMP (Chemical Mechanical Polishing) process to ensure the flatness of the upper surface of the second dielectric layer 114.

[0119] Optionally, in this embodiment of the application, a plurality of vias 115 are formed in the second dielectric layer 114 based on a patterning process, including: forming a patterned photoresist structure on the second dielectric layer 114 based on processes such as coating, exposure and development, and then using the photoresist structure as a mask, forming vias 106 in the second dielectric layer 114 based on an etching process to expose the conductive step surface of the step structure.

[0120] Optionally, in this embodiment of the application, forming an electrode structure 116 located within a via 115 includes: forming an electrode structure 116 filling each via 115 based on a deposition process. Optionally, each electrode structure 116 can be processed using a CMP process to make the upper surfaces of all electrode structures 116 flush.

[0121] In the semiconductor device manufacturing method provided in this application embodiment, since a stepped structure can be directly formed and there is no electrical connection between any two adjacent stepped structures, compared with related technologies, it is possible to avoid forming an insulating layer on the periphery of the via 115, thereby simplifying the semiconductor structure manufacturing process and reducing the manufacturing complexity and cost of the semiconductor structure.

[0122] Based on the same inventive concept, this application provides a semiconductor device, which is obtained based on the manufacturing method of any of the above-mentioned semiconductor devices. The semiconductor device includes at least two stepped structures disposed on one side of a substrate 100, and the stepped structures are electrically connected to peripheral circuits.

[0123] In this embodiment, the semiconductor device is obtained by using any of the semiconductor device manufacturing methods provided in the foregoing embodiments. The principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0124] Optionally, the substrate 100 includes a core region and a peripheral region 102 located outside the core region. The stepped structure is located within the peripheral region 102. The core region is provided with an array structure. The stepped structure is electrically connected to the array structure, so that the array structure is electrically connected to the peripheral circuit through the electrode structure 116 provided on the stepped structure.

[0125] Optionally, in one embodiment of this application, an electrode structure 116 is provided on the side of the stepped structure away from the substrate 100; along the first direction parallel to the substrate 100, the spacing between any two adjacent electrode structures 116 is equal.

[0126] Optionally, in this embodiment of the application, the spacing between any two adjacent electrode structures 116 is equal along the first direction, which can ensure that the spacing between adjacent electrode structures 116 is greater than the minimum spacing threshold, which helps to reduce the probability of parasitic capacitance between adjacent electrode structures 116 and the probability of crosstalk between adjacent electrode structures 116.

[0127] Optionally, in one embodiment of this application, the distance between the upper surfaces of any two adjacent stepped structures is equal along a direction perpendicular to the substrate 100.

[0128] Optionally, in this embodiment of the application, the distance between the upper surfaces of any two adjacent step structures is equal along the direction perpendicular to the substrate 100, thereby preventing any electrical connection between any two adjacent step structures.

[0129] Based on the same inventive concept, this application provides a memory obtained by the manufacturing method of any of the above-mentioned semiconductor devices. The memory includes: at least one memory array structure disposed on one side of a substrate; the memory array structure includes at least two stacked memory cell arrays; at least two step structures disposed on one side of the memory array structure, and each layer of memory cell array is electrically connected to the peripheral circuit through the corresponding step structure.

[0130] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes any of the semiconductor devices provided in the above embodiments.

[0131] Optionally, in this embodiment, the semiconductor device includes a memory.

[0132] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.

[0133] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0134] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.

[0135] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0136] In the semiconductor device manufacturing method provided in this application embodiment, the number of stacked units covering the (i-1)th transition step structure formed by the i-th deposition is half the number of stacked units formed by the (i-1)th deposition. Thus, after the i-th deposition of the stacked units is patterned for the i-th time, the number of steps in the i-th transition step structure is twice the number of steps in the (i-1)th transition step structure. This significantly reduces the number of patterning processes required to form the desired step structure, which helps to reduce the manufacturing difficulty and cost of semiconductor devices.

[0137] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0138] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0139] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0140] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0141] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0142] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: The first deposition is performed to form at least two stacked units on one side of the substrate; The stacking unit includes at least two stacks; The first patterning is performed to expose a portion of the substrate surface and form a first transition step structure; Perform the i-th deposition to form a stacked unit covering the (i-1)-th transition step structure and part of the substrate; The number of superimposed units formed by the i-th deposition is half the number of superimposed units formed by the (i-1)-th deposition; The stacked unit formed by the i-th deposition is patterned for the i-th time to expose part of the surface of the substrate and form the i-th transition step structure; wherein, the number of steps of the i-th transition step structure is twice the number of steps of the (i-1)-th transition step structure; Determine whether the number of steps in the i-th transition step structure meets the set number; if yes, a step structure that meets the expectations is obtained; if no, continue to manufacture the (i+1)-th transition step structure; where i is a positive integer greater than 1.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first patterning process exposes a portion of the substrate surface and forms a first transition structure, including: A first mask structure is formed that covers half of the area of ​​the stacked units; Based on the first mask structure, the stacked units are etched to expose a portion of the substrate surface and form the first transition step structure; And, the i-th deposition-formed stacked unit is patterned for the i-th time, exposing a portion of the substrate surface and forming the i-th transition step structure, including: Form the i-th mask structure covering half of the region of each step structure in the stacked unit formed by the i-th deposition; Based on the i-th mask structure, the stacked units formed by the i-th deposition are etched to expose part of the surface of the substrate and form the i-th transition step structure.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Perform the i-th deposition to form a stacked unit covering the (i-1)-th transition step structure and a portion of the substrate, including: Based on the deposition process, a first dielectric layer is formed covering the (i-1)th transition step structure and a portion of the substrate; The first dielectric layer is etched to form a first dielectric structure located on the (i-1)th transition step structure and part of the substrate; A first conductive layer is formed covering the sidewalls of the first dielectric structure and the (i-1)th transition step structure. The first conductive layer is etched to form a first conductive structure located on the first dielectric structure, and all the stacked first dielectric structures and the first conductive structure form the stacked unit.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The i-th deposition layer is patterned to expose a portion of the substrate surface and form the i-th transition step structure, including: In the i-th transition step structure formed by the i-th patterning, the number of steps is equal to 2 to the power of i.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After obtaining the desired stepped structure, the following steps are also included: An electrode structure is formed on the side of each step structure away from the substrate, such that each electrode structure is electrically connected to the step surface of each step structure in a one-to-one correspondence.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, An electrode structure is formed on the side of each step structure away from the substrate, such that each electrode structure is electrically connected to the step surface of each step structure in a one-to-one correspondence, including: A second dielectric layer is formed covering all of the aforementioned step structures; Multiple vias are formed in the second dielectric layer using a patterning process, exposing part of the stepped surface of the stepped structure. The electrode structure is formed within the via.

7. A semiconductor device, characterized in that, The semiconductor device is obtained by a method for manufacturing the semiconductor device according to any one of claims 1-6, wherein the semiconductor device comprises: At least two stepped structures are disposed on one side of the substrate, and the stepped structures are electrically connected to the peripheral circuit.

8. The semiconductor device according to claim 7, characterized in that, An electrode structure is provided on the side of the stepped structure away from the substrate; Along a first direction parallel to the substrate, the distance between any two adjacent electrode structures is equal.

9. The semiconductor device according to claim 7, characterized in that, Along a direction perpendicular to the substrate, the distance between any two adjacent upper surfaces of the stepped structures is equal.

10. A memory, characterized in that, The memory is obtained by a method for manufacturing the semiconductor device according to any one of claims 1-6, wherein the memory comprises: At least one memory array structure is disposed on one side of a substrate; the memory array structure includes at least two stacked memory cell arrays; At least two stepped structures are disposed on one side of the storage array structure, and each layer of the storage cell array is electrically connected to the peripheral circuit through the corresponding stepped structure.

Images