Preparation method and structure of electrostatic protection device

Abstract

According to the preparation method and the structure of the electrostatic protection device provided by the invention, the first P-type well region, the second P-type well region, the first N-type injection region and the second N-type injection region can be formed only through twice photoetching, so that the electrostatic protection device is simple in structure, simple in process step and low in process cost. Moreover, the structure can simultaneously meet the two characteristics of low residual voltage and simple structure, and further, the electrostatic protection device structure provided by the invention is a bidirectional electrostatic protection device structure, so that greater flexibility can be provided during product design, and the application scene of the device is widened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a preparation method and structure of an electrostatic protection device. Background Art

[0002] ESD protection devices are passive components used to protect electronic devices from damage caused by static electricity. They work by providing a controlled discharge path in the circuit, directing the static discharge to a place where it will not cause damage to the electronic device. Residual voltage is the voltage generated by the ESD protection device during the discharge process, which is usually closely related to the performance of the device. Among them, when the residual voltage exceeds the withstand voltage level of the protected electronic device, the electronic device will be damaged.

[0003] However, it is difficult for the electrostatic protection device in the prior art to have both the low residual voltage and the simple structure. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a preparation method and structure of an electrostatic protection device, which solves the problem that the electrostatic protection device in the prior art is difficult to have both the characteristics of low residual voltage and simple structure.

[0005] According to a first aspect of the present invention, there is provided a method for preparing an electrostatic protection device, comprising:

[0006] providing a substrate;

[0007] forming an N-type epitaxial layer on the substrate;

[0008] forming a first P-type well region and a second P-type well region independent of each other in the N-type epitaxial layer;

[0009] After forming the first P-type well region and the second P-type well region, a first N-type implantation region and a second N-type implantation region are formed in the N-type epitaxial layer, wherein the first N-type implantation region is located on the first P-type well region and the second N-type implantation region is located on the second P-type well region.

[0010] Optionally, also include:

[0011] forming a dielectric layer on the N-type epitaxial layer, wherein the dielectric layer covers the first P-type well region, the second P-type well region, the first N-type implantation region, and the second N-type implantation region;

[0012] forming a first conductive via and a second conductive via in the dielectric layer;

[0013] After forming the first conductive via and the second conductive via, forming a first metal electrode and a second metal electrode on the dielectric layer, wherein two ends of the first conductive via are respectively in contact with the first metal electrode and the first N-type implantation region, and two ends of the second conductive via are respectively in contact with the second metal electrode and the second N-type implantation region;

[0014] A passivation film is formed on the surface of the dielectric layer, the surface of the first metal electrode and the surface of the second metal electrode, the passivation film having a first electrode window and a second electrode window, the first electrode window exposing a portion of the top surface of the first metal electrode, and the second electrode window exposing a portion of the top surface of the second metal electrode.

[0015] Optionally, the method of forming the first P-type well region and the second P-type well region includes:

[0016] forming a patterned first mask layer on the N-type epitaxial layer;

[0017] Using the first mask layer as a mask, performing P-type ion implantation;

[0018] After performing the P-type ion implantation, removing the first mask layer;

[0019] After removing the first mask layer, a first thermal annealing is performed.

[0020] Optionally, in the process of P-type ion implantation, the implanted element is boron, the energy range is 80 KeV to 120 KeV, and the dose range is 2e 14 Ion number / cm2 to 5e 14 Number of ions / cm2;

[0021] The first thermal annealing is performed in a nitrogen environment. In the process of the first thermal annealing, the process temperature is 1000° C. to 1100° C., and the duration is 60 minutes to 90 minutes.

[0022] Optionally, the method of forming the first N-type implantation region and the second N-type implantation region in the N-type epitaxial layer includes:

[0023] forming a second mask layer on the N-type epitaxial layer, wherein the second mask layer exposes a portion of the surface of the first P-type well region and a portion of the surface of the second P-type well region;

[0024] Using the second mask layer as a mask, performing N-type ion implantation;

[0025] After performing N-type ion implantation, removing the second mask layer;

[0026] After removing the second mask layer, a second thermal annealing is performed. 6. The method for preparing an electrostatic protection device according to claim 5, characterized in that in the process of N-type ion implantation, the implanted element is arsenic, the energy range is 30 KeV to 80 KeV, and the dose range is 5e 15 Ion number / cm2 to 8e 15 Number of ions / cm2;

[0027] The second thermal annealing is rapid thermal annealing, and process parameters of the second thermal annealing include: duration of 30 seconds to 40 seconds, and process temperature of 1050° C. to 1100° C.

[0028] According to a second aspect of the present invention, there is provided an electrostatic protection device structure, comprising:

[0029] substrate;

[0030] An N-type epitaxial layer, wherein the N-type epitaxial layer is located on the surface of the substrate;

[0031] A first P-type well region, wherein the first P-type well region is located in the N-type epitaxial layer;

[0032] a second P-type well region, wherein the first P-type well region is located in the N-type epitaxial layer, and the first P-type well region and the second P-type well region are independent of each other;

[0033] A first N-type implantation region, wherein the first N-type implantation region is located on the first P-type well region;

[0034] A second N-type implantation region, wherein the first N-type implantation region is located on the second P-type well region.

[0035] Optionally, also include:

[0036] A dielectric layer, wherein the dielectric layer is located on a surface of the N-type epitaxial layer, and the dielectric layer covers the first P-type well region, the second P-type well region, the first N-type injection region, and the second N-type injection region;

[0037] A first conductive via and a second conductive via, wherein the first conductive via and the second conductive via are both located in the dielectric layer, and one end of the first conductive via is in contact with the first N-type implantation region, and one end of the second conductive via is in contact with the second N-type implantation region;

[0038] A first metal electrode and a second metal electrode, wherein the first metal electrode and the second metal electrode are both located on the dielectric layer; wherein the first metal electrode is in contact with the other end of the second conductive through hole, and the second metal electrode is in contact with the other end of the second conductive through hole;

[0039] A passivation film, wherein the passivation film is located on the surface of the dielectric layer, the surface of the first metal electrode and the surface of the second metal electrode, and the passivation film has a first electrode window and a second electrode window, wherein the first electrode window exposes a portion of the top surface of the first metal electrode, and the second electrode window exposes a portion of the top surface of the second metal electrode.

[0040] Optionally, the doping element of the N-type epitaxial layer is phosphorus, and the resistivity of the N-type epitaxial layer is between 0.9 ohm·cm and 1.1 ohm·cm.

[0041] Optionally, a distance between the first P-type well region and the second P-type well region is 5 microns to 10 microns.

[0042] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0043] In the preparation method of the electrostatic protection device provided by the technical solution of the present invention, only two photolithography steps are required to form the first P-type well region, the second P-type well region, the first N-type injection region and the second N-type injection region, so that the electrostatic protection device has a simple structure, simple process steps and low process cost.

[0044] The electrostatic protection device structure provided by the technical solution of the present invention includes a substrate, an N-type epitaxial layer, a first P-type well region, a second P-type well region, a first N-type injection region and a second N-type injection region. Among them, the first N-type injection region, the first P-type well region and the N-type epitaxial layer constitute an NPN triode, the first P-type well region, the N-type epitaxial layer and the second P-type well region constitute a PNP triode, and the second P-type well region and the second N-type injection region constitute a diode. Since the NPN triode and the PNP triode can generate positive feedback after the electrostatic protection device is turned on, the residual voltage of the electrostatic protection device is reduced, and because the PNP tube is connected in series with a diode, the electrostatic protection device has a low residual voltage while avoiding the latch effect caused by the positive feedback. Therefore, the electrostatic protection device structure provided by the technical solution of the present invention satisfies the two characteristics of low residual voltage and simple structure at the same time.

[0045] Furthermore, the electrostatic protection device structure provided by the technical solution of the present invention is a bidirectional electrostatic protection device structure, which can provide greater flexibility in product design, thereby broadening the application scenarios of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of the structure of a PNPN thyristor;

[0047] Figure 2-Figure 9It is a schematic diagram of a device structure cross-section corresponding to each step of a method for preparing an electrostatic protection device provided in an embodiment of the present invention.

[0048] Reference numerals:

[0049] 1-PNPN thyristor;

[0050] 2-PN diode;

[0051] 3-deep trench isolation structure;

[0052] 4-substrate;

[0053] 5-N-type epitaxial layer;

[0054] 6-first P-type well region;

[0055] 7-a second P-type well region;

[0056] 8-first N-type implantation region;

[0057] 9-second N-type implantation region;

[0058] 10- dielectric layer;

[0059] 11-first conductive via;

[0060] 12- a second conductive via;

[0061] 13- a first metal electrode;

[0062] 14- a second metal electrode;

[0063] 15-passivation film;

[0064] 16-first electrode window;

[0065] 17- second electrode window;

[0066] d-the distance between the first P-type well region and the second P-type well region. DETAILED DESCRIPTION

[0067] As described in the background art, it is difficult for existing electrostatic protection devices to simultaneously have both low residual voltage and simple structure.

[0068] Specifically, in order to reduce the residual voltage, the existing electrostatic protection device adopts a PNP transistor or an NPN transistor with a shallow back-off structure, which has a negative resistance function and can reduce the residual voltage to a certain extent, but the process is complicated and the cost is high.

[0069] In order to further reduce the residual pressure, Figure 1 A PNPN thyristor structure is also shown. However, this structure is more complex and the process cost is higher. Figure 1Provide specific instructions.

[0070] Please refer to Figure 1 , a PNPN thyristor 1 with a deep back-off structure is provided. A PNP transistor and an NPN transistor are parasitic in the structure. When the PNPN thyristor 1 is turned on, the parasitic PNP transistor and NPN transistor in the PNPN thyristor 1 will generate positive feedback, so that the residual voltage is further reduced compared with the PNP transistor or NPN transistor with a shallow back-off structure. However, its structure is more complicated and the process cost is higher than that of the PNP transistor or NPN transistor with a shallow back-off structure.

[0071] Moreover, the PNPN thyristor 1 is prone to latch-up, which can cause the device to burn out in a short time. Figure 1 A PN diode 2 is connected in series in the PNPN thyristor 1. However, the more diodes 2 are connected in series, the greater the residual voltage of the device is, which is not conducive to reducing the residual voltage.

[0072] In addition, in order to ensure that the current flows in the designed direction, the PNPN thyristor 1 and the PN diode 2 need to be isolated by a deep trench isolation structure 3, which makes the structure more complicated and the process cost higher.

[0073] Therefore, it is difficult for the above-mentioned electrostatic protection device to have both the characteristics of low residual voltage and simple structure at the same time.

[0074] In view of this, the present invention creatively proposes a method and structure for preparing an electrostatic protection device, and the method for preparing the electrostatic protection device comprises:

[0075] providing a substrate;

[0076] forming an N-type epitaxial layer on the substrate;

[0077] forming a first P-type well region and a second P-type well region independent of each other in the N-type epitaxial layer;

[0078] After forming the first P-type well region and the second P-type well region, a first N-type implantation region and a second N-type implantation region are formed in the N-type epitaxial layer, wherein the first N-type implantation region is located on the first P-type well region and the second N-type implantation region is located on the second P-type well region.

[0079] It can be seen that only two photolithography steps are required to form the first P-type well region, the second P-type well region, the first N-type injection region and the second N-type injection region, so that the electrostatic protection device has a simple structure, simple process steps and low process cost. Among them, the first N-type injection region, the first P-type well region and the N-type epitaxial layer constitute an NPN triode, the first P-type well region, the N-type epitaxial layer and the second P-type well region constitute a PNP triode, and the second P-type well region and the second N-type injection region constitute a diode. Since the NPN triode and the PNP triode can generate positive feedback after the electrostatic protection device is turned on, the residual voltage of the electrostatic protection device is reduced, and because the PNP tube is connected in series with a diode, the electrostatic protection device has a low residual voltage while avoiding the latch effect caused by the positive feedback, so that the electrostatic protection device structure produced satisfies both the characteristics of low residual voltage and simple structure.

[0080] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0081] in, Figure 2-Figure 9 It is a schematic diagram of a device structure cross-section corresponding to each step of a method for preparing an electrostatic protection device provided in an embodiment of the present invention.

[0082] Please refer to Figure 2-Figure 9 An embodiment of the present invention provides a method for preparing an electrostatic protection device, comprising:

[0083] S1: Please refer to Figure 2 , providing a substrate 4.

[0084] In this embodiment, the substrate 4 is a P-type substrate 4, the element doped in the substrate 4 is boron, the resistivity is 10 ohm·cm, and the crystal orientation of the substrate 4 is 100. Of course, there are many options for the doping elements and resistivity of the N-type epitaxial layer 5, and the present invention does not limit this.

[0085] S2: Please refer to Figure 3 , an N-type epitaxial layer 5 is formed on the substrate 4.

[0086] In this embodiment, the doping element in the N-type epitaxial layer 5 is phosphorus, the thickness is 10 microns, and the resistivity is 0.9 ohm·cm to 1.1 ohm·cm. Of course, there are many options for the doping element, thickness, and resistivity of the N-type epitaxial layer 5, and the present invention does not limit this.

[0087] Before forming the N-type epitaxial layer 5 on the substrate 4 , the method further includes: preparing a zero-layer photolithography alignment mark groove on the substrate 4 .

[0088] S3: Please refer to Figure 4 , a first P-type well region 6 and a second P-type well region 7 independent of each other are formed in the N-type epitaxial layer 5 .

[0089] Among them, S3 specifically includes:

[0090] S31 : forming a patterned first mask layer on the N-type epitaxial layer 5 .

[0091] S32: performing P-type ion implantation using the first mask layer as a mask.

[0092] In this embodiment, the P-type ions are boron ions, the energy range is 80 KeV to 120 KeV, and the dose range is 2e 14 Ion number / cm2 to 5e 14 The number of ions / cm2, the implantation angle is 7°. Of course, there are many other options for the type, energy, dosage and implantation angle of the P-type ions, and the present invention is not limited thereto.

[0093] S33: After performing the P-type ion implantation, removing the first mask layer.

[0094] S34: after removing the first mask layer, performing a first thermal annealing.

[0095] The material of the patterned first mask layer may be, for example, photoresist, and the method of forming the patterned first mask layer may specifically include:

[0096] S311 : forming a first photoresist layer on the N-type epitaxial layer 5 .

[0097] S312: using a first photomask to expose and develop the first photoresist layer to form a patterned photoresist layer as the patterned first mask layer.

[0098] Of course, it should be appreciated that the patterned first mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0099] In this embodiment, the first thermal annealing is performed in a nitrogen environment, and the process temperature of the first thermal annealing is 1000° C. to 1100° C., and the duration is 60 minutes to 90 minutes. The first thermal annealing can activate the P-type ions and push them deeper into the N-type epitaxial layer 5.

[0100] In this embodiment, the distance d between the first P-type well region 6 and the second P-type well region 7 is 5 microns to 10 microns. If the distance d between the first P-type well region 6 and the second P-type well region 7 is greater than 10 microns, the residual voltage of the electrostatic protection device will increase, and if the distance d between the first P-type well region 6 and the second P-type well region 7 is less than 5 microns, the electrostatic protection device is prone to leakage and other undesirable phenomena.

[0101] S4: Please refer to Figure 5 After forming the first P-type well region 6 and the second P-type well region 7, a first N-type implantation region 8 and a second N-type implantation region 9 are formed in the N-type epitaxial layer 5, wherein the first N-type implantation region 8 is located on the first P-type well region 6, and the second N-type implantation region 9 is located on the second P-type well region 7.

[0102] Among them, S4 specifically includes:

[0103] S41 : forming a second mask layer on the N-type epitaxial layer 5 , wherein the second mask layer exposes a portion of the surface of the first P-type well region 6 and a portion of the surface of the second P-type well region 7 .

[0104] S42: performing N-type ion implantation using the second mask layer as a mask.

[0105] In this embodiment, the N-type ions are arsenic ions, the energy range is 30 KeV to 80 KeV, and the dose range is 5e 15 Ion number / cm2 to 8e 15 Of course, there are many other options for the type, energy and dosage of the N-type ions, and the present invention is not limited thereto.

[0106] S43: After performing the N-type ion implantation, removing the second mask layer.

[0107] S44: after removing the second mask layer, performing a second thermal annealing.

[0108] In this embodiment, the second thermal annealing is rapid thermal annealing, and process parameters of the second thermal annealing include: a duration of 30 seconds to 40 seconds, and a process temperature of 1050° C. to 1100° C.

[0109] The material of the patterned second mask layer may be, for example, photoresist, and the method of forming the patterned second mask layer may specifically include:

[0110] S411 : forming a second photoresist layer on the N-type epitaxial layer 5 .

[0111] S412: using a second photomask to expose and develop the second photoresist layer to form a patterned photoresist layer as the patterned second mask layer.

[0112] Of course, it should be appreciated that the patterned second mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0113] S5: Please refer to Figure 6 , a dielectric layer 10 is formed on the N-type epitaxial layer 5 , and the dielectric layer 10 covers the first P-type well region 6 , the second P-type well region 7 , the first N-type implantation region 8 and the second N-type implantation region 9 .

[0114] In this embodiment, S5 specifically includes:

[0115] S51 : forming a first silicon dioxide film on the epitaxial layer, wherein the first silicon dioxide film covers the epitaxial layer, the first P-type well region 6 , the second P-type well region 7 , the first N-type implantation region 8 , and the second N-type implantation region 9 .

[0116] S52: sequentially depositing a second silicon dioxide film and a third silicon dioxide film on the first silicon dioxide film.

[0117] The thickness of the first silicon dioxide film, the second silicon dioxide film and the third silicon dioxide film are all 5000 angstroms.

[0118] S53 : depositing borophosphide silicon glass on the third silicon dioxide film to form the dielectric layer 10 .

[0119] The borophosphide silicon glass includes 4% boron and 4% phosphorus, and the thickness of the borophosphide silicon glass is 8000 angstroms.

[0120] S53: performing a planarization process on the dielectric layer 10 .

[0121] The planarization process is implemented by a thermal reflow process. Of course, the planarization process can also be completed by other processes, which will not be elaborated in the present invention.

[0122] S6: Please refer to Figure 7 , a first conductive via 11 and a second conductive via 12 are formed in the dielectric layer 10 .

[0123] Among them, S6 specifically includes:

[0124] S61 : forming a patterned third mask layer on the dielectric layer 10 .

[0125] S62 : using the third mask layer as a mask, etching the dielectric layer 10 to form the first conductive via 11 and the second conductive via 12 .

[0126] S63: removing the third mask layer.

[0127] The material of the patterned third mask layer may be, for example, photoresist, and the method of forming the patterned third mask layer may specifically include:

[0128] S611 : forming a third photoresist layer on the dielectric layer 10 .

[0129] S612: using a third photomask to expose and develop the third photoresist layer to form a patterned photoresist layer as the patterned third mask layer.

[0130] Of course, it should be appreciated that the patterned third mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0131] S7: Please refer to Figure 8 After forming the first conductive via 11 and the second conductive via 12, a first metal electrode 13 and a second metal electrode 14 are formed on the dielectric layer 10, and the two ends of the first conductive via 11 contact the first metal electrode 13 and the first N-type injection region 8 respectively, and the two ends of the second conductive via 12 contact the second metal electrode 14 and the second N-type injection region 9 respectively.

[0132] The first metal electrode 13 forms a good ohmic contact with the first N-type implantation region 8 through the first conductive via 11 , and the second metal electrode 14 forms a good ohmic contact with the second N-type implantation region 9 through the second conductive via 12 .

[0133] In this embodiment, over-etching is required when forming the first conductive via 11 and the second conductive via 12, and the over-etching amount is 500 angstroms. If the over-etching amount is small, the first metal electrode 13 and the first N-type injection region 8 and the second metal electrode 14 and the second N-type injection region 9 will form a poor ohmic contact. If the over-etching amount is small, it will cause insufficient junction holes, thereby causing leakage.

[0134] In this embodiment, S7 specifically includes:

[0135] S71 : depositing a first metal layer on the dielectric layer 10 , wherein the first metal layer covers the dielectric layer 10 , the first conductive via 11 , and the second conductive via 12 .

[0136] Wherein, the material of the first metal layer is titanium, and the thickness is 300 angstroms.

[0137] S72: depositing a second metal layer on the first metal layer.

[0138] Wherein, the material of the second metal layer is titanium nitride, and the thickness is 1000 angstroms.

[0139] S73: Perform rapid thermal annealing.

[0140] S74: depositing a third metal layer on the second metal layer.

[0141] The third metal layer is an alloy material including three elements: aluminum, silicon and copper, and the thickness of the third metal layer is 4 microns.

[0142] S75: forming a patterned fourth mask layer on the third metal layer.

[0143] S76 : using the fourth mask layer as a mask, etching the first metal layer, the second metal layer, and the third metal layer to form a first metal electrode 13 and the second metal electrode 14 .

[0144] The material of the patterned fourth mask layer may be, for example, photoresist, and the method of forming the patterned fourth mask layer may specifically include:

[0145] S751: forming a fourth photoresist layer on the fourth metal layer.

[0146] S752: using a fourth photomask to expose and develop the third photoresist layer to form a patterned photoresist layer as the patterned fourth mask layer.

[0147] Of course, it should be appreciated that the patterned fourth mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0148] S8: Please refer to Fig. 9 A passivation film 15 is formed on the surface of the dielectric layer 10, the surface of the first metal electrode 13 and the surface of the second metal electrode 14, and the passivation film 15 has a first electrode window 16 and a second electrode window 17, the first electrode window 16 exposes a portion of the top surface of the first metal electrode 13, and the second electrode window 17 exposes a portion of the top surface of the second metal electrode 14.

[0149] Among them, S8 specifically includes:

[0150] S81 : depositing a fourth silicon dioxide film on the surface of the dielectric layer 10 , the surface of the first metal electrode 13 , and the surface of the second metal electrode 14 .

[0151] Wherein, the thickness of the fourth silicon dioxide film is 5000 angstroms.

[0152] S82: depositing a silicon nitride layer on the fourth silicon dioxide film.

[0153] Wherein, the thickness of the silicon nitride layer is 5000 angstroms.

[0154] S83 : forming a patterned fifth mask layer on the passivation film 15 , wherein the fifth mask layer exposes a portion of the top surface of the first metal electrode 13 and a portion of the top surface of the second metal electrode 14 .

[0155] S84 : using the fifth mask layer as a mask, etching the fourth silicon dioxide film and the silicon nitride layer to form the passivation film 15 , wherein the passivation film 15 has a first electrode window 16 and a second electrode window 17 .

[0156] The material of the patterned fifth mask layer may be, for example, photoresist, and the method of forming the patterned fifth mask layer may specifically include:

[0157] S831: forming a fifth photoresist layer on the silicon nitride layer.

[0158] S832: using a fifth photomask to expose and develop the fifth photoresist layer to form a patterned photoresist layer as the patterned fifth mask layer.

[0159] Of course, it should be appreciated that the patterned fifth mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0160] In summary, in the preparation method of the electrostatic protection device provided by the technical solution of the present invention, only two photolithography steps are needed to form the first P-type well region, the second P-type well region, the first N-type injection region and the second N-type injection region, so that the electrostatic protection device has a simple structure, simple process steps and low process cost.

[0161] Please continue to refer to Fig. 9 The present invention also provides an electrostatic protection device structure, comprising:

[0162] Substrate 4;

[0163] An N-type epitaxial layer 5, wherein the N-type epitaxial layer 5 is located on the surface of the substrate 4;

[0164] A first P-type well region 6, wherein the first P-type well region 6 is located in the N-type epitaxial layer 5;

[0165] a second P-type well region 7, wherein the first P-type well region 6 is located in the N-type epitaxial layer 5, and the first P-type well region 6 and the second P-type well region 7 are independent of each other;

[0166] A first N-type implantation region 8, wherein the first N-type implantation region 8 is located on the first P-type well region 6;

[0167] A second N-type implantation region 9, wherein the first N-type implantation region 8 is located on the second P-type well region 7;

[0168] A dielectric layer 10, wherein the dielectric layer 10 is located on the surface of the N-type epitaxial layer 5, and the dielectric layer 10 covers the first P-type well region 6, the second P-type well region 7, the first N-type implantation region 8, and the second N-type implantation region 9;

[0169] A first conductive via 11 and a second conductive via 12, wherein the first conductive via 11 and the second conductive via 12 are both located in the dielectric layer 10, and one end of the first conductive via 11 is in contact with the first N-type implantation region 8, and one end of the second conductive via 12 is in contact with the second N-type implantation region 9;

[0170] A first metal electrode 13 and a second metal electrode 14, wherein the first metal electrode 13 and the second metal electrode 14 are both located on the dielectric layer 10; wherein the first metal electrode 13 contacts the other end of the second conductive via 12, and the second metal electrode 14 contacts the other end of the second conductive via 12;

[0171] A passivation film 15, wherein the passivation film 15 is located on the surface of the dielectric layer 10, the surface of the first metal electrode 13 and the surface of the second metal electrode 14, and the passivation film 15 has a first electrode window 16 and a second electrode window 17, wherein the first electrode window 16 exposes a portion of the top surface of the first metal electrode 13, and the second electrode window 17 exposes a portion of the top surface of the second metal electrode 14.

[0172] Among them, the first N-type injection region 8, the first P-type well region 6 and the N-type epitaxial layer 5 constitute an NPN transistor, the first P-type well region 6, the N-type epitaxial layer 5 and the second P-type well region 7 constitute a PNP transistor, and the second P-type well region 7 and the second N-type injection region 9 constitute a diode. Since the NPN transistor and the PNP transistor can generate positive feedback after the electrostatic protection device is turned on, the residual voltage of the electrostatic protection device is reduced, and because the PNP transistor is connected in series with a PN diode, the electrostatic protection device has a low residual voltage and avoids the latch effect caused by the positive feedback. Therefore, the electrostatic protection device structure provided by the technical solution of the present invention satisfies both the characteristics of low residual voltage and simple structure.

[0173] In addition, the second N-type injection region 9, the second P-type well region 7 and the N-type epitaxial layer 5 can also form an NPN transistor, the second P-type well region 7, the N-type epitaxial layer 5 and the first P-type well region 6 can also form a PNP transistor, and the first P-type well region 6 and the first N-type injection region 8 can also form a PN diode. Therefore, the electrostatic protection device structure is a bidirectional electrostatic protection device structure, which can provide greater flexibility in product design, thereby broadening the application scenarios of the device.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing an electrostatic protection device, characterized in that: include: providing a substrate; forming an N-type epitaxial layer on the substrate; forming a first P-type well region and a second P-type well region independent of each other in the N-type epitaxial layer; After forming the first P-type well region and the second P-type well region, a first N-type implantation region and a second N-type implantation region are formed in the N-type epitaxial layer, wherein the first N-type implantation region is located on the first P-type well region and the second N-type implantation region is located on the second P-type well region.

2. The method for preparing an electrostatic protection device according to claim 1, characterized in that: Also includes: forming a dielectric layer on the N-type epitaxial layer, wherein the dielectric layer covers the first P-type well region, the second P-type well region, the first N-type implantation region, and the second N-type implantation region; forming a first conductive via and a second conductive via in the dielectric layer; After forming the first conductive via and the second conductive via, forming a first metal electrode and a second metal electrode on the dielectric layer, wherein two ends of the first conductive via are respectively in contact with the first metal electrode and the first N-type implantation region, and two ends of the second conductive via are respectively in contact with the second metal electrode and the second N-type implantation region; A passivation film is formed on the surface of the dielectric layer, the surface of the first metal electrode and the surface of the second metal electrode, the passivation film having a first electrode window and a second electrode window, the first electrode window exposing a portion of the top surface of the first metal electrode, and the second electrode window exposing a portion of the top surface of the second metal electrode.

3. The method for preparing an electrostatic protection device according to claim 1, characterized in that: The method of forming the first P-type well region and the second P-type well region includes: forming a patterned first mask layer on the N-type epitaxial layer; Using the first mask layer as a mask, performing P-type ion implantation; After performing the P-type ion implantation, removing the first mask layer; After removing the first mask layer, a first thermal annealing is performed.

4. The method for preparing an electrostatic protection device according to claim 3, characterized in that: In the process of P-type ion implantation, the implanted element is boron, the energy range is 80 KeV to 120 KeV, and the dose range is 2e 14 Ion number / cm2 to 5e 14 Number of ions / cm2; The first thermal annealing is performed in a nitrogen environment. In the process of the first thermal annealing, the process temperature is 1000° C. to 1100° C., and the duration is 60 minutes to 90 minutes.

5. The method for preparing an electrostatic protection device according to claim 1, characterized in that: The method of forming a first N-type implantation region and a second N-type implantation region in the N-type epitaxial layer includes: forming a second mask layer on the N-type epitaxial layer, wherein the second mask layer exposes a portion of the surface of the first P-type well region and a portion of the surface of the second P-type well region; Using the second mask layer as a mask, performing N-type ion implantation; After performing N-type ion implantation, removing the second mask layer; After removing the second mask layer, a second thermal annealing is performed.

6. The method for preparing an electrostatic protection device according to claim 5, characterized in that: In the process of N-type ion implantation, the implanted element is arsenic, the energy range is 30 KeV to 80 KeV, and the dose range is 5e 15 Ion number / cm2 to 8e 15 Number of ions / cm2; The second thermal annealing is rapid thermal annealing, and process parameters of the second thermal annealing include: duration of 30 seconds to 40 seconds, and process temperature of 1050° C. to 1100° C.

7. An electrostatic protection device structure, characterized in that: include: substrate; An N-type epitaxial layer, wherein the N-type epitaxial layer is located on the surface of the substrate; A first P-type well region, wherein the first P-type well region is located in the N-type epitaxial layer; a second P-type well region, wherein the first P-type well region is located in the N-type epitaxial layer, and the first P-type well region and the second P-type well region are independent of each other; A first N-type implantation region, wherein the first N-type implantation region is located on the first P-type well region; A second N-type implantation region, wherein the first N-type implantation region is located on the second P-type well region.

8. The electrostatic protection device structure according to claim 7, characterized in that: Also includes: a dielectric layer, the dielectric layer being located on a surface of the N-type epitaxial layer, and the dielectric layer covering the first P-type well region, the second P-type well region, the first N-type injection region, and the second N-type injection region; A first conductive via and a second conductive via, wherein the first conductive via and the second conductive via are both located in the dielectric layer, and one end of the first conductive via is in contact with the first N-type implantation region, and one end of the second conductive via is in contact with the second N-type implantation region; A first metal electrode and a second metal electrode, wherein the first metal electrode and the second metal electrode are both located on the dielectric layer; wherein the first metal electrode is in contact with the other end of the second conductive through hole, and the second metal electrode is in contact with the other end of the second conductive through hole; A passivation film is located on the surface of the dielectric layer, the surface of the first metal electrode and the surface of the second metal electrode, and the passivation film has a first electrode window and a second electrode window, the first electrode window exposes a portion of the top surface of the first metal electrode, and the second electrode window exposes a portion of the top surface of the second metal electrode.

9. The electrostatic protection device structure according to claim 7, characterized in that: The doping element of the N-type epitaxial layer is phosphorus, and the resistivity of the N-type epitaxial layer is between 0.9 ohm·cm and 1.1 ohm·cm.

10. The electrostatic protection device structure according to claim 7, characterized in that: The distance between the first P-type well region and the second P-type well region is 5 micrometers to 10 micrometers.

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