Semiconductor device structure and forming method thereof

Abstract

The invention relates to a semiconductor device structure and a forming method thereof. A method for forming a semiconductor device structure is described. The method includes: removing a portion of a fin structure to form a first portion of an isolation trench in the fin structure; passivating an exposed surface of a first portion of the isolation trench to change an etch selectivity of the exposed surface to a first etchant; removing a portion of the passivated surface at the bottom of the first portion of the isolation trench using the first etchant; removing a portion of the substrate by a second etchant to form a second portion of the isolation trench; and filling the isolation trench with a dielectric material.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and more particularly to semiconductor device structures and methods of forming the same. Background Art

[0002] As the semiconductor industry moves to nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from both manufacturing and design issues have led to the development of multi-gate devices such as FinFETs and gate-all-around (GAA) transistors. In order to continue to provide the required scaling and increased density for multi-gate devices in advanced technology nodes, the gate pitch needs to continue to be reduced. Various schemes (such as poly on diffusion edge (PODE) and continuous poly on diffusion edge (CPODE)) have been used to reduce the gate pitch while preventing leakage current between transistors. However, such schemes cannot provide the etch profiles required for aggressively scaled circuits and devices, especially when it comes to backside power rail applications.

[0003] Therefore, there is a need for improvements in the processing and manufacturing of ICs. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: removing a portion of a fin structure to form a first portion of an isolation trench in the fin structure; passivating an exposed surface of the first portion of the isolation trench to change the etching selectivity of the exposed surface to a first etchant; removing a portion of the passivated surface at the bottom of the first portion of the isolation trench using the first etchant; removing a portion of a substrate by a second etchant to form a second portion of the isolation trench; and filling the isolation trench with a dielectric material.

[0005] According to an embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: (1) forming a first fin structure and a second fin structure on a first side of a substrate, each of the first fin structure and the second fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; (2) forming a source / drain feature on the first side of the substrate between the first fin structure and the second fin structure; (3) removing portions of the plurality of first semiconductor layers and the plurality of second semiconductor layers from the first fin structure to form an isolation trench having a first depth; (4) forming a passivation layer on the sidewalls and bottom surface of the isolation trench; and (5) removing the passivation layer from the bottom surface of the isolation trench to expose the (6) removing the passivation layer and the portion of the substrate to extend the isolation trench from the first depth to a second depth; (7) filling the isolation trench with a dielectric material; (8) removing the plurality of second semiconductor layers from the second fin structure; (9) surrounding each of the first semiconductor layers of the second fin structure with a gate electrode layer; (10) forming an opening from the second side of the substrate to expose the source / drain feature; and (11) filling the opening with a conductive material to form a backside via contact for the source / drain feature, wherein the isolation trench and the backside via contact are arranged in parallel and are separated from each other by a constant gap along the boundary of the isolation trench and the backside via contact.

[0006] According to one embodiment of the present disclosure, a semiconductor device structure is provided, comprising: a fin structure formed on a substrate; a source / drain feature adjacent to the fin structure and arranged above the substrate; an isolation trench extending from the front side of the substrate toward the back side of the substrate; and a back side via contact extending from the back side of the substrate and contacting the source / drain region, wherein the back side via contact and the isolation trench are arranged in parallel and are separated from each other by a constant gap along a boundary of the back side via contact and the isolation trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following specific implementations. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1-Figure 6 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Figures 7A-11A According to some embodiments, Figure 6 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at section AA.

[0010] Figure 7B-Figure 11B According to some embodiments, Figure 6 Section BB is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0011] Figure 7C-Figure 11C According to some embodiments, Figure 6 Section CC is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0012] Figure 12A-12B to Figure 21A-21B and Figure 23A-23B to Figure 40A-40B According to some embodiments of the invention Fig.11A and Fig. 11B A cross-sectional side view of one stage in various stages of a semiconductor device structure, Fig.11A and Fig. 11B A plurality of fin structures arranged along the X and Y directions are shown respectively.

[0013] Figure 22A-22G An exemplary cyclic etching process for forming isolation trenches is shown in accordance with some embodiments.

[0014] Figure 28A-1 According to some embodiments Fig.28A An enlarged view of a portion of the semiconductor device structure shown in FIG.

[0015] Figure 41A-41C According to some embodiments Fig.40A Schematic diagram of an area of ​​a semiconductor device structure in FIG. 1 , showing various arrangements of isolation trench (CPODE) structures and backside via contacts.

[0016] Fig.42A and Fig.42B is a cross-sectional view of a semiconductor device structure, which shows Fig.41B The illustrated embodiment arranges isolation trench structures and backside via contacts. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat the figure marks and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, spatially relative terms (e.g., "below," "lower," "above," "over," "up," "top," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0019] As integrated circuits scale down, the epitaxial critical dimension (EPI CD), which refers to the spacing between epitaxial regions, becomes smaller and smaller. Small EPI CD makes it challenging to etch trenches for insulating structures without damaging adjacent structures (e.g., epitaxial source / drain features). Exemplary insulating structures may include a continuous polysilicon on diffusion edge (CPODE) structure, which removes part or all of a selected fin structure and replaces it with an insulating material to form an isolation trench. The CPODE structure avoids leakage current through the epitaxial source / drain features, transistors, and the silicon substrate. Embodiments of the present disclosure provide an improved etching process for forming a high aspect ratio CPODE structure with a straight sidewall profile, which is helpful for backside power rail applications.

[0020] Although the embodiments of the present disclosure describe a CPODE first processing method, i.e., during the front-end-of-line (FEOL) processing before the metal gate is formed, these embodiments are equally applicable to a CPODE post-processing method (or so-called CMODE process), i.e., during the middle-end-of-line (MEOL) processing after the metal gate is formed. The embodiments of the present disclosure may also be applicable to other devices that may include CPODE or CMODE structures, such as planar FETs, fin FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices.

[0021] Figures 1 to 42B FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 42B Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes is not limiting and may be interchangeable.

[0022] The semiconductor device structure 100 generally includes a semiconductor layer stack 104 disposed on a substrate 101. The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, the dopant may be, for example, boron for a p-type field effect transistor (p-type FET) and phosphorus for an n-type field effect transistor (n-type FET).

[0023] The semiconductor layer stack 104 includes semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices (e.g., nanosheet channel FETs). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked on the substrate 101. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some examples, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination of the foregoing.

[0024] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0025] The first semiconductor layer 106 or a portion thereof may form (one or more) nanosheet channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanosheet is used herein to represent any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to an elongated material portion having a circular and substantially circular cross-section, and a beam-shaped or strip-shaped material portion including, for example, a cylindrical or substantially rectangular cross-section. The (one or more) nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. The nanosheet transistor may be referred to as a nanowire transistor, a gate all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 is further discussed below.

[0026] Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is only for the purpose of illustration and is not intended to limit the scope of the specific description in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0027] In some embodiments, a sacrificial layer 107 may be formed between the substrate 101 and the semiconductor layer stack 104. The sacrificial layer 107 is used as an etch stop layer to prevent damage to the epitaxial source / drain features during the wafer thinning process for backside power rail applications. The material of the sacrificial layer 107 is selected so that the sacrificial layer 107 has a different etch selectivity relative to the material of the substrate 101. In various embodiments, the sacrificial layer 107 may be a silicon germanium (SiGe) layer. The SiGe layer may be a single crystal SiGe layer, a graded SiGe layer (wherein the germanium concentration varies with the distance of the interface of the graded SiGe layer from the exposed substrate 101), or a non-graded SiGe layer (wherein the germanium concentration does not vary with the distance of the interface of the non-graded SiGe layer from the exposed substrate). In some cases, the SiGe layer may have a germanium composition percentage between about 50% and 95%. Other materials, such as silicon carbide, silicon nitride, may also be used.

[0028] exist Figure 2 In the figure, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a sacrificial layer 107 and a well portion (not shown) formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multi-patterning operation including a photolithography process and an etching process. The etching process forms trenches 114 through the hard mask layer, through the semiconductor layer stack 104 and into the substrate 101 in unprotected areas, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof. As shown in FIG. Figure 2 As shown, two fins are formed, but the number of fins is not limited to two. Figures 12A-12B arrive Figures 42A-42B As shown, in some embodiments, three or more fins are arranged along the X direction.

[0029] exist Figure 3In the embodiment, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (e.g., a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed so that the top of the structure 112 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0030] Depending on the application, the position of the sacrificial layer 107 can be changed relative to the bottom 118b of the insulating material 118 to control the grinding process ( Fig.35A and Fig.35B ) during the process. If the sacrificial layer 107 is disposed at a height higher than the bottom 118b of the insulating material 118, a greater amount of the substrate 101 will be removed, thereby forming a thinner substrate 101, for example Fig.40A and Fig.40B On the other hand, if the sacrificial layer 107 is disposed at a height lower than the bottom 118b of the insulating material 118, a smaller amount of the substrate 101 will be removed, thereby forming a thicker substrate 101, for example Fig.42A and Fig.42B The embodiment shown.

[0031] exist Figure 4, the insulating material 118 is recessed to form an isolation region 120. The recess of the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recess of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101. Thereafter, an optional liner 109 is formed on the isolation region 120 and the exposed surface of the fin structure 112. The liner 109 can be made of an oxygen-containing material, a dielectric material (e.g., SiO2, SiN, SiCN, SiOC, SiOCN, etc.), or any suitable material with a high etching selectivity relative to the first semiconductor layer 106 and the second semiconductor layer 108. The liner 109 protects the first semiconductor layer 106 and the second semiconductor layer 108 from being damaged during the subsequent removal of the sacrificial gate structure. The liner 109 can also be used as a subsequent sacrificial gate structure 130 ( Figure 5 ) of the sacrificial gate dielectric layer. The liner 109 may be a conformal layer and may be formed by a conformal process such as an atomic layer deposition (ALD) process.

[0032] exist Figure 5 , one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate electrode layer 134 and a mask layer 136. The sacrificial gate electrode layer 134 and the mask layer 136 may be formed by sequentially depositing uniform layers of the sacrificial gate electrode layer 134 and the mask layer 136 and then patterning the layers into the sacrificial gate structure 130. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers of the gate spacers 138 and anisotropically etching the one or more layers. Although one sacrificial gate structure 130 is shown, it should be understood that two or more sacrificial gate structures 130 may be arranged along the X direction, for example Figures 12A-12B arrive Figures 42A-42B The embodiment shown.

[0033] The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination of the foregoing.

[0034] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 is used as a channel region of the semiconductor device structure 100. The portion of the fin structure 112 partially exposed to the opposite side of the sacrificial gate structure 130 defines a source / drain (S / D) region of the semiconductor device structure 100. In some cases, some S / D regions can be shared between various transistors. For example, various regions in these S / D regions can be connected together and implemented as multiple functional transistors.

[0035] exist Figure 6 In the embodiment, portions of the fin structure 112 in the S / D region (e.g., regions on the opposite side of the sacrificial gate structure 130) are recessed downward below the top surface of the isolation region 120 (or the insulating material 118) by removing portions of the fin structure 112 that are not covered by the sacrificial gate structure 130. The removal process may not etch the sacrificial layer 107. The recessing of these portions of the fin structure 112 may be accomplished by any suitable etching process. The trenches 119 are formed in the S / D region as a result of the recessing of these portions of the fin structure 112.

[0036] Figures 7A-11A According to some embodiments, Figure 6 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section AA. Figure 7B-Figure 11B According to some embodiments, Figure 6 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section BB. Figure 7C-Figure 11C According to some embodiments, Figure 6 The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken from the cross-sectional view CC. The cross-sectional view AA is at the fin structure 112 ( Figure 4 ) in a plane along the X direction. Section BB is in a plane perpendicular to section AA and in the sacrificial gate structure 130 along the Y direction. Section CC is in a plane perpendicular to section AA and in the epitaxial S / D feature 146 ( Fig. 9A )middle.

[0037] exist Figure 8A-8C, the edge portion of each second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed along the X direction. The removal of the edge portion of the second semiconductor layer 108 forms a cavity. Next, a dielectric layer is formed on the exposed surface of the sacrificial gate structure 130 and the first semiconductor layer 106 and the second semiconductor layer 108. The dielectric layer also fills the cavity provided by removing the edge portion of the second semiconductor layer 108. Suitable materials for the dielectric layer may include, but are not limited to, SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN, and / or other suitable materials. The dielectric layer can be formed by a conformal deposition process (e.g., ALD). Then, a removal process (e.g., anisotropic etching process) is performed so that only a portion of the dielectric layer 144 remains in the cavity to form an internal spacer 144. The remaining second semiconductor layer 108 is capped between the internal spacers 144 along the X direction.

[0038] exist Figure 9A-9C In the embodiment of the present invention, epitaxial S / D features 146 are formed in the source / drain (S / D) region. The epitaxial S / D features 146 can be grown vertically and horizontally to form facets, which can correspond to crystal planes of the material used for the first semiconductor layer 106. In some cases, such as Fig. 9C As an example shown, the epitaxial S / D features 146 of the fin structure may be grown and merged with the epitaxial S / D features of the adjacent fin structure. In some embodiments, the epitaxial S / D features 146 of the fin structure may not be merged with the epitaxial S / D features of the adjacent fin structure. The epitaxial S / D features 146 may include one or more layers of Si, SiP, SiC and SiCP for n-type FETs or Si, SiGe, Ge for p-type FETs. The epitaxial S / D features 146 may be formed by epitaxial growth methods using selective epitaxial growth (SEG), CVD, ALD or MBE. The epitaxial S / D features 146 are in contact with the first semiconductor layer 106 and the internal spacer 144. The second semiconductor layer 108 below the sacrificial gate structure 130 is separated from the epitaxial S / D features 146 by the dielectric spacer 144.

[0039] The epitaxial S / D features 146 can be S / D regions. For example, one of a pair of epitaxial S / D features 146 located on one side of the sacrificial gate structure 130 can be a source region, and the other of a pair of epitaxial S / D features 146 located on the other side of the sacrificial gate structure 130 can be a drain region. A pair of S / D epitaxial features 146 includes a source epitaxial feature 146 and a drain epitaxial feature 146 connected by a channel (i.e., the first semiconductor layer 106). (One or more) source / drain regions can refer to a source or a drain, which depends on the context individually or collectively. In the present disclosure, source and drain are used interchangeably, and their structures are substantially the same.

[0040] exist Figure 10A-10C In the embodiment of the present invention, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the sacrificial gate structure 130, the insulating material 118, the epitaxial S / D feature 146, and the exposed surface of the semiconductor layer stack 104. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material for the first ILD layer 164 may include a compound containing Si, O, C, and / or H, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) may also be used for the first ILD layer 164.

[0041] exist Figures 11A-11C In the embodiment, after forming the first ILD layer 164, a planarization operation (e.g., CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. The top surfaces of the sacrificial gate electrode layer 134, the gate spacers 138, the CESL 162, and the first ILD layer 164 are substantially coplanar after CMP.

[0042] Figure 12A-12B arrive Figure 21A-21B and Figure 23A-23B arrive Figure 40A-40B According to some embodiments of the invention Fig.11A and Fig. 11B A cross-sectional side view of a semiconductor device structure 100 at one of various stages shows a plurality of fin structures arranged along the X and Y directions, respectively. Fig. 12A and Fig. 12B An embodiment is shown in which the first ILD layer 164 is recessed to a level below the top of the sacrificial gate electrode layer 134 before the CMP process. In this case, a cap layer 139, such as a SiN, SiCN, or TiN layer, may be formed on the recessed first ILD layer 164. The cap layer 139 may protect the first ILD layer 164 during subsequent CMP and etching processes. After the planarization process, the top surfaces of the cap layer 139, the CESL 162, the gate spacer 138, and the sacrificial gate electrode layer 134 are substantially coplanar. Although three fin structures are shown in the Y-cut view, it should be understood that any suitable number of fin structures may be formed in the multilayer structure to form the desired GAA semiconductor device structure 100, depending on the design and number of the desired GAA semiconductor device structure 100.

[0043] exist Fig.13A and Fig. 13BIn the embodiment of the present invention, a mask structure 1302 is formed on the top surface of the sacrificial gate electrode layer 134, the gate spacer 138, the CESL 162 and the cap layer 139 (or if the cap layer 139 is not formed, the first ILD layer 164). The mask structure 1302 may include a hard mask 1304 and a resist layer 1306. The hard mask 1304 may be any suitable masking material. In some embodiments, the hard mask 1304 is formed of a nitrogen-containing material, such as SiN or SiCN. The resist layer 1306 may be a single layer of photoresist or a three-layer photoresist. An exemplary three-layer photoresist may include a bottom layer 1308, an intermediate layer 1310 disposed on the bottom layer 1308, and a photoresist top layer 1312 disposed on the intermediate layer 1310. The resist layer 1306 may be formed by any suitable process, such as spin coating. The bottom layer 1308 may be a bottom anti-reflective coating (BARC). The middle layer 1310 may be a silicon-containing inorganic polymer that provides anti-reflective properties and / or hard mask properties for photolithography processes. The photoresist top layer 1312 may be a DUV resist (KrF) resist, an argon fluoride (ArF) resist, an EUV resist, an electron beam (e-beam) resist, or an ion beam resist.

[0044] exist Fig.14A and Fig. 14B In the embodiment of the present invention, the photoresist top layer 1312 is patterned to form a plurality of photoresist mandrels separated from each other by openings. For ease of illustration, only two openings 1402a, 1402b are shown. The patterned photoresist top layer 1312 is used as a mask to transfer the pattern (i.e., openings 1402a, 1402b) in the photoresist top layer 1312 to the intermediate layer 1310, the bottom layer 1308, and the mask layer 1304. The openings 1402a, 1402b define the isolation trenches to be formed in the substrate portions of the fin structures 102b, 102c. The isolation trenches may be disposed between adjacent active regions. The term "active region" refers to the region where transistors are formed. As will be discussed in more detail below, the isolation trenches may be formed by performing a fin cutting (or slice cutting) process. The isolation trenches are then filled with a dielectric to form a continuous polysilicon on diffusion edge (CPODE) trench. This fin cutting (or sheet cutting) process may be referred to as a CPODE process. The term "diffusion edge" is equivalently referred to as an active edge, which is an edge that abuts adjacent active areas. The CPODE process may be used to reduce gate pitch, thereby increasing the density of multi-gate devices, thereby improving device performance required for aggressive scaling of circuits and devices.

[0045] exist Fig.15A and Fig. 15B In the process, the photoresist top layer 1312 ( Fig.14A and Fig. 14B) in the pattern (i.e., openings 1402a, 1402b) are transferred to the mask layer 1304 to form a patterned mask layer 1304'. The bottom layer 1308, the middle layer 1310, and the photoresist top layer 1312 are then removed. The formation of the patterned mask layer 1304' can be achieved by one or more photolithography processes. As a result of the one or more photolithography processes, a portion of the hard mask 1304 is removed, and groove patterns 1402a', 1402b' (collectively referred to as groove patterns 1402') are formed in the patterned mask layer 1304', and a portion of the sacrificial gate electrode layer 134 is exposed. The groove patterns 1402a', 1402b' are elongated openings aligned with the sacrificial gate structure 130. Removal of portions of the hard mask 1304 (and the native oxide formed thereon) can be performed using etching chemicals such as CF4, CHF3, CH2F2, CHF3, and C4F6. The patterned mask layer 1304 ′ may then be used to protect the active area during subsequent removal of the exposed sacrificial gate structure and fin cutting (or slice cutting) processes.

[0046] exist Fig.16A and Fig. 16B , the exposed sacrificial gate structure (e.g., sacrificial gate electrode layer 134) is selectively removed to form openings 1602a, 1602b (collectively referred to as openings 1602). The openings 1602 expose the gate spacers 138 and the liner 109. The removal of the exposed sacrificial gate structure can be performed by a selective etching process that removes the sacrificial gate electrode layer 134 but does not substantially affect the gate spacers 138 and the liner 109. The liner 109 protects the first semiconductor layer 106 and the second semiconductor layer 108 during the etch-back process. In some embodiments, the liner 109 can also be removed during the selective etching process. In some embodiments, the etching chemistry is selective to the sacrificial gate structure to be etched while minimizing the etching of the surrounding dielectric layers (e.g., insulating material 118, gate spacers 138, CESL 162, and first ILD layer 164). In some embodiments, the sacrificial gate structure 130 may be removed using a chlorine-containing gas (e.g., SiCl4, BCl3, Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof.

[0047] exist Fig.17A and Fig. 17B In the embodiment of the present invention, an etching process is performed to remove the liner 109. The etching process may be dry etching, wet etching, or a combination thereof. The etching process selectively removes the liner 109 without affecting the first semiconductor layer 106 and the second semiconductor layer 108 and the sacrificial gate electrode layer 134.

[0048] Fig.18A and FIG. 18B to FIG. 21A and Fig. 21B The process of extending the opening 1602 into the substrate portion of the fin structures 102b, 102c to form the isolation trench is shown. In particular, the isolation trench (and thus the subsequent CPODE structure) is formed to have a straight and symmetrical sidewall profile to facilitate backside power rail applications. Fig.18A and Fig.18B In the embodiment, a first semiconductor etching process 141 is performed to remove the first semiconductor layer 106 and the second semiconductor layer 108, thereby forming a first portion of the isolation trench 1802. The first semiconductor etching process 141 is a fin cutting (or slice cutting) process. The first semiconductor etching process 141 is performed using the patterned and shifted mask layer 1304' as an etching mask. The first semiconductor etching process 141 can be dry etching, reactive ion etching (RIE) and / or other suitable processes. The first semiconductor etching process 141 is performed so that the exposed first semiconductor layer 106, the second semiconductor layer 108 and the portion of the substrate 101 forming the fin structure 102b, 102c are selectively removed. A portion of the insulating material 118 around the fin structure 102b, 102c can also be removed. In some embodiments, a self-aligned CPODE etching process is used to achieve the removal of the exposed first semiconductor layer 106, the second semiconductor layer 108 and the portion of the substrate 101. The self-aligned CPODE etching process is configured to have a high etching selectivity such that the etching rate of the first semiconductor layer 106 and the second semiconductor layer 108 is greater than the etching rate of the inner spacer 144. As a result, the inner spacer 144 remains substantially intact after the fin cutting process.

[0049] As a result of the first semiconductor etching process 141, isolation trenches 1802a, 1802b (collectively referred to as isolation trenches 1802) are formed and extend into portions of the substrate 101 where the fin structures 102b, 102c are formed ( Fig.17A). In various embodiments, the first semiconductor etching process 141 is performed so that the first portion of the isolation trenches 1802a, 1802b is formed with a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the corresponding isolation trenches 1802a, 1802b in the depth direction of the isolation trenches 1802a, 1802b. In some embodiments, the isolation trenches 1802a, 1802b may have a first depth D1, which is defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b. The first depth D1 may be selected according to the desired level of the narrowest CD. In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is at substantially the same height as the bottom of the epitaxial S / D feature 146. In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is lower than the top surface of the well portion of the substrate 101. In some embodiments, first depth D1 is in a range between about 30 nm and about 100 nm, which may vary depending on the height of epitaxial S / D features 146. In some embodiments, first depth D1 should be substantially equal to the height of the epitaxial S / D features. In some embodiments, a ratio of first depth D1 to height H1 of semiconductor layer stack 104 may be in a range between about 1.1 and about 1.5.

[0050] The self-aligned CPODE etching process can be achieved by plasma etching using bromine-based etching chemicals and oxygen-based chemicals. Exemplary bromine-based etching chemicals may include but are not limited to HBr, Br2, BBr3, etc. or a combination thereof. Exemplary oxygen-based etching chemicals may include but are not limited to O2, CO2, O3, water vapor, etc. or a combination thereof. In some embodiments, plasma etching is a high-density plasma process chamber using ICP (inductively coupled plasma) or a dipole antenna plasma source. In some embodiments, a resonant antenna plasma source or an electron cyclotron resonance (ECR) plasma source may also be used to achieve low-pressure operation (e.g., about 0.2 ± 0.05 mTorr). Plasma can be driven by an RF power generator using an AC current operating at a frequency of multiples of 13.56 MHz. The process chamber can operate at a pressure in the range of about 0.2 mTorr to about 150 mTorr and at a temperature of about 20 degrees Celsius to about 120 degrees Celsius. The RF power generator is operated to provide a source power between about 100 W and about 2500 W. A bias voltage operating in the range of about 0 W to about 2500 W may be applied to a substrate pedestal in a process chamber. In some cases, pulsed plasma etching may be used. In this case, the output of the power generator may be controlled by a pulse signal with a duty cycle in the range of about 5% to 95%. Alternatively, the self-aligned CPODE etching process may use only a bias voltage (with zero source power) to enhance etching directionality.

[0051] Although bromine-based etching chemicals are discussed, other etching chemicals may also be used, such as chlorine-based etching chemicals or fluorine-based etching chemicals. Exemplary chlorine-based etching chemicals may include, but are not limited to, Cl2, CHCl3, CCl4, BCl3, etc. or combinations thereof. Exemplary fluorine-containing gases may include, but are not limited to, CF4, SF6, CH2F2, C2H4F2, CHF3, C2F6, etc. or combinations thereof. Alternatively, the etchant used in the first semiconductor etching process 141 may be a chlorine-based / bromine-based etching chemical, a fluorine-based / chlorine-based etching chemical, a fluorine-based / bromine-based etching chemical, or any combination thereof.

[0052] In some embodiments, plasma etching may be performed in a plasma etching chamber with in-situ ALD capability to form silicon oxide or silicon nitride so that a passivation layer with adequate protection may be formed in subsequent operations.

[0053] exist Fig.19A and Fig.19BIn the embodiment, the passivation layer 143 is formed on the exposed surfaces of the isolation trenches 1802a, 1802b, such as the sidewalls 1802s and the bottom surface 1802bs1 of the isolation trench 1802. The passivation layer 143 is configured to reduce the etching selectivity of the exposed surfaces of the isolation trenches 1802a, 1802b to the etchant used in the subsequent etching process, such as Fig. 20A and Fig. 20B Thus, although the etchant may still remove a portion of the passivation layer 143, the passivation layer 143 and the underlying silicon substrate at the bottom surface 1802bs1 of the isolation trench 1802 are removed at a faster rate (due to the bias voltage on the substrate support) than the passivation layer 143 on the sidewalls 1802s of the isolation trench 1802.

[0054] Unlike conventional methods (conventional methods modify the selectivity of an etching recipe (e.g., using a high-selectivity etching recipe) to form isolation trenches according to the material to be etched), the passivation layer 143 is configured to reduce the etching selectivity of the exposed surfaces of the isolation trenches 1802a, 1802b to the etchant used in the subsequent etching process, e.g. Fig. 20A and Fig. 20B Thus, while the etchant may still remove a portion of the passivation layer 143, the passivation layer 143 and the underlying silicon substrate at the bottom surface 1802bs1 of the isolation trench 1802 are removed at a faster rate (due to the bias voltage to the substrate support) than the passivation layer 143 on the sidewalls 1802s of the isolation trench 180. In this way, the etchant (e.g., as described below with respect to Fig. 20A and Fig. 20B The discussed penetration etching process 145) minimizes the impact on the sidewalls of the isolation trenches, making it a low selectivity etching process. Therefore, the isolation trenches 1802a, 1802b can extend vertically with a straight and symmetrical sidewall profile without a bowing phenomenon, which may otherwise occur if a high selectivity etching recipe is used to remove the passivation layer or an excessively thick passivation layer (e.g., about 6nm or more), and thus produce an over-etching effect on the lower portion of the isolation trenches 1802a, 1802b and / or the substrate 101 adjacent to the bottom of the isolation trenches 1802a, 1802b. When the isolation trench has a curved profile, the adjacent epitaxial source / drain feature 146 may be damaged, and the subsequent backside contact may contact the end of the isolation trench, which in turn increases the resistance of the backside contact of the source / drain feature. In addition, the risk of blocking the subsequent backside contact etching increases.

[0055] The passivation layer 143 may be a dielectric material or an oxide-based passivation layer, such as an amorphous SiO, SiO2, SiON, SiN or Si x Ny (the ratio of y / x can be between 1 and 2) etc. or any combination thereof. In some embodiments, the passivation layer 143 is formed to have a porous film property (e.g., amorphous). In some embodiments, the passivation layer 143 can be formed by exposing the exposed surfaces of the isolation trenches 1802a, 1802b to a plasma having a gas mixture containing a silicon-containing precursor (e.g., SiCl4) and an oxygen-containing precursor (e.g., O2). Precursors of the silicon-containing precursor and the oxygen-containing precursor can flow into the process chamber simultaneously or sequentially. In some embodiments, a hydrogen halide (e.g., hydrogen bromide (HBr)) can flow with the silicon-containing precursor and the oxygen-containing precursor. In some embodiments, the passivation layer 143 may contain impurities from the precursor, such as Br and / or H. In various embodiments, the passivation layer 143 may have an atomic percentage of impurities of about 30 at.% to about 70 at.%, for example, about 45 at.% to about 60 at.%. In one embodiment, the passivation layer 143 is bromine-containing silicon monoxide (SiO) or SiO2. In this case, a gas mixture including SiCl4, HBr, O2 may be used. Additionally or alternatively, the gas mixture may contain SiCl4, HBr, SiO (sulfur dioxide), and CO2 precursors. In another embodiment, the passivation layer 143 is hydrogenated SiO or SiON.

[0056] In some embodiments, the passivation layer 143 is deposited by an in-situ ALD process in the same chamber as the plasma etching process used for the first semiconductor etching process 141. For example, the in-situ ALD technique uses precursors such as DIPAS (di(isopropylamino)silane) and BTBAS (bis(tert-butylamino)silane) in combination with Ar or O2 plasma treatment to form a silicon-containing film. For example, the passivation layer 143 can be formed by supplying a silicon-containing source gas such as DIPAS or BTBAS to a process chamber, and supplying a plasma of a reactive gas such as an oxygen-containing gas or a nitrogen-containing gas to the process chamber. Free radicals from the plasma of the reactive gas oxidize or nitride substances derived from the silicon-containing source gas to form a silicon-containing film.

[0057] The etching resistivity of the passivation layer 143 can be controlled by adjusting the thickness of the precursor, the film density, the plasma power, the temperature, the pressure or the composition or any combination thereof. In some embodiments, the lower etching resistivity of the passivation layer 143 is achieved by reducing the deposition time or the plasma power, or increasing the temperature, thereby obtaining a thinner passivation layer. In some embodiments, the passivation layer 143 can have a thickness between about 0.5 nm and about 5 nm. In some embodiments, the passivation layer 143 can be formed to have enhanced plasma dissociation to achieve different film densities. In some embodiments, the passivation layer 143 can be a density of about 2.648 g / cm 3 and about 4.0g / cm 3Silicon oxide in the range between.

[0058] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, a breakthrough etching process 145 is performed to remove the passivation layer 143 from the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b. The breakthrough etching process 145 may be directional (anisotropic) so as to remove the passivation layer 143 from the horizontal surface of the semiconductor device structure 100. The removal of the passivation layer 143 reveals the bottom surface 1802bs1 of the isolation trench 1802, or in other words, exposes a limited area of ​​the substrate portion forming the fin structure 102b, 102c. In some embodiments, the passivation layer 143 may remain on the sidewalls 1802s of the sacrificial gate electrode layer 134 and a portion of the insulating material 118. Since the passivation layer 143 remaining on the sidewalls 1802s of the isolation trench 1802 blocks the etchant from laterally expanding the isolation trench 1801, the etchant in the subsequent second semiconductor etching process 147 is confined to a limited area of ​​the substrate portion forming the fin structure 102b, 102c. As a result, the isolation trench 1802 is formed to have a straight and symmetrical sidewall profile along the depth direction of the isolation trench 1802 .

[0059] The penetration etching process 145 may use a CH and / or CF-based chemical, such as CF4, CHF3, CH2F2, C4F6, etc. or any combination thereof. In some embodiments, where the passivation layer 143 includes bromine-containing SiO, a low selectivity etchant (e.g., CF4, C4F6, CHF3) may be used for a highly directional penetration etching process to remove the passivation layer 143 from the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b. A bias voltage (to a pedestal on which the semiconductor device structure 100 is disposed) may be provided during the penetration etching process 145 to achieve anisotropic etching. The use of a bias voltage also compensates for the etching selectivity required to remove the substrate portion of the insulating material 118 and the fin structures 102b, 102c. Higher directionality may be achieved by adding a bias voltage to a substrate pedestal in a process chamber and / or using a lower frequency for the bias power. In some embodiments, a bias voltage used during the breakthrough etching process 145 is greater than a bias voltage of the first semiconductor etching process 141 , and a bias power frequency used during the breakthrough etching process 145 is lower than a bias power frequency of the first semiconductor etching process 141 .

[0060] An exemplary through-etching process 145 for removing a portion of the passivation layer 143 may utilize a CCP, ICP, or GDP source driven by an RF power generator, or use a microwave plasma source with a frequency ranging from about 2 MHz to about 2.45 GHz (e.g., about 13.56 MHz). The process chamber may operate at a pressure in the range of about 0.2 mTorr to about 20 Torr and a temperature of about -80 degrees Celsius to about 240 degrees Celsius. The RF power generator is operated to provide a source power between about 100 W and about 1000 W, and the output of the RF power generator is controlled by an optional pulse signal having a duty cycle in the range of about 10% to about 90%. The substrate pedestal on which the semiconductor device structure 100 is disposed may be biased relative to the plasma in the range of about 100 W to about 1000 W.

[0061] After the breakthrough etching process 145 , the passivation layer 143 is removed from the bottom surface 1802bs1 of the isolation trenches 1802a , 1802b , while a portion of the passivation layer 143 remains on the sidewalls 1802s of the isolation trenches 1802a , 1802b .

[0062] In some embodiments, the breakthrough etching process 145 is performed in the same chamber as the process chamber used to deposit the passivation layer 143 and perform the first semiconductor etching process 141. In some embodiments, the process chamber is an ALD chamber.

[0063] exist Fig.21A and Fig. 21BIn the embodiment of the present invention, a second semiconductor etching process 147 is performed to further remove the substrate portion forming the fin structures 102b, 102c. The second semiconductor etching process 147 also removes the passivation layer 143 remaining on the sidewalls of the isolation trenches 1802a, 1802b. Similarly, the second semiconductor etching process 147 is performed so that the second portions of the isolation trenches 1802a, 1802b are formed to have straight and symmetrical sidewall profiles relative to an imaginary line passing through the center of the corresponding isolation trenches 1802a, 1802b in the depth direction of the isolation trenches 1802a, 1802b. In some embodiments, the second portions of the isolation trenches 1802a, 1802b are formed in a tapered manner with minimal or no curved profile. The term "bend" refers to a hole within the isolation trench 1802a, 1802 having a diameter that is larger than the diameter of the trench pattern 1402a', 1402b', which may otherwise occur if ions are asymmetrically scattered in a very narrow etched space of the isolation trenches 1802a, 1802b and / or an overly thick passivation layer is used (as described previously). The bend profile and position can be controlled by adjusting the time ratio of the passivation, semiconductor etching, and penetration steps. Less passivation but more penetration and semiconductor etching can result in a less bend profile but a wider etched trench, resulting in a higher risk of source or drain damage. As will be discussed in more detail below (e.g., Figures 18A-22G ), a favorable etch profile of the CPODE / CMODE trench for backside power rail applications should have a triangular, square, or trapezoidal shape, which can minimize the risk of blocking the backside contact etch. Isolation trenches 1802a, 1802b with straight and symmetrical sidewall profiles are beneficial because they are less likely to interfere with backside contact vias for epitaxial source / drain features 146 (e.g., source features), thereby facilitating backside power rail applications.

[0064] The second semiconductor etching process 147 can be performed using etching chemicals similar to the first semiconductor etching process 141. The second semiconductor etching process 147 can be implemented by plasma etching including HBr (sometimes with BCl3 added). In some cases, BCl3 can be used to adjust the selectivity of Si relative to silicon oxide, which can be the main component of the passivation layer. In some embodiments, a non-bend etching profile can be achieved by carefully controlling the ratio of HBr and BCl3. In some embodiments, a non-bend profile can also be achieved using etching conditions with low pressure (e.g., less than about 50mTorr). In some embodiments, O2 and / or CO2 can be added to the HBr-based plasma to promote the dissociation of plasma byproducts. In some embodiments, the plasma etching process can be a high-density plasma process with conditions similar to the first semiconductor etching process 141. In some embodiments, the second semiconductor etching process 147 is performed to extend the isolation trenches 1802a, 1802b into the substrate portion of the fin structure 102b, 102c to a depth below the sacrificial layer 107. The extended isolation trenches 1802a, 1802b have a second depth D2 measured from the topmost first semiconductor layer 106 to the bottom surface 1802bs2 of the isolation trenches 1802a, 1802b. In other words, the depth of each isolation trench 1802a, 1802b extends from the first depth D1 to the second depth D2. In some embodiments, the bottom surface 1802bs2 of the isolation trenches 1802a, 1802b may be at a height of the accumulation region entering the substrate 101. The term "accumulation region" refers to a non-conductive region in the substrate 101, which is below the depletion region (a conductive region located at / near the well portion of the substrate 101). In any case, the second depth D2 is sufficient to block the path of the leakage current through the epitaxial source / drain features and the silicon substrate. In some embodiments, the second depth D2 may be in a range between about 60nm and about 200nm. In some embodiments, the ratio of the second depth D2 to the height H1 of the semiconductor layer stack 104 may be in a range between about 1.2 and about 4.0.

[0065] like Fig.21AAs shown, the isolation trenches 1802a, 1802b have a substantially uniform critical dimension (CD) from top to bottom. In some embodiments, the first portion of the isolation trenches 1802a, 1802b located at or near the topmost first semiconductor layer 106 has a first CD (CD1), the middle portion of the isolation trenches 1802a, 1802b located at or near the bottom of the epitaxial source / drain feature 146 has a second CD (CD2), and the second portion of the isolation trenches 1802a, 1802b located at or near the bottom of the isolation trenches 1802a, 1802b has a third CD (CD3). In some embodiments, CD1, CD2, and CD3 are substantially the same. In some embodiments, CD1, CD2, and CD3 are slightly different from each other. For example, CD1 can be slightly larger than CD3, and CD3 can be slightly larger than CD2. CD1, CD2, and CD3 discussed herein are applicable to both thin wafers and thick wafers. In some embodiments, the bottom of the isolation trenches 1802a, 1802b below the sacrificial layer 107 may have a tapered shape.

[0066] An isolation trench 1802 having a uniform CD along the depth direction can be obtained by multi-cycle operation. In some alternative embodiments, Fig.18A and FIG. 18B to FIG. 21A and Fig. 21B The process in the embodiment can be repeated for two or more cycles, so that the isolation trenches 1802a, 1802b are formed with uniform CD along the depth direction. That is, CD1, CD2 and CD3 in the isolation trenches 1802a, 1802b are substantially the same from top to bottom. Fig.18A and FIG. 18B to FIG. 21A and Fig. 21B The process is continued until the isolation trench 1802 reaches a predetermined depth.

[0067] Figure 22A-22G An exemplary cyclic etching process for forming the isolation trench 2802 according to some embodiments is shown. For simplicity, Figure 22A-22G Only an incomplete portion of the semiconductor device structure 100 is shown. Fig.22A In the embodiment, a first etching process 2141 (e.g., a first semiconductor etching process 141) is performed to form an isolation trench 2802 (e.g., isolation trench 1802) into a substrate portion 2102 of a fin structure (e.g., fin structure 102b). The isolation trench 2802 may have a first depth D3 measured from a top of the isolation trench 2802 to a bottom of the isolation trench 2802. Fig. 22BIn the embodiment, a first passivation layer 2143 (eg, passivation layer 143) is formed on the sidewalls 2802s and the bottom surface 2802bs1 of the isolation trench 2802. Fig. 22C In the embodiment, a first through etching process 2145 (eg, through etching process 145) is performed to remove a portion of the first passivation layer 2143 from the bottom surface 2802bs1 of the isolation trench 2802. The removal of the first passivation layer 2143 reveals the bottom surface 2802bs1 of the isolation trench 2802. Fig.22D In the embodiment, a second etching process 2147 (e.g., a second semiconductor etching process 147) is performed to remove the remaining first passivation layer 2143 while extending the depth of the isolation trench 2802 from the first depth D3 to the second depth D4. The extended bottom surface 2802bs2 is at a height lower than the bottom surface 2802bs1. Fig.22E In the embodiment, a second passivation layer 2149 (eg, passivation layer 143) is formed on the exposed surface of the isolation trench 2802. Fig.22F In the embodiment, a second through etching process 2151 (eg, through etching process 145) is performed to remove a portion of the second passivation layer 2149 from the extended bottom surface 2802bs2 of the isolation trench 2802. The removal of the second passivation layer 2149 reveals the extended bottom surface 2802bs2 of the isolation trench 2802. Figure 22G , a third etching process 2153 (e.g., the first semiconductor etching process 141) is performed to remove the remaining second passivation layer 2149 while extending the depth of the isolation trench 2802 from the second depth D4 to the third depth D5. The extended bottom surface 2802bs3 is at a height lower than the bottom surface 2802b. A bias voltage (to a base on which the semiconductor device structure 100 is disposed) may be provided during the first etching process 2141, the first penetration etching process 2145, and the second etching process 2147 to achieve anisotropic etching with higher directionality. Figures 22A-22G The process described in can be repeated until the isolation trench 2802 reaches a predetermined depth.

[0068] In some embodiments, the first etching process 2141 may be performed for a first time period (T1), and the first penetration etching process 2145 may be performed for a second time period (T2), and the ratio of T1:T2 may be about 0.7:1 to about 6:1. In most cases, the first penetration time (T2) should be similar to or less than the main etching time (e.g., the first etching process). The cyclic process may be repeated, for example, for 2 to 5 cycles.

[0069] exist Fig.23A and Fig. 23B , the isolation trench 1802 is filled with a dielectric material 2130 ( Fig.21A and Fig. 21BIn some embodiments, dielectric liner 2132 may be disposed between dielectric material 2130 and exposed surfaces of isolation trench 1802. Fig.21A and Fig. 21B The dielectric material 2130 and dielectric liner 2132 in the isolation trenches 1802a, 1802b shown form an isolation trench structure (so-called CPODE trench) 2134. The dielectric material 2130 and dielectric liner 2132 can be made of the following materials: oxygen-containing materials, such as silicon oxide (SiO2); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-K dielectric materials; or any suitable dielectric material. The dielectric material 2130 may include a material that is chemically different from the dielectric liner 2132 and may be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD processes.

[0070] exist Fig.24A and Fig. 24B Once the isolation trench 1802 is filled, a planarization process, such as a CMP process, may be performed to remove portions of the dielectric material formed on the patterned mask layer 1304'. The planarization process may be performed until a portion of the cap layer 139 or the sacrificial gate electrode layer is exposed.

[0071] exist Fig.25A and Fig.25B , the sacrificial gate structure 130, the liner 109, and the second semiconductor layer 108 are removed. The exposed dielectric liner 2132 on the sidewalls of the dielectric material 2130 may also be removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening 166 between the first semiconductor layer 106. The cap layer 139, the CESL 162, and the first ILD layer 164 protect the epitaxial source / drain features 146 during the removal process. The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134 and the liner 109, but the gate spacer 138, the isolation trench structure 2134, the first ILD layer 164, and the CESL 162 are not removed. After removing the sacrificial gate structure 130, the first semiconductor layer 106 and the inner spacer 144 are exposed to the opening 166.

[0072] exist Fig.26A and Fig.26B, a replacement gate structure 190 is formed. The replacement gate structures 190 may each include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interfacial layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178 may also be formed on the exposed surfaces of the substrate 101, the insulating material 118, and the dielectric layer 2132. The IL 178 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.) and / or a dielectric layer (e.g., hafnium silicate) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106, or may be made of these materials. Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the IL (if any), the sidewalls of the gate spacer 138, the top surface of the first ILD layer 164, the CESL 162, and the cap layer 139). The gate dielectric layer 180 may be formed of a material that is chemically different from the material of the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material. The gate dielectric layer 180 may be a conformal layer formed by a conformal process, such as an ALD process, a PECVD process, a molecular beam deposition (MBD) process, or the like, or a combination thereof.

[0073] After forming the IL (if any) and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer. The gate electrode layer 182 fills the opening 166 ( Fig.25A ), and surrounds a portion of each first semiconductor layer 106. The gate electrode layer 182 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be conformally (and if more than one, sequentially) deposited between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers can include one or more barrier layers and / or capping layers and one or more work function tuning layers. One or more barrier and / or capping layers may include or be: nitrides, silicon nitrides, carbonitrides, and / or aluminum nitrides of tantalum and / or titanium; nitrides, carbonitrides, and / or carbides of tungsten; etc. or combinations thereof. One or more work function tuning layers may include or be: nitrides, silicon nitrides, carbonitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides of titanium and / or tantalum; nitrides, carbonitrides, and / or carbides of tungsten; cobalt; platinum; etc. or combinations thereof.

[0074] Portions of the gate electrode layer 182, the one or more optional conformal layers (if any), and the gate dielectric layer 180 that are higher than the top surfaces of the first ILD layer 164, the CESL 162, the cap layer 139 (if any), and the gate spacers 138 can be removed by a planarization process (e.g., a CMP process). After the CMP process, the top surfaces of the isolation trench structure 2134, the first ILD layer 164, the CESL 162, the gate spacers 138, and the gate electrode layer 182 are substantially coplanar.

[0075] exist Fig.27A and Fig.27B , a first etch stop layer 192 and a second ILD layer 194 are sequentially formed on the semiconductor device structure 100. The first etch stop layer 192 and the second ILD layer 194 may include the same materials as the CESL 162 and the first ILD layer 164, respectively, and may be formed in a similar manner as described above.

[0076] exist Fig.28A and Fig.28B In the embodiment of the present invention, one or more etching processes are performed to remove the second ILD layer 194, the first etch stop layer 192, and portions of the first ILD layer 164. In some embodiments, the one or more etching processes may also partially or completely remove the CESL 162. As a result of the removal process, openings 196 are formed. Each opening 196 may be an elongated opening and is arranged to align with a corresponding epitaxial S / D feature 146. The openings 196 expose the top surface of the epitaxial S / D feature 146. The openings 196 will be filled with a conductive material and form metal contacts for the epitaxial S / D features 146.

[0077] In some embodiments, after forming the opening 196 , a liner 175 is optionally formed on the exposed sidewall surfaces of the first etch stop layer 192 , the second ILD layer 194 , and the CESL 162 . Figure 28A-1 According to some embodiments Fig.28A 1. An enlarged view of a portion of the semiconductor device structure 100 is shown. The liner 175 may be formed of a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the liner 175 includes the same material as the CESL 162. Although not shown, it is contemplated that this embodiment may be equally applicable to any one or more of the embodiments shown in the present disclosure.

[0078] exist Fig.29A and Fig.29B, the opening 196 is filled with a conductive material. The opening 196 is overfilled until a predetermined height above the first ILD layer 164 is reached. The conductive material can be made of a metal or a metal nitride, such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or a combination thereof. The conductive material can be deposited by any suitable process, such as PVD or electroplating. A silicide layer (not shown) is formed between the epitaxial source / drain features 146 and the conductive material. The silicide layer can be made of a metal or a metal alloy silicide, and the metal can include a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof.

[0079] Thereafter, a planarization operation, such as CMP, is performed until the top surface of the second ILD layer 194 is exposed. As a result of the planarization process, the conductive material in the openings 196 becomes source / drain contacts 195 b for corresponding epitaxial source / drain features 146 .

[0080] exist Fig. 30A and Fig. 30B , a second etch stop layer 197 and a third ILD layer 199 are sequentially formed on the semiconductor device structure 100. The second etch stop layer 197 and the third ILD layer 199 may include the same materials as the CESL 162 and the first ILD layer 164, respectively, and may be formed in a similar manner as described above. Thereafter, the second etch stop layer 197 and the third ILD layer 199 are patterned to form an opening 187. The opening 187 extends through the third ILD layer 199 and the etch stop layer 197 to expose the top surface of the source / source contact 195b for the epitaxial source / drain feature 146.

[0081] exist Fig.31A and Fig.31B In the embodiment of the present invention, the opening 187 is filled with a conductive material to form a contact via 189b. The contact via 189b is electrically connected to the epitaxial source / drain feature 146 through the source / drain contact 195b. The contact via 189b can be made of the same material as the source / drain contact 195b. The conductive material can be deposited by any suitable process, such as PVD or electroplating. Then, a planarization operation such as CMP is performed until the top surface of the third ILD layer 199 is exposed.

[0082] exist Fig.32A and Fig.32B, a third etch stop layer 165 and a fourth ILD layer 167 are sequentially formed on the semiconductor device structure 100. The third etch stop layer 165 and the fourth ILD layer 167 may include the same materials as the CESL 162 and the first ILD layer 164, respectively, and may be formed in a manner similar to that described above. Thereafter, the third etch stop layer 165 and the fourth ILD layer 167 are patterned to form openings (only one opening is shown). The opening extends through the fourth ILD layer 167, the third etch stop layer 165, the third ILD layer 199, the second etch stop layer 197, the second ILD layer 194, and the first etch stop layer 192 to expose the top surface of the gate electrode layer 182. The opening is then filled with a conductive material to form a gate contact 195a for the gate electrode layer 182. The gate contact 195a may be used as a contact via electrically connected to the gate electrode layer 182. Likewise, the conductive material may be made of a metal or metal nitride, such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or a combination thereof, and may be deposited by any suitable process, such as PVD or electroplating.

[0083] Although not shown, it is contemplated that a liner, such as liner 175 ( Figure 28A-1 ). The liner helps prevent metal diffusion or migration into adjacent dielectrics.

[0084] exist Fig.33A and Fig.33B In the embodiment of the present invention, a front side interconnect structure 171 is formed over the third ILD layer 199 and the contact via 189b. The front side interconnect structure 171 may be a back end of line (BEOL) interconnect structure including one or more layers of dielectric material having a plurality of metal lines (not shown) and vias (not shown) embedded therein. The metal lines and vias in the front side interconnect structure 171 may be formed of copper, copper alloys, or any suitable conductive material using one or more damascene processes. The metal lines and vias provide electrical paths to features such as the epitaxial S / D features 146. In some embodiments, the front side interconnect structure 171 includes metal lines and vias for connecting only signal lines but not to power rails or connectors connected to power rails. In some embodiments, the front side interconnect structure 171 includes a portion of a power rail. The power rail includes a conductor connected between the epitaxial S / D features 146 and a power source, such as VDD and VSS (GND).

[0085] After forming the front side interconnect structure 171, the semiconductor device structure 100 is temporarily bonded to a carrier substrate 173. The carrier substrate 173 is used to provide mechanical support for the semiconductor device structure 100 to facilitate back side processing of the substrate 101.

[0086] exist Fig.34A and Fig.34B , the semiconductor device structure 100 is flipped over so that the substrate 101 is located above the epitaxial S / D features 146 as shown.

[0087] exist Fig.35A and Fig.35B In the process, backside grinding is performed to remove portions of substrate 101 and insulating material 118 until sacrificial layer 107 is exposed. In some embodiments, sacrificial layer 107 is also removed during backside grinding.

[0088] exist Fig.36A and Fig.36B In the embodiment, a mask structure 3602 is formed on the top surface of the trimmed substrate 101, the dielectric material 2130 and the dielectric liner 2132, for example Fig.13A and Fig. 13B 3602. The mask structure 3602 may include a hard mask 3604 and a resist layer 3606, such as a three-layer photoresist. The exemplary three-layer photoresist may include a bottom layer 3608, an intermediate layer 3610 disposed on the bottom layer 3608, and a photoresist top layer 3612 disposed on the intermediate layer 3612. The photoresist top layer 3612 is then patterned to form a plurality of openings 3602a, 3062b (only two openings are shown). The openings 3602a, 3602b are aligned with the center of the corresponding epitaxial source / drain features 146. In some embodiments, the openings 3602a, 3602b are aligned with the epitaxial S / D features 146 at the source region (i.e., the source terminal). In various embodiments, the openings 3602a, 3602b are aligned with the corresponding source terminals disposed adjacent to the isolation trench structure (i.e., the CPODE trench) 2134.

[0089] exist Fig.37A and Fig.37B 36, the patterned photoresist top layer 3612 is used as a mask to transfer the pattern in the photoresist top layer 3612 (i.e., the openings 3602a, 3602b) into the intermediate layer 3610, the bottom layer 3608, and the mask layer 3604. The openings 3602a, 3602b extend to expose the bottom surface of the epitaxial source / drain features 146, such as the source features disposed proximate to the isolation trench structures 2134. The resist layer 3606 is then removed.

[0090] exist Fig.38A and Fig.38B, the openings 3602a, 3602b are filled with a conductive material 179. The conductive material may be a metal or a metal nitride, such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or a combination thereof, and may be formed by any suitable process, such as PVD or electroplating. Although not shown, in some embodiments, a liner, such as a liner 175 ( Figure 28A-1 ) to avoid metal diffusion or migration into adjacent dielectrics.

[0091] exist Fig.39A and Fig.39B In the process, a planarization operation, such as CMP, is performed on the conductive material 179. The CMP can continue until the substrate 101 is exposed. After CMP, the bottom surfaces of the substrate 101, the dielectric material 2130, the dielectric liner 2132, and the conductive material 179 are substantially coplanar. The remaining conductive material serves as the backside via contact 181 of the corresponding epitaxial source / drain features 146. Fig.39A In one exemplary embodiment shown, the backside via contact 181 contacts the source terminal disposed proximate to the isolation trench structure 2134 .

[0092] A fourth ILD layer 183 may be formed on the back side of the semiconductor device structure 100. The fourth ILD layer 183 contacts the bottom surface of the substrate 101, the dielectric material 2130, the dielectric liner 2132, and the backside via contact 181, which are at substantially the same height. One or more conductive features 185 (only one is shown) are then formed in the fourth ILD layer 183. The conductive feature 185 is electrically connected to the front side source / drain contact 195b through the backside via contact 181 and the epitaxial S / D feature 146 (e.g., the epitaxial S / D feature 146 at the source region). The conductive feature 185 electrically connects the backside via contact 181 to a power rail (not shown) to be connected to the power supply 161. Depending on the conductivity type of the device, the power supply 161 can be fed with a positive voltage (VDD) or a negative voltage (VSS) (i.e., ground voltage or zero voltage). Connecting the backside via contact 181 to the power rail at the backside of the semiconductor device structure 100 allows the device to be powered directly by the backside power supply, thereby enhancing device performance, saving the amount of routing resources used on the front side of the device, and reducing BEOL process complexity without abnormal electrical misconnection issues.

[0093] exist Fig.40A and Fig.40B, removing the carrier substrate 173. The semiconductor device structure 100 may undergo further complementary metal oxide semiconductor (CMOS) and / or back end of line (BEOL) processes on the back side and / or the front side to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0094] Above about Figures 18A-22G The discussed etching profile for controlling semiconductor etching (e.g., semiconductor etching, passivation, and penetration steps) allows the formation of an isolation trench (CPODE) structure having a straight and symmetrical sidewall profile (i.e., a non-curved CPODE profile) along the depth direction of the isolation trench 2134. Therefore, the isolation trench (CPODE) structure 2134 and the backside via contact 181 for the epitaxial source / drain feature 146 are arranged in a parallel relationship, which minimizes the risk of blocking the backside contact etching and thus facilitates the application of the backside power rail.

[0095] Figure 41A-41C According to some embodiments Fig.40A Schematic diagram of a region 400 of a semiconductor device structure 100 in FIG. 1 , which shows various arrangements of isolation trench (CPODE) structures 4134 (eg, isolation trench structures 2134 ) and backside via contacts 4181 (eg, backside via contacts 181 ). Fig.41A , each of the isolation trench structure 4134 and the backside via contact 4181 has a straight profile. The isolation trench structure 4134 and the backside via contact 4181 are arranged in parallel and are separated from each other by a constant gap "G" along the boundary of the isolation trench structure 413 and the backside via contact 4181. As shown in the figure, the first end of each of the backside via contact 4181 and the isolation trench structure 4134 and the second end of each of the isolation trench structure 413 and the backside via contact 4181 are at different heights.

[0096] Fig.41B Examples and Fig.41AThe embodiments of the present invention are substantially the same, except that each of the backside via contact 4181a and the isolation trench structure 4134a includes a trapezoidal portion. The isolation trench structure 4134a and the backside via contact 4181a are arranged in parallel and are separated from each other by a constant gap "G" along the boundary of the isolation trench structure 4134a and the backside via contact 4182a. In some embodiments, a first portion 4181-1 of the backside via contact 4181a that contacts the bottom of the source / drain feature (e.g., the epitaxial source / drain electrode feature 146) may have a first diameter, and a second portion 4181-2 of the backside via contact 4181a that is away from the bottom of the source / source feature may have a second diameter greater than the first diameter. For the thick wafer approach, the first portion 4181-1 may extend in the isolation region 4120 (highly doped region) from a first imaginary line (4146b) at the same height as the bottom of the source / drain feature (e.g., epitaxial source / drain electrode feature 146) to a first imaginary line (4146b) at the same height as the bottom of the isolation region 4120 (e.g., Fig.40B The second portion 4181-2 may be formed on the substrate 4101 (eg, Fig.40A In some embodiments, the second diameter of the second portion 4181 - 2 gradually increases in a direction away from the bottom 4120 b of the isolation region 4120 .

[0097] Likewise, the isolation trench structure 4134a has a first portion 4134-1 extending in the isolation region 4120 and a second portion 4134-2 extending in the well region of the substrate 4101 in a direction away from the bottom 4120b of the isolation region 4120. The first portion 4134-1 has a first diameter, and the second portion 4134-2 has a second diameter that is smaller than the first diameter. In some embodiments, the second diameter of the second portion 4134-2 is at a distance from the isolation region 4120 (e.g., Fig.40B The bottom surface 118b of the insulating material 118 is shown to be connected to the bottom of the substrate (eg, Fig.40AThe back surface 101b of the substrate 101 shown in the figure gradually decreases in the direction of an imaginary line 4101b at the same height, so that the upper side wall of the second part 4134-2 of the isolation trench structure 4134a (adjacent to the bottom 4120b of the isolation region 4122) and the bottom 4120b of the isolation region 4120 define an angle θ1 less than 90 degrees, and the lower side wall of the second part 4134-2 of the isolation trench structure 4134a (adjacent to the bottom of the substrate) and the bottom 4120b of the isolation region 4120 define an angle θ2 greater than 90 degrees. In some embodiments, the first portion 4181-1 of the back side via contact 4181a and the first portion 4134-1 of the isolation trench structure 4134a are configured to have a rectangular shape, and the second portion 4181-2 of the back side via contact 4181a and the second portion 4134-2 of the isolation trench structure 4134a are configured as two inverted trapezoids or inverted triangles, which may be a natural result of (one or more) etching processes when forming the isolation trench structure 413 and the back side via connector 4181a.

[0098] exist Fig.41C , the isolation trench structure 4134b and the backside via contact 4181b are arranged in parallel and are separated by a constant gap “G” along the boundary of the isolation trench structure 4134a and the backside via contact 4181a. Fig.41C Examples and Fig.41A The embodiments are substantially the same except that the backside via contact 4181b and the isolation trench structure 4134b have a gradient profile, which may be a natural result of the etching process(es) when forming the isolation trench structure 4134b and the backside via connector 4181b.

[0099] Fig.42A and Fig.42B is a cross-sectional view of a semiconductor device structure 100, which shows Fig.41B The illustrated embodiment arranges an isolation trench structure 2134 and a backside via contact 181. In some embodiments, the isolation trench structure 2134 has a gradient profile extending on an interface defined by the bottom 118b of the insulating material 118 and the substrate 101.

[0100] Embodiments of the present disclosure provide an improved etch profile control method for an isolation trench (e.g., CPODE) by forming a passivation layer on the sidewalls of the isolation trench to reduce the etch selectivity of the isolation trench to an etchant used during a directional through-etch process, allowing the isolation trench to be formed with a straight and symmetrical sidewall profile without a curved profile. The isolation trench is parallel to a backside via contact for an epitaxial source / drain feature to facilitate backside power rail applications.

[0101] A method for forming a semiconductor device structure is described. The method includes: removing a portion of a fin structure to form a first portion of an isolation trench in the fin structure; passivating an exposed surface of the first portion of the isolation trench to change the etching selectivity of the exposed surface to a first etchant; removing a portion of the passivated surface at the bottom of the first portion of the isolation trench using the first etchant; removing a portion of a substrate by a second etchant to form a second portion of the isolation trench; and filling the isolation trench with a dielectric material.

[0102] Another embodiment is a method for forming a semiconductor device structure. The method includes (1) forming a first fin structure and a second fin structure on a first side of a substrate, each of the first fin structure and the second fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. The method also includes (2) forming a source / drain feature between the first fin structure and the second fin structure and on the first side of the substrate; (3) removing portions of the plurality of first semiconductor layers and the plurality of second semiconductor layers from the first fin structure to form an isolation trench having a first depth; (4) forming a passivation layer on the sidewalls and bottom surface of the isolation trench; (5) removing the passivation layer from the bottom surface of the isolation trench to expose a portion of the substrate; (6) removing the passivation layer and the portion of the substrate to extend the isolation trench from the first depth to a second depth; (7) filling the isolation trench with a dielectric material; (8) removing the plurality of second semiconductor layers from the second fin structure; (9) surrounding each of the first semiconductor layers of the second fin structure with a gate electrode layer; (10) forming an opening from the second side of the substrate to expose the source / drain features; and (11) filling the opening with a conductive material to form a backside via contact for the source / drain features, wherein the isolation trench and the backside via contact are arranged in parallel and separated from each other by a constant gap along the boundary of the isolation trench and the backside via contact.

[0103] Another embodiment is a semiconductor device structure. The structure includes: a fin structure formed on a substrate; a source / drain feature adjacent to the fin structure and disposed above the substrate, wherein a top surface of the source / drain feature is substantially coplanar with a front side of the substrate. The structure also includes: an isolation trench extending from the front side of the substrate toward a back side of the substrate; and a backside via contact extending from the back side of the substrate and contacting the source / drain region, wherein the backside via contact and the isolation trench are arranged in parallel and separated from each other by a constant gap along a boundary of the backside via contact and the isolation trench.

[0104] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0105] Example 1 is a method for forming a semiconductor device structure, comprising: removing a portion of a fin structure to form a first portion of an isolation trench in the fin structure; passivating an exposed surface of the first portion of the isolation trench to change the etching selectivity of the exposed surface to a first etchant; removing a portion of the passivated surface at the bottom of the first portion of the isolation trench using the first etchant; removing a portion of the substrate by a second etchant to form a second portion of the isolation trench; and filling the isolation trench with a dielectric material.

[0106] Example 2 is the method of Example 1, wherein the etching selectivity of the exposed surface is changed by forming a passivation layer on the exposed surface of the first portion of the isolation trench.

[0107] Example 3 is the method of Example 2, wherein the passivation layer is formed by exposing an exposed surface of the first portion of the isolation trench to a gas mixture including a silicon-containing precursor and an oxygen-containing precursor.

[0108] Example 4 is the method described in Example 3, wherein the gas mixture also includes hydrogen halide.

[0109] Example 5 is the method of Example 4, wherein the passivation layer is an amorphous phase of bromine- or hydrogen-containing silicon monoxide, SiO2 or Si x N y .

[0110] Example 6 is the method of Example 1, wherein the first etchant includes a bromine-based etching chemistry and an oxygen-based chemistry.

[0111] Example 7 is the method of Example 6, wherein the first etchant and the second etchant are substantially the same.

[0112] Example 8 is the method described in Example 1, further comprising: applying a first bias voltage to the substrate base while removing a portion of the substrate; and applying a second bias voltage to the substrate base while removing a portion of the passivated surface, wherein the second bias voltage is greater than the first bias voltage.

[0113] Example 9 is the method of Example 1, wherein the first portion of the isolation trench has a first diameter, and the second portion of the isolation trench has a second diameter that is substantially the same as the first diameter.

[0114] Example 10 is a method for forming a semiconductor device structure, comprising: (1) forming a first fin structure and a second fin structure on a first side of a substrate, each of the first fin structure and the second fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; (2) forming a source / drain feature on the first side of the substrate between the first fin structure and the second fin structure; (3) removing portions of the plurality of first semiconductor layers and the plurality of second semiconductor layers from the first fin structure to form an isolation trench having a first depth; (4) forming a passivation layer on sidewalls and a bottom surface of the isolation trench; and (5) removing the passivation layer from the bottom surface of the isolation trench to expose a portion of the substrate. (6) removing the passivation layer and the portion of the substrate to extend the isolation trench from the first depth to the second depth; (7) filling the isolation trench with a dielectric material; (8) removing the plurality of second semiconductor layers from the second fin structure; (9) surrounding each of the first semiconductor layers of the second fin structure with a gate electrode layer; (10) forming an opening from the second side of the substrate to expose the source / drain feature; and (11) filling the opening with a conductive material to form a backside via contact for the source / drain feature, wherein the isolation trench and the backside via contact are arranged in parallel and are separated from each other by a constant gap along the boundary of the isolation trench and the backside via contact.

[0115] Example 11 is the method of Example 10, further comprising: after operation (6), repeating operations (4) to (6) until the isolation trench reaches a predetermined depth.

[0116] Example 12 is the method described in Example 10, further comprising: applying a first bias voltage to the substrate base during operation (3); and applying a second bias voltage to the substrate base during operation (5), wherein the second bias voltage is greater than the first bias voltage.

[0117] Example 13 is the method described in Example 12, further comprising: during operation (3), operating the first bias voltage at a first bias power frequency; and during operation (5), operating the second bias voltage at a second bias power frequency, wherein the second bias power frequency is lower than the first bias power frequency.

[0118] Example 14 is the method of Example 13, wherein the operation (3) is performed for a first time period, and the operation (5) is performed for a second time period greater than the first time period.

[0119] Example 15 is the method of Example 10, wherein operation (4) and operation (5) are performed in the same process chamber.

[0120] Example 16 is the method of Example 10, wherein the isolation trench is formed with a straight and symmetrical sidewall profile.

[0121] Example 17 is a semiconductor device structure comprising: a fin structure formed on a substrate; a source / drain feature adjacent to the fin structure and disposed above the substrate; an isolation trench extending from the front side of the substrate toward the back side of the substrate; and a back side via contact extending from the back side of the substrate and contacting the source / drain region, wherein the back side via contact and the isolation trench are arranged in parallel and are separated from each other by a constant gap along a boundary of the back side via contact and the isolation trench.

[0122] Example 18 is a semiconductor device structure described in Example 17, wherein the isolation trench includes a first portion having a first diameter and a second portion having a second diameter smaller than the first diameter, and wherein the back side via contact includes a first portion having a first diameter and a second portion having a second diameter smaller than the first diameter of the back side via contact.

[0123] Example 19 is the semiconductor device structure described in Example 17, further comprising: an interlayer dielectric disposed on the back side of the substrate, wherein the bottom surface of the isolation trench, the bottom surface of the back side via contact and the surface of the interlayer dielectric are substantially coplanar.

[0124] Example 20 is the semiconductor device structure of Example 18, wherein a bottom of the isolation trench has a gradient profile extending above an interface defined by the isolation region and the substrate.

Claims

1. A method for forming a semiconductor device structure, comprising: removing a portion of a fin structure to form a first portion of an isolation trench in the fin structure; passivating an exposed surface of a first portion of the isolation trench to change an etching selectivity of the exposed surface to a first etchant; removing a portion of the passivated surface at a bottom of a first portion of the isolation trench using the first etchant; removing a portion of the substrate by a second etchant to form a second portion of the isolation trench; as well as The isolation trenches are filled with a dielectric material.

2. The method according to claim 1, wherein: The etching selectivity of the exposed surface is changed by forming a passivation layer on the exposed surface of the first portion of the isolation trench.

3. The method according to claim 2, wherein: The passivation layer is formed by exposing an exposed surface of the first portion of the isolation trench to a gas mixture including a silicon-containing precursor and an oxygen-containing precursor.

4. The method according to claim 3, wherein: The gas mixture also includes a hydrogen halide.

5. The method according to claim 4, wherein: The passivation layer is an amorphous phase of bromine- or hydrogen-containing silicon monoxide, SiO2 or Si x N y .

6. The method according to claim 1, wherein: The first etchant includes a bromine-based etching chemistry and an oxygen-based chemistry.

7. The method according to claim 6, wherein: The first etchant and the second etchant are substantially the same.

8. The method according to claim 1, further comprising: applying a first bias voltage to the substrate pedestal while removing a portion of the substrate; as well as A second bias voltage is applied to the substrate pedestal while removing a portion of the passivated surface, wherein the second bias voltage is greater than the first bias voltage.

9. A method for forming a semiconductor device structure, comprising: (1) forming a first fin structure and a second fin structure on a first side of a substrate, each of the first fin structure and the second fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; (2) forming a source / drain feature on a first side of the substrate between the first fin structure and the second fin structure; (3) removing portions of the plurality of first semiconductor layers and the plurality of second semiconductor layers from the first fin structure to form an isolation trench having a first depth; (4) forming a passivation layer on the sidewalls and bottom surface of the isolation trench; (5) removing the passivation layer from the bottom surface of the isolation trench to expose a portion of the substrate; (6) removing the passivation layer and the portion of the substrate to extend the isolation trench from the first depth to a second depth; (7) filling the isolation trench with a dielectric material; (8) removing the plurality of second semiconductor layers from the second fin structure; (9) surrounding each of the first semiconductor layers of the second fin structure with a gate electrode layer; (10) forming an opening from the second side of the substrate to expose the source / drain features; as well as (11) Filling the opening with a conductive material to form a backside via contact for the source / drain feature, wherein the isolation trench and the backside via contact are arranged in parallel and separated from each other by a constant gap along a boundary of the isolation trench and the backside via contact.

10. A semiconductor device structure, comprising: a fin structure formed on a substrate; a source / drain feature disposed adjacent to the fin structure and above the substrate; an isolation trench extending from the front side of the substrate toward the back side of the substrate; as well as a backside via contact extending from the backside of the substrate and contacting the source / drain region, Wherein, the backside via contact and the isolation trench are arranged in parallel and are separated from each other by a constant gap along the boundary of the backside via contact and the isolation trench.

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