Semiconductor device structure and forming method thereof

Abstract

The invention relates to a semiconductor device structure and a forming method thereof. Embodiments of the present disclosure provide an etch process for forming high aspect ratio trenches (e.g., CPODE / CMODE trenches) without damaging adjacent structures (e.g., epitaxial source / drain features).

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device structure and a method for forming the same. Background Art

[0002] As the semiconductor industry advances to nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of multi-gate devices, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors. In order to continue to provide the desired scaling and increased density for multi-gate devices in advanced technology nodes, the gate pitch needs to continue to decrease.

[0003] Device layouts may employ polysilicon (poly) segments formed as diffusion edges (PODE) or continuous polysilicon on diffusion edges (COPED) to avoid leakage between adjacent devices. PODE patterns or CPODE patterns are used to form polysilicon segments. As device dimensions (e.g., gate pitch) shrink, design schemes such as PODE and CPODE schemes may face difficulties in providing device density, cell isolation, and device performance levels required for highly competitive scaled circuits and devices. Summary of the invention

[0004] In one aspect, an embodiment of the present application provides a method comprising: forming a fin structure along a first direction, a gate structure spanning the fin structure, and a source / drain region on an opposite side of the gate structure on a substrate; depositing a mask layer on the gate structure; forming a pattern in the mask layer, wherein the pattern comprises a longitudinal opening formed on a portion of the gate structure; etching the gate structure through the longitudinal opening to expose the fin structure; etching the fin structure to a first depth; depositing an enhanced passivation layer; performing a penetration etching process; etching the fin structure and the substrate to a second depth to form an isolation opening; and filling the isolation opening with a dielectric material.

[0005] In some implementations, etching the fin structure to the first depth is performed continuously.

[0006] In some implementations, the first depth is below the source / drain region.

[0007] In some implementations, depositing the enhanced passivation layer includes performing an atomic layer deposition process.

[0008] In some implementations, etching the fin structure to a first depth, depositing the enhanced passivation layer, performing a break-through etch process, and etching the fin structure and the substrate to a second depth are performed in the same chamber.

[0009] In some implementations, the isolation opening has a maximum width between the first depth and the second depth.

[0010] In some implementations, the isolation opening has a minimum width above the first depth.

[0011] In one aspect, an embodiment of the present application provides a semiconductor device, comprising: a semiconductor substrate; a fin structure on the semiconductor substrate and extending along a first direction; a gate structure arranged across the fin structure and extending along a second direction; a first source / drain region and a second source / drain region formed on the fin structure and on opposite sides of the gate structure; and an isolation structure arranged in the gate structure, wherein the isolation structure extends from a top surface of the fin structure into the semiconductor substrate, the isolation structure having a maximum width at a first level below the first source / drain region and the second source / drain region and having a necking width at a second level between the top surface of the fin structure and the first level.

[0012] In some implementations, the maximum width is greater than a spacing between the first source / drain region and the second source / drain region.

[0013] In some implementations, the semiconductor device further includes a passivation layer disposed on a sidewall of the isolation structure, wherein the passivation layer is disposed above the first level.

[0014] In some implementations, the passivation layer includes Br-containing silicon oxide.

[0015] In some implementations, a ratio of the maximum width to the necked width is in a range between about 1.5 and about 2.0.

[0016] In some implementations, the fin structure includes two or more semiconductor channel layers stacked vertically, and the second level is below a bottommost semiconductor channel layer.

[0017] In some implementations, the isolation structure has a first overlay offset relative to the gate structure above a top surface of the fin structure and a second overlay offset relative to the gate structure at a first level.

[0018] In some implementations, the first coverage offset is greater than the second coverage offset.

[0019] In one aspect, an embodiment of the present application provides a method, comprising: forming a fin structure along a first direction and a first gate structure and a second gate structure across the fin structure on a substrate; depositing a mask layer on the first gate structure and the second gate structure; forming a pattern in the mask layer, wherein the pattern comprises: a first longitudinal opening formed above the first gate structure and parallel to the first gate structure, wherein the first longitudinal opening deviates from the first gate structure by a first covering offset; and a second longitudinal opening formed above the second gate structure and parallel to the second gate structure; etching through the first longitudinal opening and the second longitudinal opening in the mask layer to form a first isolation opening and a second isolation opening in the substrate, wherein the first isolation opening is substantially aligned with the first gate structure; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

[0020] In some embodiments, etching through the first longitudinal opening and the second longitudinal opening includes: etching the first gate structure and the second gate structure through the first longitudinal opening and the second longitudinal opening to expose the fin structure; and etching through the fin structure and into the substrate through the first longitudinal opening and the second longitudinal opening to form a first isolation opening and a second isolation opening in the substrate.

[0021] In some implementations, etching through the fin structure and into the substrate includes: etching the fin structure to a first depth; depositing a passivation layer; performing a break-through etch; and etching the fin structure and the substrate to form a first isolation opening and a second isolation opening.

[0022] In some implementations, the first depth is below a top surface of the substrate.

[0023] In some implementations, the first isolation opening has a first width above the first depth and a second width below the first depth, and the second width is greater than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It is worth noting that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0025] Figure 1 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0026] Figure 2A-2B 11A-11B schematically illustrate various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0027] Figures 12A-12D It is a partial cross-sectional view of a semiconductor device at different stages.

[0028] Fig.12E is a schematic cross-sectional view of an example device according to the present disclosure.

[0029] Fig.13 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0030] Fig.14A is a schematic layout diagram of a semiconductor device according to the present disclosure.

[0031] Fig. 14B yes Fig.14A Schematic cross-sectional view of a semiconductor device.

[0032] Fig. 14C is a schematic layout diagram of a semiconductor device according to the present disclosure.

[0033] Fig.14D yes Fig. 14C Schematic cross-sectional view of a semiconductor device.

[0034] Fig.14E is a schematic layout diagram of a semiconductor device according to the present disclosure.

[0035] Fig.14F yes Fig.14E Schematic cross-sectional view of a semiconductor device. DETAILED DESCRIPTION

[0036] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature is not in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself govern the relationship between the various embodiments and / or configurations discussed.

[0037] Additionally, for ease of description, spatially relative terms, such as "below," "below," "below," "above," "top," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0038] The foregoing generally summarizes some aspects of the embodiments described in the present disclosure. Although some of the embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used for other processes and / or other devices, for example, planar FETs, fin FETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around FETs, and other suitable devices. It will be readily appreciated by those of ordinary skill in the art that other modifications that may be made within the scope of the present disclosure are foreseeable. In addition, although the method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than described herein. In the present disclosure, the source / drain region refers to the source and / or drain. The source and drain may be used interchangeably.

[0039] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a smaller pitch than is achievable using a single direct photolithography process.

[0040] Embodiments of the present disclosure relate to forming an isolation structure in a gate structure to prevent current leakage through a source / drain region (EPI), a transistor, and a silicon substrate. The isolation structure can be formed in the gate structure before or after a replacement gate sequence. A continuous polysilicon on diffusion edge (CPODE) process, including a silicon gate etch process, can be performed before the replacement gate sequence. A continuous metal on diffusion edge (CMODE) process including a metal gate etch process can be performed after the replacement gate sequence.

[0041] Embodiments of the present disclosure relate to methods for forming CPODE or CMODE openings in small epitaxial spacing without damaging the epitaxial regions. As integrated circuits scale down, the epitaxial critical dimension (EPI CD), i.e., the spacing between epitaxial regions, becomes smaller and smaller. Small EPI CD makes it challenging to etch CPODE or CMODE trenches without damaging adjacent epitaxial features. Embodiments of the present disclosure provide an etching process for forming high aspect ratio trenches (e.g., CPODE / CMODE trenches) without damaging adjacent structures (e.g., epitaxial source / drain features).

[0042] Conventionally, a CPODE / CMODE opening with very small EPI CD can be achieved using a cyclical step of passivation, penetration, and semiconductor etching. However, this cyclical scheme is time-consuming and has high manufacturing costs. Embodiments of the present disclosure provide an adjustable etching scheme near the epitaxial region to achieve maximum economic benefits. In some embodiments, a semiconductor etching process can be performed by continuously etching to a first depth, depositing a passivation layer with improved etching resistance, performing a passivation penetration process, and then etching the semiconductor material to a desired depth. The first depth can be adjusted according to the process design. In some embodiments, the first depth is adjusted to the position of the desired minimum EPI CD.

[0043] In advanced nodes with high transistor density, overlay shift can be applied when forming CPODE / CMODE patterns in a mask layer to prevent photoresist stripping during manufacturing. The etching process according to the present disclosure can be used to correct the overlay shift of CPODE / CMODE openings in semiconductor fins, thereby improving product quality and performance.

[0044] Figure 1 is a flow chart of a method 100 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. In particular, the method 100 relates to forming a semiconductor device having a CMODE isolation structure. Figure 2A-2B 11A- 11B schematically illustrate various stages of manufacturing a semiconductor device 200 according to an embodiment of the present disclosure using the method 100 .

[0045] The method 100 begins at operation 102, where a plurality of semiconductor fins 220 are formed on a substrate 210, such as Figure 2A-2B shown. Figure 2A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 2B is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0046] The substrate 210 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 210 may include various doping configurations depending on the circuit design. For example, different doping profiles, such as n-wells, p-wells, may be formed in regions of the substrate 210 designed for different device types (e.g., n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs)). In some embodiments, the substrate 210 may be a silicon-on-insulator (SOI) substrate including an insulator structure for enhancement.

[0047] The semiconductor fins 220 are formed on and in the substrate 210. Each semiconductor fin 220 includes a well portion 212 formed from the semiconductor substrate 210 and a semiconductor stack including a sacrificial layer 214 and a semiconductor channel layer 216 that are alternately stacked. The semiconductor fins 220 may be formed by patterning a hard mask deposited on the semiconductor stack and performing one or more etching processes. The semiconductor fins 220 are formed along the x-direction. The semiconductor stack of the semiconductor fins 220 has a stack height H 220 In some embodiments, the stack height H 220 In the range between about 20nm to 50nm.

[0048] Then, an isolation layer 222 is formed in the trenches between the semiconductor fins 220. The isolation layer 222 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or a combination thereof. In some embodiments, the isolation layer is formed to cover the semiconductor fins 220 by a suitable deposition process, such as atomic layer deposition (ALD), and then recessed etching is performed using a suitable anisotropic etching process to expose the channel portion 218 of the semiconductor fin 220.

[0049] Then, in operation 104, a sacrificial gate structure 228 and a spacer layer 230 are formed on the semiconductor fin 220, such as Figure 2A-2B As shown. Sacrificial gate dielectric layer 224 is deposited on the exposed surface of semiconductor device 200. Sacrificial gate dielectric layer 224 may be conformally formed on semiconductor fin 220 and isolation layer 222. In some embodiments, sacrificial gate dielectric layer 224 may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable processes. Sacrificial gate dielectric layer 224 may include one or more layers of dielectric material, for example, SiO 2 , SiN, high-K dielectric materials, and / or other suitable dielectric materials.

[0050] The sacrificial gate electrode layer 226 is deposited on the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 may be blanket deposited on the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 includes silicon, such as polysilicon or amorphous silicon. In some embodiments, a planarization operation is performed on the sacrificial gate electrode layer 226. The sacrificial gate electrode layer 226 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A patterning operation is performed on the sacrificial gate dielectric layer 224 and the sacrificial gate electrode layer 226 to form a sacrificial gate structure 228, which is formed overlying a portion of the semiconductor fin 220 designed as a channel region.

[0051] Then, a gate sidewall spacer 230 is formed on the sidewall of each sacrificial gate structure 228. After forming the sacrificial gate structure 228, the gate sidewall spacer 230 can be formed by blanket deposition of an insulating material, followed by anisotropic etching to remove the insulating material from the horizontal surface. The gate sidewall spacer 230 can have a thickness in the range of about 3nm to about 8nm. In some embodiments, the insulating material of the gate sidewall spacer 230 is a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN, and combinations thereof. In some embodiments, the gate sidewall spacer 230 can be formed of two or more layers of dielectric material.

[0052] After forming the gate sidewall spacers 230, the semiconductor fins 220 are etched back to form source / drain recesses on both sides of the sacrificial gate structure 228. The ends of the sacrificial layer 214 and the semiconductor channel layer 216 are exposed to the source / drain recesses. In some embodiments, the sacrificial layer 214 is a semiconductor layer. In other embodiments, the sacrificial layer 214 is an oxide layer. The sacrificial layer 214 is first etched horizontally along the X direction to form a cavity between the semiconductor channel layers 216. In some embodiments, a wet etchant or a dry etchant (such as, but not limited to, ammonium hydroxide (NH 2 4 The sacrificial layer 214 is selectively etched by using a solution of N,N,N,N-(OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH), or a halogen-based gas, such as Cl2, NF3, or HF, and NH3). In some embodiments, the etching amount of the sacrificial layer 214 is in a range between about 2 nm and about 10 nm along the X direction. After the cavity is formed in the sacrificial layer 214, an inner spacer 232 may be formed in the cavity by conformally depositing an insulating layer and then partially removing the insulating layer. The insulating layer may be formed by ALD or any other suitable method. In some embodiments, the insulating layer may include silicon nitride (SiN) and silicon oxide (SiO 2) and has a thickness in the range of about 0.5 nm to about 3.0 nm. A subsequent etching process removes most of the insulating layer outside the cavity, thereby forming an inner spacer 232.

[0053] The sacrificial gate structure 228 has a gate pitch GP. In some embodiments, the gate pitch GP is less than 50 nm, for example, the gate pitch is between about 20 nm and about 30 nm.

[0054] In operation 106, if Figure 2A-2B As shown, source / drain regions 240 are formed in the source / drain recesses. The source / drain regions 240 may be formed from the semiconductor channel layer 216 and the well portion 212 of the fin structure 220 by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). The source / drain regions 240 may include one or more layers of Si, SiP, SiC, and SiCP for NFETs, or one or more layers of Si, SiGe, and Ge for PFETs. For PFETs, p-type dopants such as boron (B) may also be included in the source / drain regions 240.

[0055] like Figure 2A As shown, the spacing between the source / drain regions 240 across each gate structure 228 along the x-direction may be referred to as the epitaxial CD. In some embodiments, the epitaxial CD may be in a range between about 10 nm and about 20 nm.

[0056] In operation 108, a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are formed on the exposed surface, such as Figure 2A-2B CESL 242 is formed on the epitaxial source / drain regions 240 and the gate sidewall spacers 230. CESL 242 may include Si 3 N 4 , SiON, SiCN, or any other suitable material, and can be formed by CVD, PVD, or ALD. An interlayer dielectric (ILD) layer 244 is formed on the contact etch stop layer (CESL) 242. Materials for the ILD layer 244 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) can be used for the ILD layer 244. After the ILD layer 244 is formed, a planarization operation (e.g., CMP) is performed to expose the sacrificial gate electrode layer 226 so that the sacrificial gate structure 228 is subsequently removed. During the removal of the sacrificial gate structure 228, the ILD layer 244 protects the epitaxial source / drain region 240.

[0057] In some embodiments, a cut polysilicon gate (CPO) process may be performed to remove a portion of the sacrificial gate structure 228 to form a cut feature, such as a trench, and then fill the cut feature with a dielectric material to form a gate isolation feature 221 in the sacrificial gate structure 228 .

[0058] In operation 110, Figure 3A-3B As shown, a replacement gate process is performed. Figure 3A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 3B is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0059] First, the sacrificial gate structure 228 is removed. Specifically, the sacrificial gate electrode layer 226 and the sacrificial gate dielectric layer 224 are removed in sequence to expose the semiconductor fin 220, that is, the well portion 212 and the semiconductor channel layer 216 of the semiconductor fin 220. Then, a replacement gate structure 274 is formed around the semiconductor channel layer 216 and the well portion 212. The gate dielectric layer 270 is formed on the semiconductor channel layer 216 and the well portion 212. The gate electrode layer 272 is formed on the gate dielectric layer 270. The gate dielectric layer 270 and the gate electrode layer 272 may be referred to as a replacement gate structure 274.

[0060] The gate dielectric layer 270 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 270 is formed using a highly conformal deposition process such as ALD. The gate dielectric layer 270 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、zirconia、alumina、titanium oxide、hafnium dioxide-alumina (HfO 2 -Al 2 O 3 ) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0061] The gate electrode layer 272 is formed on the gate dielectric layer 270. The gate electrode layer 272 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 272 may be formed by CVD, ALD, electroplating, or other suitable methods.

[0062] In operation 112, a mask layer 248 is deposited on the semiconductor device 200, such as Figure 4A-4B shown. Figure 4A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 4B is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0063] The mask layer 248 may include one or more dielectric layers. The mask layer 248 may be deposited on the replacement gate structure 274, the gate sidewall spacer 230, the CESL 242, and the ILD layer 244. In some examples, the one or more mask layers may include or may be silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, etc., or a combination thereof, and may be deposited by CVD, PVD, ALD, or other deposition techniques. In some embodiments, the mask layer 248 may be a film having compressive stress, because the opening formed in the compressive stress film may not have a gap. In some embodiments, the mask layer 248 may be silicon nitride, and its thickness may be in the range of about 650 angstroms to 850 angstroms, for example, between about 730 angstroms to about 750 angstroms.

[0064] A photolithography process is performed to form a CMODE pattern in the photoresist layer, such as Figure 4A-4B In some embodiments, a three-layer photoresist stack including a bottom layer 250, a back anti-reflective coating (BARC) 252, and a photoresist (PR) layer 254 is deposited. A photolithography process is performed to form a CMODE pattern.

[0065] In some embodiments, the CMODE pattern is transferred to the mask layer 248, such as Figure 5A-5B shown. Figure 5A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 5B 2 is a schematic cross-sectional view of the semiconductor device 200 along the y direction. The CMODE pattern may include one or more elongated openings 256 aligned with the replacement gate structure 274. The elongated openings 256 may be arranged in a pattern to achieve isolation across the semiconductor fin 220. Figure 5A-5B As shown, the elongated opening 256 exposes a section of the replacement gate structure 274. In some embodiments, the elongated opening 256 may have a width W along the x-direction. 256 In some embodiments, the width W 256 is at least about 50% of the gate pitch GP, for example, the width W 256 In the range between about 15 nm to about 30 nm.

[0066] In operation 114, an etching process is performed to selectively remove a portion of the replacement gate structure 274 through the elongated opening 256 in the mask layer 248, such as Figure 6A-6B shown. Fig. 6A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 6Bis a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0067] In some embodiments, the etching chemistry is selective to the one or more metal gate structure layers to be etched while minimizing etching of surrounding dielectric layers (e.g., isolation layer 222, sidewall spacers 230, CESL 242, and ILD layer 244). In some embodiments, a chlorine-containing gas (e.g., SiCl 4 , BCl 3 , Cl 2 , CHCl 3 , CCl 4 , and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gas, other suitable gas and / or plasma and / or their combination to remove the replacement gate structure 274. In some embodiments, the gate dielectric layer 270 can be removed by any suitable etching process, for example, plasma dry etching and / or wet etching. Figure 6B As shown, the replacement gate structure 274 may be substantially removed beneath the elongated opening 256 in the mask layer 248 , thereby exposing the gate spacer 230 , the semiconductor channel layer 216 , and the well portion 212 .

[0068] In operations 116, 118, 120, and 122, the semiconductor material exposed by the elongated opening 256 is removed to form an isolation opening. In particular, operations 116, 118, 120, and 122 can be used to form trenches in the semiconductor material without damaging the epitaxial source / drain regions 240 having a small pitch. In some embodiments, operations 116, 118, 120, and 122 can be performed in the same processing chamber (e.g., an ALD chamber) to achieve lower manufacturing costs.

[0069] In operation 116, a suitable etching process is performed to remove semiconductor materials, for example, the semiconductor channel layer 216 and the well portion 212 of the substrate 210 to form the isolation opening 262, as shown in FIG. Figure 7A-7B shown. Fig. 7A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 7B is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0070] In some embodiments, the etching process can be achieved by HBr-based plasma etching. In some embodiments, O 2 or CO 2Added to HBr. In some embodiments, the plasma etching process can be a high-density plasma process. The etching process can be performed using a processing chamber with an ICP (inductively coupled plasma) or a dipole antenna plasma source. The plasma can be driven by an RF power generator using an AC current operating at a frequency multiple of 13.56MHz and 27MHz. The processing chamber can operate at a pressure in the range of about 2 millitorr to about 150 millitorr. The etching process can be performed at a temperature range between about 20 degrees Celsius to about 120 degrees Celsius. The RF power generator can operate at a power level between about 100W to about 2500W. In some etching operations, the etching plasma can be pulsed with a duty cycle in the range of about 5% to 95%. In some embodiments, an RF bias power can be applied to a substrate base in the processing chamber. The RF bias power can be in the range of about 0W to about 2500W. In some embodiments, the plasma operation can be performed only with the bias power, that is, the plasma power is zero to enhance the etching directionality.

[0071] In some embodiments, the etching process may be performed in a plasma etching chamber having in-situ ALD capabilities so that a passivation layer with sufficient protection may be formed in a subsequent operation (ie, operation 118 ).

[0072] In some embodiments, the etching process in operation 116 may be performed continuously to achieve a fast etching rate. After operation 116, an opening 260 is formed. In some embodiments, the opening 260 may have a first depth D 260 , which is defined by the distance between the topmost semiconductor channel layer 216 and the bottom 260b of the opening 260. Depth D 260 The depth D may be selected based on the desired level of the narrowest CD. In some embodiments, the bottom 260b of the opening 260 is below the top surface 212f of the well portion 212 of the substrate 210. In some embodiments, the depth D 260 In some embodiments, the depth D of the semiconductor fin 220 is in the range of about 30 nm to about 100 nm. 260 With stack height H 220 The ratio can be in the range of about 1.1 to 1.5.

[0073] In operation 118, an enhanced passivation layer 264 is formed in the opening 260, such as Figures 8A-8B shown. Fig. 8A is a cross-sectional view of the semiconductor device 200 along the x direction. Figure 8B is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0074] According to an embodiment of the present disclosure, the enhanced passivation layer 264 has an increased etch resistance to an etch chemistry used for subsequent semiconductor etching (e.g., the etch chemistry used in operation 116). The enhanced passivation layer 264 may include one or more dielectric materials having an etch resistance relative to the semiconductor etching chemistry (e.g., the etch chemistry used in operation 116). In some embodiments, the enhanced passivation layer 264 may be a dielectric material, such as SiO, SiNO, SiN, etc. In some embodiments, a dielectric material containing SiCl may be used. 4 , O 2 , and HBr precursor to form enhanced passivation layer 264. In some embodiments, enhanced passivation layer 264 may include impurities from the precursor, such as Br and H. In some embodiments, enhanced passivation layer 264 may be formed using SiCl4 / HBr and O 2 / SO 2 / CO 2 The precursor forms Br-containing SiO.

[0075] In some embodiments, the enhanced passivation layer 264 is deposited by an ALD process in the same chamber as the etching process performed in operation 116. In some embodiments, the enhanced passivation layer 264 can be formed in the etching chamber using an in-situ ALD technique. For example, an in-situ ALD technique using precursors such as DIPAS (diisopropylaminosilane) and BTBAS (bis(tert-butylamino)silane) in combination with an Ar or O2 plasma treatment is used to form a silicon-containing film. For example, the enhanced passivation layer 264 can be formed by supplying a silicon source gas such as DIPAS or BTBAS to a processing chamber and supplying a plasma of a reactive gas such as oxygen or a nitrogen-containing gas to the processing chamber. The radicals from the plasma of the reactive gas oxidize or nitride the substances derived from the silicon source to form a silicon-containing passivation film.

[0076] The etch resistance of the enhanced passivation layer 264 can be increased by increasing the thickness, density, changing the composition of the precursor, or a combination thereof. In some embodiments, the enhanced passivation layer 264 is formed by increasing the deposition time to achieve an increased thickness. In some embodiments, the enhanced passivation layer 264 can have a thickness between about 0.5 nm and about 5 nm. In some embodiments, the enhanced passivation layer 264 can be formed by enhanced plasma dissociation to achieve a greater density. In some embodiments, the enhanced passivation layer 264 can be a density of about 2.648 g / cm 3 and about 4.0g / cm 3 In some embodiments, a precursor containing a higher concentration of nitrogen may be used to form the enhanced passivation layer 264.

[0077] In operation 120, a directional penetration operation is performed to remove the enhanced passivation layer 264 from the bottom 260b of the opening 260, such as Figures 9A-9B shown. Fig. 9A is a cross-sectional view of the semiconductor device 200 along the x direction. Fig. 9B is a schematic cross-sectional view of the semiconductor device 200 along the y direction. Fig. 9A As shown, the process gas is vertically biased toward the bottom 260 b of the opening 260 .

[0078] In some embodiments, the punch-through operation may be based on a fluorine-containing etchant (e.g., CF 4 , CHF 3 , CH 2 F 2 , CHF 3 , C 4 F 6 In some embodiments, when the enhanced passivation layer 264 includes SiO containing Br, a low selectivity etchant is used in a highly directional penetration operation, for example, CF 4 / C 4 F 6 / CHF 3 , to remove the enhanced passivation layer 264 from the bottom 260b of the opening 260. After the penetration operation, the enhanced passivation layer 264 is removed from the bottom 260b of the opening 260 and remains on the sidewall 260s of the opening 260. Figures 9A-9B As shown, after operation 120 , the enhanced passivation layer 264 remains only on the vertical surfaces and is removed from other horizontal and inclined surfaces (eg, the top of the horizontal and inclined surfaces of the mask layer 248 ).

[0079] In some embodiments, the breakthrough process is performed in the same chamber as the deposition process in operation 118 and the etching process performed in operation 116 .

[0080] In operation 122, a second semiconductor etching process is performed to etch the substrate 210 below the enhanced passivation layer 264 to form an opening 262, such as Figures 10A-10B shown. Fig. 10A is a cross-sectional view of the semiconductor device 200 along the x direction. Fig. 10B is a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0081] In some embodiments, the second etching process may be performed using an etching chemistry similar to the first etching process in operation 116. The etching process may be implemented by HBr-based plasma etching. 2 or CO 2In some embodiments, the plasma etching process may be a high density plasma process, and its conditions are similar to the etching process in operation 116. In some embodiments, a second etching process is performed to form an opening 262 in the semiconductor substrate 210 below the enhanced passivation layer 264. The bottom 262b of the opening 262 has a depth D from the topmost semiconductor channel layer 216. 262 . Depth D 262 It can be determined according to the device design. For example, the depth D 262 is selected to disconnect the electrical connection between the source / drain regions 240 through the semiconductor substrate 210. In some embodiments, the depth D 262 It may be in the range of about 100 nm to about 200 nm.

[0082] like Fig. 10A As shown, the enhanced passivation layer 264 reduces the diameter of the opening 260, especially at the level of the semiconductor channel layer 216. In the case of smaller spacing between the EPI CD or source / drain regions 240, the diameter of the opening 260 is further reduced, thereby forming a choke for the etchant fluid flow 261 in operation 122. After passivating the choke, the etchant fluid flow 261 fans out to a wider angle, resulting in a large diameter of the opening 262. As shown in FIG. Fig. 10A As shown, the opening 262 is wider than the opening 260 in the x-direction. The combination of the openings 260 and 262 may be at a depth D from the fin top 220t or the topmost semiconductor channel layer 216. Wmax The maximum width W max , and at a depth D from the fin top 220t or the topmost semiconductor channel layer 216 Wmin The minimum width W min In some embodiments, the maximum width or depth of the curved width D Wmax At the first depth D 260 Below and at the second depth D 262 The minimum width or the depth of the neck width D Wmin At the first depth D 260 Specifically, the minimum width W min The semiconductor channel layer 216 is located below the fin top 220t or the topmost semiconductor channel layer 216 and at a first depth D 260 In some embodiments, the depth D Wmin Under all semiconductor channel layers 216. When the first depth D 260 When below the lowermost semiconductor channel layer 216 or below the source / drain regions 240 , the formation of the openings 260 , 262 is less likely to damage the epitaxial source / drain regions 240 .

[0083] In some embodiments, the maximum width W max In some embodiments, the maximum width W max The ratio of the depth D to the EPI CD may be in the range of about 0.8 to 2.0. Wmax In some embodiments, the depth D Wmax The stack height H of the semiconductor fin 220 220 The ratio can be in the range of about 1.2 to 2.0.

[0084] In some embodiments, the minimum width W min In some embodiments, the minimum width W min The ratio of the depth D to the EPI CD may be in the range of about 0.5 to 0.8. Wmin In some embodiments, the depth D Wmin The stack height H of the semiconductor fin 220 220 The ratio can be in the range of about 0.5 to 1.1.

[0085] In addition, if Fig. 10A As shown, the opening 262 is also substantially symmetrical. While not meant to be theoretical, the choking of the fluid flow 261 during the etching operation 122 causes the fluid flow 261 exiting the opening 260 to be substantially symmetrical with respect to the central axis of the opening 260, thereby producing a substantially symmetrical opening 262. In some embodiments, the opening 262 may be substantially symmetrical about the central axis 275 of the gate structure 274. As discussed later, the etching processes in operations 116, 118, 120, 122 may be used to correct for pattern overlay shifts in the mask layer 248.

[0086] like Figures 10A-10B As shown, the enhanced passivation layer 264 may remain on the vertical sidewalls of the opening 256 during and after the second etching process to protect the adjacent source / drain regions 240 .

[0087] In some embodiments, the second etching process is performed in the same chamber as the penetration process in operation 120 , the deposition process in operation 118 , and the etching process performed in operation 116 .

[0088] In operation 124, openings 260 and 262 are filled with an isolation material to form isolation structure 266, such as Figures 11A-11B shown. Fig.11A is a cross-sectional view of the semiconductor device 200 along the x direction. Fig. 11Bis a schematic cross-sectional view of the semiconductor device 200 along the y direction.

[0089] A pre-cleaning process may be performed before filling the openings 260, 262. During the pre-cleaning process, all or part of the enhanced passivation layer 264 may be removed. In some embodiments, a thin film of the enhanced passivation layer 264 may remain on the sidewalls 260s of the opening 260 before the dielectric fill operation.

[0090] In some embodiments, a filling material is deposited in the openings 260, 262 to replace the removed semiconductor substrate 210, the semiconductor fins 220, and the portion of the replacement gate structure 274. The filling material may be an insulating material. In some examples, the filling material may be a single insulating material, while in other examples, the filling material may include a variety of different insulating materials, for example, a multilayer configuration. The filling material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbon, or the like, or a combination thereof, and may be deposited by CVD, PVD, ALD, or other deposition techniques. In some embodiments, a liner layer 265 may be formed before depositing the filling material. After depositing the liner layer 265 and the filling material, a CMP process may be performed to expose the sacrificial gate structure 228 for subsequent processes. In some embodiments, an enhanced passivation layer 264 may be disposed around the upper portion of the isolation structure 266.

[0091] The isolation structure 266 extends sufficiently deep into the semiconductor substrate 210 and provides electrical isolation between the source / drain regions 240 on opposite sides.

[0092] Etching, passivation, and etching processes according to the present disclosure, such as described in operations 116, 118, 120, and 122, can be used to form high aspect ratio trenches, such as CMODE and CPODE, without damaging nearby features. In a first etching process, such as described in operation 116, the trench is etched to a first depth, such as a depth D 260 The first depth can be selected based on the desired position of the minimum width or necking width, e.g. Fig. 10A In some embodiments, the minimum width Wmin corresponds to min The necking depth 260n of the opening 260 is above the bottom 260b of the opening 260. In some embodiments, the necking distance D 260n It refers to the distance between the bottom 260b and the necking depth 260n, which is in the range of about 0 nm to about 10 nm.

[0093] Figures 12A-12B is a partial cross-sectional view of semiconductor device 200 after operations 116 and 122 in one example. Figures 12C-12DFIG. 1 is a partial cross-sectional view of a semiconductor device 200 after operations 116 and 122 in one example. The longer etching step in operation 116 results in Fig. 12A The lower first depth and Fig. 12B The lower depth D shown Wmin The shorter etching step in operation 116 results in Fig. 12C The higher first depth and Fig.12D The higher depth D shown Wmin For a CMODE or CPODE process, it is desirable to have the minimum width or neck width at the level of the epitaxial source / drain region, while the maximum width or bow width is below the epitaxial source or drain region.

[0094] Fig.12E is a schematic cross-sectional view of an example device according to the present disclosure. Fig.12E In the device of FIG. 1 , the isolation structure 266 is formed between the two epitaxial source / drain regions 240 and extends into the substrate 210. The minimum width W of the isolation structure 266 is min Located at the level between the epitaxial source / drain regions 240, the maximum width Wmax of the isolation structure 266 is lower than the level of the source / drain regions 240. The maximum width Wmax is greater than the spacing between the epitaxial source / drain regions 240. The enhanced passivation layer 264 is located on the sidewalls of the isolation structure 266 and above the maximum width Wmax.

[0095] Although the semiconductor device 200 described above is a GAA device, the method 100 can also be used to manufacture FinFET devices. The method 100 can be used to manufacture semiconductor devices with various designs, such as dummy fins.

[0096] The etch passivation etch process according to the present disclosure may also be used to form an isolation structure in a CPODE process. Fig.13 1 is a flow chart of a method 100a for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Method 100a involves forming an isolation structure using a CPODE process. Method 100a is similar to method 100, except that a replacement gate process is performed after the CPODE process. In particular, in method 100a, the operation of forming a replacement gate structure (operation 110) is performed after forming an isolation structure (operations 116, 118, 120, 122, 124).

[0097] Due to the limitations of manufacturing equipment, there may be inherent coverage offset in the patterning process. In some cases, coverage offset can be intentionally added to certain patterns to avoid photoresist stripping. However, coverage offset may reduce device performance and / or cause reliability issues. As the functional size decreases, the impact of coverage offset on device performance is more significant. During CMODE / CPODE, the coverage offset between the opening in the mask layer (e.g., the opening 256 in the mask layer 248) and the gate structure may cause further offset of the isolation opening or asymmetric isolation opening. As described above, according to the etching, passivation, and etching process disclosed in the present invention can be used to reduce the impact of pattern coverage offset on the symmetry of the etching profile in the horizontal direction. By using sufficient passivation in the etching process, the CD in the horizontal direction can be retained, minimizing the risk of EPI damage caused by the coverage offset of the CPODE pattern. Figures 14A-14E Various examples of semiconductor devices according to embodiments of the present disclosure are schematically illustrated.

[0098] Fig.14A is a schematic layout diagram of the semiconductor device 200a. Fig.14A As shown, the semiconductor device 200 a includes an isolation structure 266 formed in every other gate structure 272 . Fig. 14B The semiconductor device 200a is along Fig.14A Schematic cross-sectional view along line 14B in FIG.

[0099] like Fig. 14B As shown, an isolation structure 266 is formed according to method 100 or 100a. The isolation structure 266 is formed by etching through the opening 256 in the mask layer 248 using the etching scheme described in operations 116, 118, 120, and 122 above. In the semiconductor device 200a, the average width W220t at the fin top 220t is about 17.7nm, the minimum width Wmin or the necking width is about 17.4nm, and the maximum width Wmax or the bending width is about 30.3nm. The average depth D of the isolation structure 266 from the fin top 220t is about 17.7nm. 262 is about 156.8 nm, and the average necking depth D Wmin is 39.0 nm, and the average bending depth D Wmax The opening 256 has an average overlay offset of about -0.2 nm at level a and a horizontal bending position offset of about 0.4 nm at level b.

[0100] Fig. 14C is a schematic layout diagram of the semiconductor device 200b. Fig. 14C As shown, the semiconductor device 200 b includes an isolation structure 266 formed in every other gate structure 272 . Fig.14DThe semiconductor device 200b is along Fig. 14C Schematic cross-sectional view along line 14D in FIG.

[0101] like Fig.14D As shown, an isolation structure 266 is formed according to method 100 or 100a. The isolation structure 266 can be formed by etching through 256a, 256b, 256c in the mask layer 248 using the etching scheme described in operations 116, 118, 120, 122 above. During patterning, an overlay offset is intentionally introduced into the openings 256b, 256c to facilitate PR stripping. In the semiconductor device 200b, the average width W220t at the fin top 220t is about 17.7nm, the minimum width Wmin or necking width is about 17.7mm, and the maximum width Wmax or bending width is about 28.3nm. The average depth D of the isolation structure 266 from the fin top 220t is about 17.7nm. 262 is about 152.8 nm, and the average necking depth D Wmin is 51.4 nm, and the average bending depth D Wmax The opening 256 has an average overlay offset of about −3.9 nm at level a and a horizontal bending position offset of about −0.7 nm at level b. The semiconductor device 200 b shows that the method of the present disclosure reduces the overlay offset in the isolation structure 266 .

[0102] Fig.14E is a schematic layout diagram of the semiconductor device 200c. Fig.14E As shown, the semiconductor device 200 c includes an isolation structure 266 formed in every plurality of gate structures 272 . Fig.14E The semiconductor device 200c is along Fig.14F Schematic cross-sectional view along line 14E in FIG.

[0103] like Fig.14F As shown, an isolation structure 266 is formed according to method 100 or 100a. The isolation structure 266 is formed by etching through the opening 256 in the mask layer 248 using the etching scheme described in operations 116, 118, 120, and 122 above. The semiconductor device 200c is a semiconductor device having three semiconductor layers 216. 1 ,216 2 ,216 3 In the semiconductor device 200c, the average width W at the top 220t of the fin is 220t is about 17.9 nm, and the second semiconductor channel layer 216 2 The average width W216 2 The second semiconductor channel layer 216 is about 16.6 nm. 3 The average width W216 3The average depth D of the isolation structure 266 from the fin top 220t is about 16.9 nm, the minimum width Wmin or the neck width is about 16.1 nm, and the maximum width Wmax or the bend width is about 31.0 nm. 262 is about 182.6 nm, and the average necking depth D Wmin is 50.9 nm, and the average bending depth D Wmax The necking depth D is 68.2 nm. Wmin Below the bottommost semiconductor channel layer 216. The opening 256 has an average overlay offset of about -0.2 nm at level a and a horizontal bending position offset of about 0.4 nm at level b.

[0104] Various embodiments or examples described herein provide several advantages over the prior art. The method according to the present disclosure enables gate pitch scaling in CPODE or CMODE processes without damaging the epitaxial source / drain regions.

[0105] It should be understood that not all advantages are necessarily discussed herein, that all embodiments or examples do not require a particular advantage, and that other embodiments or examples may provide different advantages.

[0106] Some embodiments of the present invention provide a method. The method includes: forming a fin structure along a first direction, a gate structure across the fin structure, and a source / drain region on the opposite side of the gate structure on a substrate; depositing a mask layer on the gate structure; forming a pattern in the mask layer, wherein the pattern includes a longitudinal opening formed on a portion of the gate structure; etching the gate structure through the longitudinal opening to expose the fin structure; etching the fin structure to a first depth; depositing an enhanced passivation layer; performing a penetration etching process; and etching the fin structure and the substrate to a second depth to form an isolation opening; and filling the isolation opening with a dielectric material.

[0107] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; a fin structure on the semiconductor substrate and extending in a first direction; a gate structure disposed on the fin structure and extending in a second direction; a first source / drain region and a second source / drain region formed on the fin structure and on opposite sides of the gate structure; and an isolation structure disposed in the gate structure, wherein the isolation structure extends from a top surface of the fin structure into the semiconductor substrate, the isolation structure having a maximum width at a first level below the first source / drain region and the second source / drain region, and having a necking width at a second level between the first level and an upper surface of the fin structure.

[0108] Some embodiments provide a method for forming a semiconductor device. The method includes: forming a fin structure along a first direction and a first gate structure and a second gate structure across the fin structure on a substrate; depositing a mask layer on the first gate structure and the second gate structure; forming a pattern in the mask layer, wherein the pattern includes: a first longitudinal opening formed above and parallel to the first gate structure, wherein the first longitudinal opening deviates from the first gate structure by a first covering offset; and a second longitudinal opening formed above and parallel to the second gate structure; etching through the first longitudinal opening and the second longitudinal opening in the mask layer to form a first isolation opening and a second isolation opening in the substrate, wherein the first isolation opening is substantially aligned with the first gate structure; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: forming a fin structure along a first direction, a gate structure spanning the fin structure, and source / drain regions on opposite sides of the gate structure on a substrate; depositing a mask layer on the gate structure; forming a pattern in the mask layer, wherein the pattern includes an elongated opening formed on a portion of the gate structure; etching the gate structure through the elongated opening to expose the fin structure; etching the fin structure to a first depth; Deposition of enhanced passivation layer; performing a breakthrough etching process; etching the fin structure and the substrate to a second depth to form an isolation opening; and The isolation openings are filled with a dielectric material.

2. The method according to claim 1, wherein: Etching the fin structure to a first depth is performed continuously.

3. The method according to claim 2, wherein: The first depth is below the source / drain region.

4. The method according to claim 1, wherein: Depositing the enhanced passivation layer includes performing an atomic layer deposition process.

5. The method according to claim 4, wherein: Etching the fin structure to a first depth, depositing the enhanced passivation layer, performing a breakthrough etching process, and etching the fin structure and the substrate to a second depth are performed in a same chamber.

6. The method according to claim 1, wherein: The isolation opening has a maximum width between the first depth and the second depth.

7. The method according to claim 6, wherein: The isolation opening has a minimum width above the first depth.

8. A semiconductor device comprising: Semiconductor substrate; A fin structure, on the semiconductor substrate and extending along a first direction; A gate structure, arranged across the fin structure and extending along a second direction; a first source / drain region and a second source / drain region formed on the fin structure and on opposite sides of the gate structure; as well as An isolation structure is arranged in the gate structure, wherein the isolation structure extends from the top surface of the fin structure into the semiconductor substrate, the isolation structure has a maximum width at a first level below the first source / drain region and the second source / drain region and has a necking width at a second level between the top surface of the fin structure and the first level.

9. The semiconductor device according to claim 8, wherein: The maximum width is greater than a spacing between the first source / drain region and the second source / drain region.

10. A method comprising: forming a fin structure along a first direction and a first gate structure and a second gate structure spanning the fin structure on a substrate; depositing a mask layer on the first gate structure and the second gate structure; A pattern is formed in the mask layer, wherein the pattern comprises: a first longitudinal opening formed above and parallel to the first gate structure, wherein the first longitudinal opening is offset from the first gate structure by a first overlay offset; and A second longitudinal opening formed above the second gate structure and parallel to the second gate structure; etching through the first and second elongated openings in the mask layer to form first and second isolation openings in the substrate, wherein the first isolation opening is substantially aligned with the first gate structure; and A dielectric layer is deposited to fill the first isolation opening and the second isolation opening.

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