Shield gate MOSFET preparation method and shield gate MOSFET

Abstract

The invention provides a preparation method of a shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and the shield gate MOSFET, and belongs to the technical field of semiconductor power devices. The method comprises the following steps: forming a groove in a substrate on which a mask grows; forming an ONO lamination layer on the substrate with the groove; wherein the ONO lamination layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are laminated in sequence; shield gate polycrystalline silicon is formed in the groove provided with the ONO lamination layer; forming an isolation layer on the shield gate polycrystalline silicon; wherein the isolation layer is coated above the silicon nitride layer; and forming control gate polycrystalline silicon on the isolation layer. According to the method, the control gate polycrystalline silicon and the silicon nitride are isolated through the isolation layer, so that the forward high-temperature gate bias reliability is improved under the condition that the threshold voltage and the on resistance of the shield gate MOSFET are not influenced, and the product performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a preparation method of a shielded gate MOSFET and the shielded gate MOSFET. Background Art

[0002] In the design and manufacturing of low-voltage shielded gate MOSFETs, in order to meet the low specific on-resistance characteristics of the device, it is necessary to pursue smaller and smaller cell pitches. With the reduction of trench CD and the increase of aspect ratio, the insulating dielectric layer between the control gate polysilicon and the shield gate polysilicon of the shielded gate MOSFET becomes difficult to fill using HDP-CVD (high-density plasma chemical vapor deposition) technology. Therefore, the insulating dielectric layer is mostly formed directly using furnace tube thermal oxidation. However, with the reduction of trench CD, the size of the bottom shield gate polysilicon becomes thinner, resulting in the insulating oxide layer formed by the polysilicon through furnace tube thermal oxidation is also thin, which will reduce the gate-source withstand voltage of the device.

[0003] In order to overcome the limitations of the above-mentioned processes, the industry generally adopts a process technology that uses a silicon oxide-silicon nitride-silicon oxide (ONO) stack to replace silicon oxide as the shielded gate MOSFET ReSurf layer. This technology separates the device epitaxial layer and the shielded gate polysilicon dielectric through the dielectric isolation of the nitride layer, so that the oxide layer between the control gate polysilicon and the shielded gate polysilicon can be grown using a longer oxidation time to achieve the ideal thickness without affecting the device epitaxial layer, thereby meeting the design and application requirements of the device gate-source withstand voltage. However, this process technology also introduces a new problem. After completing the subsequent process, the control gate polysilicon of the device will directly contact the nitride layer. When the device is tested by the forward high temperature gate bias (HTGB, High Temperature Gate Bias), the control gate polysilicon has a forward potential, while the drain and source of the device are connected to zero potential. Since silicon nitride has a hole conduction characteristic, silicon nitride also has a forward potential. At the same time, because the thickness of the silicon oxide between the silicon nitride and the device epitaxial layer (that is, the first layer of silicon oxide in the silicon oxide-silicon nitride-silicon oxide stack) is often greater than (angstroms), the holes in the silicon nitride cannot be injected from the oxide layer to the epitaxial layer, resulting in the accumulation of holes in the silicon oxide / nitride layer, which aggravates the aging of the bottom silicon oxide. Ultimately, the shielded gate MOSFET often fails due to high drain-source leakage after the forward high temperature gate bias (HTGB) test. To address the above problems, the industry generally uses CVD (chemical vapor deposition) or HTO (high temperature oxidation) methods to deposit silicon dioxide to isolate the control gate polysilicon and the silicon nitride in the ONO stack, while forming a gate oxide layer on the sidewalls. This method can prevent the device from failing in the forward high temperature gate bias (HTGB) reliability test, while increasing the thickness of the silicon oxide between the control gate polysilicon and the shield gate polysilicon, which greatly improves the drain-source withstand voltage. However, this method also has certain defects. Since the trench depth-to-width ratio of small-linewidth low-voltage shielded gate MOSFET is relatively high, the uniformity of silicon oxide thickness deposited by CVD or HTO on the wafer surface, trench sidewalls, trench corners and trench bottom is much worse than that of thermally grown oxide layer. This situation is particularly obvious in the 12-inch wafer process. In severe cases, the thickness of the oxide layer on the trench sidewalls can vary by as much as Or even more. This will cause the threshold voltage of the device to drift under the same doping conditions, resulting in large differences in the threshold voltage of chips produced in different batches or even in the same wafer of the same batch, which seriously affects the consistency of the electrical properties of the cores, reduces the core rate, and is not conducive to management and control. The instability of the threshold voltage will in turn affect many parameters of the device. If the threshold voltage is too high, the on-resistance of the device will increase, especially for devices working in the application scenario of VGS=4.5V. Such devices are highly sensitive to the threshold voltage. A high threshold voltage will increase the channel resistance of the device, seriously affecting the working efficiency; if the threshold voltage is too low, the channel leakage of the device may increase, and it may be mistakenly turned on during operation.

[0004] Therefore, it is necessary to improve the existing production process of low-voltage shielded gate MOSFET to overcome the defects of the prior art. Summary of the invention

[0005] In order to overcome the problems existing in the related art, one of the purposes of the present invention is to provide a method for preparing a shielded gate MOSFET, which isolates the control gate polysilicon and silicon nitride through an isolation layer, thereby improving the forward high-temperature gate bias reliability and enhancing the performance of the product while ensuring that the threshold voltage and on-resistance of the shielded gate MOSFET are not affected.

[0006] A method for preparing a shielded gate MOSFET, comprising:

[0007] opening a groove in a substrate having a mask grown thereon;

[0008] An ONO stack is formed on a substrate with grooves, wherein the ONO stack includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence;

[0009] forming shield gate polysilicon in the trench provided with the ONO stack;

[0010] Forming an isolation layer on the shielding gate polysilicon; wherein the isolation layer is coated on the silicon nitride layer;

[0011] A control gate polysilicon is formed on the isolation layer.

[0012] Specifically, the substrate can be a semiconductor material such as silicon or silicon carbide, and a hard mask is grown or deposited on the substrate to provide protection for subsequent etching steps. Through photolithography and dry etching processes, a small-sized groove with a depth controlled at 1-1.5μm and a CD (critical dimension) of 0.2-0.3μm is formed. A silicon oxide / silicon nitride / silicon oxide (ONO) stack is formed in the groove through a furnace tube process, and the total thickness of the ONO stack is greater than

[0013] Then, polysilicon is deposited in the trench with the ONO stack, and the polysilicon is etched back to the designed depth by chemical mechanical polishing (CMP) and dry etching technology to form a shield gate polysilicon structure. An isolation layer is formed on the shield gate polysilicon. In this embodiment, the isolation layer material can be silicon oxide formed by deposition or thermal oxidation, ensuring that it is completely covered on the silicon nitride layer in the ONO stack.

[0014] During the production process, this method effectively isolates the direct contact between the control gate polysilicon and silicon nitride by introducing an isolation layer between the two, avoiding oxide layer aging caused by charge accumulation during the forward high temperature gate bias (HTGB) test, thereby significantly improving the reliability of the device. While improving reliability, this preparation method greatly reduces the impact of the process on the threshold voltage and on-resistance of the shielded gate MOSFET. Due to the introduction of the isolation layer, the gate-source withstand voltage of the device will also be improved to a certain extent, and the gate-source oxide layer withstand voltage will be increased, which improves the gate reliability of the device to a certain extent.

[0015] In a preferred technical solution of the present invention, the isolation layer is located in the trench, and the isolation layer covers the ONO stack in the trench and the top of the shield gate polysilicon;

[0016] The isolation layer includes a silicon oxide layer formed by thermal oxidation of saturated doped polysilicon.

[0017] In a preferred technical solution of the present invention, the step of forming an isolation layer on the shielding gate polysilicon comprises:

[0018] Removing the second silicon oxide layer and the silicon nitride layer above the shielding gate polysilicon to expose the first silicon oxide layer, and retaining the second silicon oxide layer and the silicon nitride layer below the shielding gate polysilicon in the trench;

[0019] Depositing saturated doped polysilicon into the trench, so that the saturated doped polysilicon covers the shielding gate polysilicon, the silicon nitride layer and the second silicon oxide layer in the trench after being deposited;

[0020] Removing the first silicon oxide layer above the deposited saturated doped polysilicon to expose the trench sidewalls and the silicon surface above;

[0021] The oxidation operation causes the exposed silicon surface to be oxidized into a gate oxide layer, and the saturated doped polysilicon to be oxidized into a third silicon oxide layer; wherein the interface between the gate oxide layer and the third silicon oxide layer is closed.

[0022] In a preferred technical solution of the present invention, the step of forming an isolation layer on the shielding gate polysilicon comprises:

[0023] The second silicon oxide layer above the shielding gate polysilicon is removed to expose the silicon nitride layer, and the second silicon oxide layer below the shielding gate polysilicon in the groove is retained; on the shielding gate polysilicon, the second silicon oxide layer above it is removed by wet etching technology to expose the silicon nitride layer.

[0024] The polysilicon on the shielding gate polysilicon is oxidized to form a fourth silicon oxide layer on the top of the shielding gate polysilicon; the polysilicon on the shielding gate polysilicon is oxidized through a furnace tube oxidation process to form a new fourth silicon oxide layer on the top of the shielding gate polysilicon, and the thickness is controlled to be

[0025] The silicon nitride layer above the fourth silicon oxide layer is removed; the silicon nitride layer above the fourth silicon oxide layer is removed by wet etching technology to prepare for the subsequent polysilicon deposition step.

[0026] Saturated doped polysilicon is deposited in the trench, so that the saturated doped polysilicon covers the silicon nitride layer in the trench after deposition; saturated doped polysilicon is deposited in the trench, and the doping concentration is controlled at 10 18 cm -3 -10 21 cm -3 After deposition, ensure that the saturated doped polysilicon covers the silicon nitride layer in the trench.

[0027] removing the oxide layer in the first silicon oxide layer above the deposited saturated doped polysilicon to expose the silicon surface;

[0028] The oxidation operation causes the exposed silicon surface to be oxidized into a gate oxide layer, and the saturated doped polysilicon to be oxidized into a third silicon oxide layer; wherein the interface between the gate oxide layer and the third silicon oxide layer is closed.

[0029] In this step, the oxide layer in the first silicon oxide layer above the deposited saturated doped polysilicon is removed to expose the silicon surface. Subsequently, an oxidation operation is performed to oxidize the exposed silicon surface to form a gate oxide layer, and at the same time, the saturated doped polysilicon is oxidized to form a third silicon oxide layer. The interface between the gate oxide layer and the third silicon oxide layer is closed. The closed gate oxide layer and the third silicon oxide layer can avoid the formation of "spikes" at the bottom during the subsequent control gate polysilicon deposition or the formation of voids due to incomplete deposition, which helps to improve the gate-source withstand voltage of the device and enhances the stability and durability of the device under gate-source high voltage conditions.

[0030] In a preferred technical solution of the present invention, the process of removing the second silicon oxide layer above the shielding gate polysilicon includes:

[0031] Using wet etching to remove the second silicon oxide above the shielding gate polysilicon, and retaining the second silicon oxide and silicon nitride layer on the sidewall and bottom of the trench below the shielding gate polysilicon;

[0032] Wherein, in the trench, the upper surface of the retained second silicon oxide layer is lower than the upper surface of the shielding gate polysilicon, and the distance between the upper surface of the retained second silicon oxide layer and the upper surface of the shielding gate polysilicon is

[0033] The distance between the upper surface of the second silicon oxide and the upper surface of the shield gate polysilicon causes the upper surface of the second silicon oxide to sink relative to the upper surface of the shield gate polysilicon, and the sinking depth can be controlled by the overetching time of the wet etching. Before oxidizing the shield gate polysilicon, the oxide layer on the surface of the ONO stack is removed in advance, which also avoids the thickness of the shield gate polysilicon oxide layer being thinned during the wet etching, thereby improving the gate-source withstand voltage characteristics.

[0034] In a preferred technical solution of the present invention, the removing of the silicon nitride layer above the fourth silicon oxide layer comprises:

[0035] removing the silicon nitride layer above the fourth silicon oxide layer by wet etching, and retaining the silicon nitride layer in the groove;

[0036] Wherein, in the groove, the upper surface of the retained silicon nitride layer is lower than the upper surface of the fourth silicon oxide layer, and the distance between the upper surface of the retained silicon nitride layer and the upper surface of the fourth silicon oxide layer is

[0037]

[0038] Similarly, by forming a sunken space on the upper surface of the silicon nitride layer relative to the upper surface of the fourth silicon oxide layer, it is ensured that the edge of the saturated doped polysilicon after deposition can cover the silicon nitride in the ONO stack, and in the subsequent oxidation process, the silicon oxide formed by the saturated doped polysilicon can more easily contact and close with the silicon oxide formed by the silicon epitaxial layer.

[0039] In a preferred technical solution of the present invention, in the step of depositing saturated doped polysilicon into the trench, the doping concentration of the polysilicon is 10 18 cm -3 -10 21 cm -3 .

[0040] The silicon oxide formed after the saturated doped polysilicon is oxidized can be used as an isolation layer to isolate the control gate polysilicon and the silicon nitride layer to avoid direct contact, thereby improving the forward high-temperature gate bias reliability of the device. In addition, the deposited polysilicon can be used as a protective layer for the third silicon oxide layer to prevent the fourth silicon oxide layer from being corroded when the first silicon oxide layer is removed. Finally, a thicker oxide layer can be formed between the device shielding gate polysilicon and the control gate polysilicon, thereby improving the gate-source withstand voltage of the device and improving the gate reliability of the device.

[0041] In a preferred technical solution of the present invention, the step of removing the oxide layer in the first silicon oxide layer above the deposited saturated doped polysilicon comprises:

[0042] The oxide layer in the first silicon oxide layer above the saturated doped polysilicon is removed by wet etching, and the oxide layer below the saturated doped polysilicon in the trench is retained.

[0043] Wet etching has good material selectivity and can accurately remove the first silicon oxide layer without affecting other materials. In addition, wet etching can provide uniform etching effects over a large area, which is critical to maintaining device consistency and performance.

[0044] In a preferred technical solution of the present invention, the step of depositing saturated doped polysilicon into the trench further includes:

[0045] Grinding and etching the deposited saturated doped polysilicon so that the saturated doped polysilicon above the third silicon oxide layer reaches a preset thickness;

[0046] The preset thickness is At this thickness, the saturated doped polysilicon can be fully reacted and oxidized during the gate oxide oxidation process.

[0047] In a preferred technical solution of the present invention, after forming control gate polysilicon on the isolation layer, the method further comprises:

[0048] depositing an interlayer dielectric on the control gate polysilicon;

[0049] Making a contact hole on the intermediate layer dielectric, and making a metal interconnection layer on the intermediate layer dielectric, so that the metal interconnection layer is connected to the substrate through the contact hole;

[0050] A passivation layer is deposited on the metal interconnect layer.

[0051] A second object of the present invention is to provide a shielded gate MOSFET, which is prepared based on the preparation method of the shielded gate MOSFET as described above.

[0052] The device can prevent direct contact between the silicon nitride layer and the control gate polysilicon, thereby improving the reliability of forward high-temperature gate bias; and the use of the isolation layer improves the gate-source withstand voltage of the device, enhances the gate breakdown characteristics of the device, and improves the reliability of the device under gate-source high-voltage conditions.

[0053] The beneficial effects of the present invention are:

[0054] The present invention provides a method for preparing a shielded gate MOSFET, the method comprising: opening a groove on a substrate with a mask grown thereon; forming an ONO stack on the substrate with the groove; wherein the ONO stack comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence; forming a shielded gate polysilicon in the groove provided with the ONO stack; forming an isolation layer on the shielded gate polysilicon; wherein the isolation layer is coated on the silicon nitride layer; and forming a control gate polysilicon on the isolation layer. In the production process, the method effectively isolates the direct contact between the control gate polysilicon and the silicon nitride by introducing an isolation layer between the control gate polysilicon and the silicon nitride, prevents the silicon nitride layer and the control gate polysilicon from direct contact, and the silicon nitride layer is not affected by the potential of the control gate polysilicon, thereby significantly improving the reliability of the device. While improving the reliability, the preparation method also greatly reduces the influence of the process on the threshold voltage and on-resistance of the shielded gate MOSFET. Due to the introduction of the isolation layer, the gate-source withstand voltage of the device will also be improved to a certain extent, and the gate-source oxide layer has enhanced anti-breakdown capability, which improves the reliability of the device gate to a certain extent.

[0055] The present application also provides a MOSFET prepared based on the above-mentioned shielded gate MOSFET preparation method. The device can prevent the silicon nitride layer and the control gate polysilicon from direct contact. The silicon nitride layer is not affected by the potential of the control gate polysilicon and has high reliability. Moreover, the introduction of the isolation layer improves the gate-source withstand voltage of the device and enhances the reliability of the device gate under high gate-source voltage conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 is a flow chart of a method for preparing a shielded gate MOSFET provided in an embodiment of the present invention;

[0057] Figure 2 is a flow chart of forming an isolation layer on shield gate polysilicon provided in Embodiment 1 of the present invention;

[0058] Figure 3 is a flow chart of forming an isolation layer on shield gate polysilicon provided in Embodiment 2 of the present invention;

[0059] Figure 4It is a schematic structural diagram of a shielded gate MOSFET manufactured by the manufacturing method of forming an isolation layer on shielded gate polysilicon in Example 1 provided by the present invention;

[0060] Figure 5 is a schematic diagram of a method for preparing a shielded gate MOSFET provided in Example 1 of the present invention;

[0061] Figure 6 It is a schematic structural diagram of a shielded gate MOSFET manufactured by the manufacturing method of forming an isolation layer on shielded gate polysilicon in Example 2 provided by the present invention;

[0062] Figure 7 It is a schematic diagram of the method for preparing the shielded gate MOSFET provided in Example 2 of the present invention.

[0063] Reference numerals:

[0064] 1. Substrate; 2. First silicon oxide layer; 3. Silicon nitride layer; 4. Second silicon oxide layer; 5. Shield gate polysilicon; 6. Saturation doped polysilicon; 6', third silicon oxide layer; 7. Fourth silicon oxide layer; 8. Control gate polysilicon; 9. Gate oxide layer; 10. Intermediate layer dielectric; 11. Metal interconnect layer; 12. Passivation layer. DETAILED DESCRIPTION

[0065] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0066] While the existing shielded gate MOSFET manufacturing process improves device performance, it also introduces new reliability issues, especially failure issues in the forward high-temperature gate bias test. During the forward high-temperature gate bias test, the control gate polysilicon has a forward potential, the device drain and source are at zero potential, and the silicon nitride has a forward potential due to its hole conduction characteristics. Since the silicon oxide thickness between the silicon nitride and the device epitaxial layer is often greater than Holes cannot be injected from the oxide layer into the epitaxial layer, causing holes to accumulate in the silicon oxide / nitride layer, aggravating the aging of the bottom silicon oxide, and ultimately causing the shielded gate MOSFET to fail due to high drain-source leakage after passing the forward high-temperature gate bias test.

[0067] Example 1

[0068] like Figure 1-Figure 5 As shown, this embodiment provides a method for preparing a shielded gate MOSFET provided in this embodiment, comprising:

[0069] S100, opening a groove on the substrate 1 having the mask grown thereon;

[0070] S200, forming an ONO stack on a substrate 1 having a groove, wherein the ONO stack comprises a first silicon oxide layer 2, a silicon nitride layer 3 and a second silicon oxide layer 4 stacked in sequence;

[0071] S300, forming a shield gate polysilicon 5 in the trench provided with the ONO stack;

[0072] In this step, polysilicon is deposited in the trench with the ONO stack, and the polysilicon is etched back to the designed depth by chemical mechanical polishing (CMP) and dry etching technology to form a shield gate polysilicon 5 structure.

[0073] S400, forming an isolation layer on the shielding gate polysilicon 5; wherein the isolation layer is coated on the silicon nitride layer 3;

[0074] S500 , forming a control gate polysilicon 8 on the isolation layer.

[0075] In this embodiment, forming an isolation layer on the shielding gate polysilicon 5 includes:

[0076] S421, using a wet etching method to remove the second silicon oxide layer 4 and the silicon nitride layer 3 above the shield gate polysilicon 5, so that the first silicon oxide layer 2 is exposed, and the second silicon oxide layer 4 and the silicon nitride layer 3 below the shield gate polysilicon 5 in the trench are retained;

[0077] In this process flow, the second silicon oxide layer 4 and the silicon nitride layer 3 in the ONO stack are removed at one time, thereby skipping the oxidation process of the shield gate polysilicon 5, saving costs and sacrificing a part of the gate-source withstand voltage performance.

[0078] S422, depositing saturated doped polysilicon 6 into the trench, so that the saturated doped polysilicon 6 covers the shielding gate polysilicon 5, the silicon nitride layer 3 and the second silicon oxide layer 4 in the trench after deposition;

[0079] S423, removing the first silicon oxide layer 2 above the deposited saturated doped polysilicon 6 to expose the trench sidewalls and the silicon surface above;

[0080] S424, oxidation operation, so that the exposed silicon surface is oxidized into a gate oxide layer 9, and the saturated doped polysilicon 6 is oxidized into a third silicon oxide layer 6'; wherein the interface between the gate oxide layer 9 and the third silicon oxide layer 6' is closed.

[0081] In this embodiment, the step of depositing saturated doped polysilicon 6 into the trench so that the saturated doped polysilicon 6 covers the silicon nitride layer 3 in the trench after being deposited further includes:

[0082] Grinding and etching the deposited saturated doped polysilicon 6 so that the deposited saturated doped polysilicon 6 reaches a preset thickness;

[0083] The preset thickness is

[0084] In this embodiment, after forming the control gate polysilicon 8 on the isolation layer, the method further includes:

[0085] Depositing an intermediate dielectric layer 10 on the control gate polysilicon 8;

[0086] A contact hole is formed on the intermediate dielectric layer 10, and a metal interconnection layer 11 is formed on the intermediate dielectric layer 10, so that the metal interconnection layer 11 is connected to the substrate 1 through the contact hole;

[0087] A passivation layer 12 is deposited on the metal interconnect layer 11 .

[0088] Example 2

[0089] like Figure 1-Figure 3 , Figure 6-Figure 7 As shown, the present embodiment provides a method for preparing a shielded gate MOSFET, comprising:

[0090] S100, a groove is formed on the substrate 1 with a mask grown thereon; specifically, the substrate 1 may be a semiconductor material such as silicon or silicon carbide, and a hard mask is grown or deposited on the substrate 1 to provide protection for subsequent etching steps. Through photolithography and dry etching processes, a small-sized groove with a depth controlled at 1-1.5 μm and a CD critical dimension of 0.2-0.3 μm is formed.

[0091] S200, forming an ONO stack on a substrate 1 having a groove, wherein the ONO stack comprises a first silicon oxide layer 2, a silicon nitride layer 3 and a second silicon oxide layer 4 stacked in sequence;

[0092] A silicon oxide / silicon nitride / silicon oxide ONO stack is formed in the trench by a furnace process, and the total thickness of the ONO stack is greater than

[0093] S300, forming a shield gate polysilicon 5 in the trench provided with the ONO stack;

[0094] In this step, polysilicon is deposited in the trench with the ONO stack, and the polysilicon is etched back to the designed depth by chemical mechanical polishing (CMP) and dry etching technology to form a shield gate polysilicon 5 structure.

[0095] S400, forming an isolation layer on the shielding gate polysilicon 5; wherein the isolation layer is coated on the silicon nitride layer 3;

[0096] S500 , forming a control gate polysilicon 8 on the isolation layer.

[0097] In practical applications, an isolation layer is formed on the shielding gate polysilicon 5. The isolation layer material may be silicon oxide formed by deposition or thermal oxidation, ensuring that it completely covers the silicon nitride layer 3 in the ONO stack.

[0098] After forming the control gate polysilicon 8 on the isolation layer, the method further comprises:

[0099] S600, depositing an intermediate dielectric layer 10 on the control gate polysilicon 8; the deposited intermediate dielectric layer 10 may be silicon dioxide SiO2 or silicon nitride Si3N4, for providing electrical isolation and mechanical protection.

[0100] S700, making contact holes on the intermediate dielectric 10, and making a metal interconnection layer 11 on the intermediate dielectric 10, so that the metal interconnection layer 11 is connected to the substrate 1 through the contact holes; the position of the contact hole is designed to be aligned with the connection point between the control gate polysilicon 8 and the substrate 1, so as to facilitate the subsequent formation of the metal interconnection layer 11. Deposit a metal material such as aluminum or copper on the intermediate dielectric 10 to form the metal interconnection layer 11. The metal interconnection layer 11 is connected to the substrate 1 through the contact hole to ensure the reliability of the electrical connection.

[0101] S800: deposit a passivation layer 12 on the metal interconnection layer 11. The function of the passivation layer 12 is to protect the device from environmental influences such as moisture penetration and mechanical scratches.

[0102] In the production process, the method effectively isolates the direct contact between the control gate polysilicon 8 and the silicon nitride by introducing an isolation layer between the two, so that the silicon nitride layer is not affected by the potential of the control gate polysilicon, thereby significantly improving the reliability of the device. While improving the reliability, the preparation method also greatly reduces the impact of the process on the threshold voltage and on-resistance of the shielded gate MOSFET. Due to the introduction of the isolation layer, the gate-source withstand voltage of the device will also be improved to a certain extent, and the gate-source oxide layer will have an enhanced ability to resist breakdown, which improves the gate reliability of the device to a certain extent.

[0103] In this embodiment, a detailed step of forming an isolation layer different from that in Embodiment 1 is provided:

[0104] Specifically, the step of forming an isolation layer on the shielding gate polysilicon 5 includes:

[0105] S411, remove the second silicon oxide layer 4 above the shielding gate polysilicon 5 to expose the silicon nitride layer 3, and retain the second silicon oxide layer 4 below the shielding gate polysilicon 5 in the groove; on the shielding gate polysilicon 5, use wet etching technology to remove the second silicon oxide layer 4 above it to expose the silicon nitride layer 3.

[0106] S412, oxidizing the polysilicon on the shielding gate polysilicon 5 so that a fourth silicon oxide layer 7 is formed on the top of the shielding gate polysilicon 5; oxidizing the polysilicon on the shielding gate polysilicon 5 through a furnace tube oxidation process so that a new fourth silicon oxide layer 7 is formed on the top of the shielding gate polysilicon 5, and the thickness is controlled to be

[0107] S413, removing the silicon nitride layer 3 above the fourth silicon oxide layer 7; using a wet etching technique to remove the silicon nitride layer 3 above the fourth silicon oxide layer 7, so as to prepare for the subsequent polysilicon deposition step.

[0108] S414, depositing saturated doped polysilicon 6 into the trench, so that the saturated doped polysilicon 6 covers the silicon nitride layer 3 in the trench after deposition; wherein the saturated doped polysilicon 6 is deposited into the trench, and the doping concentration is controlled at 10 18 cm -3 -10 21 cm -3 After deposition, ensure that the saturated doped polysilicon 6 covers the silicon nitride layer 3 in the trench.

[0109] By depositing saturated doped polysilicon 6 in an additional step and oxidizing it to form an oxide layer to isolate the silicon nitride layer 3 and the control gate polysilicon 8, the reliability of the HTGB can be improved, and the following advantages can be brought about: 1. The sidewall gate oxide layer is formed by oxidation, and has good thickness uniformity and good threshold voltage consistency. 2. The process avoids corrosion of the third silicon oxide layer during wet etching, the oxide layer thickness is retained to be relatively thick, and the gate-source withstand voltage characteristics are better.

[0110] S415, removing the oxide layer in the first silicon oxide layer 2 above the deposited saturated doped polysilicon 6 to expose the silicon surface;

[0111] S416, oxidation operation, so that the exposed silicon surface is oxidized into gate oxide layer 9, and the saturated doped polysilicon 6 is oxidized into third silicon oxide layer 6'; wherein the interface between gate oxide layer 9 and third silicon oxide layer 6' is closed. During the oxidation operation, the gate oxide layer 9 is formed by oxidation in the furnace tube.

[0112] In this step, the oxide layer in the first silicon oxide layer 2 above the deposited saturated doped polysilicon 6 is removed to expose the silicon surface. Subsequently, an oxidation operation is performed so that the exposed silicon surface is oxidized to form a gate oxide layer 9, and the saturated doped polysilicon 6 is oxidized to form a third silicon oxide layer 6'. The interface between the gate oxide layer 9 and the third silicon oxide layer 6' is closed. The closed gate oxide layer 9 and the third silicon oxide layer 6' can avoid the formation of "spikes" at the bottom or incomplete deposition to form voids during the subsequent control gate polysilicon 8 deposition, which helps to improve the gate-source withstand voltage of the device and enhances the stability and durability of the device under gate-source high voltage conditions.

[0113] In this embodiment, the process of removing the second silicon oxide layer 4 above the shielding gate polysilicon 5 includes:

[0114] The second silicon oxide layer 4 above the shielding gate polysilicon 5 is removed by wet etching, and the second silicon oxide layer 4 and the silicon nitride layer 3 on the sidewall and bottom of the trench below the shielding gate polysilicon 5 are retained;

[0115] Wherein, in the trench, the upper surface of the retained second silicon oxide layer 4 is lower than the upper surface of the shielding gate polysilicon 5, and the distance between the upper surface of the retained second silicon oxide layer 4 and the upper surface of the shielding gate polysilicon 5 is

[0116] The distance between the upper surface of the second silicon oxide layer 4 and the upper surface of the shield gate polysilicon 5 makes the upper surface of the second silicon oxide layer 4 sink relative to the upper surface of the shield gate polysilicon 5, and the sinking depth can be controlled by the overetching time of wet etching. Before oxidizing the shield gate polysilicon 5, the oxide layer on the surface of the ONO stack is removed in advance, which also avoids the thickness of the oxide layer of the shield gate polysilicon 5 being thinned during wet etching, thereby improving the gate-source withstand voltage characteristics.

[0117] In this embodiment, removing the silicon nitride layer 3 above the fourth silicon oxide layer 7 includes:

[0118] The silicon nitride layer 3 above the fourth silicon oxide layer 7 is removed by wet etching, and the silicon nitride layer 3 in the groove is retained;

[0119] In the groove, the upper surface of the retained silicon nitride layer 3 is lower than the upper surface of the fourth silicon oxide layer 7, and the distance between the upper surface of the retained silicon nitride layer 3 and the upper surface of the fourth silicon oxide layer 7 is

[0120] Similarly, by forming a sunken space on the upper surface of the silicon nitride layer 3 relative to the upper surface of the fourth silicon oxide layer 7, it is ensured that the edge of the saturated doped polysilicon 6 after deposition can cover the silicon nitride in the ONO stack, and in the subsequent oxidation process, the silicon oxide formed by the saturated doped polysilicon can more easily contact and close with the silicon oxide formed by the silicon epitaxial layer.

[0121] In this embodiment, in the saturated doped polysilicon 6 deposited into the trench, the doping concentration of the polysilicon is 10 18 cm -3 -10 21 cm -3 .

[0122] The silicon oxide formed after the saturated doped polysilicon is oxidized can be used as an isolation layer to isolate the control gate polysilicon 8 and the silicon nitride layer 3 to avoid direct contact, thereby improving the forward high temperature gate bias HTGB reliability of the device. In addition, the doped polysilicon can adjust the device conductivity so that the gate can effectively control the channel area, thereby improving the threshold voltage and on-resistance of the device, and improving the switching speed and efficiency of the device. In addition, the oxide layer formed by the saturated doped polysilicon can increase the gate-source withstand voltage and improve the stability and durability of the device under high voltage conditions.

[0123] In this embodiment, the removal of the first silicon oxide layer 2 above the deposited saturated doped polysilicon 6 includes:

[0124] The first silicon oxide layer 2 above the saturated doped polysilicon 6 is removed by wet etching, and the oxide layer below the saturated doped polysilicon 6 in the trench is retained.

[0125] Wet etching has good material selectivity and can accurately remove the first silicon oxide layer 2 without affecting other materials such as the oxide layer below the saturated doped polysilicon layer 6. In addition, wet etching can provide uniform etching effects over a large area, which is critical to maintaining device consistency and performance.

[0126] The preparation method of this embodiment is described in detail below:

[0127] After growing / depositing a hard mask on the substrate 1, a small-sized groove is formed on the substrate 1 by photolithography and dry etching. The groove is generally 1-1.5 μm deep and the CD is 0.2 μm-0.3 μm.

[0128] A silicon oxide / silicon nitride / silicon oxide (ONO) stack is formed in the surface groove of the substrate 1 by a furnace process as the ReSurF layer of the shielded gate MOSFET. Generally, the total thickness of the three layers is greater than To meet the voltage withstand requirements of the device.

[0129] Polysilicon is deposited, chemical mechanical polishing (CMP) and dry etching are performed, and the polysilicon is etched back to the designed depth to form shielding gate polysilicon 5. In practical applications, a furnace tube process can be used for polysilicon deposition, and a single impurity such as phosphine or borane is introduced during the deposition process for doping. Another method is to add an ion implantation process after the polysilicon deposition to further concentrate the doping of the polysilicon. The former process is relatively simple and easy to implement, while the latter process cost is slightly higher, but the resistance of the polysilicon can be reduced to a lower level.

[0130] The second silicon oxide layer 4 is removed by wet etching to expose the silicon nitride layer 3 in the ONO stack. The upper surface of the second silicon oxide layer 4 of the ONO stack is sunk to a level lower than the upper surface of the shield gate polysilicon 5. The sinking depth can be controlled by the wet etching over-etching time. Then the process enters the furnace tube for oxidation, so that the upper surface of the shielding gate polysilicon 5 is oxidized to form a fourth silicon oxide layer (7).

[0131] Then, the silicon nitride layer 3 on the surface is removed by wet etching. During the removal of the silicon nitride layer 3, the wet etching over-etching time is controlled so that the upper surface of the silicon nitride is about 1000 nm lower than the upper surface of the oxide layer 3.

[0132]

[0133] Then, saturated doped polysilicon is deposited in the trench. The higher the doping concentration of the polysilicon, the faster the polysilicon oxidation rate is, and the more it can ensure that it can be completely oxidized in the subsequent oxidation process.

[0134] The deposited polysilicon is subjected to chemical mechanical polishing (CMP) and dry etching to etch the polysilicon back to a specific depth. Generally, the remaining saturated doped polysilicon 6 on the fourth silicon oxide layer 7 is Even if the saturated doped polysilicon 6 remains on the fourth silicon oxide layer 7 In this case, as long as the saturated doped polysilicon 6 is still retained in the grooves on both sides of the fourth silicon oxide layer 7, the purpose of isolating the control gate polysilicon 8 and the silicon nitride in the ONO stack can be achieved. However, in this case, a portion of the fourth silicon oxide layer 7 will be corroded in the subsequent wet etching process, and the gate-source withstand voltage of the final device will be reduced to a certain extent.

[0135] The oxide layer in the first silicon oxide layer 2 on the surface is removed by wet etching to expose the silicon surface. In this process, a longer wet etching time is required to ensure that the upper surface of the first silicon oxide layer 2 close to the silicon epitaxy in the ONO stack is corroded below the lower surface of the saturated doped polysilicon 6, which is beneficial to the full oxidation of the side of the saturated doped polysilicon 6.

[0136] The device with the oxide layer in the first silicon oxide layer 2 etched away is sent into a furnace tube for oxidation to form a gate oxide layer 9. The thickness of the gate oxide layer 9 can be During this process, the doped polysilicon will also be oxidized to form silicon oxide, and because the silicon sidewalls and the polysilicon sidewalls will be oxidized at the same time, the oxide layers grown by the two materials of the epitaxial silicon and polysilicon will eventually connect and close, avoiding the formation of "spikes" at the bottom during the subsequent deposition of the control gate polysilicon 8 or the formation of voids due to incomplete deposition.

[0137] Then, subsequent processing steps are carried out, including depositing polysilicon to form control gate polysilicon 8, depositing intermediate layer dielectric 10, etching to form contact holes, making metal interconnections, depositing passivation layer 12, thinning back gold, etc.

[0138] Example 3

[0139] like Figure 1-Figure 7As shown, this embodiment provides a method for preparing a shielded gate MOSFET, which is prepared based on the method for preparing a shielded gate MOSFET as described above.

[0140] In the device, an isolation layer is formed on the shielding gate polysilicon of the device; wherein the isolation layer is coated on top of the silicon nitride layer 3;

[0141] Wherein, the isolation layer is located in the trench, and the isolation layer covers the ONO stack in the trench and the top of the shielding gate polysilicon 5;

[0142] The isolation layer includes a silicon oxide layer formed by thermal oxidation of saturated doped polysilicon.

[0143] The silicon nitride layer of the device is not affected by the potential of the control gate polysilicon, thereby significantly improving the reliability of the device. While improving the reliability, the preparation method also greatly reduces the impact of the process on the threshold voltage and on-resistance of the shielded gate MOSFET. Due to the introduction of the isolation layer, the gate-source withstand voltage of the device will also be improved to a certain extent, and the gate-source oxide layer will have an enhanced ability to resist breakdown, which improves the gate reliability of the device to a certain extent.

[0144] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings. In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0145] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, and the spatially relative descriptions used here are interpreted accordingly.

[0146] In addition, it should be noted that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this application. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a shielded gate MOSFET, characterized in that: include: Opening a groove on a substrate (1) having a mask grown thereon; An ONO stack is formed on a substrate (1) having grooves therein; wherein the ONO stack comprises a first silicon oxide layer (2), a silicon nitride layer (3) and a second silicon oxide layer (4) stacked in sequence from bottom to top; Forming shield gate polysilicon (5) in the trench provided with the ONO stack; forming an isolation layer on the shielding gate polysilicon (5); wherein the isolation layer is coated on top of the silicon nitride layer (3); A control gate polysilicon (8) is formed on the isolation layer.

2. The method for preparing a shielded gate MOSFET according to claim 1, characterized in that: The isolation layer is located in the groove, and the isolation layer covers the ONO stack in the groove and the top of the shielding gate polysilicon (5); The isolation layer includes a silicon oxide layer formed by thermal oxidation of saturated doped polysilicon.

3. A method for preparing a shielded gate MOSFET according to claim 1 or 2, characterized in that: The step of forming an isolation layer on the shielding gate polysilicon (5) comprises: Removing the second silicon oxide layer (4) and the silicon nitride layer (3) above the shielding gate polysilicon (5) so that the first silicon oxide layer (2) is exposed, and retaining the second silicon oxide layer (4) and the silicon nitride layer (3) below the shielding gate polysilicon (5) in the trench; Depositing saturated doped polysilicon (6) into the trench, so that the saturated doped polysilicon (6) covers the shielding gate polysilicon (5), the silicon nitride layer (3) and the second silicon oxide layer (4) in the trench after deposition; Removing the first silicon oxide layer (2) above the deposited saturated doped polysilicon (6) to expose the trench sidewalls and the silicon surface above; The oxidation operation causes the exposed silicon surface to be oxidized into a gate oxide layer (9), and the saturated doped polysilicon (6) to be oxidized into a third silicon oxide layer (6'); wherein the interface between the gate oxide layer (9) and the third silicon oxide layer (6') is closed.

4. The method for preparing a shielded gate MOSFET according to claim 1 or 2, characterized in that: The step of forming an isolation layer on the shielding gate polysilicon (5) comprises: Removing the second silicon oxide layer (4) above the shielding gate polysilicon (5) to expose the silicon nitride layer (3), and retaining the second silicon oxide layer (4) below the shielding gate polysilicon (5) in the trench; Oxidizing the polysilicon on the surface of the shielding gate polysilicon (5) so that a fourth silicon oxide layer (7) is formed on the top of the shielding gate polysilicon (5); removing the silicon nitride layer (3) above the fourth silicon oxide layer (7), and retaining the silicon nitride layer (3) and the second silicon oxide layer (4) below the fourth silicon oxide layer (7) in the groove; Depositing saturated doped polysilicon (6) into the trench, so that the saturated doped polysilicon (6) covers the fourth silicon oxide layer (7) and the silicon nitride layer (3) in the trench after deposition; Removing the first silicon oxide layer (2) above the deposited saturated doped polysilicon (6) to expose the trench sidewalls and the silicon surface above; The oxidation operation causes the exposed silicon surface to be oxidized into a gate oxide layer (9), and the saturated doped polysilicon (6) to be oxidized into a third silicon oxide layer (6'); wherein the third silicon oxide layer (6') is closed at the interface with the gate oxide layer (9) and the fourth silicon oxide layer (7).

5. The method for preparing a shielded gate MOSFET according to claim 4, characterized in that: The process of removing the second silicon oxide layer (4) above the shielding gate polysilicon (5) includes: Using wet etching to remove the second silicon oxide above the shielding gate polysilicon (5), and retaining the second silicon oxide layer (4) and the silicon nitride layer (3) on the sidewall and bottom of the trench below the shielding gate polysilicon (5); Wherein, in the trench, the upper surface of the retained second silicon oxide layer (4) is lower than the upper surface of the shielding gate polysilicon (5), and the distance between the upper surface of the retained second silicon oxide layer (4) and the upper surface of the shielding gate polysilicon (5) is 6. The method for preparing a shielded gate MOSFET according to claim 4, characterized in that: The removing of the silicon nitride layer (3) above the fourth silicon oxide layer (7) comprises: The silicon nitride layer (3) above the fourth silicon oxide layer (7) is removed by wet etching, and the silicon nitride layer (3) and the second silicon oxide layer (4) on the sidewall and bottom of the trench below the shielding gate polysilicon (5) are retained; Wherein, in the groove, the upper surface of the retained silicon nitride layer (3) is lower than the upper surface of the fourth silicon oxide layer (7), and the distance between the upper surface of the retained silicon nitride layer (3) and the upper surface of the fourth silicon oxide layer (7) is 7. A method for preparing a shielded gate MOSFET according to claim 3 or 4, characterized in that: In the step of depositing saturated doped polysilicon (6) into the trench, the doping concentration of the polysilicon is 10 18 cm -3 -10 21 cm -3 .

8. A method for preparing a shielded gate MOSFET according to claim 2 or 3, characterized in that: The step of depositing saturated doped polysilicon (6) into the trench further comprises: Grinding and etching the deposited saturated doped polysilicon (6) so that the deposited saturated doped polysilicon (6) reaches a preset thickness; The preset thickness is 9. A method for preparing a shielded gate MOSFET according to any one of claims 1 to 7, characterized in that: After forming control gate polysilicon (8) on the isolation layer, the method further comprises: Depositing an intermediate layer dielectric (10) on the control gate polysilicon (8); Making a contact hole on the intermediate layer dielectric (10), and making a metal interconnection layer (11) on the intermediate layer dielectric (10), so that the metal interconnection layer (11) is connected to the substrate (1) through the contact hole; A passivation layer (12) is deposited on the metal interconnect layer (11).

10. A shielded gate MOSFET, characterized in that: The shielded gate MOSFET is prepared based on the preparation method of any one of claims 1 to 9.

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