SiC MOSFET junction temperature on-line monitoring circuit system based on grid peak current method

Abstract

The invention discloses a SiC MOSFET junction temperature on-line monitoring circuit system based on a grid peak current method, which is connected with a SiC MOSFET to be detected for junction temperature monitoring, and comprises an FPGA, a digital driving circuit, a di / dt detection circuit, a peak current acquisition circuit and a sampling resistor, and the FPGA is connected with an output end of a PWM input signal; the FPGA dynamically adjusts the driving logic of the digital driving circuit by receiving a trigger signal of the di / dt detection circuit and a PWM input signal, and after effective output data of the peak acquisition circuit is obtained, a junction temperature data processing module in the FPGA analyzes and processes the data in real time, and finally outputs junction temperature information of the SiC MOSFET device. The junction temperature monitoring circuit has the advantages of high junction temperature monitoring sensitivity, strong anti-interference capability, simple circuit structure and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of power device state monitoring, and relates to a SiC MOSFET junction temperature online monitoring circuit system based on a gate peak current method. Background Art

[0002] As a core device in third-generation wide-bandgap semiconductors, the Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET), with its advantages such as high withstand voltage, high switching frequency, and low conduction losses, has become a key component for achieving high power density and efficient energy conversion in new energy equipment. However, these technological advantages come with significant challenges: First, device miniaturization reduces thermal capacity, leading to significant thermal stress accumulation under extreme operating conditions, with junction temperature fluctuations reaching 2-3 times that of traditional silicon-based devices. Second, high-frequency switching behavior exacerbates electromagnetic oscillations and dynamic electrical stresses, inducing localized hotspots. Third, the dramatic junction temperature fluctuations caused by complex operating conditions (such as transient overload in electric vehicle inverters) can lead to mechanical failures such as interface delamination and bond wire breakage due to differences in the thermal expansion coefficients of the module's multi-layer packaging materials, significantly shortening device life. Real-time and accurate junction temperature monitoring is not only a core basis for thermal failure warning but also a key enabling technology for optimizing dynamic thermal stress distribution and improving system overload resistance. It holds irreplaceable engineering value in ensuring equipment reliability and maximizing energy efficiency.

[0003] Online monitoring of power device junction temperature based on temperature-sensitive electrical parameters (TSEP) is a current research hotspot in semiconductor thermal management, with significant advantages in non-invasive detection and dynamic response. Traditional TSEP parameters (such as threshold voltage, on-state voltage drop, and turn-off delay time) face key technical bottlenecks, including sensitivity to device aging, nonlinear temperature-parameter mapping, and insufficient robustness to operating disturbances. While gate peak current, a new temperature-sensitive electrical parameter, offers the unique advantage of being unaffected by bus voltage, load current, and device aging, its application is limited by its low sensitivity, making it difficult to maintain high junction temperature measurement accuracy under complex operating conditions.

[0004] Therefore, it is particularly important to improve the sensitivity of gate peak current as a temperature-sensitive electrical parameter. Summary of the Invention

[0005] The purpose of the present invention is to provide a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method, which solves the problem of low sensitivity of gate peak current as a temperature-sensitive electrical parameter in the prior art and realizes online monitoring of junction temperature under strong switching conditions.

[0006] The technical solution adopted by the present invention is a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method, which is connected to the SiC MOSFET to be tested for junction temperature monitoring. The system includes an FPGA, a digital drive circuit, a di / dt detection circuit, a peak current acquisition circuit, and a sampling resistor. The FPGA is connected to the output end of the PWM input signal. The FPGA dynamically adjusts the driving logic of the digital drive circuit by receiving the trigger signal from the di / dt detection circuit and the PWM input signal. After obtaining the valid output data from the peak acquisition circuit, the junction temperature data processing module inside the FPGA analyzes and processes the data in real time, and finally outputs the junction temperature information of the SiC MOSFET device.

[0007] The present invention is also characterized in that: The FPGA is respectively connected to the output end of the PWM input signal, the input end of the digital drive circuit, the peak current acquisition circuit, and the output end of the di / dt detection circuit; The output end of the PWM input signal transmits the SiC MOSFET drive signal to the FPGA for processing. The input end of the digital drive circuit receives the digital drive circuit control signal output by the FPGA. The peak acquisition circuit receives the control signal output by the FPGA and outputs a digital signal to the FPGA for processing. The generated junction temperature data is then output. The output end of the di / dt detection circuit outputs a digital signal to the FPGA to adjust the control logic of the digital drive circuit.

[0008] The digital drive circuit is connected to the gate of the SiC MOSFET to be tested and one end of the sampling resistor. The digital drive circuit includes a switching device, which includes one or more of a bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a gate drive chip. The digital drive circuit receives a control signal input from the FPGA and controls the switching device to turn on and off to achieve segmented control of the gate resistor value in the digital drive circuit, thereby adjusting the gate peak current of the SiC MOSFET to be tested in different switching stages.

[0009] The di / dt detection circuit is connected to the power source of the SiC MOSFET device under test. The di / dt detection circuit determines the switching phase of the SiC MOSFET device under test by detecting the rate of change of the drain current of the SiC MOSFET under test. In response to the detected current change, the di / dt detection circuit generates a trigger signal and transmits it to the trigger signal input port of the FPGA.

[0010] The peak current acquisition circuit is connected to both ends of the sampling resistor respectively, and the peak current acquisition circuit includes a differential amplifier, a peak holding circuit, and an analog-to-digital converter ADC.

[0011] The differential amplifier extracts the transient narrow pulse peak voltage signal across the sampling resistor and amplifies the voltage signal; the peak hold circuit includes a diode and an analog switch, and the peak hold circuit maintains the narrow pulse peak voltage signal as a stable square wave signal.

[0012] The analog-to-digital converter (ADC) converts the square wave signal into a digital signal and outputs it to the FPGA. At the same time, the peak hold circuit receives the control signal output by the FPGA to control the timing charge and discharge of the holding capacitor in the peak current acquisition circuit to maintain the normal operation of the peak current acquisition circuit.

[0013] The sampling resistor is connected to the auxiliary source of the SiC MOSFET to be tested. The sampling resistor converts the gate peak current of the SiC MOSFET to be tested into a voltage signal so that the peak current acquisition circuit can collect the current.

[0014] The beneficial effects of the present invention are: The present invention discloses an online SiC MOSFET junction temperature monitoring circuit system based on the gate peak current method. The system controls the switching logic of a digital drive circuit through an FPGA to achieve segmented control of the SiC MOSFET gate resistance and drive voltage switching. When the PWM input signal is high, the digital drive circuit operates in a gate-resistance-free state. At this time, the peak current acquisition circuit operates, collecting the gate peak current magnitude at this time and sending it to the FPGA for processing. Because the gate peak current occurs during the SiC MOSFET switching delay phase, the di / dt detection circuit determines the rate of change of the drain current of the SiC MOSFET device under test. When the device is in the current rise phase, the digital drive circuit switches to a normal gate resistance state. As the gate peak current is a temperature-sensitive electrical parameter, its sensitivity decreases as the gate resistance increases. Therefore, this control logic and digital drive structure can significantly improve the sensitivity of the gate peak current as a temperature-sensitive electrical parameter, while simplifying the drive power supply design and efficiently driving the SiC MOSFET device.

[0015] In addition, the present invention uses a sampling resistor instead of the traditional acquisition method of directly acquiring the differential voltage across the gate resistor, effectively avoiding the strong interference problem faced by signal acquisition in the high common-mode voltage area in the gate loop, and further improving the accuracy of the acquisition circuit.

[0016] In summary, the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method provided by the present invention has high sensitivity, high monitoring accuracy and strong anti-interference capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the circuit connection of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention; Figure 2 Schematic diagram of an RLC second-order network obtained by mathematically modeling the gate loop of a SiC MOSFET to be tested in Example 2 of the present invention; Figure 3 1 is a schematic diagram of the circuit structure of a digital driving circuit according to embodiment 4 of the present invention; Figure 4 4 is a waveform diagram of a control signal of a digital drive circuit according to a fourth embodiment of the present invention; Figure 5 1 is a schematic diagram of the circuit structure of a peak current acquisition circuit according to Embodiment 5 of the present invention; Figure 6 2 is a schematic diagram of the circuit structure of the di / dt detection circuit according to embodiment 6 of the present invention. DETAILED DESCRIPTION

[0018] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] Example 1 This embodiment provides a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method. The system is connected to a SiC MOSFET to be tested for junction temperature monitoring. The system includes a field-programmable gate array (FPGA), a digital drive circuit, a di / dt detection circuit, a peak current acquisition circuit, and a sampling resistor. The FPGA is connected to an output terminal of a PWM input signal. The FPGA dynamically adjusts the driving logic of the digital drive circuit by receiving the trigger signal from the di / dt detection circuit and the PWM input signal. After obtaining the valid output data from the peak acquisition circuit, the junction temperature data processing module inside the FPGA analyzes and processes the data in real time, and finally outputs the junction temperature information of the SiC MOSFET device.

[0020] This embodiment only represents a preferred implementation of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention. Any SiC MOSFET junction temperature online monitoring circuit system designed with similar technical features to the present invention will fall within the protection scope of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention.

[0021] Example 2 This embodiment provides a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method, which is connected to the SiC MOSFET to be tested to monitor the junction temperature. Figure 1 As shown, it includes FPGA, digital drive circuit, di / dt detection circuit, peak current acquisition circuit and sampling resistor R G(meas) , the FPGA is connected to the output terminal of the PWM input signal; The FPGA is respectively connected to the output end of the PWM input signal, the input end of the digital drive circuit, the peak current acquisition circuit, and the output end of the di / dt detection circuit; The output end of the PWM input signal transmits the SiC MOSFET drive signal to the FPGA for processing. The input end of the digital drive circuit receives the digital drive circuit control signal output by the FPGA. The peak acquisition circuit receives the control signal output by the FPGA and outputs a digital signal to the FPGA for processing. The generated junction temperature data is then output. The output end of the di / dt detection circuit outputs a digital signal to the FPGA to adjust the control logic of the digital drive circuit.

[0022] The digital drive circuit is connected to the gate of the SiC MOSFET to be tested and one end of the sampling resistor. The digital drive circuit includes a switching device, which includes one or more of a bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a gate drive chip. The digital drive circuit receives a control signal input from the FPGA and controls the switching device to turn on and off to achieve segmented control of the gate resistor value in the digital drive circuit, thereby adjusting the gate peak current of the SiC MOSFET to be tested in different switching stages.

[0023] The di / dt detection circuit is connected to the power source of the SiC MOSFET device under test. The di / dt detection circuit determines the switching phase of the SiC MOSFET device under test by detecting the rate of change of the drain current of the SiC MOSFET under test. In response to the detected current change, the di / dt detection circuit generates a trigger signal and transmits it to the trigger signal input port of the FPGA.

[0024] The peak current acquisition circuit is connected to both ends of the sampling resistor respectively, and the peak current acquisition circuit includes a differential amplifier, a peak hold circuit, and an analog-to-digital converter ADC (Analog-to-Digital Converter).

[0025] The sampling resistor is connected to the auxiliary source of the SiC MOSFET to be tested. The sampling resistor converts the gate peak current of the SiC MOSFET to be tested into a voltage signal so that the peak current acquisition circuit can collect the current.

[0026] The gate loop of the SiC MOSFET to be tested is mathematically modeled to obtain the following Figure 2 The diagram of a second-order RLC network is shown in Figure 1, where R in RLC represents resistance, L represents inductance, and C represents capacitance. Figure 2 As shown, R Q(on) is the total on-resistance of the switching devices in the digital drive circuit, R G(int) is the gate internal resistance of the SiC MOSFET to be tested, L G is the gate parasitic inductance, C GS is the gate-source parasitic capacitance, V G is the gate voltage. Since the parasitic inductance in the gate loop is extremely small, this second-order network model can be simplified to a first-order RC network model by ignoring it. The gate peak current I G(peak) It can be expressed as the following formula:

[0027] SiC MOSFET gate peak current I G(peak) The peak voltage across the sampling resistor is collected during the on-state of the SiC MOSFET under test, and the gate peak current is accurately measured based on the linear relationship between this voltage and the gate peak current. Based on this principle, the real-time changes in the junction temperature of the SiC MOSFET under test can be indirectly determined by monitoring the dynamic changes in the gate peak current of the SiC MOSFET under test.

[0028] This embodiment only represents a preferred implementation of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention. Any SiC MOSFET junction temperature online monitoring circuit system designed with similar technical features to the present invention will fall within the protection scope of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention.

[0029] Example 3 This embodiment provides a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method. Based on Example 2, a differential amplifier extracts the transient narrow pulse peak voltage signal across the sampling resistor and amplifies the voltage signal. A peak hold circuit includes a diode and an analog switch, and the peak hold circuit maintains the narrow pulse peak voltage signal as a stable square wave signal. The ADC converts the square wave signal into a digital signal and outputs it to the FPGA. At the same time, the peak hold circuit receives a control signal output by the FPGA to control the timing charging and discharging of the holding capacitor in the peak current acquisition circuit to maintain normal operation of the peak current acquisition circuit.

[0030] This embodiment only represents a preferred implementation of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention. Any SiC MOSFET junction temperature online monitoring circuit system designed with similar technical features to the present invention will fall within the protection scope of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention.

[0031] Example 4 This embodiment provides a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method. Based on the embodiment 2-3, as shown in FIG. Figure 3 As shown, the digital driving circuit includes a resistor R1, a resistor R2, a switching device Q1, a switching device Q2, a switching device Q3, a switching device Q4, and a switching device Q5.

[0032] Among them, CTRL1, CTRL2, CTRL3, CTRL4, and CTRL5 are all FPGA output ports. CTRL1 is connected to the control end of the switching device Q1, CTRL2 is connected to the control end of the switching device Q2, CTRL3 is connected to the control end of the switching device Q3, CTRL4 is connected to the control end of the switching device Q4, and CTRL5 is connected to the control end of the switching device Q5. One end of Q1 is connected to the power supply voltage +VCC_H, and the other end of Q1 is connected to the gate G of the SiC MOSFET. One end of Q2 is connected to the power supply voltage +VCC_H, and the other end of Q2 is connected to one end of R1, and the other end of R1 is connected to the gate G of the SiC MOSFET. One end of Q3 is connected to one end of R2, and the other end of Q3 is grounded. The other end of R2 is connected to the gate G of the SiC MOSFET. One end of Q4 is connected to the power supply voltage +VCC_L, and the other end of Q4 is connected to one end of the sampling resistor S_R. One end of Q5 is connected to one end of the sampling resistor S_R, and the other end of Q5 is grounded.

[0033] The switching device includes, but is not limited to, at least one of a bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a gate driver chip. Taking a bipolar transistor as an example, if the switching device is a bipolar transistor, the control terminal is the base of the bipolar transistor, one terminal of the switching device is the collector of the bipolar transistor, and the other terminal of the switching device is the emitter of the bipolar transistor. When CTRL1 and CTRL5 are high, the driving voltage of the digital drive circuit is +VCC_H, and it is in a gate-resistor-free working state; when CTRL2 and CTRL5 are high, the driving voltage of the digital drive circuit is +VCC_H, and the gate resistor is R1; when CTRL3 and CTRL4 are high, the driving voltage of the digital drive circuit is -VCC_L, and the gate resistor is R2. This circuit structure not only uses the positive power supply voltage to generate a negative driving voltage, but also realizes segmented control of the gate resistor value in the digital drive circuit.

[0034] like Figure 4 The figure shows the waveforms of the control signals of the digital drive circuit. PWM is the drive input signal, Trig is the trigger signal output by the di / dt detection circuit, CTRL1 is the control signal for switching device Q1, CTRL2 is the control signal for switching device Q2, CTRL4 is the control signal for switching device Q4, and CTRL5 is the control signal for switching device Q5. When PWM transitions from high to low, CTRL3 and CTRL4 transition from low to high, CTRL2 and CTRL5 transition from high to low, and CTRL1 remains low. When PWM transitions from low to high, CTRL1 and CTRL5 transition from low to high, CTRL3 and CTRL4 transition from high to low, and CTRL2 remains low. When PWM is high and Trig transitions from high to low, or when PWM is high and Trig transitions from low to high, CTRL1 transitions from high to low, CTRL2 transitions from low to high, CTRL3 and CTRL4 remain low, and CTRL5 remains high.

[0035] Figure 4 The digital drive circuit control logic can effectively improve the sensitivity of the junction temperature acquisition circuit, simplify the drive power supply design, and drive SiC MOSFET with high efficiency.

[0036] This embodiment only represents a preferred implementation of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention. Any SiC MOSFET junction temperature online monitoring circuit system designed with similar technical features to the present invention will fall within the protection scope of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention.

[0037] Example 5 This embodiment provides a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method. Based on the embodiments 2-4, as shown in FIG. Figure 5 As shown, the peak current acquisition circuit includes: resistor R3, capacitor C1, diode D1, diode D2, analog switch K1, operational amplifier U1, operational amplifier U2, operational amplifier U3, and analog-to-digital converter ADC. Among them, the SiC MOSFET auxiliary source s is connected to the non-inverting end of U1, one end S_R of the sampling resistor is connected to the reverse end of U1, the output of U1 is connected to the non-inverting end of U2, one end of R3 and the cathode of D1 are simultaneously connected to the reverse end of U2, the other end of R3 is connected to the power supply voltage VEE, the output of U2 is simultaneously connected to the anode of D1 and the anode of D2, the cathode of D2 is simultaneously connected to one end of C1, the positive end of K1, and the non-inverting input of U3, the other end of C1 and the negative end of K1 are grounded, the control end of K1 is connected to the CTRL6 pin of the FPGA, the reverse end of U3 is connected to the input of the ADC and the output of U3, and the output of the ADC is finally connected to the FPGA.

[0038] During the SiC MOSFET turn-on delay phase, the gate current reaches its peak value. U1 forms a differential amplifier, which connects the sampling resistor R G(meas) The peak differential voltage signals on both sides are converted into single-ended signals for easy processing by subsequent circuits. After receiving the peak signal output by U1, U2 charges C1. D2 prevents capacitor C1 from leaking to the output of U2. By configuring a matching diode in the local feedback loop of U2, the voltage drop of D2 is compensated. R3 is used to set the bias current in D1, which will enable the voltage drop of D1 to offset the voltage drop of D2, minimizing the acquisition error. U3 constitutes a voltage follower with high input impedance, which effectively reduces the leakage current of C1. At the same time, its low output impedance can well drive the ADC. The ADC converts the maintained peak voltage signal into a digital signal for subsequent processing by the FPGA junction temperature data processing module.

[0039] When PWM is at a low level, the FPGA CTRL6 pin outputs a high-level signal to turn on K1, controlling C1 to discharge so that the acquisition circuit can work normally in the next signal cycle.

[0040] This embodiment only represents a preferred implementation of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention. Any SiC MOSFET junction temperature online monitoring circuit system designed with similar technical features to the present invention will fall within the protection scope of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention.

[0041] Example 6 This embodiment provides a SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method. Based on the embodiments 2-5, as shown in FIG. Figure 6 As shown, the di / dt detection circuit includes a resistor R4, a resistor R5, a diode D3, a diode D4, and a voltage comparator U4.

[0042] Among them, one end of R4 is connected to the SiC MOSFET power source S, the other end of R4 is connected to one end of the resistor R5, the cathode of D4, and the same-direction end of U4, the other end of R5 and the cathode of D3 are simultaneously connected to the power supply voltage +VCC_L, the anode of D4 is grounded, and the reference voltage V REF Connected to the reverse end of U4, the output of U4 is connected to the FPGA.

[0043] When the drain current of SiC MOSFET is in the rising stage, due to the existence of the source parasitic inductance of the device, a negative induced voltage will be generated at the power source end. In order to effectively suppress the negative voltage effect, the circuit applies a +VCC_L positive bias voltage through resistor R5. This bias voltage is equal to the negative terminal reference voltage V of the comparator U4. REF It constitutes a threshold comparison mechanism. When the source terminal voltage exceeds V REF When , it triggers the comparator U4 output level to flip from high to low. R4 is a current limiting resistor. D3 and D4 clamp the U4 input voltage to +VCC_L to GND to prevent excessive input voltage from damaging U4.

[0044] This embodiment only represents a preferred implementation of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention. Any SiC MOSFET junction temperature online monitoring circuit system designed with similar technical features to the present invention will fall within the protection scope of the SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method of the present invention.

Claims

1. A SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method is connected to the SiC MOSFET to be tested to monitor the junction temperature, characterized in that: It includes an FPGA, a digital drive circuit, a di / dt detection circuit, a peak current acquisition circuit and a sampling resistor, wherein the FPGA is connected to the output end of the PWM input signal; The FPGA dynamically adjusts the driving logic of the digital drive circuit by receiving the trigger signal of the di / dt detection circuit and the PWM input signal. After obtaining the valid output data of the peak acquisition circuit, the junction temperature data processing module inside the FPGA analyzes and processes the data in real time, and finally outputs the junction temperature information of the SiC MOSFET.

2. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 1, characterized in that: The FPGA is respectively connected to the output end of the PWM input signal, the input end of the digital drive circuit, the peak current acquisition circuit, and the output end of the di / dt detection circuit; After the output end of the PWM input signal transmits the SiC MOSFET drive signal to the FPGA for processing, the input end of the digital drive circuit receives the digital drive circuit control signal output by the FPGA. The peak acquisition circuit receives the control signal output by the FPGA and outputs a digital signal to the FPGA for processing, generating junction temperature data and outputting it. The output end of the di / dt detection circuit outputs a digital signal to the FPGA to adjust the control logic of the digital drive circuit.

3. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 1, characterized in that: The digital drive circuit is connected to the gate of the SiC MOSFET to be tested and one end of the sampling resistor. The digital drive circuit includes a switching device, which includes one or more of a bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a gate drive chip. The digital drive circuit receives a control signal input by the FPGA and controls the switching device to turn on and off, thereby achieving segmented control of the gate resistance value in the digital drive circuit, thereby adjusting the gate peak current of the SiC MOSFET to be tested in different switching stages.

4. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 1, characterized in that: The di / dt detection circuit is connected to the power source of the SiC MOSFET device to be tested. The di / dt detection circuit determines the switching phase of the SiC MOSFET device to be tested by detecting the rate of change of the drain current of the SiC MOSFET to be tested. The di / dt detection circuit generates a trigger signal in response to the detected current change and transmits the trigger signal to the FPGA trigger signal input port.

5. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 1, characterized in that: The peak current acquisition circuit is connected to both ends of the sampling resistor respectively, and the peak current acquisition circuit includes a differential amplifier, a peak holding circuit, and an analog-to-digital converter ADC.

6. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 5, characterized in that: The differential amplifier extracts the transient narrow pulse peak voltage signal across the sampling resistor and amplifies the voltage signal; the peak hold circuit includes a diode and an analog switch, and the peak hold circuit maintains the narrow pulse peak voltage signal as a stable square wave signal.

7. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 5, characterized in that: The analog-to-digital converter ADC converts the square wave signal into a digital signal and outputs it to the FPGA. At the same time, the peak hold circuit receives the control signal output by the FPGA to control the holding capacitor in the peak current acquisition circuit to perform regular charging and discharging to maintain the normal operation of the peak current acquisition circuit.

8. The SiC MOSFET junction temperature online monitoring circuit system based on the gate peak current method according to claim 1, characterized in that: The sampling resistor is connected to the auxiliary source of the SiC MOSFET to be tested, and the sampling resistor converts the gate peak current of the SiC MOSFET to be tested into a voltage signal so that the peak current collection circuit can collect the current.

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