capacitively coupled gate-controlled junction field effect transistor

Abstract

The application provides a capacitor-coupled gate-controlled junction field effect transistor, which comprises a substrate and an epitaxial layer, a drain, a trench formed downward from the upper surface of the epitaxial layer, a gate of a first doping type in a trench type formed on the inner wall and the bottom of the trench, a first source electrode for connecting a source voltage formed above the bottom of the gate, the gate and the first source electrode being connected so as to have the same potential, a dielectric layer in a trench type formed above the first source electrode, a gate electrode filled in the inner wall and the bottom of the dielectric layer, a source region of the first doping type arranged at least at one side of the gate, the source region and the first source electrode each being connected to the source voltage, a channel region of a second doping type formed between the source region and the gate, wherein the source region, the channel region and the structure under the gate serve as a gate-surrounding structure of the second doping type, and the gate and the gate-surrounding structure form a PN junction. The application solves the technical problem of large switching loss and improves the conduction capacity of the body diode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a capacitor-coupled gate-controlled junction field effect transistor. BACKGROUND

[0002] Silicon carbide devices have high voltage resistance, low on-resistance, faster switching speed, higher operating temperature, heat dissipation capacity, and good radiation resistance, and have been widely used in power electronic circuits. Silicon carbide devices include MOSFET and JFET devices. JFET devices, as a kind of three-port device similar to MOSFET, work by using gate voltage to control the reverse bias of PN, thereby achieving the purpose of controlling the opening and closing of the channel. It has the advantages of low noise, small size, and high frequency response. JFET devices made of silicon carbide material can also be used in high-power application scenarios such as new energy vehicles and high-voltage power transmission.

[0003] Silicon carbide capacitor-coupled gate-controlled JFET solves the problem that JFET devices cannot be applied to power (the control gate voltage is too small), and also solves the gate oxide reliability problem of SiC MOSFET, becoming the focus of power device research and development.

[0004] The vertical trench type capacitor-coupled gate-controlled junction field effect transistor of the present patent CN117613098B is shown in FIG. 1, which includes a substrate 1-1, an epitaxial layer 1-2, a second-doped-type ohmic contact region 1-3, a source region 1-4, a channel 1-5, a gate 1-6, a dielectric layer 1-7, a coupling capacitor upper electrode 1-8, a source electrode 1-9, and a drain electrode 1-10. Figure 1

[0005] Power devices are actually switches, so in the application process, switching loss cannot be ignored. The original vertical trench type capacitor-coupled gate-controlled junction field effect transistor does not take this into account, which will result in a larger Miller platform capacitance when setting the gate, increasing the switching loss of the device.

[0006] The device needs to achieve higher voltage resistance under the same epitaxial concentration, which improves the reliability of the device. The original BV (breakdown voltage) of the device needs to be improved from other design aspects.

[0007] Therefore, the switching loss of the traditional capacitor-coupled gate-controlled junction field effect transistor is large, which is a technical problem that needs to be solved by those skilled in the art.

[0008] The above information disclosed in the background art is only used to enhance the understanding of the background of the present application, and therefore it may contain information that is not prior art known to those skilled in the art. SUMMARY ​

[0009] The embodiment of the present application provides a capacitor-coupled gate-controlled junction field effect transistor to solve the technical problem of large switching loss of a conventional capacitor-coupled gate-controlled junction field effect transistor.

[0010] The present application provides a capacitor-coupled gate-controlled junction field effect transistor, comprising:

[0011] a substrate and an epitaxial layer of a second doping type, the epitaxial layer being located on the substrate;

[0012] a trench formed downward from an upper surface of the epitaxial layer;

[0013] a gate of a first doping type in a trench type, formed on an inner wall and a bottom of the trench;

[0014] a first source electrode for connecting a source voltage, formed on a bottom of the gate, the gate and the first source electrode being connected so as to have the same potential;

[0015] a dielectric layer in a trench type, formed on the first source electrode;

[0016] a gate electrode, filled in an inner wall and a bottom of the dielectric layer;

[0017] a source region of the first doping type, at least arranged at one side of the gate; the source region and the first source electrode each being connected to the source voltage;

[0018] a channel region of the second doping type, formed between the source region and the gate;

[0019] wherein the source region, the channel region, and the structure under the gate form a gate-surrounding structure of the second doping type, and the gate and the gate-surrounding structure form a PN junction.

[0020] The embodiment of the present application has the following technical effects due to the above technical solution:

[0021] The gate-drain capacitance Cgd (i.e. Miller plateau capacitance) of the prior art capacitor-coupled gate-controlled junction field-effect transistor is large. The capacitor-coupled gate-controlled junction field-effect transistor of the present application converts part of the Miller capacitance into gate-source capacitance Cgs and drain-source capacitance Cds. Among them, the gate-source capacitance Cgs is the parasitic capacitance between the gate and the source, and the drain-source capacitance Cds is the parasitic capacitance between the drain and the source. Compared with the prior art, the gate-drain capacitance Cgd of the capacitor-coupled gate-controlled junction field-effect transistor of the present application is small, i.e. the gate-drain capacitance Cgd that needs to be overcome during the turn-on and turn-off of the capacitor-coupled gate-controlled junction field-effect transistor of the present application is small, which has a faster turn-on and turn-off speed, and also has a smaller switching loss. The introduction of the built-in first source electrode also improves the turn-on capability of the body diode. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings described herein are intended to provide further understanding of the present application, and form a part of the present application. The schematic embodiments of the present application and the description thereof are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0023] Figure 1 A schematic diagram of the vertical trench capacitor-coupled gate-controlled junction field-effect transistor of the patent CN117613098B;

[0024] Figure 2-1 A schematic diagram of the turn-on of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment;

[0025] Figure 2-2 A schematic diagram of the turn-off of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment;

[0026] Figure 3 A schematic diagram of the preparation method of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment completing step 2;

[0027] Figure 4 A schematic diagram of the preparation method of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment completing step 5;

[0028] Figure 5 A schematic diagram of the preparation method of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment completing step 7;

[0029] Figure 6 A schematic diagram of the preparation method of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment completing step 8;

[0030] Figure 7 A schematic diagram of the preparation method of the capacitor-coupled gate-controlled junction field-effect transistor of the present application embodiment completing step 9;

[0031] Figure 8 Schematic diagram for completing step 10 of the preparation method of the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application;

[0032] Figure 9 Simulation diagram of the on-current density when the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is in forward conduction;

[0033] Figure 10 Curve of the drain-source current Ids varying with the drain-source voltage Vds when the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is in breakdown voltage;

[0034] Figure 11 Simulation diagram of the electric field distribution when the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is in breakdown voltage;

[0035] Figure 12 Curve of the drain-source current Ids varying with the drain-source voltage Vds when the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is in breakdown voltage;

[0036] Figure 13 Simulation diagram of the diode current path being turned off for the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application;

[0037] Figure 14 Curve of the source-drain current Ids varying with the source-drain voltage Vsd when the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off.

[0038] Reference signs:

[0039] In the background art:

[0040] Substrate 1-1, epitaxial layer 1-2, second-doped-type ohmic contact region 1-3, source region 1-4, channel 1-5,

[0041] Gate 1-6,

[0042] Dielectric layer 1-7, coupling capacitor upper electrode 1-8, source 1-9, drain 1-10;

[0043] The present application:

[0044] Source region 1, first-doped-type source contact region 2, second-doped-type source contact region 3,

[0045] Channel region 4, gate 5, dielectric layer 6, gate electrode 7, current guide layer 8, first source electrode 9,

[0046] Epitaxial layer 10, substrate 11, drain 12, second source electrode 13,

[0047] current guide layer base 8-0, source region base 1-0, channel region base 4-0. DETAILED DESCRIPTION

[0048] In order to make the technical solutions and advantages in the embodiments of the present application more clear and explicit, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0049] Embodiment one

[0050] As shown in Figure 2-1 and Figure 2-2 The capacitor-coupled gate-controlled junction field effect transistor of the embodiments of the present application comprises:

[0051] a substrate 11 and an epitaxial layer of a second doping type, the epitaxial layer being located on the substrate;

[0052] a trench formed downward from the upper surface of the epitaxial layer;

[0053] a gate 5 of the first doping type in the form of a trench formed on the inner wall and bottom of the trench;

[0054] a first source electrode 9 for connecting a source voltage formed on the bottom of the gate 5, the gate 5 and the first source electrode 9 being connected so as to be at the same potential;

[0055] a dielectric layer 6 in the form of a trench formed on the first source electrode 9;

[0056] a gate electrode 7 for connecting a gate voltage filled in the inner wall and bottom of the dielectric layer;

[0057] a source region 1 of the first doping type at least spaced apart on one side of the gate 5; the source region 1 and the first source electrode 9 are each connected to a source voltage;

[0058] a channel region 4 of the second doping type formed between the source region 1 and the gate 5;

[0059] wherein the structure below the source region 1, the channel region 4 and the gate 5 serves as a gate-surrounding structure of the second doping type, and the gate 5 and the gate-surrounding structure form a PN junction.

[0060] In the implementation, the source region 1 and the structure below the source region 1 form a PN junction. Specifically, there are at least two implementation modes:

[0061] The first implementation manner is that the source region 1 and the substrate 11 are both epitaxial layers, and the source region 1 and a part of the epitaxial layer below the source region 1 form a PN junction.

[0062] The second implementation manner is that the field effect transistor further comprises:

[0063] A current guide layer 8 of a second doping type is formed in the epitaxial layer below the source region 1, the channel region 4 and the gate 5; correspondingly, the source region 1 and the current guide layer 8 form a PN junction.

[0064] In the implementation, the source region 1 of the first doping type is two, and the two source regions 1 of the first doping type are respectively arranged on the two sides of the gate 5.

[0065] The channel region 4 is two, and is respectively formed between the two source regions 1 and the channel region 4.

[0066] The gate-drain capacitance Cgd (i.e. Miller platform capacitance) of the prior art capacitive coupled gate-controlled junction field effect transistor is large. The capacitive coupled gate-controlled junction field effect transistor of the application converts part of the Miller capacitance into gate-source capacitance Cgs and drain-source capacitance Cds. The gate-source capacitance Cgs is the parasitic capacitance between the gate and the source, and the drain-source capacitance Cds is the parasitic capacitance between the drain and the source. Compared with the prior art, the gate-drain capacitance Cgd of the capacitive coupled gate-controlled junction field effect transistor of the embodiment of the application is small, that is, the capacitive coupled gate-controlled junction field effect transistor of the embodiment of the application needs to overcome a smaller gate-drain capacitance Cgd in the process of turning on and turning off, has a faster turn-on and turn-off speed, and has a smaller switching loss. The introduction of the built-in first source electrode also improves the turn-on capability of the body diode.

[0067] The source region 1 of the capacitive coupled gate-controlled junction field effect transistor of the embodiment of the application is connected to the source voltage, and the first source electrode 9 is also connected to the source voltage, and the gate 5 and the first source electrode 9 are connected to have the same potential. In this way, the gate 5 is no longer in a floating state, but has the same potential as the first source electrode 9.

[0068] When the capacitive coupled gate-controlled junction field effect transistor of the embodiment of the application is turned off, the diode current path is as shown in Figure 2-2

[0069] The diode current path ① formed by the PN junction formed by the source region 1 and the structure below the source region 1;

[0070] The diode current path ② formed by the PN junction formed by the side wall of the gate 5 and the structure outside the side wall of the gate 5;

[0071] ​The PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5 forms a diode current path ③.

[0072] In the diode current path ② and the diode current path ③, the structure outside the sidewall of the gate 5 and the structure outside the bottom of the gate 5 are connected to the drain electrode, and are connected through the epitaxial layer 10, the substrate 11 and the drain 12, because the gate 5 and the first source electrode 9 are at the same potential, that is, both are connected to the source voltage.

[0073] In the diode current path ①, the source region 1 is connected to the source voltage, and the structure below the source region 1 is connected to the drain electrode, and is connected through the epitaxial layer 10, the substrate 11 and the drain 12.

[0074] Therefore, the diode current paths are more, not only the body diode (that is, the PN junction formed by the source region 1 and the structure below the source region 1) can withstand voltage; but also the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5, and the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5 can withstand voltage. In this way, the requirement for the voltage resistance of the body diode is reduced.

[0075] In the field of semiconductor technology, under certain temperature conditions, the minority carrier concentration determined by intrinsic excitation is certain, so the drift current formed by the minority carrier is constant, and basically has nothing to do with the size of the negative voltage. This current is also called diode current. That is, the total diode current in the application has nothing to do with the size of the negative voltage. The total diode current is divided into more separate diode current paths

[0076] When the capacitor-coupled gate-controlled junction field-effect transistor of the embodiment of the application is turned off,

[0077] The depletion region of the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5 is widened, the electric field at the channel region 4 is reduced, and lateral depletion is achieved to withstand a larger potential difference;

[0078] The depletion region of the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5 is widened, the electric field at the channel region 4 is reduced, and vertical depletion is achieved to withstand a larger potential difference.

[0079] That is, the PN junction at the lower corner of the gate 5 (the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5, and the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5) has a wider depletion region. At the same time, the electric field falling on the epitaxial layer is more balanced, and the breakdown voltage of the device can also be effectively improved.

[0080] When the capacitor-coupled gate-controlled junction field-effect transistor of the embodiment of the application is turned off,

[0081] The depletion region of the PN junction formed by the sidewalls of gate 5 and the structure outside the sidewalls of gate 5 is widened, reducing the electric field at channel region 4 and achieving lateral depletion to withstand a larger potential difference.

[0082] The depletion region of the PN junction formed by the bottom of gate 5 and the structure outside the bottom of gate 5 is widened, reducing the electric field at channel region 4, achieving vertical depletion, and thus being able to withstand a larger potential difference.

[0083] In implementation, the source region 1, the channel region 4, and the gate 5 form a first JFET structure. The first JFET structure is controlled by the gate 5, and the opening and closing of the channel region 4 is controlled by the depletion region of the PN junction formed by the channel region 4 and the gate 5.

[0084] The PN junction formed by the channel region 4 and the gate 5, the dielectric layer 6 and the gate electrode 7 form a capacitively coupled gate-controlled second JFET structure. The second JFET structure is indirectly controlled by the gate electrode 7. The gate electrode 7 indirectly controls the depletion region of the PN junction formed by the channel region 4 and the gate 5 through the dielectric layer 6, thereby turning the channel region 4 on and off.

[0085] Thus, when a capacitively coupled gate-controlled junction field-effect transistor is turned on, as Figure 2-1 As shown, in the first JFET structure, the gate 5 and in the second JFET structure, the gate electrode 7 together shrink the depletion region of the PN junction formed by the channel region 4 and the gate 5, enabling the field-effect transistor to conduct rapidly in the forward direction.

[0086] When the capacitively coupled gate-controlled junction field-effect transistor is turned off, and the PN junction formed by the source region 1 and the channel region 4 and the PN junction formed by the channel region 4 and the gate 5 are reverse biased, the channel region is depleted, the device is turned off, and the PN junction reduces the potential at the bottom of the channel region 4, thereby reducing the leakage current.

[0087] In addition, the gate 5 is located outside the dielectric layer 6, and the dielectric layer 6 surrounds the gate 5. This arrangement solves the reliability problems caused by the gate oxide layer, and avoids the electrical characteristic drift such as VTH drift that occurs in MOSFETs; it also avoids the stress breakdown problem of the gate oxide layer over a long period of time, thus greatly improving reliability.

[0088] That is, the first JFET structure is directly controlled by the gate 5, resulting in higher control stability. Compared with the prior art, in this application, the first JFET structure is directly controlled by the gate 5, while the second JFET structure is indirectly controlled by the gate electrode 7.

[0089] During implementation, such as Figure 2-1 and Figure 2-2 As shown, the doping concentration of the current guiding layer 8 is greater than the doping concentration of the epitaxial layer 10;

[0090] The PN junction formed by the gate 5 and the gate-surrounding structure is specifically a PN junction formed by the current guide layer 8 and the gate 5.

[0091] The current guide layer 8 makes the on-resistance small.

[0092] In the implementation, as shown in Figure 2-1 and Figure 2-2 , the upper surface of the first source electrode 9 is lower than the bottom of the channel region 4, so that the bottom of the gate 5 is lower than the bottom of the channel region 4.

[0093] In the implementation, as shown in Figure 2-1 and Figure 2-2 , the lower bottom surface of the source region 1 is lower than the lower bottom surface of the channel region 4.

[0094] That is, the lower surface of the gate 5 and the lower surface of the source region 1 are both lower than the lower surface of the channel region 4. The pinch-off of the first JFET structure formed by the source region 1, the channel region 4 and the gate 5 is facilitated, so that the opening and closing of the channel region 4 are controlled.

[0095] In the implementation, as shown in Figure 2-1 and Figure 2-2 , the field effect transistor further comprises:

[0096] two first-doped-type source contact regions 2 respectively connected to the two source regions 1;

[0097] two second-doped-type source contact regions 3 respectively connected to the two channel regions 4, and the second-doped-type source contact regions 3 and the first-doped-type source contact regions 2 on the same side are connected;

[0098] two second source electrodes 13 respectively located on the two first-doped-type source contact regions 2, and the second source electrodes 13 on the same side are connected to the first-doped-type source contact regions 2 and the second-doped-type source contact regions 3 on the same side.

[0099] The first source electrode 9 and the second source electrode 13 are connected, so that the first source electrode 9 is connected to the source voltage.

[0100] Figure 9 A simulation diagram of the on-current density when the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is in forward conduction.

[0101] Figure 10 A curve of the drain-source current Ids of the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application varying with the drain-source voltage Vds when the capacitor-coupled gate-controlled junction field effect transistor is in forward conduction. Figure 10 In the implementation, the abscissa is the drain-source voltage Vds, and the unit is V; the ordinate is the drain-source current Ids, and the unit is A.

[0102] FromFigure 10 As can be seen from the above, when the capacitively coupled gate-controlled junction field-effect transistor of this application is forward-biased, the drain-source current Ids changes linearly with the drain-source voltage Vds.

[0103] Figure 11 This is a simulation diagram of the electric field distribution under the breakdown voltage of a capacitively coupled gate-controlled junction field-effect transistor according to an embodiment of this application.

[0104] Figure 12 The curves showing the change of drain-source current Ids with drain-source voltage Vds at the breakdown voltage of the capacitively coupled gate-controlled junction field-effect transistor according to an embodiment of this application are shown. Figure 12 The horizontal axis represents the drain-source voltage Vds, in volts (V); the vertical axis represents the drain-source current Ids, in amperes (A).

[0105] from Figure 11 As can be seen from the diagram, the electric field position under breakdown voltage is far from the channel region 4 and located at the corner of the gate 5. That is, under reverse bias, the PN junction formed by the source region 1 and the channel region 4, the PN junction formed by the channel region 4 and the gate 5, and the PN junction formed by the gate 5 and the current guiding layer 8 reduces the potential at the bottom of the channel region 4.

[0106] from Figure 12 As can be seen from the present application, in the capacitively coupled gate-controlled junction field-effect transistor of this application, the drain-source current Ids suddenly increases when the drain-source voltage Vds reaches the breakdown voltage.

[0107] Figure 13 This is a simulation diagram of the current path of the body diode of a capacitively coupled gate-controlled junction field-effect transistor according to an embodiment of this application.

[0108] Figure 14 The curves showing the change of source-current Ids with source-drain voltage Vsd for the capacitively coupled gate-controlled junction field-effect transistor in this application are shown. Figure 14 The horizontal axis represents the source-drain voltage Vsd, in volts (V); the vertical axis represents the source-drain current Isd, in amperes (A).

[0109] from Figure 13 As can be seen from the above, the diode current path ① is formed by the PN junction formed by the source region 1 and the structure below the source region 1;

[0110] The diode current path formed by the PN junction formed by the sidewall of gate 5 and the structure outside the sidewall of gate 5;

[0111] The diode current path formed by the PN junction formed by the bottom of gate 5 and the structure outside the bottom of gate 5.

[0112] from Figure 14It can be seen that, in the process that the source-drain current Isd increases from zero to the source voltage, the source-drain current Isd increases rapidly when the source-drain voltage Vsd approaches the source voltage. The reason is that the diode current paths ①, ② and ③ jointly act.

[0113] Specifically, the doping concentration of the source region 1 is greater than or equal to 10 17 cm 3 and less than or equal to 10 18 cm 3 .

[0114] The doping concentration of the first-doped-type source contact region 2 is greater than or equal to 10 18 cm 3 .

[0115] The preparation method of the capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the application comprises the following steps:

[0116] Step 1: After the epitaxy is prepared, the N-type ion implantation is performed based on the hard mask to form a current guide layer base 8-0;

[0117] Step 2: The P-type ion implantation is performed based on the hard mask to form a source region base 1-0; as Figure 3 shown;

[0118] Step 3: The second N-type ion implantation is performed based on the hard mask to form a partial channel region base 4-0;

[0119] Step 4: The third N-type ion implantation is performed based on the hard mask to form a second-doped-type source contact region 3 of N type;

[0120] Step 5: The P-type ion implantation is performed based on the hard mask to form a first-doped-type source contact region 2 of P type; as Figure 4 shown;

[0121] Step 6: Etching to form a trench 14;

[0122] Step 7: Based on the mask, the ion implantation is performed to form a heavily doped gate 5 of P type at the bottom and sidewall of the trench 14; impurity annealing is performed to activate the ion implantation; as Figure 5 shown;

[0123] Step 8: Depositing a first source electrode 9, the thickness of the first source electrode 9 is in a range of 300 nanometers to 500 nanometers; as Figure 6 shown;

[0124] Step 9: depositing a dielectric layer 6 having a bottom thickness in a range of greater than or equal to 50 nm and less than or equal to 80 nm and a sidewall thickness in a range of greater than or equal to 30 nm and less than or equal to 60 nm; as shown in Figure 7 ;

[0125] Step 10: depositing a second source electrode 13 based on the mask; as shown in Figure 8 .

[0126] Those skilled in the art will understand that embodiments of the present application can be provided as methods, systems, or computer program products. Thus, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer readable program code.

[0127] The present application is described in reference to the flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams block or blocks. Figure 1 The flowchart illustrations and / or block diagrams Figure 1 illustrate the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0128] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams block or blocks. Figure 1 The flowchart illustrations and / or block diagrams Figure 1 illustrate the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0129] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams block or blocks. Figure 1 The flowchart illustrations and / or block diagrams Figure 1 illustrate the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0130] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all such variations and modifications as are included within the spirit and scope of the application.

[0131] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A capacitively coupled gate-controlled junction field effect transistor, characterized by The application relates to a capacitor-coupled gate-controlled junction field effect transistor, comprising: a substrate (11) and an epitaxial layer of a second doping type, the epitaxial layer being located on the substrate, and a drain (12) located on the back side of the substrate; a trench formed downward from the upper surface of the epitaxial layer; a gate (5) of a first doping type in the form of a trench formed on the inner wall and bottom of the trench; a first source electrode (9) for connecting a source voltage formed on the bottom of the gate (5), the gate (5) and the first source electrode (9) being connected so as to be at the same potential; a dielectric layer (6) in the form of a trench formed on the first source electrode (9); a gate electrode (7) filled in the inner wall and bottom of the dielectric layer; a source region (1) of the first doping type arranged at least at one side of the gate (5); the source region (1) and the first source electrode (9) each being connected to a source voltage; a channel region (4) of the second doping type formed between the source region (1) and the gate (5); wherein the structure below the source region (1), the channel region (4) and the gate (5) is a gate-surrounding structure of the second doping type, and the gate (5) and the gate-surrounding structure form a PN junction. The source region (1) and the part of the epitaxial layer below the source region (1) form a PN junction. The source region (1) of the first doping type is two, and the two source regions (1) of the first doping type are arranged at two sides of the gate (5) respectively. The channel region (4) is two, and the two channel regions (4) are formed between the two source regions (1) and the gate (5) respectively. When the capacitor-coupled gate-controlled junction field effect transistor is turned off, the PN junction formed by the gate (5) and the gate-surrounding structure forms a diode current path; the PN junction formed by the source region (1) and the structure below the source region (1) forms a diode current path. The source region (1), the channel region (4) and the gate (5) form a first JFET structure, and the first JFET structure is controlled by the gate (5) and the depletion region of the PN junction formed by the channel region (4) and the gate (5) to control the opening and closing of the channel region (4). The PN junction formed by the channel region (4) and the gate (5), the dielectric layer (6) and the gate electrode (7) form a second JFET structure of the capacitor-coupled gate-controlled, and the second JFET structure is indirectly controlled by the gate electrode (7), and the gate electrode (7) indirectly controls the depletion region of the PN junction formed by the channel region (4) and the gate (5) through the dielectric layer (6) to control the opening and closing of the channel region (4). When the capacitor-coupled gate-controlled junction field effect transistor is turned on, the gate (5) in the first JFET structure and the gate electrode (7) in the second JFET structure jointly shrink the depletion region of the PN junction formed by the channel region (4) and the gate (5), so that the field effect transistor is rapidly turned on in the positive direction. ​ ​ 2. The field effect transistor of claim 1, wherein ​ 3. The field effect transistor of claim 2, wherein ​ ​ 4. The field effect transistor of claim 3, wherein ​ ​ ​ 5. The field effect transistor of claim 4, wherein, ​ ​ 6. The field effect transistor of claim 5, wherein ​ When the capacitor-coupled gate-controlled junction field effect transistor is turned off, and the PN junction formed by the source region (1) and the channel region (4) and the PN junction formed by the channel region (4) and the gate (5) are reverse-biased, the channel region is depleted, the device is turned off, and the PN junction reduces the potential at the bottom of the channel region (4), thereby reducing the leakage current.

7. The field effect transistor according to any one of claims 2 to 6, characterized in that Further comprising: a current guiding layer (8) of a second doping type formed in the epitaxial layer at a position below the source region (1), the channel region (4) and the gate (5), the source region (1) and the current guiding layer (8) forming a PN junction; wherein the doping concentration of the current guiding layer (8) is greater than the doping concentration of the epitaxial layer (10); the PN junction formed by the gate (5) and the structure around the gate is specifically a PN junction formed by the current guiding layer (8) and the gate (5).

8. The field effect transistor of claim 7, wherein, The upper surface of the first source electrode (9) is lower than the bottom of the channel region (4), so that the bottom of the gate (5) is lower than the bottom of the channel region (4). The lower surface of the source region (1) is lower than the bottom of the channel region (4).

9. The field effect transistor of claim 7, wherein, The lower surface of the source region (1) is lower than the lower surface of the channel region (4).

10. The field effect transistor of claim 7, wherein, Further comprising: two first-doped-type source contact regions (2) respectively connected to the two source regions (1); two second-doped-type source contact regions (3) respectively connected to the two channel regions (4), and the second-doped-type source contact regions (3) and the first-doped-type source contact regions (2) on the same side are connected; two second source electrodes (13) respectively located on the two first-doped-type source contact regions (2), and the second source electrodes (13) on the same side connect the first-doped-type source contact regions (2) and the second-doped-type source contact regions (3) on the same side.

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