Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer. The semiconductor layer has opposite first and second surfaces. The semiconductor layer includes a source region and a gate region. The source region comprises an N-type source region, a first P-type body layer and a carrier storage layer. The gate region includes a gate oxide layer and polysilicon. And the side wall and the bottom of the polycrystalline silicon are surrounded by the gate oxide layer. The source region is disposed between two adjacent gate regions and contacts the gate oxide layers of the two adjacent gate regions. In the gate region, the gate oxide layer extends from a depth at which the top of the N-type source region is located to a first depth relative to the first surface. The bottom of the polysilicon is away from the first surface and at a second depth. A portion of the gate oxide layer from the top of the gate oxide layer to the third depth has a constant lateral thickness. The portion of the gate oxide layer from the third depth to the second depth has a gradually increasing lateral thickness. The third depth is within the depth range of the first P-type body layer.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor devices, and in particular relates to a semiconductor device having a source region and a plurality of gate regions and a manufacturing method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field effect transistor (MOSFET). The threshold voltage V th The input capacitance C iss , reverse transfer capacitance (C rss ) and the doping concentration of the gate oxide layer, among which the reverse transfer capacitance C rss Affected by the gate-collector capacitance C gc The impact of (for example, C rss =C GC ), input capacitor C iss Affected by the gate-emitter capacitance C ge and gate-collector capacitance C gc The common influence of iss =C GE + CGC ).

[0003] In the prior art IGBT semiconductor devices, especially IGBT semiconductor devices with a trench structure, in order to stabilize the threshold voltage of the semiconductor device, the gate-collector capacitance C is usually reduced by increasing the thickness of the gate oxide layer at the bottom of the trench. gc To reduce the reverse transfer capacitance C rss For example, US9000514B2 discloses one of the prior art designs, in which, Figure 1 As shown in FIG. 1 , the gate oxide thickness change P23 occurs in the region below the bottom of the P-type body layer P12 of the semiconductor device. However, this design cannot reduce the gate-collector capacitance C gc While reducing the gate-emitter capacitance C ge , so the input capacitance C cannot be effectively adjusted iss , and cannot effectively stabilize the threshold voltage of semiconductor devices.

[0004] Therefore, it is necessary to provide an improved semiconductor device that can solve the above technical problems. Summary of the invention

[0005] In order to solve the above technical problems in the prior art, the present disclosure provides a semiconductor device and a method for manufacturing the same.

[0006] The semiconductor device provided by the present disclosure includes a semiconductor layer, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and the semiconductor layer includes: a source region, wherein the source region includes an N-type source region, a first P-type body layer, and a carrier storage layer stacked along a first direction pointing from the first surface to the second surface; and a plurality of gate regions, wherein the plurality of gate regions are arranged along a second direction perpendicular to the first direction, each gate region includes a gate oxide layer and polysilicon, and the sidewall and bottom of the polysilicon are surrounded by the gate oxide layer, wherein the source region is arranged between two adjacent gate regions among the plurality of gate regions in the second direction, and contacts the two adjacent gate regions along the second direction a gate oxide layer; and wherein, in each gate region, relative to the first surface, the gate oxide layer extends along the first direction from the depth at which the top of the N-type source region is located to a first depth h1; the bottom of the polysilicon is away from the first surface and is at a second depth h2 relative to the first surface; the portion of the gate oxide layer from the top of the gate oxide layer to a third depth h3 has a constant thickness in the second direction, wherein h3<h2

[0007] In some embodiments, for each gate region, the thickness of the gate oxide layer in the second direction at any depth hx in the depth range from the third depth h3 to the second depth h2 is equal to the P-type well concentration N of the first P-type body layer at the depth hx. a function.

[0008] In some embodiments, for each gate region, the thickness T of the gate oxide layer in the second direction at any depth hx in the depth range from the third depth h3 to the second depth h2 is ox and the P-type well concentration N of the first P-type body layer at the depth hx a The relationship between them satisfies the following formula:

[0009]

[0010] Where K is the Boltzmann constant, T is the absolute temperature, and N i is the concentration of intrinsic carriers in the first P-type body layer at the depth hx, ε0 is the vacuum dielectric constant, ε s is the relative dielectric constant of silicon, ε ox is the relative dielectric constant of the gate oxide layer, V th_1 is a preset constant. ​

[0011] In some embodiments, along the first direction, the second depth h2 is within the range of the depth of the carrier storage layer; or, along the first direction, the second depth h2 exceeds the range of the depth of the carrier storage layer.

[0012] In some embodiments, for each gate region, in the second direction, a portion of the gate oxide layer from the third depth h3 to the second depth h2 has a gradually increasing thickness on both sides along the second direction.

[0013] In some embodiments, for each gate region, in the second direction, a portion of the gate oxide layer from the third depth h3 to the second depth h2 has a gradually increasing thickness only on a side close to the source region.

[0014] In some embodiments, for each gate region, in the second direction, a side of the portion of the gate oxide layer from the first surface to the third depth h3 away from the source region is exposed toward the outside of the semiconductor device along the second direction.

[0015] In some embodiments, the semiconductor layer further includes a second P-type body layer extending from a depth at a top of the N-type source region along the first direction, and the second P-type body layer contacts a gate oxide layer of a gate region adjacent thereto along the second direction.

[0016] In some embodiments, a gate region among the multiple gate regions that is adjacent to the N-type source region is an active gate region, and a gate region among the multiple gate regions that is adjacent to the second P-type body layer but not adjacent to the N-type source region is a passive gate region, and the passive gate region and the active gate region are arranged in a preset quantity ratio in the semiconductor device.

[0017] In some embodiments, at least one gate region among the plurality of gate regions includes a gate oxide layer and two polysilicon layers, and the two polysilicon layers are arranged in the gate oxide layer along the second direction.

[0018] In some embodiments, the semiconductor device is a Trench type IGBT cell.

[0019] In some embodiments, the semiconductor layer also includes an interlayer dielectric (ILD) extending from the first surface along the first direction, and the interlayer dielectric contacts the top surface of the N+ source region and the top surface of the gate oxide layer and the top surface of the polysilicon of each gate region along the first direction.

[0020] In some embodiments, the semiconductor device also includes: a top metal layer, the top metal layer including a first portion arranged on the interlayer dielectric and a second portion extending from the bottom surface of the first portion along the first direction through the interlayer dielectric and the N+ source region to contact the first P-type body layer; and a bottom metal layer, the bottom metal layer being arranged to cover the second surface of the semiconductor layer along a direction opposite to the first direction.

[0021] The method for manufacturing the aforementioned semiconductor device provided by the present disclosure includes: providing a semiconductor substrate layer; etching a plurality of grooves in the semiconductor substrate layer, so that each groove is configured to extend from the first surface side of the semiconductor substrate layer along the first direction to a position corresponding to the first depth h1; filling oxide in each groove; forming the gate oxide layer in each groove; depositing polysilicon in the etched oxide in each groove; and etching the polysilicon to form the plurality of gate regions.

[0022] In some embodiments, forming the gate oxide layer in each trench includes: dry isotropically etching the oxide to a position corresponding to the third depth h3, and dry anisotropically etching the oxide from the third depth h3 to a position corresponding to the second depth h2.

[0023] In some embodiments, forming the gate oxide layer in each trench further includes: after etching the oxide from the third depth h3 to a position corresponding to the second depth h2, filling additional oxide in each trench to form a sidewall of the gate oxide layer.

[0024] In some embodiments, the method further includes: forming the source region in the semiconductor base layer.

[0025] In some embodiments, forming the source region in the semiconductor base layer includes: from the first surface side of the semiconductor base layer, successively forming the first P-type body layer and the carrier storage layer by ion implantation and stacking; and forming the N-type source region in the first P-type body layer along a direction opposite to the first direction.

[0026] In some embodiments, the method further includes: forming an interlayer dielectric covering the plurality of gate regions and the source region by depositing oxide, wherein a top surface of the interlayer dielectric is the first surface of the semiconductor layer.

[0027] In some embodiments, the method also includes: forming a contact hole at a position corresponding to the source region, the contact hole extending from the top surface of the interlayer dielectric along the first direction through the interlayer dielectric and the N-type source region and reaching the first P-type body layer; forming a top metal layer on the top surface of the interlayer dielectric and in the contact hole; and forming a bottom metal layer on the second surface side of the semiconductor base layer.

[0028] The semiconductor device and the manufacturing method disclosed herein can simultaneously adjust the gate-collector capacitance C of the semiconductor device by setting the starting point of the gate oxide layer thickness change in the region overlapping with the P-type body layer in the longitudinal depth direction and gradually increasing the thickness of the gate oxide layer in the depth direction. gc and the gate-emitter capacitance C ge , thereby stabilizing the threshold voltage of the semiconductor device and obtaining better didt (current change rate) and dvdt (voltage change rate) control capabilities for switching transients. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A design of a semiconductor device of the prior art is shown;

[0030] Figure 2 A schematic structural diagram of a semiconductor device according to a first embodiment of the present disclosure is shown;

[0031] Figure 3 shows a schematic structural diagram of a semiconductor device according to a second embodiment of the present disclosure;

[0032] Figure 4 A schematic structural diagram of a semiconductor device according to a third embodiment of the present disclosure is shown;

[0033] Figure 5 shows a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present disclosure;

[0034] Figure 6 shows a schematic structural diagram of a semiconductor device according to a fifth embodiment of the present disclosure;

[0035] Figure 7 An example of a graph showing a relationship between a gate oxide thickness and a P-type well concentration of a P-type body layer of a semiconductor device according to an embodiment of the present disclosure;

[0036] Figure 8 A flowchart showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present disclosure is shown;

[0037] Fig. 9 A schematic structural diagram of a semiconductor device after trenches are formed according to a sixth embodiment of the present disclosure is shown;

[0038] Fig.10 A schematic diagram of the structure of a semiconductor device obtained after oxide is filled in a trench according to a sixth embodiment of the present disclosure is shown;

[0039] Fig.11 A schematic structural diagram of a semiconductor device according to a sixth embodiment of the present disclosure after a first portion of a gate oxide layer is formed in a trench is shown;

[0040] Fig.12 A schematic structural diagram of a semiconductor device according to a sixth embodiment of the present disclosure after a second portion of a gate oxide layer is formed in a trench is shown;

[0041] Fig.13 A schematic diagram of the structure of a semiconductor device obtained after forming a sidewall of a gate oxide layer in a trench according to a sixth embodiment of the present disclosure is shown;

[0042] Fig.14 A schematic diagram of the structure of a semiconductor device according to a sixth embodiment of the present disclosure obtained after polysilicon is deposited in an etched oxide in a trench;

[0043] Fig.15 A schematic diagram of the structure of a semiconductor device according to a sixth embodiment of the present disclosure obtained after etching the polysilicon is shown;

[0044] Fig.16 A schematic diagram of the structure of the semiconductor device according to the sixth embodiment of the present disclosure is shown after ion implantation and stacking to successively form a carrier storage layer and a first P-type body layer;

[0045] Fig.17 A schematic diagram showing the structure of a semiconductor device after forming an N-type source region according to a sixth embodiment of the present disclosure; and

[0046] Fig.18 FIG. 4 is a schematic structural diagram of a semiconductor device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The present disclosure will be described below by way of example with reference to the accompanying drawings. The following description discloses or shows various objects, features and aspects of the present disclosure. It will be appreciated by those skilled in the art that the following discussion is only used to describe exemplary embodiments and is not intended to limit the broader aspects of the present disclosure as embodied in exemplary configurations. Table 1 is a list of components in the accompanying drawings and corresponding reference numerals, wherein reference numerals that are identical or similar to each other represent components that are identical or similar to each other in the accompanying drawings. Therefore, once a component is defined in one embodiment, further definition and explanation thereof may be omitted in other embodiments.

[0048]

[0049]

[0050] Table 1

[0051] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by the terms "top", "bottom", "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product is usually placed when in use, which is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. Of course, when the semiconductor device is installed in a circuit, the positional relationship between the components shall be based on the actual orientation.

[0052] Furthermore, in the description of the present disclosure, unless otherwise specified, expressions in the singular form may include plural concepts.

[0053] Furthermore, the terms “first”, “second”, etc. are only used to distinguish the descriptions and should not be understood as indicating or implying relative importance or order.

[0054] In addition, it should be noted that, unless there is any conflict, the features in the embodiments of the present disclosure may be arbitrarily combined with each other.

[0055] Semiconductor Devices

[0056] Figures 2 to 6 A semiconductor device 1 according to various embodiments of the present disclosure is shown. The semiconductor device 1 includes a semiconductor layer 10. The semiconductor layer 10 has a first surface S1 and a second surface S2 opposite to each other. The semiconductor layer 10 includes a source region (110; 210; 310; 410; 510) and a plurality of gate regions (120; 220; 320; 420; 520).

[0057] The source region (110; 210; 310; 410; 510) includes an N-type source region (111; 211; 311; 411; 511), a first P-type body layer (112; 212; 312; 412; 512), and a carrier storage layer (113; 213; 313; 413; 513) stacked along a first direction D1 (i.e., a downward direction in the drawing) pointing from the first surface S1 to the second surface S2. In other words, the N-type source region (111; 211; 311; 411; 511), the first P-type body layer (112; 212; 312; 412; 512), and the carrier storage layer (113; 213; 313; 413; 513) are stacked in sequence from top to bottom along the first direction D1.

[0058] A plurality of gate regions (120; 220; 320; 420; 520) are arranged along a second direction D2 (i.e., a lateral direction in the drawings) perpendicular to the first direction D1. Each gate region (120; 220; 320; 420; 520) includes a gate oxide layer (121; 221; 321; 421; 521) and polysilicon (122; 222; 322; 422; 522). The sidewall and bottom (124; 224) of the polysilicon are surrounded by the gate oxide layer (121; 221; 321; 421; 521).

[0059] The source region (110; 210; 310; 410; 510) is arranged between two adjacent gate regions among the plurality of gate regions (120; 220; 320; 420; 520) in the second direction D2, and contacts the gate oxide layers (121; 221; 321; 421; 521) of the two adjacent gate regions along the second direction D2. In other words, the source region (110; 210; 310; 410; 510) is arranged between the two adjacent gate regions in the lateral direction.

[0060] In each gate region (120; 220; 320; 420; 520), relative to the first surface S1, the gate oxide layer (121; 221; 321; 421; 521) extends from the depth of the top (114; 214; 314; 414; 514) of the N-type source region (111; 211; 311; 411; 511) to a first depth h1 along a first direction D1. The bottom (124; 224) of the polysilicon is away from the first surface S1 and is at a second depth h2 relative to the first surface S1. The portion of the gate oxide layer (121; 221; 321; 421; 521) from the top of the gate oxide layer to the third depth h3 has a constant thickness in the second direction. The third depth h3<the second depth h2<the first depth h1. The portion of the gate oxide layer (121; 221; 321; 421; 521) from the third depth h3 to the second depth h2 has a gradually increasing thickness in the second direction D2. In other words, in the first direction D1, from top to bottom are the top of the gate oxide layer (121; 221; 321; 421; 521) (i.e., the top of the polysilicon), the third depth h3 (i.e., the starting point of the thickening of the gate oxide layer (123; 223; 323; 423; 523)), the second depth h2 (i.e., the bottom of the polysilicon), and the first depth h1 (i.e., the bottom of the gate oxide layer). The lateral thickness of the gate oxide layer (121; 221; 321; 421; 521) gradually increases downward from the third depth h3 (at least until the second depth h2). The third depth h3 is within the range of the depth of the first P-type body layer. In other words, the depth of the starting point of the thickening of the gate oxide layer is located between the depth of the top of the first P-type body layer (112; 212; 312; 412; 512) (the bottom of the N-type source region) and the depth of the bottom of the first P-type body layer (112; 212; 312; 412; 512) (the top of the carrier storage layer). That is, the starting point of the thickening of the gate oxide layer overlaps with the lateral projection of the first P-type body layer. Within the range of the depth of the first P-type body layer (112; 212; 312; 412; 512), the thickness of the gate oxide layer affects the gate-emitter capacitance C ge Based on this, the semiconductor device disclosed in the present invention changes the gate-emitter capacitance C by gradually increasing the thickness of the gate oxide layer. ge .

[0061] Through the above design, the semiconductor device disclosed in the present invention has the following advantages: the gate-collector capacitance C of the semiconductor device can be adjusted at the same time. gc and the gate-emitter capacitance C ge , thereby adjusting the reverse transfer capacitance C rss and input capacitor C iss , thereby stabilizing the threshold voltage of the semiconductor device and obtaining better didt and dvdt control capabilities for switching transients.

[0062] According to an embodiment of the present disclosure, for each gate region (120; 220; 320; 420; 520), the thickness of the gate oxide layer (121; 221; 321; 421; 521) in the second direction D2 at any depth hx in the depth range from the third depth h3 to the second depth h2 may be the P-type well concentration N of the first P-type body layer (112; 212; 312; 412; 512) at the depth hx. a In other words, at any depth hx in the depth range from the third depth h3 to the second depth h2, the thickness of the gate oxide layer in the lateral direction is determined by the first P-type body layer (112; 212; 312; 412; 512) depending on the P-type well concentration N at the depth hx. a .

[0063] As mentioned above, the thickness of the gate oxide layer affects the gate-emitter capacitance C ge and gate-collector capacitance C gc Through the above design, the semiconductor device disclosed in the present invention reduces the gate oxide layer thickness and the P-type well concentration N among the factors affecting the threshold voltage. a The threshold voltage is always determined by the P-type well concentration N a The decision can stabilize the threshold voltage of the semiconductor device and reduce the complexity of design and manufacturing.

[0064] According to an embodiment of the present disclosure, for each gate region, the gate oxide layer (121; 221; 321; 421; 521) has a thickness T in the second direction at any depth hx in the depth range from the third depth h3 to the second depth h2. ox The P-type well concentration N of the first P-type body layer (112; 212; 312; 412; 512) at the depth hx a The relationship between them satisfies the following formula:

[0065]

[0066] Where K is the Boltzmann constant, T is the absolute temperature, and N i is the concentration of intrinsic carriers in the first P-type body layer at the depth hx, ε0 is the vacuum dielectric constant, ε s is the relative dielectric constant of silicon, ε ox is the relative dielectric constant of the gate oxide layer, V th_1 is a preset constant. For example, when the threshold voltage V th When V is 5V, th_1 It can be set to 4V to 4.2V. Through the above design, the thickness of the gate oxide layer T ox Affected by the P-type well concentration Na At the same time, the oxide thickness T ox The effect of the change on the threshold voltage of the semiconductor device is less than that of the P-type well concentration N a Reduce the impact caused.

[0067] For example, Figure 7 shows the gate oxide thickness T of the semiconductor device according to the embodiment of the present disclosure. ox and the P-type well concentration N of the first P-type body layer a An example of a graph of the relationship between . Figure 7 The P-type well concentration N of the first P-type body layer under different processing conditions (annealing temperature is 1150°C, annealing time is 25 minutes / 120 minutes / 200 minutes (25M / 120M / 200M)) is shown. a (left coordinate axis and multiple solid curves) at different depths, and also shows the P-type well concentration N of the first P-type body layer under the above different processing conditions. a The oxide thickness T of the phase is calculated by formula 1 ox Variation range (right coordinate axis and multiple dashed curves). In this example, the depth of the trench where the gate oxide layer of the gate region is located is between 1.8 μm and 2.0 μm. The depth of the trench can be other values ​​as needed, which is not limited here. The P-type well concentration N of the first P-type body layer a (solid line) In the example, the horizontal axis shows a depth of 0.5 μm and then decreases. Therefore, the thickness of the gate oxide layer T ox Increases continuously to match the P-type well concentration N a , and preferably not higher than the curve shown by the dotted line (obtained according to Formula 1).

[0068] <![CDATA[V th_1 ]]> 4.18V 4.15V 4.12V 4.17V Gate oxide thickness 1200A 2050A 4700A 5800A depth 0.50μm 1.50μm 2μm 2.80μm <![CDATA[P-type well concentration N a > 1.20E+17 4.00E+16 9.00E+15 1.27E+14

[0069] Table 2

[0070] For example, Table 2 shows that the constant V th_1 When set in the range of 4V to 4.2V, at different depths, the oxide thickness T ox According to the P-type well concentration N of the first P-type body layer a The value of the change.

[0071] According to the embodiments of the present disclosure, Figure 2 As shown, along the first direction D1, the second depth h2 may be within the depth range of the carrier storage layer 113. In other words, the bottom 124 of the polysilicon 122 may be within the depth range of the carrier storage layer 113.

[0072] According to the embodiments of the present disclosure, Figure 3As shown, along the first direction D1, the second depth h2 may exceed the depth range of the carrier storage layer 213. In other words, the bottom 224 of the polysilicon 222 may exceed the depth range of the carrier storage layer 213.

[0073] According to the embodiments of the present disclosure, Figure 2 , Figure 3 and Figure 5 As shown, for each gate region (120; 220; 420), in the second direction D2, the portion of the gate oxide layer (121; 221; 421) from the third depth h3 to the second depth h2 and the two sides along the second direction D2 can have a gradually increasing thickness. In other words, the thickness of the two side walls of the gate oxide layer (121; 221; 421) that are in contact with the two side surfaces of the polysilicon are gradually increased. Through the above design, the thickness of the gate oxide layer can be smoothly increased, and the formation of the gate oxide layer is also facilitated.

[0074] According to the embodiments of the present disclosure, Figure 4 and Figure 6 As shown, for each gate region (320; 520), in the second direction D2, a portion of the gate oxide layer (321; 521) from the third depth h3 to the second depth h2 may have a gradually increasing thickness only on one side close to the source region (310; 510).

[0075] According to the embodiments of the present disclosure, Figure 4 As shown, for each gate region 320 , in the second direction D2 , a portion of the gate oxide layer 321 from the first surface S1 to the third depth h3 away from the source region 310 may be exposed toward the outside of the semiconductor device along the second direction D2 .

[0076] According to the embodiments of the present disclosure, Figure 2 , Figure 3 and Figure 5 As shown, the semiconductor layer 10 may further include a second P-type body layer (131; 231; 431). The second P-type body layer (131; 231; 431) extends from the depth at which the top (114; 214; 414) of the N-type source region (111; 211; 411) is located along the first direction D1, and the second P-type body layer (131; 231; 431) contacts the gate oxide layer (121; 221; 421) of the gate region (120; 220; 420) adjacent thereto along the second direction D2. In some embodiments, as Figure 5 As shown, the second P-type body layer 431 surrounds the bottom of the gate oxide layer 421 of the gate region 420 adjacent thereto.

[0077] According to the embodiments of the present disclosure, Figure 6As shown, at least one gate region among the plurality of gate regions 520 may include a gate oxide layer 521 and two polysilicon layers 522. The two polysilicon layers 522 are arranged along a second direction D2 perpendicular to the first direction D1 in one gate oxide layer 521. It should be noted that the distance between the two polysilicon layers in a single gate oxide layer satisfies the requirement of not interfering with each other.

[0078] According to an embodiment of the present disclosure, the semiconductor device 1 may be a Trench type IGBT cell.

[0079] According to an embodiment of the present disclosure, the N-type source region may be an N+ source region.

[0080] According to the embodiments of the present disclosure, Figures 2 to 6 As shown, the semiconductor layer 10 may further include an N-type drift layer 133 , a buffer layer 134 and an emitter layer 135 .

[0081] According to the embodiments of the present disclosure, Figures 2 to 6 As shown, the semiconductor layer 10 further includes an interlayer dielectric (ILD) (132; 432) extending from the first surface along a first direction. The interlayer dielectric may be an oxide layer. The interlayer dielectric (132; 432) contacts the top (114; 414) of the N-type source region (111; 411) and the top of the gate oxide layer (121; 421) and the top of the polysilicon (122; 422) of each gate region (120; 420) along the first direction D1.

[0082] According to the embodiments of the present disclosure, Figures 2 to 6 As shown, the semiconductor device further includes a top metal layer 20. The top metal layer 20 includes a first portion 21 disposed on the interlayer dielectric 132 and a second portion 22 extending from the bottom surface of the first portion along a first direction through the interlayer dielectric 132 and the N-type source region 111 to contact the first P-type body layer 121.

[0083] According to the embodiments of the present disclosure, Figures 2 to 6 As shown, the semiconductor device 1 further includes a bottom metal layer 30. The bottom metal layer 30 is arranged to cover the second surface S2 of the semiconductor layer 10 along a direction opposite to the first direction D1.

[0084] According to an embodiment of the present disclosure, the threshold voltage V th for:

[0085]

[0086] Among them, θ ms is the gold half-work function difference, k is the Boltzmann constant, T is the absolute temperature, q is the charge, Q m is the charge in the equivalent metal, Qss is the equivalent surface state charge, Q fc is the equivalent fixed charge, C ox is the oxide layer capacitance.

[0087] According to an embodiment of the present disclosure, at least one of the plurality of gate regions may be adjacent only to the second P-type body layer but not to the N-type source region. In other words, the gate oxide layer of the at least one gate region contacts the second P-type body layer adjacent thereto along the second direction.

[0088] In some embodiments, the gate region adjacent to the N-type source region among the multiple gate regions is an active gate region, and the gate region adjacent to the second P-type body layer but not adjacent to the N-type source region among the multiple gate regions is a passive gate region. The passive gate region and the active gate region are arranged in a preset ratio in the semiconductor device to obtain a better didt and dvdt control capability of the switching transient. Figure 2 and Figure 3 As shown, the ratio of the passive gate region to the active gate region can be 1:2. It should be noted that the lower the ratio of the number of active gate regions to the number of all gate regions, the higher the didt and dvdt of the semiconductor device, and the higher the ratio, the lower the didt and dvdt of the semiconductor device. In some embodiments, the passive gate region can be called a dummy gate region. In some embodiments, the passive gate region can be a grounded gate region.

[0089] Below, various embodiments of the present disclosure are described in detail.

[0090] First embodiment

[0091] Figure 2 FIG. 1 shows a semiconductor device 1 according to a first embodiment of the present disclosure, wherein the semiconductor device 1 is a Trench-type IGBT unit. Figure 2 As shown, the semiconductor device 1 includes a semiconductor layer 10 , a top metal layer 20 and a bottom metal layer 30 .

[0092] The semiconductor layer 10 has a first surface S1 and a second surface S2 opposite to each other and includes two source regions 110 , six gate regions 120 , three second P-type body layers 131 , an interlayer dielectric 132 , an N-type drift layer 133 , a buffer layer 134 and an emitter layer 135 .

[0093] Each source region 110 includes an N-type source region 111, a first P-type body layer 112, and a carrier storage layer 113 stacked in a first direction D1 from the first surface S1 to the second surface S2. The N-type source region is an N+ source region.

[0094] The six gate regions 120 are arranged along a second direction D2 perpendicular to the first direction D1. Each gate region 120 includes a gate oxide layer 121 and polysilicon 122. The sidewall and bottom 124 of the polysilicon 122 are surrounded by the gate oxide layer 121.

[0095] Each source region 110 is arranged between two adjacent gate regions among the six gate regions 120 in the second direction D2 and contacts the gate oxide layers 121; 221 of the two adjacent gate regions along the second direction D2.

[0096] In each gate region 120, relative to the first surface S1, the gate oxide layer 121 extends from the depth at which the top 114 of the N-type source region 111 is located to the first depth h1 along the first direction D1. The bottom 124 of the polysilicon is away from the first surface S1 and is at a second depth h2 relative to the first surface S1. The portion of the gate oxide layer 121 from the top of the gate oxide layer to the third depth h3 has a constant thickness in the second direction. The third depth h3<the second depth h2<the first depth h1. The portion of the gate oxide layer 121 from the third depth h3 to the second depth h2 has a gradually increasing thickness in the second direction D2. The third depth h3 is within the range of the depth at which the first P-type body layer 112 is located. Along the first direction D1, the second depth h2 can be within the range of the depth at which the carrier storage layer 113 is located.

[0097] For each gate region 120, the thickness of the gate oxide layer 121 in the second direction D2 at any depth hx in the depth range from the third depth h3 to the second depth h2 is equal to the P-type well concentration N of the first P-type body layer 112 at the depth hx. a The relationship between can satisfy Formula 1.

[0098] For each gate region 120 , in the second direction D2 , a portion of the gate oxide layer 121 from the third depth h3 to the second depth h2 has a gradually increasing thickness on both sides along the second direction D2 .

[0099] The second P type body layer 131 extends from a depth where the top 114 of the N type source region 111 is located along the first direction D1 , and the second P type body layer 131 contacts the gate oxide layer 121 of the gate region 120 adjacent thereto along the second direction D2 .

[0100] Among the six gate regions 120 arranged along the second direction D2, the gate region 120 adjacent to the N-type source region 111 (ie, Figure 2 The first, second, fifth, and sixth gate regions from the left in the middle) are active gate regions, and the gate region 120 adjacent to the second P-type body layer 131 but not adjacent to the N-type source region 111 (i.e., the third and fourth gate regions from the left) are passive gate regions. In the semiconductor device 1, the passive gate regions and the active gate regions are arranged in a ratio of 1:2.

[0101] The interlayer dielectric 132 extends from the first surface along a first direction. The interlayer dielectric is an oxide layer. The interlayer dielectric 132 contacts the top 114 of the N-type source region 111 and the top of the gate oxide layer 121 and the top of the polysilicon 122 of each gate region 120 along the first direction D1.

[0102] The top metal layer 20 includes a first portion 21 disposed on the interlayer dielectric 132 and a second portion 22 extending from a bottom surface of the first portion along a first direction through the interlayer dielectric 132 and the N-type source region 111 to contact the first P-type body layer 121 .

[0103] The bottom metal layer 30 is arranged to cover the second surface S2 of the semiconductor layer 10 in a direction opposite to the first direction D1 .

[0104] As described above, the first embodiment according to the present disclosure has been described in conjunction with the accompanying drawings. In the following description of other embodiments, components corresponding to or having the same functions as those in the first embodiment will be represented by the same or similar reference numerals, and descriptions of certain components, operations, and effects may be omitted to avoid repetition.

[0105] Second embodiment

[0106] Figure 3 The semiconductor device 1 according to the second embodiment of the present disclosure is shown. The difference from the first embodiment is that in the semiconductor device 1 of the second embodiment, along the first direction D1, the second depth h2 exceeds the depth range of the carrier storage layer 213 (closer to the second surface S2).

[0107] Third embodiment

[0108] Figure 4 A semiconductor device 1 according to a third embodiment of the present disclosure is shown. The semiconductor layer of the semiconductor device 1 has a source region 310 and two gate regions 320. For each gate region 320, in the second direction D2, a portion of the gate oxide layer 321 from the third depth h3 to the second depth h2 may have a gradually increasing thickness only on one side close to the source region 310, and have a substantially constant thickness on the other side.

[0109] In addition, for each gate region 320 , in the second direction D2 , a portion of the gate oxide layer 321 from the first surface S1 to the third depth h3 , which is away from the source region 310 , is exposed toward the outside of the semiconductor device along the second direction D2 .

[0110] like Figure 4 As shown, the semiconductor device 1 of the third embodiment does not include a second P-type body layer, and both gate regions 320 are active gate regions.

[0111] Fourth embodiment

[0112] Figure 5 A semiconductor device 1 according to a fourth embodiment of the present disclosure is shown. The difference from the first embodiment is that in the semiconductor device 1 of the fourth embodiment, the second P-type body layer 431 surrounds the bottom of the gate oxide layer 421 of the gate region 420 adjacent thereto.

[0113] Fifth embodiment

[0114] Figure 6 A semiconductor device 1 according to a fifth embodiment of the present disclosure is shown. The difference from the first embodiment is that in the semiconductor device 1 of the fifth embodiment, for each gate region 520, in the second direction D2, the portion of the gate oxide layer 521 from the third depth h3 to the second depth h2 has a gradually increasing thickness only on one side close to the source region 510.

[0115] At least one gate region among the plurality of gate regions 520 ( Figure 6 The middle gate region in the gate oxide layer 521 includes a gate oxide layer 521 and two polysilicon layers 522. The two polysilicon layers 522 are arranged in a second direction D2 perpendicular to the first direction D1 in the gate oxide layer 521.

[0116] Method for manufacturing semiconductor device

[0117] The present disclosure also provides a method for manufacturing the semiconductor device described above. Figure 8 The method includes the following steps S10-S60.

[0118] Step S10, providing a semiconductor base layer.

[0119] The material of the semiconductor substrate layer may be an N-type semiconductor material or a P-type semiconductor material, wherein the main doping types of the N-type and P-type semiconductor materials may be phosphorus (Group V) and boron (Group III).

[0120] Step S20, etching a plurality of grooves in the semiconductor base layer.

[0121] The bottom of the trench will correspond to the bottom of the gate oxide layer, and therefore, each trench is etched along the first direction to a position corresponding to the first depth h1.

[0122] Here, a chemical vapor deposition process (CVD) can be used to deposit an oxide layer on the surface of the semiconductor layer as a mask layer used during the trench etching process. Alternatively, a photoresist can be used as a mask layer during the trench etching process.

[0123] Step S30 , filling each trench with oxide.

[0124] Here, the oxide may be silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), or the like.

[0125] Step S40: forming a gate oxide layer in each trench.

[0126] The gate oxide layer can be formed by etching, or etching + adding oxide, etc. The formed gate oxide layer has the shape and properties disclosed in the above embodiments.

[0127] Step S50 , depositing polysilicon in the etched oxide in each trench.

[0128] Step S60: etching polysilicon to form a plurality of gate regions.

[0129] Optionally, while etching the polysilicon, the gate oxide layer (or other oxides) adjacent thereto may be etched together to make the tops of the two layers flush.

[0130] In some embodiments, the step S40 of forming a gate oxide layer in each trench includes: etching the oxide to a position corresponding to the third depth h3, and etching the oxide from the third depth h3 to a position corresponding to the second depth h2. In some embodiments, the oxide is isotropically dry-etched to a position corresponding to the third depth h3. In some embodiments, the oxide is anisotropically dry-etched from the third depth h3 to a position corresponding to the second depth h2.

[0131] In some embodiments, the step S30 of filling oxide in each groove includes: etching the oxide while filling the oxide to form a notch (e.g., a notch with a triangular longitudinal section) on the oxide. In some embodiments, the oxide is etched by an etching gas containing carbon or fluorine (C / F). In some embodiments, the oxide is filled by a deposition gas SiH4+N20 / O2 or TEOS[Si(OC2H5)4]+O2 / O3. In some embodiments, the depth-to-width ratio of the notch (especially the triangular notch) distribution can be adjusted by adjusting the ratio of C / F contained in the deposition gas and the etching gas.

[0132] In some embodiments, the step S40 of forming a gate oxide layer in each trench includes: isotropically dry etching an oxide with a notch to form a gate oxide layer.

[0133] In some embodiments, the step S40 of forming a gate oxide layer in each trench includes: etching oxide to a position corresponding to the second depth h2, and filling oxide from a third depth h2 and reserving space required for polysilicon to a position corresponding to a third depth h3.

[0134] In some embodiments, the step S40 of forming a gate oxide layer in each trench further includes: after etching the oxide from the third depth h3 to a position corresponding to the second depth h2, filling additional oxide in each trench to form a sidewall of the gate oxide layer.

[0135] In some embodiments, the method further includes: forming a source region in the semiconductor base layer.

[0136] It should be noted that the step of forming a source region in the semiconductor base layer can be implemented between any steps after step S10, or can be divided into several sub-steps and implemented between multiple groups of different steps.

[0137] In some embodiments, the step of forming the source region in the semiconductor base layer includes: after the step S60 of etching polysilicon to form multiple gate regions, from the first surface side of the semiconductor base layer, successively forming the first P-type body layer and the carrier storage layer by ion implantation and stacking; and forming an N-type source region in the first P-type body layer along a direction opposite to the first direction.

[0138] In some embodiments, the step of forming the source region in the semiconductor base layer includes: before the step S20 of etching a plurality of grooves in the semiconductor base layer, forming a carrier storage layer on the semiconductor base layer.

[0139] In some embodiments, the method further includes forming an interlayer dielectric covering the plurality of gate regions and the source region by depositing oxide, wherein a top surface of the interlayer dielectric is the first surface of the semiconductor layer.

[0140] In some embodiments, the method further comprises:

[0141] forming a contact hole at a position corresponding to the source region, wherein the contact hole extends from a top surface of the interlayer dielectric along a first direction through the interlayer dielectric and the N-type source region and reaches the first P-type body layer;

[0142] forming a top metal layer on the top surface of the interlayer dielectric and in the contact hole;

[0143] A bottom metal layer is formed on the second surface side of the semiconductor base layer.

[0144] The following is a detailed description of the method embodiments of the present disclosure.

[0145] Sixth embodiment

[0146] Figures 9 to 18 These are the specific steps of the sixth embodiment.

[0147] A semiconductor base layer is provided.

[0148] A carrier storage layer is formed on the semiconductor substrate layer. It should be noted that for the purpose of simplicity, the carrier storage layer is not shown in the figure.

[0149] A plurality of grooves are etched in the semiconductor substrate layer, so that each groove is configured to extend from the first surface side of the semiconductor substrate layer along the first direction D1 to a position corresponding to the first depth h1. The structure after this step is as follows: Fig. 9 shown.

[0150] Fill each trench with oxide. The structure after this step is as follows Fig.10 shown.

[0151] A gate oxide layer 621 is formed in each trench, comprising:

[0152] - Dry isotropically etch the oxide to a position corresponding to the third depth h3. The structure after this step is as follows Fig.11 As shown;

[0153] - Dry anisotropically etch the oxide from the third depth h3 to the position corresponding to the second depth h2. The structure after this step is as follows Fig.12 as shown; and

[0154] - After etching the oxide from the third depth h3 to a position corresponding to the second depth h2, additional oxide is filled in each trench to form the sidewall of the gate oxide layer 621. The structure after this step is as follows: Fig.13 shown.

[0155] Polysilicon 622 is deposited in the etched oxide in each trench. The structure after this step is as follows: Fig.14 shown.

[0156] The polysilicon 622 is etched to form a plurality of gate regions 620. The structure after this step is as follows: Fig.15 shown.

[0157] A source region 610 is formed in the semiconductor substrate layer, comprising:

[0158] - From the first surface side of the semiconductor base layer, the first P-type body layer 612 and the second P-type body layer 631 are formed by ion implantation and stacking. The structure after this step is as follows Fig.16 as shown; and

[0159] - forming an N-type source region 611 in the first P-type body layer 612 along a direction opposite to the first direction D1. The structure after this step is as follows Fig.17 shown.

[0160] An interlayer dielectric 632 covering the plurality of gate regions 620 and the source region 610 is formed by depositing oxide, and a top surface of the interlayer dielectric 632 is the first surface S1 of the semiconductor layer.

[0161] A buffer layer 634 and a P-type emitter layer 635 are formed along the first direction D1 on the first surface side of the semiconductor base layer away from the trench, and the bottom surface of the P-type emitter layer 635 is the second surface S2 of the semiconductor layer.

[0162] A contact hole is formed at a position corresponding to the source region, and the contact hole extends from the top surface of the interlayer dielectric 632 along the first direction D1 through the interlayer dielectric 632 and the N-type source region 611 and reaches the first P-type body layer 612 .

[0163] A top metal layer 20 is formed on the top surface of the interlayer dielectric 632 and in the contact holes.

[0164] A bottom metal layer 30 is formed on the second surface side of the semiconductor base layer. The structure after this step is as follows Fig.18 shown.

[0165] Although the preferred embodiments of the present disclosure are described in detail above, the present disclosure is not limited thereto, and those skilled in the art may make various modifications and variations to the embodiments within the scope of the present disclosure.

[0166] For example, at least one gate region ( Figure 2 The third and fourth gate regions from the left in the middle may only be adjacent to the second P-type body layer, but not adjacent to the N-type source region. The at least one gate region is a dummy gate region. The dummy gate region and the gate region adjacent to the source region may be provided in proportion.

[0167] Although the subject matter of the invention has been disclosed in the context of certain preferred or illustrated embodiments and examples, it will be understood by those skilled in the art that the subject matter of the invention extends beyond the specifically disclosed embodiments to other optional embodiments and / or uses of the invention and the obvious modifications and equivalents of the invention. In addition, although multiple variations of the disclosed embodiments have been shown and described in detail, other modifications within the scope of the subject matter of the invention will be apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or sub-combinations may be made to the specific features and various aspects of the disclosed embodiments, and these combinations or sub-combinations still fall within the scope of the subject matter of the invention. Accordingly, it should be understood that the various features and various aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the disclosed subject matter of the invention. Therefore, the scope of the subject matter of the invention disclosed herein is not intended to be limited by the above-mentioned specifically disclosed embodiments, but should only be determined by reading the claims fairly.

Claims

1. A semiconductor device, comprising: A semiconductor layer, the semiconductor layer having a first surface and a second surface opposite to each other, the semiconductor layer comprising: a source region, the source region comprising an N-type source region, a first P-type body layer, and a carrier storage layer stacked along a first direction from the first surface to the second surface; and a plurality of gate regions, the plurality of gate regions are arranged along a second direction perpendicular to the first direction, each gate region comprises a gate oxide layer and polysilicon, and the sidewall and bottom of the polysilicon are surrounded by the gate oxide layer, The source region is arranged between two adjacent gate regions among the plurality of gate regions in the second direction, and contacts gate oxide layers of the two adjacent gate regions along the second direction; Among them, in each gate region, Relative to the first surface, the gate oxide layer extends along the first direction from the depth at which the top of the N-type source region is located to a first depth h1; The bottom of the polysilicon is far away from the first surface and is at a second depth h2 relative to the first surface; The portion of the gate oxide layer from the top of the gate oxide layer to the third depth h3 has a constant thickness in the second direction, wherein h3 <h2<h1; The portion of the gate oxide layer from the third depth h3 to the second depth h2 has a gradually increasing thickness in the second direction; and The third depth h3 is within the range of the depth at which the first P-type body layer is located.

2. The semiconductor device according to claim 1, wherein: For each gate region, the thickness of the gate oxide layer in the second direction at any depth hx in the depth range from the third depth h3 to the second depth h2 is equal to the P-type well concentration N of the first P-type body layer at the depth hx. a function.

3. The semiconductor device according to claim 2, characterized in that For each gate region, the thickness T of the gate oxide layer in the second direction at any depth hx in the depth range from the third depth h3 to the second depth h2 is ox and the P-type well concentration N of the first P-type body layer at the depth hx a The relationship between them satisfies the following formula: Where K is the Boltzmann constant, T is the absolute temperature, and N i is the concentration of intrinsic carriers in the first P-type body layer at the depth hx, ε0 is the vacuum dielectric constant, ε s is the relative dielectric constant of silicon, ε ox is the relative dielectric constant of the gate oxide layer, V th_ is a preset constant.

4. The semiconductor device according to claim 1, wherein: Along the first direction, the second depth h2 is within the range of the depth of the carrier storage layer; or, Along the first direction, the second depth h2 exceeds a range of a depth at which the carrier storage layer is located.

5. The semiconductor device according to claim 1, wherein: For each gate region, in the second direction, a portion of the gate oxide layer from the third depth h3 to the second depth h2 has a gradually increasing thickness on both sides along the second direction.

6. The semiconductor device according to claim 1, wherein: For each gate region, in the second direction, a portion of the gate oxide layer from the third depth h3 to the second depth h2 has a gradually increasing thickness only on a side close to the source region.

7. The semiconductor device according to claim 6, characterized in that For each gate region, in the second direction, a side of the gate oxide layer from the first surface to the third depth h3 away from the source region is exposed toward the outside of the semiconductor device along the second direction.

8. The semiconductor device according to claim 1, wherein: The semiconductor layer further includes a second P type body layer, which extends from a depth at which a top of the N type source region is located along the first direction, and contacts a gate oxide layer of a gate region adjacent thereto along the second direction.

9. The semiconductor device according to claim 8, characterized in that The gate region adjacent to the N-type source region among the multiple gate regions is an active gate region, and the gate region adjacent to the second P-type body layer but not adjacent to the N-type source region among the multiple gate regions is a passive gate region. The passive gate region and the active gate region are arranged in a preset quantity ratio in the semiconductor device.

10. The semiconductor device according to claim 1, wherein: At least one gate region among the plurality of gate regions comprises a gate oxide layer and two polysilicon layers, and the two polysilicon layers are arranged in the gate oxide layer along the second direction.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that: The semiconductor device is a Trench type IGBT cell.

12. A method for manufacturing a semiconductor device according to any one of claims 1 to 11, comprising: providing a semiconductor substrate layer; Etching a plurality of grooves in the semiconductor substrate layer, such that each groove is configured to extend from the first surface side of the semiconductor substrate layer along the first direction to a position corresponding to the first depth h1; filling each trench with oxide; forming the gate oxide layer in each trench; depositing polysilicon in the etched oxide in each trench; as well as The polysilicon is etched to form the plurality of gate regions.

13. The method according to claim 12, characterized in that The forming of the gate oxide layer in each trench comprises: dry isotropically etching the oxide to a position corresponding to the third depth h3, and The oxide is anisotropically dry-etched from the third depth h3 to a position corresponding to the second depth h2.

14. The method according to claim 13, characterized in that The forming of the gate oxide layer in each trench further comprises: After etching the oxide from the third depth h3 to a position corresponding to the second depth h2, additional oxide is filled in each trench to form a sidewall of the gate oxide layer.

15. The method according to claim 12, further comprising: The source region is formed in the semiconductor base layer.

16. The method according to claim 15, wherein: The step of forming the source region in the semiconductor base layer comprises: From the first surface side of the semiconductor base layer, the first P-type body layer and the carrier storage layer are formed successively by ion implantation and stacking; and The N-type source region is formed in the first P-type body layer along a direction opposite to the first direction.

17. The method according to claim 15 or 16, further comprising: An interlayer dielectric covering the plurality of gate regions and the source region is formed by depositing oxide, and a top surface of the interlayer dielectric is the first surface of the semiconductor layer.

18. The method according to claim 17, further comprising forming a contact hole at a position corresponding to the source region, wherein the contact hole extends from the top surface of the interlayer dielectric along the first direction through the interlayer dielectric and the N-type source region and reaches the first P-type body layer; forming a top metal layer on the top surface of the interlayer dielectric and in the contact hole; A bottom metal layer is formed on the second surface side of the semiconductor base layer.

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