Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the field of integrated circuits. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate, wherein the substrate comprises a first region and a second region; forming a gate dielectric layer on the substrate; forming a metal oxide layer on the substrate; the metal oxide layer comprises a first part located in the first region and a second part located in the second region; in the vertical direction, the top surface of the first part is lower than the top surface of the second part; forming a protective layer on the first region, the protective layer being in direct contact with the metal oxide layer; removing the second part of the metal oxide layer; and removing the protection layer. The selective etching of the second part of the metal oxide layer is realized, the first part of the metal oxide layer is prevented from being damaged in the process of etching and removing the second part of the metal oxide layer in the second region, and the electrical property and the reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the continuous development of complementary metal oxide semiconductor (CMOS) technology, the thickness of the gate dielectric layer has been continuously reduced, the gate length has been continuously shortened, the quantum tunneling effect has become more and more significant, and the depletion effect of the polysilicon gate has become more and more serious. Silicon dioxide gate dielectrics and polysilicon gate transistors have gradually approached their physical limits.

[0003] High-K Metal Gate (HKMG) technology has been introduced in the semiconductor field. High-K dielectric materials are used instead of silicon dioxide gate dielectrics, and metal gates are used instead of polysilicon gates to improve gate leakage current, enhance gate control capabilities, and increase carrier mobility.

[0004] During the manufacturing process of HKMG technology, especially when the gate structures of NMOS devices and PMOS devices are formed at the same time, due to the different threshold voltages of NMOS devices and PMOS devices, the high-K dielectric gate dielectric of the NMOS device is different from the high-K dielectric gate dielectric of the PMOS device. The high-K dielectric gate dielectric of the NMOS device may exist in the PMOS device, affecting the performance of the PMOS device. Summary of the invention

[0005] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure to address the problems in the prior art.

[0006] In order to achieve the above objectives, in a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0007] providing a substrate, the substrate comprising a first region and a second region;

[0008] forming a gate dielectric layer located on the substrate;

[0009] Forming a metal oxide layer, located on the substrate, comprising:

[0010] A first part, located in the first zone;

[0011] a second part, located in the second zone;

[0012] Wherein, in the vertical direction, the top surface of the first part is lower than the top surface of the second part;

[0013] forming a protective layer located on the first region, wherein the protective layer is in direct contact with the metal oxide layer;

[0014] removing the second portion located at the metal oxide layer;

[0015] Remove the protective layer.

[0016] Optionally, the first region is an NMOS region, and the second region is a PMOS region.

[0017] Optionally, forming a protective layer comprises:

[0018] forming a protective material layer located on the first region and the second region;

[0019] The protective material layer on the second region is removed, and the protective layer is formed on the first region.

[0020] Optionally, before forming the gate dielectric layer, the method further includes:

[0021] A stress adjustment layer is formed on the second region, the stress adjustment layer being in direct contact with the substrate of the second region.

[0022] Optionally, forming a gate dielectric layer includes:

[0023] forming a first gate dielectric layer located on the substrate in the first region and on the stress adjustment layer;

[0024] A second gate dielectric layer is formed, which is located on the first gate dielectric layer, to form the gate dielectric layer.

[0025] Optionally, the manufacturing method further includes:

[0026] A work function layer is formed on the first portion of the metal oxide layer and on the gate dielectric layer in the second region.

[0027] In a second aspect, the present disclosure provides a semiconductor structure, comprising:

[0028] a substrate comprising a first region and a second region;

[0029] A first gate structure, disposed in the first region, the first gate structure comprising a stacked gate dielectric layer, a metal oxide layer, and a work function layer;

[0030] The second gate structure is arranged in the second region, and the second gate structure includes a stress adjustment layer, a gate dielectric layer, and a work function layer stacked on the second region.

[0031] Optionally, the first region is an NMOS region, and the second region is a PMOS region.

[0032] Optionally, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer stacked together;

[0033] Wherein, the material of the first gate dielectric layer includes silicon oxynitride.

[0034] Optionally, the material of the metal oxide layer includes at least one of aluminum oxide or lanthanum oxide.

[0035] The manufacturing method of the semiconductor structure and the semiconductor structure disclosed in the present invention form a protective layer after forming the metal oxide layer, and the protective layer is used to protect the first part of the metal oxide layer in the first area, so as to achieve selective etching of the second part of the metal oxide layer, avoid damaging the first part of the metal oxide layer in the process of etching and removing the second part of the metal oxide layer in the second area, and help improve the electrical performance and reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0038] Figure 2 A schematic diagram of a structure after a gate dielectric layer and a metal oxide layer are formed on a substrate provided in an embodiment;

[0039] Figure 3 It is a schematic diagram of a structure after forming a protective material layer and forming a mask layer on the protective material layer located in the first area provided in an embodiment;

[0040] Figure 4 It is a structural schematic diagram of etching the protective material layer in the first area and etching the protective material layer in the second area simultaneously in one embodiment;

[0041] Figure 5 is a schematic diagram of a structure after a protective layer is formed in one embodiment;

[0042] Figure 6 is a schematic diagram of a structure after etching and removing the second portion of the metal oxide layer in one embodiment;

[0043] Figure 7 This is a schematic diagram of the structure after etching and removing the protective layer in one embodiment;

[0044] Figure 8It is a schematic diagram of the structure after the work function layer is formed in one embodiment;

[0045] Fig. 9 is a schematic structural diagram of a first device and a second device formed in an embodiment;

[0046] Fig.10 FIG. 4 is a schematic structural diagram of a first device and a second device formed in another embodiment.

[0047] Description of reference numerals:

[0048] 11. substrate; 12. stress adjustment layer; 13. gate dielectric layer; 131. first gate dielectric layer; 132. second gate dielectric layer; 14. metal oxide layer; 114. first part; 214. second part; 15. protective layer; 15a. protective material layer; 16. work function layer; 161. first barrier layer; 162. semiconductor layer; 163. second barrier layer; 164. metal gate layer; 17. mask layer; 18. isolation layer; A1. first area; A2. second area. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0051] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figure 1 As shown, the following steps are included:

[0052] Step S101: providing a substrate, the substrate comprising a first region and a second region;

[0053] Step S102: forming a gate dielectric layer on the substrate;

[0054] Step S103: forming a metal oxide layer located on the substrate; the metal oxide layer includes a first portion located in the first region and a second portion located in the second region; wherein in the vertical direction, a top surface of the first portion is lower than a top surface of the second portion;

[0055] Step S104: forming a protective layer located on the first region, wherein the protective layer is in direct contact with the metal oxide layer;

[0056] Step S105: removing the second portion located on the metal oxide layer;

[0057] Step S106: removing the protective layer.

[0058] In the method for manufacturing the semiconductor structure of the present embodiment, a protective layer is formed after the metal oxide layer is formed. The protective layer is used to protect the first part of the metal oxide layer in the first zone, thereby achieving selective etching of the second part of the metal oxide layer, avoiding damage to the first part of the metal oxide layer during the process of etching and removing the second part of the metal oxide layer in the second zone, and is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0059] Combine the following Figure 2-Figure 10 The various steps of the method for manufacturing a semiconductor structure are described in detail. Figure 2-Figure 10 FIG. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure during its manufacturing process.

[0060] In step S101, refer to Figure 2 As shown, the substrate 11 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC) or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0061] The substrate 11 includes a first area A1 and a second area A2. In this embodiment, a first device 100 is formed in the first area A1, and a second device 200 is formed in the second area A2.

[0062] In some embodiments, the first region A1 is an NMOS region having N-type dopant ions, the second region A2 is a PMOS region having P-type dopant ions, the first device 100 is an NMOS device, and the second device 200 is a PMOS device.

[0063] There is a shallow trench isolation structure (not shown) between the first area A1 and the second area A2. For example, the N-type doping ions may be group V ions such as phosphorus (P) ions, bismuth (Bi) ions, antimony (Sb) ions, or arsenic (As) ions, and the P-type doping ions may be group III ions such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

[0064] In step S102, please continue to refer to Figure 2, a gate dielectric layer 13 is formed, the gate dielectric layer 13 covers the first area A1 and the second area A2, and the gate dielectric layer 13 may include a single-layer structure or a multi-layer structure.

[0065] For example, the material of the gate dielectric layer 13 may include at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0066] In step S103, please continue to refer to Figure 2 The metal oxide layer 14 may be formed by metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes, and the metal oxide layer 14 covers the side of the gate dielectric layer 13 away from the substrate 11. The metal oxide layer 14 includes a first portion 114 located on the first area A1 and a second portion 214 located on the second area A2. The metal oxide layer 14 is a high dielectric constant layer of the first device 100. The material of the metal oxide layer 14 may include at least one of lanthanum oxide (La2O3), aluminum oxide (AlO), tantalum oxide (TaO), yttrium oxide (Y2O3), zirconium dioxide (ZrO2), strontium titanate (SrTiO3), or zirconium oxide silicate (ZrSiO4). In some embodiments, the material of the metal oxide layer 14 includes lanthanum oxide or aluminum oxide.

[0067] In this embodiment, in the vertical direction (the direction perpendicular to the top surface of the substrate 11), the top surface of the first portion 114 is lower than the top surface of the second portion 214. Figure 2 As shown, in this embodiment, a first gate structure 110 of a first device 100 is formed on a first region A1, and a second gate structure 110 of a second device 200 is formed on a second region A2. The structure of the second gate structure 110 may be more complex than that of the first gate structure 110. Before forming the gate dielectric layer 13, other film layers may be formed on the second region A2, resulting in a height difference between the film layers on the first region A1 and the second region A2, and the top surface of the first portion 114 is lower than the top surface of the second portion 214. However, this embodiment does not constitute a limitation on the inventive concept of the present disclosure. In some other embodiments, in the vertical direction (the direction perpendicular to the top surface of the substrate 11), the top surface of the first portion 114 may be flush with the top surface of the second portion 214, that is, located on the same horizontal plane. In other other embodiments, in the vertical direction (the direction perpendicular to the top surface of the substrate 11), the top surface of the first portion 114 may also be higher than the top surface of the second portion 214.

[0068] In step S104, please refer to Figure 3 , Figure 5 As shown, a protective layer 15 is formed on the first area A1, and the protective layer 15 only covers the first portion 114 of the metal oxide layer 14, exposing the second portion 214 of the metal oxide layer 14. In some embodiments, forming the protective layer 15 includes the following steps:

[0069] Step S41: forming a protective material layer 15a, which is located on the first area A1 and the second area A2. Figure 3 As shown, the protective material layer 15a can be deposited by ALD, CVD, or PVD processes, and the protective material layer 15a covers the first portion 114 and the second portion 214 of the metal oxide layer 14. In this embodiment, in the vertical direction (the direction perpendicular to the top surface of the substrate 11), the thickness of the protective material layer 15a located in the first area A1 and the protective material layer 15a located in the second area A2 can be the same or different, but the top surface of the protective material layer 15a located in the first area A1 is lower than the top surface of the protective material layer 15a located in the second area A2. For example, the material of the protective material layer 15a may include at least one of single crystal silicon, polycrystalline silicon, or amorphous silicon.

[0070] Step S42: remove the protective material layer 15a on the second area A2, and form a protective layer 15 on the first area A1. Figure 3 As shown, a mask layer 17 may be formed on the protective material layer 15a, and the mask layer 17 covers the protective material layer 15a located in the first area A1, exposing the protective material layer 15a located in the second area A2. The protective material layer 15a located in the second area A2 is etched according to the mask layer 17, and a portion of the protective material layer 15a located in the second area A2 is removed, so that the remaining thickness of the protective material layer 15a located in the second area A2 is less than the thickness of the protective material layer 15a located in the first area A1. In some embodiments, after etching the protective material layer 15a located in the second area A2 according to the mask layer 17, the top surface of the protective material layer 15a located in the second area A2 is lower than the top surface of the protective material layer 15a located in the first area A1. For example, the protective material layer 15a in the second area A2 may be etched using a dry process. Then, the mask layer 17 is removed to expose the protective material layer 15a located in the first area A1.

[0071] Step S43: Refer to Figure 4 , Figure 5As shown, the protective material layer 15a located in the first area A1 and the protective material layer 15a located in the second area A2 are etched at the same time, and the protective material layer 15a located in the second area A2 is completely etched away, exposing the second portion 214 of the metal oxide layer 14 located in the second area A2. Since the thickness of the protective material layer 15a located in the first area A1 is greater than the thickness of the protective material layer 15a located in the second area A2, after the protective material layer 15a located in the second area A2 is completely etched away, there is still the protective material layer 15a located in the first area A1 that has not been etched away, and the remaining protective material layer 15a located in the first area A1 is etched to cover the first portion 114 of the metal oxide layer 14, so as to form the protective layer 15.

[0072] For example, the protective material layer 15a may be etched using a wet process. For example, the etching solution may be ammonium hydroxide (NH4OH). Figure 6 As shown, the second portion 214 of the metal oxide layer 14 can be etched away by a wet process. For example, hydrogen chloride (HCl) can be used to etch away the second portion 214 of the metal oxide layer 14. Hydrogen chloride has a high etching selectivity to the metal oxide layer 14, and does not etch the protective layer 15. In this way, after the second portion 214 of the metal oxide layer 14 is removed by hydrogen chloride etching, and the gate dielectric layer 13 located in the second area A2 is exposed, the structure of the protective layer 15 located in the first area A1 is still relatively intact, avoiding being damaged by the etching solution, and the protective layer 15 covers the first portion 114 of the metal oxide layer 14, avoiding the first portion 114 from being contaminated by the etching solution, thereby achieving selective etching of the second portion 214 of the metal oxide layer 14.

[0073] In step S106, refer to Figure 7 As shown, the protective layer 15 can be removed by wet or dry etching to expose the first portion 114 of the metal oxide layer 14. For example, the protective layer 15 can be removed by etching with ammonium hydroxide, which can avoid damaging the first portion 114 of the metal oxide layer 14 by the step of etching and removing the protective layer 15, so that the first gate structure 110 (refer to Fig. 9 , Fig.10 ) has a complete structure, which is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0074] In the method for manufacturing the semiconductor structure of the present embodiment, a protective material layer 15a is etched based on a mask layer 17 to form a protective material layer 15a with a thickness difference on the metal oxide layer 14. The thickness of the protective material layer 15a located in the first area A1 is greater than the thickness of the protective material layer 15a located in the second area A2. After the protective material layer 15a in the second area A2 is removed by etching, the thickness of the protective material layer 15a in the first area A1 is reduced, and the remaining protective material layer 15a in the first area A1 can continue to protect the first part 114 of the metal oxide layer 14, so as to achieve selective etching of the second part 214 of the metal oxide layer 14. At the same time, the time for removing the protective layer 15 can be shortened, the process time can be saved, and the production efficiency can be improved.

[0075] In some other embodiments, reference Figure 3 , Figure 5 Alternatively, after forming the mask layer 17, all the protective material layers 15a located in the second area A2 may be directly etched away according to the mask layer 17, and the protective material layer 15a located in the first area A1 may be formed into a protective layer 15. Then, the second portion 214 of the metal oxide layer 14 located in the second area A2 is etched away to expose the top surface of the gate dielectric layer 13 located in the second area A2. Subsequently, the mask layer 17 and the protective layer 15 are removed to expose the first portion 114 of the metal oxide layer 14 located in the first area A2.

[0076] In some embodiments, before forming the gate dielectric layer 13 in step S102, the following steps are further performed:

[0077] Step S102-1: forming a stress adjustment layer 12 on the second area A2, wherein the stress adjustment layer 12 is in direct contact with the substrate 11 of the second area A2. In this embodiment, a first device 100 is formed in the first area A1, and a second device 200 is formed in the second area A2. In order to improve the performance of the second device 200, in this embodiment, referring to Figure 2 As shown, before forming the gate dielectric layer 13 , a stress adjustment layer 12 is formed on the substrate 11 in the second area A2 , and the stress adjustment layer 12 serves as a channel of the second device 200 .

[0078] In some embodiments, the substrate 11 is a silicon substrate, and the material of the stress adjustment layer 12 is germanium silicon. The carrier mobility of germanium is higher, and the lattice constant of germanium silicon is greater than the lattice constant of silicon. The substrate 11 applies compressive stress to the stress adjustment layer 12, and this compressive stress can increase the mobility of the carriers (electrons or holes) of the stress adjustment layer 12, which is beneficial to improve the driving current and response speed of the second device 200. In some other embodiments, the stress adjustment layer 12 may not be formed on the second area A2, and germanium ions may be injected into the surface layer of the substrate 11 in the second area A2 to use the silicon material doped with germanium ions as the channel of the second device 200 to improve the carrier mobility of the second device 200.

[0079] In some embodiments, step S102 of forming the gate dielectric layer 13 includes the following steps:

[0080] Step S1021: forming a first gate dielectric layer 131, which is located on the substrate 11 and the stress adjustment layer 12 in the first area A1. Figure 2 As shown, the first gate dielectric layer 131 may be formed by in-situ steam generation (ISSG), ALD, PVD and other processes, and the material of the first gate dielectric layer 131 may include at least one of silicon dioxide or silicon oxynitride. The first gate dielectric layer 131 is disposed between the substrate 11 and the metal oxide layer 14 (the high dielectric constant layer of the first device 100) of the first device 100, and between the substrate 11 and the high dielectric constant layer of the second device 200. The first gate dielectric layer 131 can be a connection interface between the substrate 11 and the metal oxide layer 14 of the first device 100, and between the substrate 11 and the high dielectric constant layer of the second device 200, which is beneficial to improving the carrier mobility of the first device 100 and the second device 200.

[0081] Step S1022: forming a second gate dielectric layer 132, which is located on the first gate dielectric layer 131, to form a gate dielectric layer 13. Figure 2 As shown, the second gate dielectric layer 132 is a high dielectric constant layer of the first device 100. The material of the second gate dielectric layer 132 may include hafnium silicate (HfSiO x ), hafnium silicon oxynitride (HfSiON), hafnium oxide silicate (HfSiO4) or hafnium dioxide (HfO2). In some embodiments, the material of the metal oxide layer 14 includes hafnium silicate, and the high dielectric constant of hafnium silicate can reduce the influence of the gate voltage on the substrate 11 and reduce the gate induced leakage current effect of the first device 100.

[0082] In some embodiments, after removing the protective layer 15 in step S106, the following steps are further performed:

[0083] Step S107: forming a work function layer 16, which is located on the first portion 114 of the metal oxide layer 14 and on the gate dielectric layer 13 of the second area A2. Figure 8 As shown, the work function layer 16 may include a first barrier layer 161, a semiconductor layer 162, a second barrier layer 163 and a metal gate layer 164 stacked in sequence. The material of the first barrier layer 161 includes a metal material, such as titanium nitride or other metal nitrides; the material of the semiconductor layer 162 may include polysilicon; the material of the second barrier layer 163 includes a metal material, such as titanium nitride or other metal nitrides. The metal gate layer 164 is formed on a side of the second barrier layer 163 away from the semiconductor layer 162, and the material of the metal gate layer 164 may include metal tungsten, metal titanium, metal tantalum, etc. In this way, using a metal material as a gate material can improve the pinning phenomenon of the Fermi level and avoid the depletion problem of the polysilicon gate. At the same time, the second barrier layer 163 can prevent the metal material of the metal gate layer 164 from diffusing into the semiconductor layer 162, and prevent the metal material of the metal gate layer 164 from contaminating other devices or film layers.

[0084] For example, the first barrier layer 161 may be formed by ALD, MOCVD or PVD deposition. The semiconductor layer 162 may be formed by ALD or CVD deposition. The second barrier layer 163 may be formed by ALD, MOCVD or PVD deposition. The metal gate layer 164 may be formed by ALD, MOCVD or PVD deposition.

[0085] In this embodiment, please continue to refer to Figure 8 As shown, after forming the work function layer 16, an isolation layer 18 is formed on the side of the work function layer 16 away from the substrate 11. The material of the isolation layer 18 may include at least one of silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbide. For example, the isolation layer 18 may be formed by ALD or CVD deposition.

[0086] Step S108 : forming a first gate structure in the first region, and forming a second gate structure in the second region at the same time.

[0087] In this embodiment, a photoresist layer (not shown in the figure) is formed on the side of the isolation layer 18 away from the substrate 11, and an exposure-development process is performed on the photoresist layer to pattern the photoresist layer to define the patterns of the first gate structure 110 and the second gate structure 210. Fig. 9 As shown, the isolation layer 18, the work function layer 16, the metal oxide layer 14, the gate dielectric layer 13 and the stress adjustment layer 12 are etched according to the patterned photoresist layer to form a first gate structure 110 in the first area A1 and a second gate structure 110 in the second area A2.

[0088] Step S109: forming a first source and a first drain in the first region on both sides of the first gate structure to form a first device 100; forming a second source and a second drain in the second region on both sides of the second gate structure to form a second device 200. Please continue to refer to Fig. 9 As shown, P-type dopant ions may be implanted into the substrate 11 on both sides of the first gate structure 110 to form a first source 120 and a first drain 130, and the first gate structure 110, the first source 120, and the first drain 130 together form a first device 100. P-type dopant ions may be implanted into the substrate 11 on both sides of the second gate structure 210 to form a second source 220 and a second drain 230, and the second gate structure 210, the second source 220, and the second drain 230 together form a second device 200.

[0089] It can be understood that the above embodiments are preferred implementations of the method for manufacturing a semiconductor structure of the present disclosure and do not constitute a limitation to the present disclosure.

[0090] For example, in some other embodiments of the present application, in the step of forming the gate dielectric layer 13 in step S102, only the first gate dielectric layer 131 may be formed, that is, the gate dielectric layer 13 in this embodiment only includes a single-layer structure of the first gate dielectric layer 131. Then, steps S103 to S106 are directly performed to form the metal oxide layer 14 only on the first area A1. Then, the second gate dielectric layer 132 is deposited to cover the metal oxide layer 14 of the first area A1 and the first gate dielectric layer 131 of the second area A2.

[0091] In other embodiments of the present application, which are not shown in the drawings, after the gate dielectric layer 13 is formed in step S102, a first protective layer may be formed to cover the gate dielectric layer 13 located in the second area A2, and the second gate dielectric layer 132 located in the first area A1 may be etched away. Then, a metal oxide layer 14 is formed to cover the gate dielectric layer 13, a second protective layer is formed to cover the metal oxide layer 14 located in the first area A1, and the metal oxide layer 14 located in the second area A2 may be etched away. In this way, the metal oxide layer 14 of the formed first gate structure 110 is in direct contact with the first gate dielectric layer 131, the first gate structure 110 does not have the second gate dielectric layer 132, and the second gate structure 210 does not have the metal oxide layer 14, thereby obtaining a semiconductor structure different from other embodiments.

[0092] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to Fig. 9 or Fig.10As shown, the semiconductor structure of this embodiment is manufactured by the manufacturing method of the semiconductor structure of the above embodiment. During the manufacturing process of the semiconductor structure of this embodiment, a protective layer 15 is formed after the metal oxide layer 14 is formed. The protective layer 15 is used to protect the metal oxide layer 14 located in the first area A1, so as to achieve selective etching of the metal oxide layer 14 located in the second area A2, and avoid the process of etching and removing the metal oxide layer 14 located in the second area A2 to damage the metal oxide layer 14 located in the first area A1, which is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0093] According to an exemplary embodiment, this embodiment provides a semiconductor structure such as Fig. 9 As shown, the semiconductor structure includes a substrate 11, a first gate structure 110 and a second gate structure 210; wherein the substrate 11 includes a first area A1 and a second area A2; the first gate structure 110 is arranged in the first area A1, and the substrate 11 on both sides of the first gate structure 110 forms a first source 120 and a first drain 130, and the first gate structure 110 and the first source 120 and the first drain 130 together form a first device 100; the first gate structure 110 includes a stacked gate dielectric layer 13, a metal oxide layer 14, and a work function layer 16; the second gate structure 210 is arranged in the second area A2, and the substrate 11 on both sides of the second gate structure 210 forms a second source 220 and a second drain 230, and the second gate structure 210 and the second source 220 and the second drain 230 together form a second device 200; the second gate structure 210 includes a stress adjustment layer 12, a gate dielectric layer 13, and a work function layer 16 stacked on the second area A2.

[0094] In the semiconductor structure of this embodiment, the structure and function of the metal oxide layer 14 of the first gate structure 110 are complete, the metal oxide layer 14 of the first gate structure 110 is less etched and damaged, and the second gate structure 210 reduces the residual metal oxide layer 14, which is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0095] In some embodiments, Fig. 9 As shown, the first region A1 is an NMOS region, and the second region A2 is a PMOS region. The first device 100 is an NMOS device, and the second device 200 is a PMOS device. In some embodiments, Fig. 9 As shown, the gate dielectric layer 13 includes a first gate dielectric layer 131 and a second gate dielectric layer 132 stacked together; wherein the material of the first gate dielectric layer 131 includes silicon oxynitride. The material of the second gate dielectric layer 132 includes at least one of hafnium silicate, hafnium silicon oxynitride, hafnium oxide silicate or hafnium dioxide. In some embodiments, as Fig. 9As shown, the material of the metal oxide layer 14 includes at least one of aluminum oxide or lanthanum oxide. The material of the metal oxide layer 14 may also include at least one of tantalum oxide, yttrium oxide, zirconium dioxide, strontium titanate, or zirconium oxide silicate. In some embodiments, as Fig. 9 As shown, the work function layer 16 includes a first barrier layer 161, a semiconductor layer 162, a second barrier layer 163 and a metal gate layer 164 which are stacked in sequence. The material of the first barrier layer 161 includes a metal material, such as titanium nitride or other metal nitrides; the material of the semiconductor layer 162 may include polysilicon; the material of the second barrier layer 163 includes a metal material, such as titanium nitride or other metal nitrides. The material of the metal gate layer 164 may include metal tungsten.

[0096] In other embodiments, the semiconductor structure is as follows Fig.10 As shown, the first gate structure 110 of the first device 100 includes a first gate dielectric layer 131, a metal oxide layer 14 and a work function layer 16 stacked on the first area A1, and the work function layer 16 includes a first barrier layer 161 and a metal gate layer 164 stacked on the metal oxide layer 14 in sequence. The second gate structure 110 of the second device 200 includes a first gate dielectric layer 131, a second gate dielectric layer 132 and a work function layer 16 stacked on the second area A2, and the work function layer 16 includes a first barrier layer 161 and a metal gate layer 164 stacked on the second gate dielectric layer 132 in sequence. Among them, the first device 100 is an NMOS device, and the second device 200 is a PMOS device. The material of the first gate dielectric layer 131 includes silicon oxynitride. The material of the second gate dielectric layer 132 includes at least one of hafnium silicate, hafnium silicon oxynitride, hafnium oxide silicate or hafnium dioxide. The material of the metal oxide layer 14 includes at least one of aluminum oxide or lanthanum oxide. Alternatively, the material of the metal oxide layer 14 may also include at least one of tantalum oxide, yttrium oxide, zirconium dioxide, strontium titanate, or zirconium oxide silicate.

[0097] In some other embodiments, in the semiconductor structure of the present embodiment, the first gate structure 110 of the first device 100 includes a first gate dielectric layer 131, a metal oxide layer 14, a second gate dielectric layer 132 and a work function layer 16 stacked on the first area A1; the second gate structure 110 of the second device 200 includes a first gate dielectric layer 131, a second gate dielectric layer 132 and a work function layer 16 stacked on the second area A2.

[0098] Among them, the semiconductor structure of the above embodiment can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM) or other types of memory.

[0099] According to an exemplary embodiment, this embodiment provides an electronic device, including the semiconductor structure in the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0100] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a gate dielectric layer located on the substrate; Forming a metal oxide layer, located on the substrate, comprising: A first part, located in the first zone; a second part, located in the second zone; Wherein, in the vertical direction, the top surface of the first part is lower than the top surface of the second part; forming a protective layer located on the first region, wherein the protective layer is in direct contact with the metal oxide layer; removing the second portion located at the metal oxide layer; Remove the protective layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first region is an NMOS region, and the second region is a PMOS region.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a protective layer, including: forming a protective material layer located on the first region and the second region; The protective material layer on the second region is removed, and the protective layer is formed on the first region.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before forming the gate dielectric layer, the method further includes: A stress adjustment layer is formed on the second region, the stress adjustment layer being in direct contact with the substrate of the second region.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: forming a gate dielectric layer, comprising: forming a first gate dielectric layer located on the substrate in the first region and on the stress adjustment layer; A second gate dielectric layer is formed, which is located on the first gate dielectric layer, to form the gate dielectric layer.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: A work function layer is formed on the first portion of the metal oxide layer and on the gate dielectric layer in the second region.

7. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A first gate structure, disposed in the first region, the first gate structure comprising a stacked gate dielectric layer, a metal oxide layer, and a work function layer; The second gate structure is arranged in the second region, and the second gate structure includes a stress adjustment layer, a gate dielectric layer, and a work function layer stacked on the second region.

8. The semiconductor structure according to claim 7, characterized in that: The first region is an NMOS region, and the second region is a PMOS region.

9. The semiconductor structure according to claim 7, characterized in that: The gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer stacked together; Wherein, the material of the first gate dielectric layer includes silicon oxynitride.

10. The semiconductor structure according to claim 7, characterized in that: The material of the metal oxide layer includes at least one of aluminum oxide and lanthanum oxide.

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